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7#ifndef __SYSTEM_GLOBAL_H_INCLUDED__
8#define __SYSTEM_GLOBAL_H_INCLUDED__
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28
29#define SH_CSS_ENABLE_PER_FRAME_PARAMS
30
31#define DMA_DDR_TO_VAMEM_WORKAROUND
32#define DMA_DDR_TO_HMEM_WORKAROUND
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34
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36
37
38#define HIVE_ISP_MAX_BURST_LENGTH 1024
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46
47#define ISP2400_DMA_MAX_BURST_LENGTH 128
48#define ISP2401_DMA_MAX_BURST_LENGTH 2
49
50#include <hive_isp_css_defs.h>
51#include <type_support.h>
52
53
54#include "hive_types.h"
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56
57
58
59#define HRT_VADDRESS_WIDTH 32
60
61#define SIZEOF_HRT_REG (HRT_DATA_WIDTH >> 3)
62#define HIVE_ISP_CTRL_DATA_BYTES (HIVE_ISP_CTRL_DATA_WIDTH / 8)
63
64
65#define HRT_BUS_WIDTH HIVE_ISP_CTRL_DATA_WIDTH
66#define HRT_BUS_BYTES HIVE_ISP_CTRL_DATA_BYTES
67
68typedef u32 hrt_bus_align_t;
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70
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74
75typedef enum {
76 DDR0_ID = 0,
77 N_DDR_ID
78} ddr_ID_t;
79
80typedef enum {
81 ISP0_ID = 0,
82 N_ISP_ID
83} isp_ID_t;
84
85typedef enum {
86 SP0_ID = 0,
87 N_SP_ID
88} sp_ID_t;
89
90typedef enum {
91 MMU0_ID = 0,
92 MMU1_ID,
93 N_MMU_ID
94} mmu_ID_t;
95
96typedef enum {
97 DMA0_ID = 0,
98 N_DMA_ID
99} dma_ID_t;
100
101typedef enum {
102 GDC0_ID = 0,
103 GDC1_ID,
104 N_GDC_ID
105} gdc_ID_t;
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107
108
109
110#define N_GDC_ID_CPP 2
111
112typedef enum {
113 VAMEM0_ID = 0,
114 VAMEM1_ID,
115 VAMEM2_ID,
116 N_VAMEM_ID
117} vamem_ID_t;
118
119typedef enum {
120 BAMEM0_ID = 0,
121 N_BAMEM_ID
122} bamem_ID_t;
123
124typedef enum {
125 HMEM0_ID = 0,
126 N_HMEM_ID
127} hmem_ID_t;
128
129typedef enum {
130 IRQ0_ID = 0,
131 IRQ1_ID,
132 IRQ2_ID,
133 IRQ3_ID,
134 N_IRQ_ID
135} irq_ID_t;
136
137typedef enum {
138 FIFO_MONITOR0_ID = 0,
139 N_FIFO_MONITOR_ID
140} fifo_monitor_ID_t;
141
142typedef enum {
143 GP_DEVICE0_ID = 0,
144 N_GP_DEVICE_ID
145} gp_device_ID_t;
146
147typedef enum {
148 GP_TIMER0_ID = 0,
149 GP_TIMER1_ID,
150 GP_TIMER2_ID,
151 GP_TIMER3_ID,
152 GP_TIMER4_ID,
153 GP_TIMER5_ID,
154 GP_TIMER6_ID,
155 GP_TIMER7_ID,
156 N_GP_TIMER_ID
157} gp_timer_ID_t;
158
159typedef enum {
160 GPIO0_ID = 0,
161 N_GPIO_ID
162} gpio_ID_t;
163
164typedef enum {
165 TIMED_CTRL0_ID = 0,
166 N_TIMED_CTRL_ID
167} timed_ctrl_ID_t;
168
169typedef enum {
170 INPUT_FORMATTER0_ID = 0,
171 INPUT_FORMATTER1_ID,
172 INPUT_FORMATTER2_ID,
173 INPUT_FORMATTER3_ID,
174 N_INPUT_FORMATTER_ID
175} input_formatter_ID_t;
176
177
178#define INPUT_FORMATTER0_SRST_OFFSET 0x0824
179#define INPUT_FORMATTER1_SRST_OFFSET 0x0624
180#define INPUT_FORMATTER2_SRST_OFFSET 0x0424
181#define INPUT_FORMATTER3_SRST_OFFSET 0x0224
182
183#define INPUT_FORMATTER0_SRST_MASK 0x0001
184#define INPUT_FORMATTER1_SRST_MASK 0x0002
185#define INPUT_FORMATTER2_SRST_MASK 0x0004
186#define INPUT_FORMATTER3_SRST_MASK 0x0008
187
188typedef enum {
189 INPUT_SYSTEM0_ID = 0,
190 N_INPUT_SYSTEM_ID
191} input_system_ID_t;
192
193typedef enum {
194 RX0_ID = 0,
195 N_RX_ID
196} rx_ID_t;
197
198enum mipi_port_id {
199 MIPI_PORT0_ID = 0,
200 MIPI_PORT1_ID,
201 MIPI_PORT2_ID,
202 N_MIPI_PORT_ID
203};
204
205#define N_RX_CHANNEL_ID 4
206
207
208typedef enum {
209 CSI_PORT0_ID = 0,
210 CSI_PORT1_ID,
211 CSI_PORT2_ID,
212 TPG_PORT0_ID,
213 PRBS_PORT0_ID,
214 FIFO_PORT0_ID,
215 MEMORY_PORT0_ID,
216 N_INPUT_PORT_ID
217} input_port_ID_t;
218
219typedef enum {
220 CAPTURE_UNIT0_ID = 0,
221 CAPTURE_UNIT1_ID,
222 CAPTURE_UNIT2_ID,
223 ACQUISITION_UNIT0_ID,
224 DMA_UNIT0_ID,
225 CTRL_UNIT0_ID,
226 GPREGS_UNIT0_ID,
227 FIFO_UNIT0_ID,
228 IRQ_UNIT0_ID,
229 N_SUB_SYSTEM_ID
230} sub_system_ID_t;
231
232#define N_CAPTURE_UNIT_ID 3
233#define N_ACQUISITION_UNIT_ID 1
234#define N_CTRL_UNIT_ID 1
235
236
237enum ia_css_isp_memories {
238 IA_CSS_ISP_PMEM0 = 0,
239 IA_CSS_ISP_DMEM0,
240 IA_CSS_ISP_VMEM0,
241 IA_CSS_ISP_VAMEM0,
242 IA_CSS_ISP_VAMEM1,
243 IA_CSS_ISP_VAMEM2,
244 IA_CSS_ISP_HMEM0,
245 IA_CSS_SP_DMEM0,
246 IA_CSS_DDR,
247 N_IA_CSS_MEMORIES
248};
249
250#define IA_CSS_NUM_MEMORIES 9
251
252#define N_IA_CSS_ISP_MEMORIES IA_CSS_NUM_MEMORIES
253#define IA_CSS_NUM_ISP_MEMORIES IA_CSS_NUM_MEMORIES
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258
259typedef enum {
260 ISYS_IRQ0_ID = 0,
261 ISYS_IRQ1_ID,
262 ISYS_IRQ2_ID,
263 N_ISYS_IRQ_ID
264} isys_irq_ID_t;
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269
270typedef enum {
271 IBUF_CTRL0_ID = 0,
272 IBUF_CTRL1_ID,
273 IBUF_CTRL2_ID,
274 N_IBUF_CTRL_ID
275} ibuf_ctrl_ID_t;
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280
281typedef enum {
282 STREAM2MMIO0_ID = 0,
283 STREAM2MMIO1_ID,
284 STREAM2MMIO2_ID,
285 N_STREAM2MMIO_ID
286} stream2mmio_ID_t;
287
288typedef enum {
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298
299 STREAM2MMIO_SID0_ID = 0,
300 STREAM2MMIO_SID1_ID,
301 STREAM2MMIO_SID2_ID,
302 STREAM2MMIO_SID3_ID,
303 STREAM2MMIO_SID4_ID,
304 STREAM2MMIO_SID5_ID,
305 STREAM2MMIO_SID6_ID,
306 STREAM2MMIO_SID7_ID,
307 N_STREAM2MMIO_SID_ID
308} stream2mmio_sid_ID_t;
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310
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312
313
314typedef enum {
315 CSI_RX_BACKEND0_ID = 0,
316 CSI_RX_BACKEND1_ID,
317 CSI_RX_BACKEND2_ID,
318 N_CSI_RX_BACKEND_ID
319} csi_rx_backend_ID_t;
320
321typedef enum {
322 CSI_RX_FRONTEND0_ID = 0,
323 CSI_RX_FRONTEND1_ID,
324 CSI_RX_FRONTEND2_ID,
325#define N_CSI_RX_FRONTEND_ID (CSI_RX_FRONTEND2_ID + 1)
326} csi_rx_frontend_ID_t;
327
328typedef enum {
329 CSI_RX_DLANE0_ID = 0,
330 CSI_RX_DLANE1_ID,
331 CSI_RX_DLANE2_ID,
332 CSI_RX_DLANE3_ID,
333 N_CSI_RX_DLANE_ID
334} csi_rx_fe_dlane_ID_t;
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336
337typedef enum {
338 ISYS2401_DMA0_ID = 0,
339 N_ISYS2401_DMA_ID
340} isys2401_dma_ID_t;
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343
344
345typedef enum {
346 PIXELGEN0_ID = 0,
347 PIXELGEN1_ID,
348 PIXELGEN2_ID,
349 N_PIXELGEN_ID
350} pixelgen_ID_t;
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352
353typedef enum {
354 INPUT_SYSTEM_CSI_PORT0_ID = 0,
355 INPUT_SYSTEM_CSI_PORT1_ID,
356 INPUT_SYSTEM_CSI_PORT2_ID,
357
358 INPUT_SYSTEM_PIXELGEN_PORT0_ID,
359 INPUT_SYSTEM_PIXELGEN_PORT1_ID,
360 INPUT_SYSTEM_PIXELGEN_PORT2_ID,
361
362 N_INPUT_SYSTEM_INPUT_PORT_ID
363} input_system_input_port_ID_t;
364
365#define N_INPUT_SYSTEM_CSI_PORT 3
366
367typedef enum {
368 ISYS2401_DMA_CHANNEL_0 = 0,
369 ISYS2401_DMA_CHANNEL_1,
370 ISYS2401_DMA_CHANNEL_2,
371 ISYS2401_DMA_CHANNEL_3,
372 ISYS2401_DMA_CHANNEL_4,
373 ISYS2401_DMA_CHANNEL_5,
374 ISYS2401_DMA_CHANNEL_6,
375 ISYS2401_DMA_CHANNEL_7,
376 ISYS2401_DMA_CHANNEL_8,
377 ISYS2401_DMA_CHANNEL_9,
378 ISYS2401_DMA_CHANNEL_10,
379 ISYS2401_DMA_CHANNEL_11,
380 N_ISYS2401_DMA_CHANNEL
381} isys2401_dma_channel;
382
383#endif
384