1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Support for Intel Camera Imaging ISP subsystem. 4 * Copyright (c) 2015, Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 */ 15 16#ifndef __SYSTEM_LOCAL_H_INCLUDED__ 17#define __SYSTEM_LOCAL_H_INCLUDED__ 18 19#ifdef HRT_ISP_CSS_CUSTOM_HOST 20#ifndef HRT_USE_VIR_ADDRS 21#define HRT_USE_VIR_ADDRS 22#endif 23#endif 24 25#include "system_global.h" 26 27/* This interface is deprecated */ 28#include "hive_types.h" 29 30/* 31 * Cell specific address maps 32 */ 33 34#define GP_FIFO_BASE ((hrt_address)0x0000000000090104) /* This is NOT a base address */ 35 36/* ISP */ 37extern const hrt_address ISP_CTRL_BASE[N_ISP_ID]; 38extern const hrt_address ISP_DMEM_BASE[N_ISP_ID]; 39extern const hrt_address ISP_BAMEM_BASE[N_BAMEM_ID]; 40 41/* SP */ 42extern const hrt_address SP_CTRL_BASE[N_SP_ID]; 43extern const hrt_address SP_DMEM_BASE[N_SP_ID]; 44 45/* MMU */ 46 47extern const hrt_address MMU_BASE[N_MMU_ID]; 48 49/* DMA */ 50extern const hrt_address DMA_BASE[N_DMA_ID]; 51extern const hrt_address ISYS2401_DMA_BASE[N_ISYS2401_DMA_ID]; 52 53/* IRQ */ 54extern const hrt_address IRQ_BASE[N_IRQ_ID]; 55 56/* GDC */ 57extern const hrt_address GDC_BASE[N_GDC_ID]; 58 59/* FIFO_MONITOR (not a subset of GP_DEVICE) */ 60extern const hrt_address FIFO_MONITOR_BASE[N_FIFO_MONITOR_ID]; 61 62/* GP_DEVICE (single base for all separate GP_REG instances) */ 63extern const hrt_address GP_DEVICE_BASE[N_GP_DEVICE_ID]; 64 65/*GP TIMER , all timer registers are inter-twined, 66 * so, having multiple base addresses for 67 * different timers does not help*/ 68extern const hrt_address GP_TIMER_BASE; 69 70/* GPIO */ 71extern const hrt_address GPIO_BASE[N_GPIO_ID]; 72 73/* TIMED_CTRL */ 74extern const hrt_address TIMED_CTRL_BASE[N_TIMED_CTRL_ID]; 75 76/* INPUT_FORMATTER */ 77extern const hrt_address INPUT_FORMATTER_BASE[N_INPUT_FORMATTER_ID]; 78 79/* INPUT_SYSTEM */ 80extern const hrt_address INPUT_SYSTEM_BASE[N_INPUT_SYSTEM_ID]; 81 82/* RX, the MIPI lane control regs start at offset 0 */ 83extern const hrt_address RX_BASE[N_RX_ID]; 84 85/* IBUF_CTRL, part of the Input System 2401 */ 86extern const hrt_address IBUF_CTRL_BASE[N_IBUF_CTRL_ID]; 87 88/* ISYS IRQ Controllers, part of the Input System 2401 */ 89extern const hrt_address ISYS_IRQ_BASE[N_ISYS_IRQ_ID]; 90 91/* CSI FE, part of the Input System 2401 */ 92extern const hrt_address CSI_RX_FE_CTRL_BASE[N_CSI_RX_FRONTEND_ID]; 93 94/* CSI BE, part of the Input System 2401 */ 95extern const hrt_address CSI_RX_BE_CTRL_BASE[N_CSI_RX_BACKEND_ID]; 96 97/* PIXEL Generator, part of the Input System 2401 */ 98extern const hrt_address PIXELGEN_CTRL_BASE[N_PIXELGEN_ID]; 99 100/* Stream2MMIO, part of the Input System 2401 */ 101extern const hrt_address STREAM2MMIO_CTRL_BASE[N_STREAM2MMIO_ID]; 102 103#endif /* __SYSTEM_LOCAL_H_INCLUDED__ */ 104