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13#include <linux/clk.h>
14#include <linux/module.h>
15#include <linux/of.h>
16#include <linux/platform_device.h>
17#include <linux/pm.h>
18#include <linux/pm_runtime.h>
19#include <linux/slab.h>
20#include <linux/videodev2.h>
21#include <linux/workqueue.h>
22#include <media/v4l2-event.h>
23#include <media/v4l2-mem2mem.h>
24#include <media/videobuf2-core.h>
25#include <media/videobuf2-vmalloc.h>
26
27#include "hantro_v4l2.h"
28#include "hantro.h"
29#include "hantro_hw.h"
30
31#define DRIVER_NAME "hantro-vpu"
32
33int hantro_debug;
34module_param_named(debug, hantro_debug, int, 0644);
35MODULE_PARM_DESC(debug,
36 "Debug level - higher value produces more verbose messages");
37
38void *hantro_get_ctrl(struct hantro_ctx *ctx, u32 id)
39{
40 struct v4l2_ctrl *ctrl;
41
42 ctrl = v4l2_ctrl_find(&ctx->ctrl_handler, id);
43 return ctrl ? ctrl->p_cur.p : NULL;
44}
45
46dma_addr_t hantro_get_ref(struct hantro_ctx *ctx, u64 ts)
47{
48 struct vb2_queue *q = v4l2_m2m_get_dst_vq(ctx->fh.m2m_ctx);
49 struct vb2_buffer *buf;
50 int index;
51
52 index = vb2_find_timestamp(q, ts, 0);
53 if (index < 0)
54 return 0;
55 buf = vb2_get_buffer(q, index);
56 return hantro_get_dec_buf_addr(ctx, buf);
57}
58
59static void hantro_job_finish_no_pm(struct hantro_dev *vpu,
60 struct hantro_ctx *ctx,
61 enum vb2_buffer_state result)
62{
63 struct vb2_v4l2_buffer *src, *dst;
64
65 src = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
66 dst = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
67
68 if (WARN_ON(!src))
69 return;
70 if (WARN_ON(!dst))
71 return;
72
73 src->sequence = ctx->sequence_out++;
74 dst->sequence = ctx->sequence_cap++;
75
76 v4l2_m2m_buf_done_and_job_finish(ctx->dev->m2m_dev, ctx->fh.m2m_ctx,
77 result);
78}
79
80static void hantro_job_finish(struct hantro_dev *vpu,
81 struct hantro_ctx *ctx,
82 enum vb2_buffer_state result)
83{
84 pm_runtime_mark_last_busy(vpu->dev);
85 pm_runtime_put_autosuspend(vpu->dev);
86
87 clk_bulk_disable(vpu->variant->num_clocks, vpu->clocks);
88
89 hantro_job_finish_no_pm(vpu, ctx, result);
90}
91
92void hantro_irq_done(struct hantro_dev *vpu,
93 enum vb2_buffer_state result)
94{
95 struct hantro_ctx *ctx =
96 v4l2_m2m_get_curr_priv(vpu->m2m_dev);
97
98
99
100
101
102
103 if (cancel_delayed_work(&vpu->watchdog_work)) {
104 if (result == VB2_BUF_STATE_DONE && ctx->codec_ops->done)
105 ctx->codec_ops->done(ctx);
106 hantro_job_finish(vpu, ctx, result);
107 }
108}
109
110void hantro_watchdog(struct work_struct *work)
111{
112 struct hantro_dev *vpu;
113 struct hantro_ctx *ctx;
114
115 vpu = container_of(to_delayed_work(work),
116 struct hantro_dev, watchdog_work);
117 ctx = v4l2_m2m_get_curr_priv(vpu->m2m_dev);
118 if (ctx) {
119 vpu_err("frame processing timed out!\n");
120 ctx->codec_ops->reset(ctx);
121 hantro_job_finish(vpu, ctx, VB2_BUF_STATE_ERROR);
122 }
123}
124
125void hantro_start_prepare_run(struct hantro_ctx *ctx)
126{
127 struct vb2_v4l2_buffer *src_buf;
128
129 src_buf = hantro_get_src_buf(ctx);
130 v4l2_ctrl_request_setup(src_buf->vb2_buf.req_obj.req,
131 &ctx->ctrl_handler);
132
133 if (!ctx->is_encoder) {
134 if (hantro_needs_postproc(ctx, ctx->vpu_dst_fmt))
135 hantro_postproc_enable(ctx);
136 else
137 hantro_postproc_disable(ctx);
138 }
139}
140
141void hantro_end_prepare_run(struct hantro_ctx *ctx)
142{
143 struct vb2_v4l2_buffer *src_buf;
144
145 src_buf = hantro_get_src_buf(ctx);
146 v4l2_ctrl_request_complete(src_buf->vb2_buf.req_obj.req,
147 &ctx->ctrl_handler);
148
149
150 schedule_delayed_work(&ctx->dev->watchdog_work,
151 msecs_to_jiffies(2000));
152}
153
154static void device_run(void *priv)
155{
156 struct hantro_ctx *ctx = priv;
157 struct vb2_v4l2_buffer *src, *dst;
158 int ret;
159
160 src = hantro_get_src_buf(ctx);
161 dst = hantro_get_dst_buf(ctx);
162
163 ret = pm_runtime_resume_and_get(ctx->dev->dev);
164 if (ret < 0)
165 goto err_cancel_job;
166
167 ret = clk_bulk_enable(ctx->dev->variant->num_clocks, ctx->dev->clocks);
168 if (ret)
169 goto err_cancel_job;
170
171 v4l2_m2m_buf_copy_metadata(src, dst, true);
172
173 if (ctx->codec_ops->run(ctx))
174 goto err_cancel_job;
175
176 return;
177
178err_cancel_job:
179 hantro_job_finish_no_pm(ctx->dev, ctx, VB2_BUF_STATE_ERROR);
180}
181
182static const struct v4l2_m2m_ops vpu_m2m_ops = {
183 .device_run = device_run,
184};
185
186static int
187queue_init(void *priv, struct vb2_queue *src_vq, struct vb2_queue *dst_vq)
188{
189 struct hantro_ctx *ctx = priv;
190 int ret;
191
192 src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
193 src_vq->io_modes = VB2_MMAP | VB2_DMABUF;
194 src_vq->drv_priv = ctx;
195 src_vq->ops = &hantro_queue_ops;
196 src_vq->mem_ops = &vb2_dma_contig_memops;
197
198
199
200
201
202
203 src_vq->dma_attrs = DMA_ATTR_ALLOC_SINGLE_PAGES |
204 DMA_ATTR_NO_KERNEL_MAPPING;
205 src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
206 src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
207 src_vq->lock = &ctx->dev->vpu_mutex;
208 src_vq->dev = ctx->dev->v4l2_dev.dev;
209 src_vq->supports_requests = true;
210
211 ret = vb2_queue_init(src_vq);
212 if (ret)
213 return ret;
214
215
216
217
218
219
220
221
222 if (ctx->is_encoder) {
223 dst_vq->mem_ops = &vb2_vmalloc_memops;
224 } else {
225 dst_vq->bidirectional = true;
226 dst_vq->mem_ops = &vb2_dma_contig_memops;
227 dst_vq->dma_attrs = DMA_ATTR_ALLOC_SINGLE_PAGES |
228 DMA_ATTR_NO_KERNEL_MAPPING;
229 }
230
231 dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
232 dst_vq->io_modes = VB2_MMAP | VB2_DMABUF;
233 dst_vq->drv_priv = ctx;
234 dst_vq->ops = &hantro_queue_ops;
235 dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
236 dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
237 dst_vq->lock = &ctx->dev->vpu_mutex;
238 dst_vq->dev = ctx->dev->v4l2_dev.dev;
239
240 return vb2_queue_init(dst_vq);
241}
242
243static int hantro_try_ctrl(struct v4l2_ctrl *ctrl)
244{
245 if (ctrl->id == V4L2_CID_STATELESS_H264_SPS) {
246 const struct v4l2_ctrl_h264_sps *sps = ctrl->p_new.p_h264_sps;
247
248 if (sps->chroma_format_idc > 1)
249
250 return -EINVAL;
251 if (sps->bit_depth_luma_minus8 != sps->bit_depth_chroma_minus8)
252
253 return -EINVAL;
254 if (sps->bit_depth_luma_minus8 != 0)
255
256 return -EINVAL;
257 } else if (ctrl->id == V4L2_CID_MPEG_VIDEO_HEVC_SPS) {
258 const struct v4l2_ctrl_hevc_sps *sps = ctrl->p_new.p_hevc_sps;
259
260 if (sps->bit_depth_luma_minus8 != sps->bit_depth_chroma_minus8)
261
262 return -EINVAL;
263 if (sps->bit_depth_luma_minus8 != 0)
264
265 return -EINVAL;
266 }
267 return 0;
268}
269
270static int hantro_jpeg_s_ctrl(struct v4l2_ctrl *ctrl)
271{
272 struct hantro_ctx *ctx;
273
274 ctx = container_of(ctrl->handler,
275 struct hantro_ctx, ctrl_handler);
276
277 vpu_debug(1, "s_ctrl: id = %d, val = %d\n", ctrl->id, ctrl->val);
278
279 switch (ctrl->id) {
280 case V4L2_CID_JPEG_COMPRESSION_QUALITY:
281 ctx->jpeg_quality = ctrl->val;
282 break;
283 default:
284 return -EINVAL;
285 }
286
287 return 0;
288}
289
290static int hantro_hevc_s_ctrl(struct v4l2_ctrl *ctrl)
291{
292 struct hantro_ctx *ctx;
293
294 ctx = container_of(ctrl->handler,
295 struct hantro_ctx, ctrl_handler);
296
297 vpu_debug(1, "s_ctrl: id = %d, val = %d\n", ctrl->id, ctrl->val);
298
299 switch (ctrl->id) {
300 case V4L2_CID_HANTRO_HEVC_SLICE_HEADER_SKIP:
301 ctx->hevc_dec.ctrls.hevc_hdr_skip_length = ctrl->val;
302 break;
303 default:
304 return -EINVAL;
305 }
306
307 return 0;
308}
309
310static const struct v4l2_ctrl_ops hantro_ctrl_ops = {
311 .try_ctrl = hantro_try_ctrl,
312};
313
314static const struct v4l2_ctrl_ops hantro_jpeg_ctrl_ops = {
315 .s_ctrl = hantro_jpeg_s_ctrl,
316};
317
318static const struct v4l2_ctrl_ops hantro_hevc_ctrl_ops = {
319 .s_ctrl = hantro_hevc_s_ctrl,
320};
321
322static const struct hantro_ctrl controls[] = {
323 {
324 .codec = HANTRO_JPEG_ENCODER,
325 .cfg = {
326 .id = V4L2_CID_JPEG_COMPRESSION_QUALITY,
327 .min = 5,
328 .max = 100,
329 .step = 1,
330 .def = 50,
331 .ops = &hantro_jpeg_ctrl_ops,
332 },
333 }, {
334 .codec = HANTRO_MPEG2_DECODER,
335 .cfg = {
336 .id = V4L2_CID_STATELESS_MPEG2_SEQUENCE,
337 },
338 }, {
339 .codec = HANTRO_MPEG2_DECODER,
340 .cfg = {
341 .id = V4L2_CID_STATELESS_MPEG2_PICTURE,
342 },
343 }, {
344 .codec = HANTRO_MPEG2_DECODER,
345 .cfg = {
346 .id = V4L2_CID_STATELESS_MPEG2_QUANTISATION,
347 },
348 }, {
349 .codec = HANTRO_VP8_DECODER,
350 .cfg = {
351 .id = V4L2_CID_STATELESS_VP8_FRAME,
352 },
353 }, {
354 .codec = HANTRO_H264_DECODER,
355 .cfg = {
356 .id = V4L2_CID_STATELESS_H264_DECODE_PARAMS,
357 },
358 }, {
359 .codec = HANTRO_H264_DECODER,
360 .cfg = {
361 .id = V4L2_CID_STATELESS_H264_SPS,
362 .ops = &hantro_ctrl_ops,
363 },
364 }, {
365 .codec = HANTRO_H264_DECODER,
366 .cfg = {
367 .id = V4L2_CID_STATELESS_H264_PPS,
368 },
369 }, {
370 .codec = HANTRO_H264_DECODER,
371 .cfg = {
372 .id = V4L2_CID_STATELESS_H264_SCALING_MATRIX,
373 },
374 }, {
375 .codec = HANTRO_H264_DECODER,
376 .cfg = {
377 .id = V4L2_CID_STATELESS_H264_DECODE_MODE,
378 .min = V4L2_STATELESS_H264_DECODE_MODE_FRAME_BASED,
379 .def = V4L2_STATELESS_H264_DECODE_MODE_FRAME_BASED,
380 .max = V4L2_STATELESS_H264_DECODE_MODE_FRAME_BASED,
381 },
382 }, {
383 .codec = HANTRO_H264_DECODER,
384 .cfg = {
385 .id = V4L2_CID_STATELESS_H264_START_CODE,
386 .min = V4L2_STATELESS_H264_START_CODE_ANNEX_B,
387 .def = V4L2_STATELESS_H264_START_CODE_ANNEX_B,
388 .max = V4L2_STATELESS_H264_START_CODE_ANNEX_B,
389 },
390 }, {
391 .codec = HANTRO_H264_DECODER,
392 .cfg = {
393 .id = V4L2_CID_MPEG_VIDEO_H264_PROFILE,
394 .min = V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE,
395 .max = V4L2_MPEG_VIDEO_H264_PROFILE_HIGH,
396 .menu_skip_mask =
397 BIT(V4L2_MPEG_VIDEO_H264_PROFILE_EXTENDED),
398 .def = V4L2_MPEG_VIDEO_H264_PROFILE_MAIN,
399 }
400 }, {
401 .codec = HANTRO_HEVC_DECODER,
402 .cfg = {
403 .id = V4L2_CID_MPEG_VIDEO_HEVC_DECODE_MODE,
404 .min = V4L2_MPEG_VIDEO_HEVC_DECODE_MODE_FRAME_BASED,
405 .max = V4L2_MPEG_VIDEO_HEVC_DECODE_MODE_FRAME_BASED,
406 .def = V4L2_MPEG_VIDEO_HEVC_DECODE_MODE_FRAME_BASED,
407 },
408 }, {
409 .codec = HANTRO_HEVC_DECODER,
410 .cfg = {
411 .id = V4L2_CID_MPEG_VIDEO_HEVC_START_CODE,
412 .min = V4L2_MPEG_VIDEO_HEVC_START_CODE_ANNEX_B,
413 .max = V4L2_MPEG_VIDEO_HEVC_START_CODE_ANNEX_B,
414 .def = V4L2_MPEG_VIDEO_HEVC_START_CODE_ANNEX_B,
415 },
416 }, {
417 .codec = HANTRO_HEVC_DECODER,
418 .cfg = {
419 .id = V4L2_CID_MPEG_VIDEO_HEVC_PROFILE,
420 .min = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN,
421 .max = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10,
422 .def = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN,
423 },
424 }, {
425 .codec = HANTRO_HEVC_DECODER,
426 .cfg = {
427 .id = V4L2_CID_MPEG_VIDEO_HEVC_LEVEL,
428 .min = V4L2_MPEG_VIDEO_HEVC_LEVEL_1,
429 .max = V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1,
430 },
431 }, {
432 .codec = HANTRO_HEVC_DECODER,
433 .cfg = {
434 .id = V4L2_CID_MPEG_VIDEO_HEVC_SPS,
435 .ops = &hantro_ctrl_ops,
436 },
437 }, {
438 .codec = HANTRO_HEVC_DECODER,
439 .cfg = {
440 .id = V4L2_CID_MPEG_VIDEO_HEVC_PPS,
441 },
442 }, {
443 .codec = HANTRO_HEVC_DECODER,
444 .cfg = {
445 .id = V4L2_CID_MPEG_VIDEO_HEVC_DECODE_PARAMS,
446 },
447 }, {
448 .codec = HANTRO_HEVC_DECODER,
449 .cfg = {
450 .id = V4L2_CID_MPEG_VIDEO_HEVC_SCALING_MATRIX,
451 },
452 }, {
453 .codec = HANTRO_HEVC_DECODER,
454 .cfg = {
455 .id = V4L2_CID_HANTRO_HEVC_SLICE_HEADER_SKIP,
456 .name = "Hantro HEVC slice header skip bytes",
457 .type = V4L2_CTRL_TYPE_INTEGER,
458 .min = 0,
459 .def = 0,
460 .max = 0x100,
461 .step = 1,
462 .ops = &hantro_hevc_ctrl_ops,
463 },
464 },
465};
466
467static int hantro_ctrls_setup(struct hantro_dev *vpu,
468 struct hantro_ctx *ctx,
469 int allowed_codecs)
470{
471 int i, num_ctrls = ARRAY_SIZE(controls);
472
473 v4l2_ctrl_handler_init(&ctx->ctrl_handler, num_ctrls);
474
475 for (i = 0; i < num_ctrls; i++) {
476 if (!(allowed_codecs & controls[i].codec))
477 continue;
478
479 v4l2_ctrl_new_custom(&ctx->ctrl_handler,
480 &controls[i].cfg, NULL);
481 if (ctx->ctrl_handler.error) {
482 vpu_err("Adding control (%d) failed %d\n",
483 controls[i].cfg.id,
484 ctx->ctrl_handler.error);
485 v4l2_ctrl_handler_free(&ctx->ctrl_handler);
486 return ctx->ctrl_handler.error;
487 }
488 }
489 return v4l2_ctrl_handler_setup(&ctx->ctrl_handler);
490}
491
492
493
494
495
496static int hantro_open(struct file *filp)
497{
498 struct hantro_dev *vpu = video_drvdata(filp);
499 struct video_device *vdev = video_devdata(filp);
500 struct hantro_func *func = hantro_vdev_to_func(vdev);
501 struct hantro_ctx *ctx;
502 int allowed_codecs, ret;
503
504
505
506
507
508
509
510
511
512
513 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
514 if (!ctx)
515 return -ENOMEM;
516
517 ctx->dev = vpu;
518 if (func->id == MEDIA_ENT_F_PROC_VIDEO_ENCODER) {
519 allowed_codecs = vpu->variant->codec & HANTRO_ENCODERS;
520 ctx->is_encoder = true;
521 } else if (func->id == MEDIA_ENT_F_PROC_VIDEO_DECODER) {
522 allowed_codecs = vpu->variant->codec & HANTRO_DECODERS;
523 ctx->is_encoder = false;
524 } else {
525 ret = -ENODEV;
526 goto err_ctx_free;
527 }
528
529 ctx->fh.m2m_ctx = v4l2_m2m_ctx_init(vpu->m2m_dev, ctx, queue_init);
530 if (IS_ERR(ctx->fh.m2m_ctx)) {
531 ret = PTR_ERR(ctx->fh.m2m_ctx);
532 goto err_ctx_free;
533 }
534
535 v4l2_fh_init(&ctx->fh, vdev);
536 filp->private_data = &ctx->fh;
537 v4l2_fh_add(&ctx->fh);
538
539 hantro_reset_fmts(ctx);
540
541 ret = hantro_ctrls_setup(vpu, ctx, allowed_codecs);
542 if (ret) {
543 vpu_err("Failed to set up controls\n");
544 goto err_fh_free;
545 }
546 ctx->fh.ctrl_handler = &ctx->ctrl_handler;
547
548 return 0;
549
550err_fh_free:
551 v4l2_fh_del(&ctx->fh);
552 v4l2_fh_exit(&ctx->fh);
553err_ctx_free:
554 kfree(ctx);
555 return ret;
556}
557
558static int hantro_release(struct file *filp)
559{
560 struct hantro_ctx *ctx =
561 container_of(filp->private_data, struct hantro_ctx, fh);
562
563
564
565
566
567 v4l2_m2m_ctx_release(ctx->fh.m2m_ctx);
568 v4l2_fh_del(&ctx->fh);
569 v4l2_fh_exit(&ctx->fh);
570 v4l2_ctrl_handler_free(&ctx->ctrl_handler);
571 kfree(ctx);
572
573 return 0;
574}
575
576static const struct v4l2_file_operations hantro_fops = {
577 .owner = THIS_MODULE,
578 .open = hantro_open,
579 .release = hantro_release,
580 .poll = v4l2_m2m_fop_poll,
581 .unlocked_ioctl = video_ioctl2,
582 .mmap = v4l2_m2m_fop_mmap,
583};
584
585static const struct of_device_id of_hantro_match[] = {
586#ifdef CONFIG_VIDEO_HANTRO_ROCKCHIP
587 { .compatible = "rockchip,px30-vpu", .data = &px30_vpu_variant, },
588 { .compatible = "rockchip,rk3036-vpu", .data = &rk3036_vpu_variant, },
589 { .compatible = "rockchip,rk3066-vpu", .data = &rk3066_vpu_variant, },
590 { .compatible = "rockchip,rk3288-vpu", .data = &rk3288_vpu_variant, },
591 { .compatible = "rockchip,rk3328-vpu", .data = &rk3328_vpu_variant, },
592 { .compatible = "rockchip,rk3399-vpu", .data = &rk3399_vpu_variant, },
593#endif
594#ifdef CONFIG_VIDEO_HANTRO_IMX8M
595 { .compatible = "nxp,imx8mq-vpu", .data = &imx8mq_vpu_variant, },
596 { .compatible = "nxp,imx8mq-vpu-g2", .data = &imx8mq_vpu_g2_variant },
597#endif
598#ifdef CONFIG_VIDEO_HANTRO_SAMA5D4
599 { .compatible = "microchip,sama5d4-vdec", .data = &sama5d4_vdec_variant, },
600#endif
601 { }
602};
603MODULE_DEVICE_TABLE(of, of_hantro_match);
604
605static int hantro_register_entity(struct media_device *mdev,
606 struct media_entity *entity,
607 const char *entity_name,
608 struct media_pad *pads, int num_pads,
609 int function, struct video_device *vdev)
610{
611 char *name;
612 int ret;
613
614 entity->obj_type = MEDIA_ENTITY_TYPE_BASE;
615 if (function == MEDIA_ENT_F_IO_V4L) {
616 entity->info.dev.major = VIDEO_MAJOR;
617 entity->info.dev.minor = vdev->minor;
618 }
619
620 name = devm_kasprintf(mdev->dev, GFP_KERNEL, "%s-%s", vdev->name,
621 entity_name);
622 if (!name)
623 return -ENOMEM;
624
625 entity->name = name;
626 entity->function = function;
627
628 ret = media_entity_pads_init(entity, num_pads, pads);
629 if (ret)
630 return ret;
631
632 ret = media_device_register_entity(mdev, entity);
633 if (ret)
634 return ret;
635
636 return 0;
637}
638
639static int hantro_attach_func(struct hantro_dev *vpu,
640 struct hantro_func *func)
641{
642 struct media_device *mdev = &vpu->mdev;
643 struct media_link *link;
644 int ret;
645
646
647 func->source_pad.flags = MEDIA_PAD_FL_SOURCE;
648 ret = hantro_register_entity(mdev, &func->vdev.entity, "source",
649 &func->source_pad, 1, MEDIA_ENT_F_IO_V4L,
650 &func->vdev);
651 if (ret)
652 return ret;
653
654 func->proc_pads[0].flags = MEDIA_PAD_FL_SINK;
655 func->proc_pads[1].flags = MEDIA_PAD_FL_SOURCE;
656 ret = hantro_register_entity(mdev, &func->proc, "proc",
657 func->proc_pads, 2, func->id,
658 &func->vdev);
659 if (ret)
660 goto err_rel_entity0;
661
662 func->sink_pad.flags = MEDIA_PAD_FL_SINK;
663 ret = hantro_register_entity(mdev, &func->sink, "sink",
664 &func->sink_pad, 1, MEDIA_ENT_F_IO_V4L,
665 &func->vdev);
666 if (ret)
667 goto err_rel_entity1;
668
669
670 ret = media_create_pad_link(&func->vdev.entity, 0, &func->proc, 0,
671 MEDIA_LNK_FL_IMMUTABLE |
672 MEDIA_LNK_FL_ENABLED);
673 if (ret)
674 goto err_rel_entity2;
675
676 ret = media_create_pad_link(&func->proc, 1, &func->sink, 0,
677 MEDIA_LNK_FL_IMMUTABLE |
678 MEDIA_LNK_FL_ENABLED);
679 if (ret)
680 goto err_rm_links0;
681
682
683 func->intf_devnode = media_devnode_create(mdev, MEDIA_INTF_T_V4L_VIDEO,
684 0, VIDEO_MAJOR,
685 func->vdev.minor);
686 if (!func->intf_devnode) {
687 ret = -ENOMEM;
688 goto err_rm_links1;
689 }
690
691
692 link = media_create_intf_link(&func->vdev.entity,
693 &func->intf_devnode->intf,
694 MEDIA_LNK_FL_IMMUTABLE |
695 MEDIA_LNK_FL_ENABLED);
696 if (!link) {
697 ret = -ENOMEM;
698 goto err_rm_devnode;
699 }
700
701 link = media_create_intf_link(&func->sink, &func->intf_devnode->intf,
702 MEDIA_LNK_FL_IMMUTABLE |
703 MEDIA_LNK_FL_ENABLED);
704 if (!link) {
705 ret = -ENOMEM;
706 goto err_rm_devnode;
707 }
708 return 0;
709
710err_rm_devnode:
711 media_devnode_remove(func->intf_devnode);
712
713err_rm_links1:
714 media_entity_remove_links(&func->sink);
715
716err_rm_links0:
717 media_entity_remove_links(&func->proc);
718 media_entity_remove_links(&func->vdev.entity);
719
720err_rel_entity2:
721 media_device_unregister_entity(&func->sink);
722
723err_rel_entity1:
724 media_device_unregister_entity(&func->proc);
725
726err_rel_entity0:
727 media_device_unregister_entity(&func->vdev.entity);
728 return ret;
729}
730
731static void hantro_detach_func(struct hantro_func *func)
732{
733 media_devnode_remove(func->intf_devnode);
734 media_entity_remove_links(&func->sink);
735 media_entity_remove_links(&func->proc);
736 media_entity_remove_links(&func->vdev.entity);
737 media_device_unregister_entity(&func->sink);
738 media_device_unregister_entity(&func->proc);
739 media_device_unregister_entity(&func->vdev.entity);
740}
741
742static int hantro_add_func(struct hantro_dev *vpu, unsigned int funcid)
743{
744 const struct of_device_id *match;
745 struct hantro_func *func;
746 struct video_device *vfd;
747 int ret;
748
749 match = of_match_node(of_hantro_match, vpu->dev->of_node);
750 func = devm_kzalloc(vpu->dev, sizeof(*func), GFP_KERNEL);
751 if (!func) {
752 v4l2_err(&vpu->v4l2_dev, "Failed to allocate video device\n");
753 return -ENOMEM;
754 }
755
756 func->id = funcid;
757
758 vfd = &func->vdev;
759 vfd->fops = &hantro_fops;
760 vfd->release = video_device_release_empty;
761 vfd->lock = &vpu->vpu_mutex;
762 vfd->v4l2_dev = &vpu->v4l2_dev;
763 vfd->vfl_dir = VFL_DIR_M2M;
764 vfd->device_caps = V4L2_CAP_STREAMING | V4L2_CAP_VIDEO_M2M_MPLANE;
765 vfd->ioctl_ops = &hantro_ioctl_ops;
766 snprintf(vfd->name, sizeof(vfd->name), "%s-%s", match->compatible,
767 funcid == MEDIA_ENT_F_PROC_VIDEO_ENCODER ? "enc" : "dec");
768
769 if (funcid == MEDIA_ENT_F_PROC_VIDEO_ENCODER)
770 vpu->encoder = func;
771 else
772 vpu->decoder = func;
773
774 video_set_drvdata(vfd, vpu);
775
776 ret = video_register_device(vfd, VFL_TYPE_VIDEO, -1);
777 if (ret) {
778 v4l2_err(&vpu->v4l2_dev, "Failed to register video device\n");
779 return ret;
780 }
781
782 ret = hantro_attach_func(vpu, func);
783 if (ret) {
784 v4l2_err(&vpu->v4l2_dev,
785 "Failed to attach functionality to the media device\n");
786 goto err_unreg_dev;
787 }
788
789 v4l2_info(&vpu->v4l2_dev, "registered %s as /dev/video%d\n", vfd->name,
790 vfd->num);
791
792 return 0;
793
794err_unreg_dev:
795 video_unregister_device(vfd);
796 return ret;
797}
798
799static int hantro_add_enc_func(struct hantro_dev *vpu)
800{
801 if (!vpu->variant->enc_fmts)
802 return 0;
803
804 return hantro_add_func(vpu, MEDIA_ENT_F_PROC_VIDEO_ENCODER);
805}
806
807static int hantro_add_dec_func(struct hantro_dev *vpu)
808{
809 if (!vpu->variant->dec_fmts)
810 return 0;
811
812 return hantro_add_func(vpu, MEDIA_ENT_F_PROC_VIDEO_DECODER);
813}
814
815static void hantro_remove_func(struct hantro_dev *vpu,
816 unsigned int funcid)
817{
818 struct hantro_func *func;
819
820 if (funcid == MEDIA_ENT_F_PROC_VIDEO_ENCODER)
821 func = vpu->encoder;
822 else
823 func = vpu->decoder;
824
825 if (!func)
826 return;
827
828 hantro_detach_func(func);
829 video_unregister_device(&func->vdev);
830}
831
832static void hantro_remove_enc_func(struct hantro_dev *vpu)
833{
834 hantro_remove_func(vpu, MEDIA_ENT_F_PROC_VIDEO_ENCODER);
835}
836
837static void hantro_remove_dec_func(struct hantro_dev *vpu)
838{
839 hantro_remove_func(vpu, MEDIA_ENT_F_PROC_VIDEO_DECODER);
840}
841
842static const struct media_device_ops hantro_m2m_media_ops = {
843 .req_validate = vb2_request_validate,
844 .req_queue = v4l2_m2m_request_queue,
845};
846
847static int hantro_probe(struct platform_device *pdev)
848{
849 const struct of_device_id *match;
850 struct hantro_dev *vpu;
851 struct resource *res;
852 int num_bases;
853 int i, ret;
854
855 vpu = devm_kzalloc(&pdev->dev, sizeof(*vpu), GFP_KERNEL);
856 if (!vpu)
857 return -ENOMEM;
858
859 vpu->dev = &pdev->dev;
860 vpu->pdev = pdev;
861 mutex_init(&vpu->vpu_mutex);
862 spin_lock_init(&vpu->irqlock);
863
864 match = of_match_node(of_hantro_match, pdev->dev.of_node);
865 vpu->variant = match->data;
866
867 INIT_DELAYED_WORK(&vpu->watchdog_work, hantro_watchdog);
868
869 vpu->clocks = devm_kcalloc(&pdev->dev, vpu->variant->num_clocks,
870 sizeof(*vpu->clocks), GFP_KERNEL);
871 if (!vpu->clocks)
872 return -ENOMEM;
873
874 if (vpu->variant->num_clocks > 1) {
875 for (i = 0; i < vpu->variant->num_clocks; i++)
876 vpu->clocks[i].id = vpu->variant->clk_names[i];
877
878 ret = devm_clk_bulk_get(&pdev->dev, vpu->variant->num_clocks,
879 vpu->clocks);
880 if (ret)
881 return ret;
882 } else {
883
884
885
886
887 vpu->clocks[0].clk = devm_clk_get(&pdev->dev, NULL);
888 if (IS_ERR(vpu->clocks[0].clk))
889 return PTR_ERR(vpu->clocks[0].clk);
890 }
891
892 num_bases = vpu->variant->num_regs ?: 1;
893 vpu->reg_bases = devm_kcalloc(&pdev->dev, num_bases,
894 sizeof(*vpu->reg_bases), GFP_KERNEL);
895 if (!vpu->reg_bases)
896 return -ENOMEM;
897
898 for (i = 0; i < num_bases; i++) {
899 res = vpu->variant->reg_names ?
900 platform_get_resource_byname(vpu->pdev, IORESOURCE_MEM,
901 vpu->variant->reg_names[i]) :
902 platform_get_resource(vpu->pdev, IORESOURCE_MEM, 0);
903 vpu->reg_bases[i] = devm_ioremap_resource(vpu->dev, res);
904 if (IS_ERR(vpu->reg_bases[i]))
905 return PTR_ERR(vpu->reg_bases[i]);
906 }
907 vpu->enc_base = vpu->reg_bases[0] + vpu->variant->enc_offset;
908 vpu->dec_base = vpu->reg_bases[0] + vpu->variant->dec_offset;
909
910 ret = dma_set_coherent_mask(vpu->dev, DMA_BIT_MASK(32));
911 if (ret) {
912 dev_err(vpu->dev, "Could not set DMA coherent mask.\n");
913 return ret;
914 }
915 vb2_dma_contig_set_max_seg_size(&pdev->dev, DMA_BIT_MASK(32));
916
917 for (i = 0; i < vpu->variant->num_irqs; i++) {
918 const char *irq_name;
919 int irq;
920
921 if (!vpu->variant->irqs[i].handler)
922 continue;
923
924 if (vpu->variant->num_irqs > 1) {
925 irq_name = vpu->variant->irqs[i].name;
926 irq = platform_get_irq_byname(vpu->pdev, irq_name);
927 } else {
928
929
930
931
932 irq_name = "default";
933 irq = platform_get_irq(vpu->pdev, 0);
934 }
935 if (irq <= 0)
936 return -ENXIO;
937
938 ret = devm_request_irq(vpu->dev, irq,
939 vpu->variant->irqs[i].handler, 0,
940 dev_name(vpu->dev), vpu);
941 if (ret) {
942 dev_err(vpu->dev, "Could not request %s IRQ.\n",
943 irq_name);
944 return ret;
945 }
946 }
947
948 if (vpu->variant->init) {
949 ret = vpu->variant->init(vpu);
950 if (ret) {
951 dev_err(&pdev->dev, "Failed to init VPU hardware\n");
952 return ret;
953 }
954 }
955
956 pm_runtime_set_autosuspend_delay(vpu->dev, 100);
957 pm_runtime_use_autosuspend(vpu->dev);
958 pm_runtime_enable(vpu->dev);
959
960 ret = clk_bulk_prepare(vpu->variant->num_clocks, vpu->clocks);
961 if (ret) {
962 dev_err(&pdev->dev, "Failed to prepare clocks\n");
963 return ret;
964 }
965
966 ret = v4l2_device_register(&pdev->dev, &vpu->v4l2_dev);
967 if (ret) {
968 dev_err(&pdev->dev, "Failed to register v4l2 device\n");
969 goto err_clk_unprepare;
970 }
971 platform_set_drvdata(pdev, vpu);
972
973 vpu->m2m_dev = v4l2_m2m_init(&vpu_m2m_ops);
974 if (IS_ERR(vpu->m2m_dev)) {
975 v4l2_err(&vpu->v4l2_dev, "Failed to init mem2mem device\n");
976 ret = PTR_ERR(vpu->m2m_dev);
977 goto err_v4l2_unreg;
978 }
979
980 vpu->mdev.dev = vpu->dev;
981 strscpy(vpu->mdev.model, DRIVER_NAME, sizeof(vpu->mdev.model));
982 strscpy(vpu->mdev.bus_info, "platform: " DRIVER_NAME,
983 sizeof(vpu->mdev.bus_info));
984 media_device_init(&vpu->mdev);
985 vpu->mdev.ops = &hantro_m2m_media_ops;
986 vpu->v4l2_dev.mdev = &vpu->mdev;
987
988 ret = hantro_add_enc_func(vpu);
989 if (ret) {
990 dev_err(&pdev->dev, "Failed to register encoder\n");
991 goto err_m2m_rel;
992 }
993
994 ret = hantro_add_dec_func(vpu);
995 if (ret) {
996 dev_err(&pdev->dev, "Failed to register decoder\n");
997 goto err_rm_enc_func;
998 }
999
1000 ret = media_device_register(&vpu->mdev);
1001 if (ret) {
1002 v4l2_err(&vpu->v4l2_dev, "Failed to register mem2mem media device\n");
1003 goto err_rm_dec_func;
1004 }
1005
1006 return 0;
1007
1008err_rm_dec_func:
1009 hantro_remove_dec_func(vpu);
1010err_rm_enc_func:
1011 hantro_remove_enc_func(vpu);
1012err_m2m_rel:
1013 media_device_cleanup(&vpu->mdev);
1014 v4l2_m2m_release(vpu->m2m_dev);
1015err_v4l2_unreg:
1016 v4l2_device_unregister(&vpu->v4l2_dev);
1017err_clk_unprepare:
1018 clk_bulk_unprepare(vpu->variant->num_clocks, vpu->clocks);
1019 pm_runtime_dont_use_autosuspend(vpu->dev);
1020 pm_runtime_disable(vpu->dev);
1021 return ret;
1022}
1023
1024static int hantro_remove(struct platform_device *pdev)
1025{
1026 struct hantro_dev *vpu = platform_get_drvdata(pdev);
1027
1028 v4l2_info(&vpu->v4l2_dev, "Removing %s\n", pdev->name);
1029
1030 media_device_unregister(&vpu->mdev);
1031 hantro_remove_dec_func(vpu);
1032 hantro_remove_enc_func(vpu);
1033 media_device_cleanup(&vpu->mdev);
1034 v4l2_m2m_release(vpu->m2m_dev);
1035 v4l2_device_unregister(&vpu->v4l2_dev);
1036 clk_bulk_unprepare(vpu->variant->num_clocks, vpu->clocks);
1037 pm_runtime_dont_use_autosuspend(vpu->dev);
1038 pm_runtime_disable(vpu->dev);
1039 return 0;
1040}
1041
1042#ifdef CONFIG_PM
1043static int hantro_runtime_resume(struct device *dev)
1044{
1045 struct hantro_dev *vpu = dev_get_drvdata(dev);
1046
1047 if (vpu->variant->runtime_resume)
1048 return vpu->variant->runtime_resume(vpu);
1049
1050 return 0;
1051}
1052#endif
1053
1054static const struct dev_pm_ops hantro_pm_ops = {
1055 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1056 pm_runtime_force_resume)
1057 SET_RUNTIME_PM_OPS(NULL, hantro_runtime_resume, NULL)
1058};
1059
1060static struct platform_driver hantro_driver = {
1061 .probe = hantro_probe,
1062 .remove = hantro_remove,
1063 .driver = {
1064 .name = DRIVER_NAME,
1065 .of_match_table = of_match_ptr(of_hantro_match),
1066 .pm = &hantro_pm_ops,
1067 },
1068};
1069module_platform_driver(hantro_driver);
1070
1071MODULE_LICENSE("GPL v2");
1072MODULE_AUTHOR("Alpha Lin <Alpha.Lin@Rock-Chips.com>");
1073MODULE_AUTHOR("Tomasz Figa <tfiga@chromium.org>");
1074MODULE_AUTHOR("Ezequiel Garcia <ezequiel@collabora.com>");
1075MODULE_DESCRIPTION("Hantro VPU codec driver");
1076
