1
2
3
4#include <linux/clk.h>
5#include <linux/console.h>
6#include <linux/io.h>
7#include <linux/iopoll.h>
8#include <linux/irq.h>
9#include <linux/module.h>
10#include <linux/of.h>
11#include <linux/of_device.h>
12#include <linux/pm_opp.h>
13#include <linux/platform_device.h>
14#include <linux/pm_runtime.h>
15#include <linux/pm_wakeirq.h>
16#include <linux/qcom-geni-se.h>
17#include <linux/serial.h>
18#include <linux/serial_core.h>
19#include <linux/slab.h>
20#include <linux/tty.h>
21#include <linux/tty_flip.h>
22
23
24#define SE_UART_LOOPBACK_CFG 0x22c
25#define SE_UART_IO_MACRO_CTRL 0x240
26#define SE_UART_TX_TRANS_CFG 0x25c
27#define SE_UART_TX_WORD_LEN 0x268
28#define SE_UART_TX_STOP_BIT_LEN 0x26c
29#define SE_UART_TX_TRANS_LEN 0x270
30#define SE_UART_RX_TRANS_CFG 0x280
31#define SE_UART_RX_WORD_LEN 0x28c
32#define SE_UART_RX_STALE_CNT 0x294
33#define SE_UART_TX_PARITY_CFG 0x2a4
34#define SE_UART_RX_PARITY_CFG 0x2a8
35#define SE_UART_MANUAL_RFR 0x2ac
36
37
38#define UART_TX_PAR_EN BIT(0)
39#define UART_CTS_MASK BIT(1)
40
41
42#define TX_WORD_LEN_MSK GENMASK(9, 0)
43
44
45#define TX_STOP_BIT_LEN_MSK GENMASK(23, 0)
46#define TX_STOP_BIT_LEN_1 0
47#define TX_STOP_BIT_LEN_1_5 1
48#define TX_STOP_BIT_LEN_2 2
49
50
51#define TX_TRANS_LEN_MSK GENMASK(23, 0)
52
53
54#define UART_RX_INS_STATUS_BIT BIT(2)
55#define UART_RX_PAR_EN BIT(3)
56
57
58#define RX_WORD_LEN_MASK GENMASK(9, 0)
59
60
61#define RX_STALE_CNT GENMASK(23, 0)
62
63
64#define PAR_CALC_EN BIT(0)
65#define PAR_MODE_MSK GENMASK(2, 1)
66#define PAR_MODE_SHFT 1
67#define PAR_EVEN 0x00
68#define PAR_ODD 0x01
69#define PAR_SPACE 0x10
70#define PAR_MARK 0x11
71
72
73#define UART_MANUAL_RFR_EN BIT(31)
74#define UART_RFR_NOT_READY BIT(1)
75#define UART_RFR_READY BIT(0)
76
77
78#define UART_START_TX 0x1
79#define UART_START_BREAK 0x4
80#define UART_STOP_BREAK 0x5
81
82#define UART_START_READ 0x1
83#define UART_PARAM 0x1
84
85#define UART_OVERSAMPLING 32
86#define STALE_TIMEOUT 16
87#define DEFAULT_BITS_PER_CHAR 10
88#define GENI_UART_CONS_PORTS 1
89#define GENI_UART_PORTS 3
90#define DEF_FIFO_DEPTH_WORDS 16
91#define DEF_TX_WM 2
92#define DEF_FIFO_WIDTH_BITS 32
93#define UART_RX_WM 2
94
95
96#define RX_TX_SORTED BIT(0)
97#define CTS_RTS_SORTED BIT(1)
98#define RX_TX_CTS_RTS_SORTED (RX_TX_SORTED | CTS_RTS_SORTED)
99
100
101#define DEFAULT_IO_MACRO_IO0_IO1_MASK GENMASK(3, 0)
102#define IO_MACRO_IO0_SEL 0x3
103#define DEFAULT_IO_MACRO_IO2_IO3_MASK GENMASK(15, 4)
104#define IO_MACRO_IO2_IO3_SWAP 0x4640
105
106
107#define BYTES_PER_FIFO_WORD 4
108
109struct qcom_geni_private_data {
110
111 struct uart_driver *drv;
112
113 u32 poll_cached_bytes;
114 unsigned int poll_cached_bytes_cnt;
115
116 u32 write_cached_bytes;
117 unsigned int write_cached_bytes_cnt;
118};
119
120struct qcom_geni_serial_port {
121 struct uart_port uport;
122 struct geni_se se;
123 const char *name;
124 u32 tx_fifo_depth;
125 u32 tx_fifo_width;
126 u32 rx_fifo_depth;
127 bool setup;
128 int (*handle_rx)(struct uart_port *uport, u32 bytes, bool drop);
129 unsigned int baud;
130 void *rx_fifo;
131 u32 loopback;
132 bool brk;
133
134 unsigned int tx_remaining;
135 int wakeup_irq;
136 bool rx_tx_swap;
137 bool cts_rts_swap;
138
139 struct qcom_geni_private_data private_data;
140};
141
142static const struct uart_ops qcom_geni_console_pops;
143static const struct uart_ops qcom_geni_uart_pops;
144static struct uart_driver qcom_geni_console_driver;
145static struct uart_driver qcom_geni_uart_driver;
146static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop);
147static int handle_rx_uart(struct uart_port *uport, u32 bytes, bool drop);
148static unsigned int qcom_geni_serial_tx_empty(struct uart_port *port);
149static void qcom_geni_serial_stop_rx(struct uart_port *uport);
150static void qcom_geni_serial_handle_rx(struct uart_port *uport, bool drop);
151
152static const unsigned long root_freq[] = {7372800, 14745600, 19200000, 29491200,
153 32000000, 48000000, 51200000, 64000000,
154 80000000, 96000000, 100000000,
155 102400000, 112000000, 120000000,
156 128000000};
157
158#define to_dev_port(ptr, member) \
159 container_of(ptr, struct qcom_geni_serial_port, member)
160
161static struct qcom_geni_serial_port qcom_geni_uart_ports[GENI_UART_PORTS] = {
162 [0] = {
163 .uport = {
164 .iotype = UPIO_MEM,
165 .ops = &qcom_geni_uart_pops,
166 .flags = UPF_BOOT_AUTOCONF,
167 .line = 0,
168 },
169 },
170 [1] = {
171 .uport = {
172 .iotype = UPIO_MEM,
173 .ops = &qcom_geni_uart_pops,
174 .flags = UPF_BOOT_AUTOCONF,
175 .line = 1,
176 },
177 },
178 [2] = {
179 .uport = {
180 .iotype = UPIO_MEM,
181 .ops = &qcom_geni_uart_pops,
182 .flags = UPF_BOOT_AUTOCONF,
183 .line = 2,
184 },
185 },
186};
187
188static struct qcom_geni_serial_port qcom_geni_console_port = {
189 .uport = {
190 .iotype = UPIO_MEM,
191 .ops = &qcom_geni_console_pops,
192 .flags = UPF_BOOT_AUTOCONF,
193 .line = 0,
194 },
195};
196
197static int qcom_geni_serial_request_port(struct uart_port *uport)
198{
199 struct platform_device *pdev = to_platform_device(uport->dev);
200 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
201
202 uport->membase = devm_platform_ioremap_resource(pdev, 0);
203 if (IS_ERR(uport->membase))
204 return PTR_ERR(uport->membase);
205 port->se.base = uport->membase;
206 return 0;
207}
208
209static void qcom_geni_serial_config_port(struct uart_port *uport, int cfg_flags)
210{
211 if (cfg_flags & UART_CONFIG_TYPE) {
212 uport->type = PORT_MSM;
213 qcom_geni_serial_request_port(uport);
214 }
215}
216
217static unsigned int qcom_geni_serial_get_mctrl(struct uart_port *uport)
218{
219 unsigned int mctrl = TIOCM_DSR | TIOCM_CAR;
220 u32 geni_ios;
221
222 if (uart_console(uport)) {
223 mctrl |= TIOCM_CTS;
224 } else {
225 geni_ios = readl(uport->membase + SE_GENI_IOS);
226 if (!(geni_ios & IO2_DATA_IN))
227 mctrl |= TIOCM_CTS;
228 }
229
230 return mctrl;
231}
232
233static void qcom_geni_serial_set_mctrl(struct uart_port *uport,
234 unsigned int mctrl)
235{
236 u32 uart_manual_rfr = 0;
237 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
238
239 if (uart_console(uport))
240 return;
241
242 if (mctrl & TIOCM_LOOP)
243 port->loopback = RX_TX_CTS_RTS_SORTED;
244
245 if (!(mctrl & TIOCM_RTS) && !uport->suspended)
246 uart_manual_rfr = UART_MANUAL_RFR_EN | UART_RFR_NOT_READY;
247 writel(uart_manual_rfr, uport->membase + SE_UART_MANUAL_RFR);
248}
249
250static const char *qcom_geni_serial_get_type(struct uart_port *uport)
251{
252 return "MSM";
253}
254
255static struct qcom_geni_serial_port *get_port_from_line(int line, bool console)
256{
257 struct qcom_geni_serial_port *port;
258 int nr_ports = console ? GENI_UART_CONS_PORTS : GENI_UART_PORTS;
259
260 if (line < 0 || line >= nr_ports)
261 return ERR_PTR(-ENXIO);
262
263 port = console ? &qcom_geni_console_port : &qcom_geni_uart_ports[line];
264 return port;
265}
266
267static bool qcom_geni_serial_poll_bit(struct uart_port *uport,
268 int offset, int field, bool set)
269{
270 u32 reg;
271 struct qcom_geni_serial_port *port;
272 unsigned int baud;
273 unsigned int fifo_bits;
274 unsigned long timeout_us = 20000;
275 struct qcom_geni_private_data *private_data = uport->private_data;
276
277 if (private_data->drv) {
278 port = to_dev_port(uport, uport);
279 baud = port->baud;
280 if (!baud)
281 baud = 115200;
282 fifo_bits = port->tx_fifo_depth * port->tx_fifo_width;
283
284
285
286
287 timeout_us = ((fifo_bits * USEC_PER_SEC) / baud) + 500;
288 }
289
290
291
292
293
294 timeout_us = DIV_ROUND_UP(timeout_us, 10) * 10;
295 while (timeout_us) {
296 reg = readl(uport->membase + offset);
297 if ((bool)(reg & field) == set)
298 return true;
299 udelay(10);
300 timeout_us -= 10;
301 }
302 return false;
303}
304
305static void qcom_geni_serial_setup_tx(struct uart_port *uport, u32 xmit_size)
306{
307 u32 m_cmd;
308
309 writel(xmit_size, uport->membase + SE_UART_TX_TRANS_LEN);
310 m_cmd = UART_START_TX << M_OPCODE_SHFT;
311 writel(m_cmd, uport->membase + SE_GENI_M_CMD0);
312}
313
314static void qcom_geni_serial_poll_tx_done(struct uart_port *uport)
315{
316 int done;
317 u32 irq_clear = M_CMD_DONE_EN;
318
319 done = qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
320 M_CMD_DONE_EN, true);
321 if (!done) {
322 writel(M_GENI_CMD_ABORT, uport->membase +
323 SE_GENI_M_CMD_CTRL_REG);
324 irq_clear |= M_CMD_ABORT_EN;
325 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
326 M_CMD_ABORT_EN, true);
327 }
328 writel(irq_clear, uport->membase + SE_GENI_M_IRQ_CLEAR);
329}
330
331static void qcom_geni_serial_abort_rx(struct uart_port *uport)
332{
333 u32 irq_clear = S_CMD_DONE_EN | S_CMD_ABORT_EN;
334
335 writel(S_GENI_CMD_ABORT, uport->membase + SE_GENI_S_CMD_CTRL_REG);
336 qcom_geni_serial_poll_bit(uport, SE_GENI_S_CMD_CTRL_REG,
337 S_GENI_CMD_ABORT, false);
338 writel(irq_clear, uport->membase + SE_GENI_S_IRQ_CLEAR);
339 writel(FORCE_DEFAULT, uport->membase + GENI_FORCE_DEFAULT_REG);
340}
341
342#ifdef CONFIG_CONSOLE_POLL
343
344static int qcom_geni_serial_get_char(struct uart_port *uport)
345{
346 struct qcom_geni_private_data *private_data = uport->private_data;
347 u32 status;
348 u32 word_cnt;
349 int ret;
350
351 if (!private_data->poll_cached_bytes_cnt) {
352 status = readl(uport->membase + SE_GENI_M_IRQ_STATUS);
353 writel(status, uport->membase + SE_GENI_M_IRQ_CLEAR);
354
355 status = readl(uport->membase + SE_GENI_S_IRQ_STATUS);
356 writel(status, uport->membase + SE_GENI_S_IRQ_CLEAR);
357
358 status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS);
359 word_cnt = status & RX_FIFO_WC_MSK;
360 if (!word_cnt)
361 return NO_POLL_CHAR;
362
363 if (word_cnt == 1 && (status & RX_LAST))
364
365
366
367
368 private_data->poll_cached_bytes_cnt =
369 (status & RX_LAST_BYTE_VALID_MSK) >>
370 RX_LAST_BYTE_VALID_SHFT;
371
372 if (private_data->poll_cached_bytes_cnt == 0)
373 private_data->poll_cached_bytes_cnt = BYTES_PER_FIFO_WORD;
374
375 private_data->poll_cached_bytes =
376 readl(uport->membase + SE_GENI_RX_FIFOn);
377 }
378
379 private_data->poll_cached_bytes_cnt--;
380 ret = private_data->poll_cached_bytes & 0xff;
381 private_data->poll_cached_bytes >>= 8;
382
383 return ret;
384}
385
386static void qcom_geni_serial_poll_put_char(struct uart_port *uport,
387 unsigned char c)
388{
389 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
390 qcom_geni_serial_setup_tx(uport, 1);
391 WARN_ON(!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
392 M_TX_FIFO_WATERMARK_EN, true));
393 writel(c, uport->membase + SE_GENI_TX_FIFOn);
394 writel(M_TX_FIFO_WATERMARK_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
395 qcom_geni_serial_poll_tx_done(uport);
396}
397#endif
398
399#ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE
400static void qcom_geni_serial_wr_char(struct uart_port *uport, int ch)
401{
402 struct qcom_geni_private_data *private_data = uport->private_data;
403
404 private_data->write_cached_bytes =
405 (private_data->write_cached_bytes >> 8) | (ch << 24);
406 private_data->write_cached_bytes_cnt++;
407
408 if (private_data->write_cached_bytes_cnt == BYTES_PER_FIFO_WORD) {
409 writel(private_data->write_cached_bytes,
410 uport->membase + SE_GENI_TX_FIFOn);
411 private_data->write_cached_bytes_cnt = 0;
412 }
413}
414
415static void
416__qcom_geni_serial_console_write(struct uart_port *uport, const char *s,
417 unsigned int count)
418{
419 struct qcom_geni_private_data *private_data = uport->private_data;
420
421 int i;
422 u32 bytes_to_send = count;
423
424 for (i = 0; i < count; i++) {
425
426
427
428
429 if (s[i] == '\n')
430 bytes_to_send++;
431 }
432
433 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
434 qcom_geni_serial_setup_tx(uport, bytes_to_send);
435 for (i = 0; i < count; ) {
436 size_t chars_to_write = 0;
437 size_t avail = DEF_FIFO_DEPTH_WORDS - DEF_TX_WM;
438
439
440
441
442
443
444
445 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
446 M_TX_FIFO_WATERMARK_EN, true))
447 break;
448 chars_to_write = min_t(size_t, count - i, avail / 2);
449 uart_console_write(uport, s + i, chars_to_write,
450 qcom_geni_serial_wr_char);
451 writel(M_TX_FIFO_WATERMARK_EN, uport->membase +
452 SE_GENI_M_IRQ_CLEAR);
453 i += chars_to_write;
454 }
455
456 if (private_data->write_cached_bytes_cnt) {
457 private_data->write_cached_bytes >>= BITS_PER_BYTE *
458 (BYTES_PER_FIFO_WORD - private_data->write_cached_bytes_cnt);
459 writel(private_data->write_cached_bytes,
460 uport->membase + SE_GENI_TX_FIFOn);
461 private_data->write_cached_bytes_cnt = 0;
462 }
463
464 qcom_geni_serial_poll_tx_done(uport);
465}
466
467static void qcom_geni_serial_console_write(struct console *co, const char *s,
468 unsigned int count)
469{
470 struct uart_port *uport;
471 struct qcom_geni_serial_port *port;
472 bool locked = true;
473 unsigned long flags;
474 u32 geni_status;
475 u32 irq_en;
476
477 WARN_ON(co->index < 0 || co->index >= GENI_UART_CONS_PORTS);
478
479 port = get_port_from_line(co->index, true);
480 if (IS_ERR(port))
481 return;
482
483 uport = &port->uport;
484 if (oops_in_progress)
485 locked = spin_trylock_irqsave(&uport->lock, flags);
486 else
487 spin_lock_irqsave(&uport->lock, flags);
488
489 geni_status = readl(uport->membase + SE_GENI_STATUS);
490
491
492 if (!locked) {
493 geni_se_cancel_m_cmd(&port->se);
494 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
495 M_CMD_CANCEL_EN, true)) {
496 geni_se_abort_m_cmd(&port->se);
497 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
498 M_CMD_ABORT_EN, true);
499 writel(M_CMD_ABORT_EN, uport->membase +
500 SE_GENI_M_IRQ_CLEAR);
501 }
502 writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
503 } else if ((geni_status & M_GENI_CMD_ACTIVE) && !port->tx_remaining) {
504
505
506
507
508 qcom_geni_serial_poll_tx_done(uport);
509
510 if (uart_circ_chars_pending(&uport->state->xmit)) {
511 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
512 writel(irq_en | M_TX_FIFO_WATERMARK_EN,
513 uport->membase + SE_GENI_M_IRQ_EN);
514 }
515 }
516
517 __qcom_geni_serial_console_write(uport, s, count);
518
519 if (port->tx_remaining)
520 qcom_geni_serial_setup_tx(uport, port->tx_remaining);
521
522 if (locked)
523 spin_unlock_irqrestore(&uport->lock, flags);
524}
525
526static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop)
527{
528 u32 i;
529 unsigned char buf[sizeof(u32)];
530 struct tty_port *tport;
531 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
532
533 tport = &uport->state->port;
534 for (i = 0; i < bytes; ) {
535 int c;
536 int chunk = min_t(int, bytes - i, BYTES_PER_FIFO_WORD);
537
538 ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, buf, 1);
539 i += chunk;
540 if (drop)
541 continue;
542
543 for (c = 0; c < chunk; c++) {
544 int sysrq;
545
546 uport->icount.rx++;
547 if (port->brk && buf[c] == 0) {
548 port->brk = false;
549 if (uart_handle_break(uport))
550 continue;
551 }
552
553 sysrq = uart_prepare_sysrq_char(uport, buf[c]);
554
555 if (!sysrq)
556 tty_insert_flip_char(tport, buf[c], TTY_NORMAL);
557 }
558 }
559 if (!drop)
560 tty_flip_buffer_push(tport);
561 return 0;
562}
563#else
564static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop)
565{
566 return -EPERM;
567}
568
569#endif
570
571static int handle_rx_uart(struct uart_port *uport, u32 bytes, bool drop)
572{
573 struct tty_port *tport;
574 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
575 u32 num_bytes_pw = port->tx_fifo_width / BITS_PER_BYTE;
576 u32 words = ALIGN(bytes, num_bytes_pw) / num_bytes_pw;
577 int ret;
578
579 tport = &uport->state->port;
580 ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, port->rx_fifo, words);
581 if (drop)
582 return 0;
583
584 ret = tty_insert_flip_string(tport, port->rx_fifo, bytes);
585 if (ret != bytes) {
586 dev_err(uport->dev, "%s:Unable to push data ret %d_bytes %d\n",
587 __func__, ret, bytes);
588 WARN_ON_ONCE(1);
589 }
590 uport->icount.rx += ret;
591 tty_flip_buffer_push(tport);
592 return ret;
593}
594
595static void qcom_geni_serial_start_tx(struct uart_port *uport)
596{
597 u32 irq_en;
598 u32 status;
599
600 status = readl(uport->membase + SE_GENI_STATUS);
601 if (status & M_GENI_CMD_ACTIVE)
602 return;
603
604 if (!qcom_geni_serial_tx_empty(uport))
605 return;
606
607 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
608 irq_en |= M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN;
609
610 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
611 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
612}
613
614static void qcom_geni_serial_stop_tx(struct uart_port *uport)
615{
616 u32 irq_en;
617 u32 status;
618 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
619
620 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
621 irq_en &= ~(M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN);
622 writel(0, uport->membase + SE_GENI_TX_WATERMARK_REG);
623 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
624 status = readl(uport->membase + SE_GENI_STATUS);
625
626 if (!(status & M_GENI_CMD_ACTIVE))
627 return;
628
629 geni_se_cancel_m_cmd(&port->se);
630 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
631 M_CMD_CANCEL_EN, true)) {
632 geni_se_abort_m_cmd(&port->se);
633 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
634 M_CMD_ABORT_EN, true);
635 writel(M_CMD_ABORT_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
636 }
637 writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
638}
639
640static void qcom_geni_serial_start_rx(struct uart_port *uport)
641{
642 u32 irq_en;
643 u32 status;
644 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
645
646 status = readl(uport->membase + SE_GENI_STATUS);
647 if (status & S_GENI_CMD_ACTIVE)
648 qcom_geni_serial_stop_rx(uport);
649
650 geni_se_setup_s_cmd(&port->se, UART_START_READ, 0);
651
652 irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN);
653 irq_en |= S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN;
654 writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN);
655
656 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
657 irq_en |= M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN;
658 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
659}
660
661static void qcom_geni_serial_stop_rx(struct uart_port *uport)
662{
663 u32 irq_en;
664 u32 status;
665 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
666 u32 s_irq_status;
667
668 irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN);
669 irq_en &= ~(S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN);
670 writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN);
671
672 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
673 irq_en &= ~(M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN);
674 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
675
676 status = readl(uport->membase + SE_GENI_STATUS);
677
678 if (!(status & S_GENI_CMD_ACTIVE))
679 return;
680
681 geni_se_cancel_s_cmd(&port->se);
682 qcom_geni_serial_poll_bit(uport, SE_GENI_S_IRQ_STATUS,
683 S_CMD_CANCEL_EN, true);
684
685
686
687
688 s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS);
689
690 if (s_irq_status & S_RX_FIFO_LAST_EN)
691 qcom_geni_serial_handle_rx(uport, true);
692 writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR);
693
694 status = readl(uport->membase + SE_GENI_STATUS);
695 if (status & S_GENI_CMD_ACTIVE)
696 qcom_geni_serial_abort_rx(uport);
697}
698
699static void qcom_geni_serial_handle_rx(struct uart_port *uport, bool drop)
700{
701 u32 status;
702 u32 word_cnt;
703 u32 last_word_byte_cnt;
704 u32 last_word_partial;
705 u32 total_bytes;
706 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
707
708 status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS);
709 word_cnt = status & RX_FIFO_WC_MSK;
710 last_word_partial = status & RX_LAST;
711 last_word_byte_cnt = (status & RX_LAST_BYTE_VALID_MSK) >>
712 RX_LAST_BYTE_VALID_SHFT;
713
714 if (!word_cnt)
715 return;
716 total_bytes = BYTES_PER_FIFO_WORD * (word_cnt - 1);
717 if (last_word_partial && last_word_byte_cnt)
718 total_bytes += last_word_byte_cnt;
719 else
720 total_bytes += BYTES_PER_FIFO_WORD;
721 port->handle_rx(uport, total_bytes, drop);
722}
723
724static void qcom_geni_serial_handle_tx(struct uart_port *uport, bool done,
725 bool active)
726{
727 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
728 struct circ_buf *xmit = &uport->state->xmit;
729 size_t avail;
730 size_t remaining;
731 size_t pending;
732 int i;
733 u32 status;
734 u32 irq_en;
735 unsigned int chunk;
736 int tail;
737
738 status = readl(uport->membase + SE_GENI_TX_FIFO_STATUS);
739
740
741 if (active)
742 pending = port->tx_remaining;
743 else
744 pending = uart_circ_chars_pending(xmit);
745
746
747 if (!pending && !status && done) {
748 qcom_geni_serial_stop_tx(uport);
749 goto out_write_wakeup;
750 }
751
752 avail = port->tx_fifo_depth - (status & TX_FIFO_WC);
753 avail *= BYTES_PER_FIFO_WORD;
754
755 tail = xmit->tail;
756 chunk = min(avail, pending);
757 if (!chunk)
758 goto out_write_wakeup;
759
760 if (!port->tx_remaining) {
761 qcom_geni_serial_setup_tx(uport, pending);
762 port->tx_remaining = pending;
763
764 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
765 if (!(irq_en & M_TX_FIFO_WATERMARK_EN))
766 writel(irq_en | M_TX_FIFO_WATERMARK_EN,
767 uport->membase + SE_GENI_M_IRQ_EN);
768 }
769
770 remaining = chunk;
771 for (i = 0; i < chunk; ) {
772 unsigned int tx_bytes;
773 u8 buf[sizeof(u32)];
774 int c;
775
776 memset(buf, 0, sizeof(buf));
777 tx_bytes = min_t(size_t, remaining, BYTES_PER_FIFO_WORD);
778
779 for (c = 0; c < tx_bytes ; c++) {
780 buf[c] = xmit->buf[tail++];
781 tail &= UART_XMIT_SIZE - 1;
782 }
783
784 iowrite32_rep(uport->membase + SE_GENI_TX_FIFOn, buf, 1);
785
786 i += tx_bytes;
787 uport->icount.tx += tx_bytes;
788 remaining -= tx_bytes;
789 port->tx_remaining -= tx_bytes;
790 }
791
792 xmit->tail = tail;
793
794
795
796
797
798
799 writel(M_TX_FIFO_WATERMARK_EN,
800 uport->membase + SE_GENI_M_IRQ_CLEAR);
801
802out_write_wakeup:
803 if (!port->tx_remaining) {
804 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
805 if (irq_en & M_TX_FIFO_WATERMARK_EN)
806 writel(irq_en & ~M_TX_FIFO_WATERMARK_EN,
807 uport->membase + SE_GENI_M_IRQ_EN);
808 }
809
810 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
811 uart_write_wakeup(uport);
812}
813
814static irqreturn_t qcom_geni_serial_isr(int isr, void *dev)
815{
816 u32 m_irq_en;
817 u32 m_irq_status;
818 u32 s_irq_status;
819 u32 geni_status;
820 struct uart_port *uport = dev;
821 bool drop_rx = false;
822 struct tty_port *tport = &uport->state->port;
823 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
824
825 if (uport->suspended)
826 return IRQ_NONE;
827
828 spin_lock(&uport->lock);
829
830 m_irq_status = readl(uport->membase + SE_GENI_M_IRQ_STATUS);
831 s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS);
832 geni_status = readl(uport->membase + SE_GENI_STATUS);
833 m_irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
834 writel(m_irq_status, uport->membase + SE_GENI_M_IRQ_CLEAR);
835 writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR);
836
837 if (WARN_ON(m_irq_status & M_ILLEGAL_CMD_EN))
838 goto out_unlock;
839
840 if (s_irq_status & S_RX_FIFO_WR_ERR_EN) {
841 uport->icount.overrun++;
842 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
843 }
844
845 if (m_irq_status & m_irq_en & (M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN))
846 qcom_geni_serial_handle_tx(uport, m_irq_status & M_CMD_DONE_EN,
847 geni_status & M_GENI_CMD_ACTIVE);
848
849 if (s_irq_status & S_GP_IRQ_0_EN || s_irq_status & S_GP_IRQ_1_EN) {
850 if (s_irq_status & S_GP_IRQ_0_EN)
851 uport->icount.parity++;
852 drop_rx = true;
853 } else if (s_irq_status & S_GP_IRQ_2_EN ||
854 s_irq_status & S_GP_IRQ_3_EN) {
855 uport->icount.brk++;
856 port->brk = true;
857 }
858
859 if (s_irq_status & S_RX_FIFO_WATERMARK_EN ||
860 s_irq_status & S_RX_FIFO_LAST_EN)
861 qcom_geni_serial_handle_rx(uport, drop_rx);
862
863out_unlock:
864 uart_unlock_and_check_sysrq(uport);
865
866 return IRQ_HANDLED;
867}
868
869static void get_tx_fifo_size(struct qcom_geni_serial_port *port)
870{
871 struct uart_port *uport;
872
873 uport = &port->uport;
874 port->tx_fifo_depth = geni_se_get_tx_fifo_depth(&port->se);
875 port->tx_fifo_width = geni_se_get_tx_fifo_width(&port->se);
876 port->rx_fifo_depth = geni_se_get_rx_fifo_depth(&port->se);
877 uport->fifosize =
878 (port->tx_fifo_depth * port->tx_fifo_width) / BITS_PER_BYTE;
879}
880
881
882static void qcom_geni_serial_shutdown(struct uart_port *uport)
883{
884 disable_irq(uport->irq);
885}
886
887static int qcom_geni_serial_port_setup(struct uart_port *uport)
888{
889 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
890 u32 rxstale = DEFAULT_BITS_PER_CHAR * STALE_TIMEOUT;
891 u32 proto;
892 u32 pin_swap;
893
894 proto = geni_se_read_proto(&port->se);
895 if (proto != GENI_SE_UART) {
896 dev_err(uport->dev, "Invalid FW loaded, proto: %d\n", proto);
897 return -ENXIO;
898 }
899
900 qcom_geni_serial_stop_rx(uport);
901
902 get_tx_fifo_size(port);
903
904 writel(rxstale, uport->membase + SE_UART_RX_STALE_CNT);
905
906 pin_swap = readl(uport->membase + SE_UART_IO_MACRO_CTRL);
907 if (port->rx_tx_swap) {
908 pin_swap &= ~DEFAULT_IO_MACRO_IO2_IO3_MASK;
909 pin_swap |= IO_MACRO_IO2_IO3_SWAP;
910 }
911 if (port->cts_rts_swap) {
912 pin_swap &= ~DEFAULT_IO_MACRO_IO0_IO1_MASK;
913 pin_swap |= IO_MACRO_IO0_SEL;
914 }
915
916 if (port->rx_tx_swap || port->cts_rts_swap)
917 writel(pin_swap, uport->membase + SE_UART_IO_MACRO_CTRL);
918
919
920
921
922
923 if (uart_console(uport))
924 qcom_geni_serial_poll_tx_done(uport);
925 geni_se_config_packing(&port->se, BITS_PER_BYTE, BYTES_PER_FIFO_WORD,
926 false, true, true);
927 geni_se_init(&port->se, UART_RX_WM, port->rx_fifo_depth - 2);
928 geni_se_select_mode(&port->se, GENI_SE_FIFO);
929 port->setup = true;
930
931 return 0;
932}
933
934static int qcom_geni_serial_startup(struct uart_port *uport)
935{
936 int ret;
937 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
938
939 if (!port->setup) {
940 ret = qcom_geni_serial_port_setup(uport);
941 if (ret)
942 return ret;
943 }
944 enable_irq(uport->irq);
945
946 return 0;
947}
948
949static unsigned long get_clk_cfg(unsigned long clk_freq)
950{
951 int i;
952
953 for (i = 0; i < ARRAY_SIZE(root_freq); i++) {
954 if (!(root_freq[i] % clk_freq))
955 return root_freq[i];
956 }
957 return 0;
958}
959
960static unsigned long get_clk_div_rate(unsigned int baud,
961 unsigned int sampling_rate, unsigned int *clk_div)
962{
963 unsigned long ser_clk;
964 unsigned long desired_clk;
965
966 desired_clk = baud * sampling_rate;
967 ser_clk = get_clk_cfg(desired_clk);
968 if (!ser_clk) {
969 pr_err("%s: Can't find matching DFS entry for baud %d\n",
970 __func__, baud);
971 return ser_clk;
972 }
973
974 *clk_div = ser_clk / desired_clk;
975 return ser_clk;
976}
977
978static void qcom_geni_serial_set_termios(struct uart_port *uport,
979 struct ktermios *termios, struct ktermios *old)
980{
981 unsigned int baud;
982 u32 bits_per_char;
983 u32 tx_trans_cfg;
984 u32 tx_parity_cfg;
985 u32 rx_trans_cfg;
986 u32 rx_parity_cfg;
987 u32 stop_bit_len;
988 unsigned int clk_div;
989 u32 ser_clk_cfg;
990 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
991 unsigned long clk_rate;
992 u32 ver, sampling_rate;
993 unsigned int avg_bw_core;
994
995 qcom_geni_serial_stop_rx(uport);
996
997 baud = uart_get_baud_rate(uport, termios, old, 300, 4000000);
998 port->baud = baud;
999
1000 sampling_rate = UART_OVERSAMPLING;
1001
1002 ver = geni_se_get_qup_hw_version(&port->se);
1003 if (ver >= QUP_SE_VERSION_2_5)
1004 sampling_rate /= 2;
1005
1006 clk_rate = get_clk_div_rate(baud, sampling_rate, &clk_div);
1007 if (!clk_rate)
1008 goto out_restart_rx;
1009
1010 uport->uartclk = clk_rate;
1011 dev_pm_opp_set_rate(uport->dev, clk_rate);
1012 ser_clk_cfg = SER_CLK_EN;
1013 ser_clk_cfg |= clk_div << CLK_DIV_SHFT;
1014
1015
1016
1017
1018
1019 avg_bw_core = (baud > 115200) ? Bps_to_icc(CORE_2X_50_MHZ)
1020 : GENI_DEFAULT_BW;
1021 port->se.icc_paths[GENI_TO_CORE].avg_bw = avg_bw_core;
1022 port->se.icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(baud);
1023 geni_icc_set_bw(&port->se);
1024
1025
1026 tx_trans_cfg = readl(uport->membase + SE_UART_TX_TRANS_CFG);
1027 tx_parity_cfg = readl(uport->membase + SE_UART_TX_PARITY_CFG);
1028 rx_trans_cfg = readl(uport->membase + SE_UART_RX_TRANS_CFG);
1029 rx_parity_cfg = readl(uport->membase + SE_UART_RX_PARITY_CFG);
1030 if (termios->c_cflag & PARENB) {
1031 tx_trans_cfg |= UART_TX_PAR_EN;
1032 rx_trans_cfg |= UART_RX_PAR_EN;
1033 tx_parity_cfg |= PAR_CALC_EN;
1034 rx_parity_cfg |= PAR_CALC_EN;
1035 if (termios->c_cflag & PARODD) {
1036 tx_parity_cfg |= PAR_ODD;
1037 rx_parity_cfg |= PAR_ODD;
1038 } else if (termios->c_cflag & CMSPAR) {
1039 tx_parity_cfg |= PAR_SPACE;
1040 rx_parity_cfg |= PAR_SPACE;
1041 } else {
1042 tx_parity_cfg |= PAR_EVEN;
1043 rx_parity_cfg |= PAR_EVEN;
1044 }
1045 } else {
1046 tx_trans_cfg &= ~UART_TX_PAR_EN;
1047 rx_trans_cfg &= ~UART_RX_PAR_EN;
1048 tx_parity_cfg &= ~PAR_CALC_EN;
1049 rx_parity_cfg &= ~PAR_CALC_EN;
1050 }
1051
1052
1053 bits_per_char = tty_get_char_size(termios->c_cflag);
1054
1055
1056 if (termios->c_cflag & CSTOPB)
1057 stop_bit_len = TX_STOP_BIT_LEN_2;
1058 else
1059 stop_bit_len = TX_STOP_BIT_LEN_1;
1060
1061
1062 if (termios->c_cflag & CRTSCTS)
1063 tx_trans_cfg &= ~UART_CTS_MASK;
1064 else
1065 tx_trans_cfg |= UART_CTS_MASK;
1066
1067 if (baud)
1068 uart_update_timeout(uport, termios->c_cflag, baud);
1069
1070 if (!uart_console(uport))
1071 writel(port->loopback,
1072 uport->membase + SE_UART_LOOPBACK_CFG);
1073 writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG);
1074 writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG);
1075 writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG);
1076 writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG);
1077 writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN);
1078 writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN);
1079 writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN);
1080 writel(ser_clk_cfg, uport->membase + GENI_SER_M_CLK_CFG);
1081 writel(ser_clk_cfg, uport->membase + GENI_SER_S_CLK_CFG);
1082out_restart_rx:
1083 qcom_geni_serial_start_rx(uport);
1084}
1085
1086static unsigned int qcom_geni_serial_tx_empty(struct uart_port *uport)
1087{
1088 return !readl(uport->membase + SE_GENI_TX_FIFO_STATUS);
1089}
1090
1091#ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE
1092static int qcom_geni_console_setup(struct console *co, char *options)
1093{
1094 struct uart_port *uport;
1095 struct qcom_geni_serial_port *port;
1096 int baud = 115200;
1097 int bits = 8;
1098 int parity = 'n';
1099 int flow = 'n';
1100 int ret;
1101
1102 if (co->index >= GENI_UART_CONS_PORTS || co->index < 0)
1103 return -ENXIO;
1104
1105 port = get_port_from_line(co->index, true);
1106 if (IS_ERR(port)) {
1107 pr_err("Invalid line %d\n", co->index);
1108 return PTR_ERR(port);
1109 }
1110
1111 uport = &port->uport;
1112
1113 if (unlikely(!uport->membase))
1114 return -ENXIO;
1115
1116 if (!port->setup) {
1117 ret = qcom_geni_serial_port_setup(uport);
1118 if (ret)
1119 return ret;
1120 }
1121
1122 if (options)
1123 uart_parse_options(options, &baud, &parity, &bits, &flow);
1124
1125 return uart_set_options(uport, co, baud, parity, bits, flow);
1126}
1127
1128static void qcom_geni_serial_earlycon_write(struct console *con,
1129 const char *s, unsigned int n)
1130{
1131 struct earlycon_device *dev = con->data;
1132
1133 __qcom_geni_serial_console_write(&dev->port, s, n);
1134}
1135
1136#ifdef CONFIG_CONSOLE_POLL
1137static int qcom_geni_serial_earlycon_read(struct console *con,
1138 char *s, unsigned int n)
1139{
1140 struct earlycon_device *dev = con->data;
1141 struct uart_port *uport = &dev->port;
1142 int num_read = 0;
1143 int ch;
1144
1145 while (num_read < n) {
1146 ch = qcom_geni_serial_get_char(uport);
1147 if (ch == NO_POLL_CHAR)
1148 break;
1149 s[num_read++] = ch;
1150 }
1151
1152 return num_read;
1153}
1154
1155static void __init qcom_geni_serial_enable_early_read(struct geni_se *se,
1156 struct console *con)
1157{
1158 geni_se_setup_s_cmd(se, UART_START_READ, 0);
1159 con->read = qcom_geni_serial_earlycon_read;
1160}
1161#else
1162static inline void qcom_geni_serial_enable_early_read(struct geni_se *se,
1163 struct console *con) { }
1164#endif
1165
1166static struct qcom_geni_private_data earlycon_private_data;
1167
1168static int __init qcom_geni_serial_earlycon_setup(struct earlycon_device *dev,
1169 const char *opt)
1170{
1171 struct uart_port *uport = &dev->port;
1172 u32 tx_trans_cfg;
1173 u32 tx_parity_cfg = 0;
1174 u32 rx_trans_cfg = 0;
1175 u32 rx_parity_cfg = 0;
1176 u32 stop_bit_len = 0;
1177 u32 bits_per_char;
1178 struct geni_se se;
1179
1180 if (!uport->membase)
1181 return -EINVAL;
1182
1183 uport->private_data = &earlycon_private_data;
1184
1185 memset(&se, 0, sizeof(se));
1186 se.base = uport->membase;
1187 if (geni_se_read_proto(&se) != GENI_SE_UART)
1188 return -ENXIO;
1189
1190
1191
1192
1193 tx_trans_cfg = UART_CTS_MASK;
1194 bits_per_char = BITS_PER_BYTE;
1195
1196
1197
1198
1199
1200 qcom_geni_serial_poll_tx_done(uport);
1201 qcom_geni_serial_abort_rx(uport);
1202 geni_se_config_packing(&se, BITS_PER_BYTE, BYTES_PER_FIFO_WORD,
1203 false, true, true);
1204 geni_se_init(&se, DEF_FIFO_DEPTH_WORDS / 2, DEF_FIFO_DEPTH_WORDS - 2);
1205 geni_se_select_mode(&se, GENI_SE_FIFO);
1206
1207 writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG);
1208 writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG);
1209 writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG);
1210 writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG);
1211 writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN);
1212 writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN);
1213 writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN);
1214
1215 dev->con->write = qcom_geni_serial_earlycon_write;
1216 dev->con->setup = NULL;
1217 qcom_geni_serial_enable_early_read(&se, dev->con);
1218
1219 return 0;
1220}
1221OF_EARLYCON_DECLARE(qcom_geni, "qcom,geni-debug-uart",
1222 qcom_geni_serial_earlycon_setup);
1223
1224static int __init console_register(struct uart_driver *drv)
1225{
1226 return uart_register_driver(drv);
1227}
1228
1229static void console_unregister(struct uart_driver *drv)
1230{
1231 uart_unregister_driver(drv);
1232}
1233
1234static struct console cons_ops = {
1235 .name = "ttyMSM",
1236 .write = qcom_geni_serial_console_write,
1237 .device = uart_console_device,
1238 .setup = qcom_geni_console_setup,
1239 .flags = CON_PRINTBUFFER,
1240 .index = -1,
1241 .data = &qcom_geni_console_driver,
1242};
1243
1244static struct uart_driver qcom_geni_console_driver = {
1245 .owner = THIS_MODULE,
1246 .driver_name = "qcom_geni_console",
1247 .dev_name = "ttyMSM",
1248 .nr = GENI_UART_CONS_PORTS,
1249 .cons = &cons_ops,
1250};
1251#else
1252static int console_register(struct uart_driver *drv)
1253{
1254 return 0;
1255}
1256
1257static void console_unregister(struct uart_driver *drv)
1258{
1259}
1260#endif
1261
1262static struct uart_driver qcom_geni_uart_driver = {
1263 .owner = THIS_MODULE,
1264 .driver_name = "qcom_geni_uart",
1265 .dev_name = "ttyHS",
1266 .nr = GENI_UART_PORTS,
1267};
1268
1269static void qcom_geni_serial_pm(struct uart_port *uport,
1270 unsigned int new_state, unsigned int old_state)
1271{
1272 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
1273
1274
1275 if (old_state == UART_PM_STATE_UNDEFINED)
1276 old_state = UART_PM_STATE_OFF;
1277
1278 if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF) {
1279 geni_icc_enable(&port->se);
1280 geni_se_resources_on(&port->se);
1281 } else if (new_state == UART_PM_STATE_OFF &&
1282 old_state == UART_PM_STATE_ON) {
1283 geni_se_resources_off(&port->se);
1284 geni_icc_disable(&port->se);
1285 }
1286}
1287
1288static const struct uart_ops qcom_geni_console_pops = {
1289 .tx_empty = qcom_geni_serial_tx_empty,
1290 .stop_tx = qcom_geni_serial_stop_tx,
1291 .start_tx = qcom_geni_serial_start_tx,
1292 .stop_rx = qcom_geni_serial_stop_rx,
1293 .set_termios = qcom_geni_serial_set_termios,
1294 .startup = qcom_geni_serial_startup,
1295 .request_port = qcom_geni_serial_request_port,
1296 .config_port = qcom_geni_serial_config_port,
1297 .shutdown = qcom_geni_serial_shutdown,
1298 .type = qcom_geni_serial_get_type,
1299 .set_mctrl = qcom_geni_serial_set_mctrl,
1300 .get_mctrl = qcom_geni_serial_get_mctrl,
1301#ifdef CONFIG_CONSOLE_POLL
1302 .poll_get_char = qcom_geni_serial_get_char,
1303 .poll_put_char = qcom_geni_serial_poll_put_char,
1304#endif
1305 .pm = qcom_geni_serial_pm,
1306};
1307
1308static const struct uart_ops qcom_geni_uart_pops = {
1309 .tx_empty = qcom_geni_serial_tx_empty,
1310 .stop_tx = qcom_geni_serial_stop_tx,
1311 .start_tx = qcom_geni_serial_start_tx,
1312 .stop_rx = qcom_geni_serial_stop_rx,
1313 .set_termios = qcom_geni_serial_set_termios,
1314 .startup = qcom_geni_serial_startup,
1315 .request_port = qcom_geni_serial_request_port,
1316 .config_port = qcom_geni_serial_config_port,
1317 .shutdown = qcom_geni_serial_shutdown,
1318 .type = qcom_geni_serial_get_type,
1319 .set_mctrl = qcom_geni_serial_set_mctrl,
1320 .get_mctrl = qcom_geni_serial_get_mctrl,
1321 .pm = qcom_geni_serial_pm,
1322};
1323
1324static int qcom_geni_serial_probe(struct platform_device *pdev)
1325{
1326 int ret = 0;
1327 int line;
1328 struct qcom_geni_serial_port *port;
1329 struct uart_port *uport;
1330 struct resource *res;
1331 int irq;
1332 bool console = false;
1333 struct uart_driver *drv;
1334
1335 if (of_device_is_compatible(pdev->dev.of_node, "qcom,geni-debug-uart"))
1336 console = true;
1337
1338 if (console) {
1339 drv = &qcom_geni_console_driver;
1340 line = of_alias_get_id(pdev->dev.of_node, "serial");
1341 } else {
1342 drv = &qcom_geni_uart_driver;
1343 line = of_alias_get_id(pdev->dev.of_node, "serial");
1344 if (line == -ENODEV)
1345 line = of_alias_get_id(pdev->dev.of_node, "hsuart");
1346 }
1347
1348 port = get_port_from_line(line, console);
1349 if (IS_ERR(port)) {
1350 dev_err(&pdev->dev, "Invalid line %d\n", line);
1351 return PTR_ERR(port);
1352 }
1353
1354 uport = &port->uport;
1355
1356 if (uport->private_data)
1357 return -ENODEV;
1358
1359 uport->dev = &pdev->dev;
1360 port->se.dev = &pdev->dev;
1361 port->se.wrapper = dev_get_drvdata(pdev->dev.parent);
1362 port->se.clk = devm_clk_get(&pdev->dev, "se");
1363 if (IS_ERR(port->se.clk)) {
1364 ret = PTR_ERR(port->se.clk);
1365 dev_err(&pdev->dev, "Err getting SE Core clk %d\n", ret);
1366 return ret;
1367 }
1368
1369 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1370 if (!res)
1371 return -EINVAL;
1372 uport->mapbase = res->start;
1373
1374 port->tx_fifo_depth = DEF_FIFO_DEPTH_WORDS;
1375 port->rx_fifo_depth = DEF_FIFO_DEPTH_WORDS;
1376 port->tx_fifo_width = DEF_FIFO_WIDTH_BITS;
1377
1378 if (!console) {
1379 port->rx_fifo = devm_kcalloc(uport->dev,
1380 port->rx_fifo_depth, sizeof(u32), GFP_KERNEL);
1381 if (!port->rx_fifo)
1382 return -ENOMEM;
1383 }
1384
1385 ret = geni_icc_get(&port->se, NULL);
1386 if (ret)
1387 return ret;
1388 port->se.icc_paths[GENI_TO_CORE].avg_bw = GENI_DEFAULT_BW;
1389 port->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW;
1390
1391
1392 ret = geni_icc_set_bw(&port->se);
1393 if (ret)
1394 return ret;
1395
1396 port->name = devm_kasprintf(uport->dev, GFP_KERNEL,
1397 "qcom_geni_serial_%s%d",
1398 uart_console(uport) ? "console" : "uart", uport->line);
1399 if (!port->name)
1400 return -ENOMEM;
1401
1402 irq = platform_get_irq(pdev, 0);
1403 if (irq < 0)
1404 return irq;
1405 uport->irq = irq;
1406 uport->has_sysrq = IS_ENABLED(CONFIG_SERIAL_QCOM_GENI_CONSOLE);
1407
1408 if (!console)
1409 port->wakeup_irq = platform_get_irq_optional(pdev, 1);
1410
1411 if (of_property_read_bool(pdev->dev.of_node, "rx-tx-swap"))
1412 port->rx_tx_swap = true;
1413
1414 if (of_property_read_bool(pdev->dev.of_node, "cts-rts-swap"))
1415 port->cts_rts_swap = true;
1416
1417 ret = devm_pm_opp_set_clkname(&pdev->dev, "se");
1418 if (ret)
1419 return ret;
1420
1421 ret = devm_pm_opp_of_add_table(&pdev->dev);
1422 if (ret && ret != -ENODEV) {
1423 dev_err(&pdev->dev, "invalid OPP table in device tree\n");
1424 return ret;
1425 }
1426
1427 port->private_data.drv = drv;
1428 uport->private_data = &port->private_data;
1429 platform_set_drvdata(pdev, port);
1430 port->handle_rx = console ? handle_rx_console : handle_rx_uart;
1431
1432 ret = uart_add_one_port(drv, uport);
1433 if (ret)
1434 return ret;
1435
1436 irq_set_status_flags(uport->irq, IRQ_NOAUTOEN);
1437 ret = devm_request_irq(uport->dev, uport->irq, qcom_geni_serial_isr,
1438 IRQF_TRIGGER_HIGH, port->name, uport);
1439 if (ret) {
1440 dev_err(uport->dev, "Failed to get IRQ ret %d\n", ret);
1441 uart_remove_one_port(drv, uport);
1442 return ret;
1443 }
1444
1445
1446
1447
1448
1449
1450 pm_runtime_set_active(&pdev->dev);
1451
1452 if (port->wakeup_irq > 0) {
1453 device_init_wakeup(&pdev->dev, true);
1454 ret = dev_pm_set_dedicated_wake_irq(&pdev->dev,
1455 port->wakeup_irq);
1456 if (ret) {
1457 device_init_wakeup(&pdev->dev, false);
1458 uart_remove_one_port(drv, uport);
1459 return ret;
1460 }
1461 }
1462
1463 return 0;
1464}
1465
1466static int qcom_geni_serial_remove(struct platform_device *pdev)
1467{
1468 struct qcom_geni_serial_port *port = platform_get_drvdata(pdev);
1469 struct uart_driver *drv = port->private_data.drv;
1470
1471 dev_pm_clear_wake_irq(&pdev->dev);
1472 device_init_wakeup(&pdev->dev, false);
1473 uart_remove_one_port(drv, &port->uport);
1474
1475 return 0;
1476}
1477
1478static int __maybe_unused qcom_geni_serial_sys_suspend(struct device *dev)
1479{
1480 struct qcom_geni_serial_port *port = dev_get_drvdata(dev);
1481 struct uart_port *uport = &port->uport;
1482 struct qcom_geni_private_data *private_data = uport->private_data;
1483
1484
1485
1486
1487
1488 if (uart_console(uport)) {
1489 geni_icc_set_tag(&port->se, 0x3);
1490 geni_icc_set_bw(&port->se);
1491 }
1492 return uart_suspend_port(private_data->drv, uport);
1493}
1494
1495static int __maybe_unused qcom_geni_serial_sys_resume(struct device *dev)
1496{
1497 int ret;
1498 struct qcom_geni_serial_port *port = dev_get_drvdata(dev);
1499 struct uart_port *uport = &port->uport;
1500 struct qcom_geni_private_data *private_data = uport->private_data;
1501
1502 ret = uart_resume_port(private_data->drv, uport);
1503 if (uart_console(uport)) {
1504 geni_icc_set_tag(&port->se, 0x7);
1505 geni_icc_set_bw(&port->se);
1506 }
1507 return ret;
1508}
1509
1510static const struct dev_pm_ops qcom_geni_serial_pm_ops = {
1511 SET_SYSTEM_SLEEP_PM_OPS(qcom_geni_serial_sys_suspend,
1512 qcom_geni_serial_sys_resume)
1513};
1514
1515static const struct of_device_id qcom_geni_serial_match_table[] = {
1516 { .compatible = "qcom,geni-debug-uart", },
1517 { .compatible = "qcom,geni-uart", },
1518 {}
1519};
1520MODULE_DEVICE_TABLE(of, qcom_geni_serial_match_table);
1521
1522static struct platform_driver qcom_geni_serial_platform_driver = {
1523 .remove = qcom_geni_serial_remove,
1524 .probe = qcom_geni_serial_probe,
1525 .driver = {
1526 .name = "qcom_geni_serial",
1527 .of_match_table = qcom_geni_serial_match_table,
1528 .pm = &qcom_geni_serial_pm_ops,
1529 },
1530};
1531
1532static int __init qcom_geni_serial_init(void)
1533{
1534 int ret;
1535
1536 ret = console_register(&qcom_geni_console_driver);
1537 if (ret)
1538 return ret;
1539
1540 ret = uart_register_driver(&qcom_geni_uart_driver);
1541 if (ret) {
1542 console_unregister(&qcom_geni_console_driver);
1543 return ret;
1544 }
1545
1546 ret = platform_driver_register(&qcom_geni_serial_platform_driver);
1547 if (ret) {
1548 console_unregister(&qcom_geni_console_driver);
1549 uart_unregister_driver(&qcom_geni_uart_driver);
1550 }
1551 return ret;
1552}
1553module_init(qcom_geni_serial_init);
1554
1555static void __exit qcom_geni_serial_exit(void)
1556{
1557 platform_driver_unregister(&qcom_geni_serial_platform_driver);
1558 console_unregister(&qcom_geni_console_driver);
1559 uart_unregister_driver(&qcom_geni_uart_driver);
1560}
1561module_exit(qcom_geni_serial_exit);
1562
1563MODULE_DESCRIPTION("Serial driver for GENI based QUP cores");
1564MODULE_LICENSE("GPL v2");
1565
