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11#ifndef __DRIVERS_USB_DWC3_CORE_H
12#define __DRIVERS_USB_DWC3_CORE_H
13
14#include <linux/device.h>
15#include <linux/spinlock.h>
16#include <linux/mutex.h>
17#include <linux/ioport.h>
18#include <linux/list.h>
19#include <linux/bitops.h>
20#include <linux/dma-mapping.h>
21#include <linux/mm.h>
22#include <linux/debugfs.h>
23#include <linux/wait.h>
24#include <linux/workqueue.h>
25
26#include <linux/usb/ch9.h>
27#include <linux/usb/gadget.h>
28#include <linux/usb/otg.h>
29#include <linux/usb/role.h>
30#include <linux/ulpi/interface.h>
31
32#include <linux/phy/phy.h>
33
34#include <linux/power_supply.h>
35
36#define DWC3_MSG_MAX 500
37
38
39#define DWC3_PULL_UP_TIMEOUT 500
40#define DWC3_BOUNCE_SIZE 1024
41#define DWC3_EP0_SETUP_SIZE 512
42#define DWC3_ENDPOINTS_NUM 32
43#define DWC3_XHCI_RESOURCES_NUM 2
44#define DWC3_ISOC_MAX_RETRIES 5
45
46#define DWC3_SCRATCHBUF_SIZE 4096
47#define DWC3_EVENT_BUFFERS_SIZE 4096
48#define DWC3_EVENT_TYPE_MASK 0xfe
49
50#define DWC3_EVENT_TYPE_DEV 0
51#define DWC3_EVENT_TYPE_CARKIT 3
52#define DWC3_EVENT_TYPE_I2C 4
53
54#define DWC3_DEVICE_EVENT_DISCONNECT 0
55#define DWC3_DEVICE_EVENT_RESET 1
56#define DWC3_DEVICE_EVENT_CONNECT_DONE 2
57#define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3
58#define DWC3_DEVICE_EVENT_WAKEUP 4
59#define DWC3_DEVICE_EVENT_HIBER_REQ 5
60#define DWC3_DEVICE_EVENT_SUSPEND 6
61#define DWC3_DEVICE_EVENT_SOF 7
62#define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9
63#define DWC3_DEVICE_EVENT_CMD_CMPL 10
64#define DWC3_DEVICE_EVENT_OVERFLOW 11
65
66
67#define DWC3_OTG_ROLE_IDLE 0
68#define DWC3_OTG_ROLE_HOST 1
69#define DWC3_OTG_ROLE_DEVICE 2
70
71#define DWC3_GEVNTCOUNT_MASK 0xfffc
72#define DWC3_GEVNTCOUNT_EHB BIT(31)
73#define DWC3_GSNPSID_MASK 0xffff0000
74#define DWC3_GSNPSREV_MASK 0xffff
75#define DWC3_GSNPS_ID(p) (((p) & DWC3_GSNPSID_MASK) >> 16)
76
77
78#define DWC3_XHCI_REGS_START 0x0
79#define DWC3_XHCI_REGS_END 0x7fff
80#define DWC3_GLOBALS_REGS_START 0xc100
81#define DWC3_GLOBALS_REGS_END 0xc6ff
82#define DWC3_DEVICE_REGS_START 0xc700
83#define DWC3_DEVICE_REGS_END 0xcbff
84#define DWC3_OTG_REGS_START 0xcc00
85#define DWC3_OTG_REGS_END 0xccff
86
87
88#define DWC3_GSBUSCFG0 0xc100
89#define DWC3_GSBUSCFG1 0xc104
90#define DWC3_GTXTHRCFG 0xc108
91#define DWC3_GRXTHRCFG 0xc10c
92#define DWC3_GCTL 0xc110
93#define DWC3_GEVTEN 0xc114
94#define DWC3_GSTS 0xc118
95#define DWC3_GUCTL1 0xc11c
96#define DWC3_GSNPSID 0xc120
97#define DWC3_GGPIO 0xc124
98#define DWC3_GUID 0xc128
99#define DWC3_GUCTL 0xc12c
100#define DWC3_GBUSERRADDR0 0xc130
101#define DWC3_GBUSERRADDR1 0xc134
102#define DWC3_GPRTBIMAP0 0xc138
103#define DWC3_GPRTBIMAP1 0xc13c
104#define DWC3_GHWPARAMS0 0xc140
105#define DWC3_GHWPARAMS1 0xc144
106#define DWC3_GHWPARAMS2 0xc148
107#define DWC3_GHWPARAMS3 0xc14c
108#define DWC3_GHWPARAMS4 0xc150
109#define DWC3_GHWPARAMS5 0xc154
110#define DWC3_GHWPARAMS6 0xc158
111#define DWC3_GHWPARAMS7 0xc15c
112#define DWC3_GDBGFIFOSPACE 0xc160
113#define DWC3_GDBGLTSSM 0xc164
114#define DWC3_GDBGBMU 0xc16c
115#define DWC3_GDBGLSPMUX 0xc170
116#define DWC3_GDBGLSP 0xc174
117#define DWC3_GDBGEPINFO0 0xc178
118#define DWC3_GDBGEPINFO1 0xc17c
119#define DWC3_GPRTBIMAP_HS0 0xc180
120#define DWC3_GPRTBIMAP_HS1 0xc184
121#define DWC3_GPRTBIMAP_FS0 0xc188
122#define DWC3_GPRTBIMAP_FS1 0xc18c
123#define DWC3_GUCTL2 0xc19c
124
125#define DWC3_VER_NUMBER 0xc1a0
126#define DWC3_VER_TYPE 0xc1a4
127
128#define DWC3_GUSB2PHYCFG(n) (0xc200 + ((n) * 0x04))
129#define DWC3_GUSB2I2CCTL(n) (0xc240 + ((n) * 0x04))
130
131#define DWC3_GUSB2PHYACC(n) (0xc280 + ((n) * 0x04))
132
133#define DWC3_GUSB3PIPECTL(n) (0xc2c0 + ((n) * 0x04))
134
135#define DWC3_GTXFIFOSIZ(n) (0xc300 + ((n) * 0x04))
136#define DWC3_GRXFIFOSIZ(n) (0xc380 + ((n) * 0x04))
137
138#define DWC3_GEVNTADRLO(n) (0xc400 + ((n) * 0x10))
139#define DWC3_GEVNTADRHI(n) (0xc404 + ((n) * 0x10))
140#define DWC3_GEVNTSIZ(n) (0xc408 + ((n) * 0x10))
141#define DWC3_GEVNTCOUNT(n) (0xc40c + ((n) * 0x10))
142
143#define DWC3_GHWPARAMS8 0xc600
144#define DWC3_GUCTL3 0xc60c
145#define DWC3_GFLADJ 0xc630
146#define DWC3_GHWPARAMS9 0xc6e0
147
148
149#define DWC3_DCFG 0xc700
150#define DWC3_DCTL 0xc704
151#define DWC3_DEVTEN 0xc708
152#define DWC3_DSTS 0xc70c
153#define DWC3_DGCMDPAR 0xc710
154#define DWC3_DGCMD 0xc714
155#define DWC3_DALEPENA 0xc720
156
157#define DWC3_DEP_BASE(n) (0xc800 + ((n) * 0x10))
158#define DWC3_DEPCMDPAR2 0x00
159#define DWC3_DEPCMDPAR1 0x04
160#define DWC3_DEPCMDPAR0 0x08
161#define DWC3_DEPCMD 0x0c
162
163#define DWC3_DEV_IMOD(n) (0xca00 + ((n) * 0x4))
164
165
166#define DWC3_OCFG 0xcc00
167#define DWC3_OCTL 0xcc04
168#define DWC3_OEVT 0xcc08
169#define DWC3_OEVTEN 0xcc0C
170#define DWC3_OSTS 0xcc10
171
172
173
174
175#define DWC3_GSBUSCFG0_INCR256BRSTENA (1 << 7)
176#define DWC3_GSBUSCFG0_INCR128BRSTENA (1 << 6)
177#define DWC3_GSBUSCFG0_INCR64BRSTENA (1 << 5)
178#define DWC3_GSBUSCFG0_INCR32BRSTENA (1 << 4)
179#define DWC3_GSBUSCFG0_INCR16BRSTENA (1 << 3)
180#define DWC3_GSBUSCFG0_INCR8BRSTENA (1 << 2)
181#define DWC3_GSBUSCFG0_INCR4BRSTENA (1 << 1)
182#define DWC3_GSBUSCFG0_INCRBRSTENA (1 << 0)
183#define DWC3_GSBUSCFG0_INCRBRST_MASK 0xff
184
185
186#define DWC3_GDBGLSPMUX_ENDBC BIT(15)
187#define DWC3_GDBGLSPMUX_HOSTSELECT(n) ((n) & 0x3fff)
188#define DWC3_GDBGLSPMUX_DEVSELECT(n) (((n) & 0xf) << 4)
189#define DWC3_GDBGLSPMUX_EPSELECT(n) ((n) & 0xf)
190
191
192#define DWC3_GDBGFIFOSPACE_NUM(n) ((n) & 0x1f)
193#define DWC3_GDBGFIFOSPACE_TYPE(n) (((n) << 5) & 0x1e0)
194#define DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(n) (((n) >> 16) & 0xffff)
195
196#define DWC3_TXFIFO 0
197#define DWC3_RXFIFO 1
198#define DWC3_TXREQQ 2
199#define DWC3_RXREQQ 3
200#define DWC3_RXINFOQ 4
201#define DWC3_PSTATQ 5
202#define DWC3_DESCFETCHQ 6
203#define DWC3_EVENTQ 7
204#define DWC3_AUXEVENTQ 8
205
206
207#define DWC3_GRXTHRCFG_MAXRXBURSTSIZE(n) (((n) & 0x1f) << 19)
208#define DWC3_GRXTHRCFG_RXPKTCNT(n) (((n) & 0xf) << 24)
209#define DWC3_GRXTHRCFG_PKTCNTSEL BIT(29)
210
211
212#define DWC31_GRXTHRCFG_MAXRXBURSTSIZE(n) (((n) & 0x1f) << 16)
213#define DWC31_GRXTHRCFG_RXPKTCNT(n) (((n) & 0x1f) << 21)
214#define DWC31_GRXTHRCFG_PKTCNTSEL BIT(26)
215#define DWC31_RXTHRNUMPKTSEL_HS_PRD BIT(15)
216#define DWC31_RXTHRNUMPKT_HS_PRD(n) (((n) & 0x3) << 13)
217#define DWC31_RXTHRNUMPKTSEL_PRD BIT(10)
218#define DWC31_RXTHRNUMPKT_PRD(n) (((n) & 0x1f) << 5)
219#define DWC31_MAXRXBURSTSIZE_PRD(n) ((n) & 0x1f)
220
221
222#define DWC31_GTXTHRCFG_MAXTXBURSTSIZE(n) (((n) & 0x1f) << 16)
223#define DWC31_GTXTHRCFG_TXPKTCNT(n) (((n) & 0x1f) << 21)
224#define DWC31_GTXTHRCFG_PKTCNTSEL BIT(26)
225#define DWC31_TXTHRNUMPKTSEL_HS_PRD BIT(15)
226#define DWC31_TXTHRNUMPKT_HS_PRD(n) (((n) & 0x3) << 13)
227#define DWC31_TXTHRNUMPKTSEL_PRD BIT(10)
228#define DWC31_TXTHRNUMPKT_PRD(n) (((n) & 0x1f) << 5)
229#define DWC31_MAXTXBURSTSIZE_PRD(n) ((n) & 0x1f)
230
231
232#define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19)
233#define DWC3_GCTL_U2RSTECN BIT(16)
234#define DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6)
235#define DWC3_GCTL_CLK_BUS (0)
236#define DWC3_GCTL_CLK_PIPE (1)
237#define DWC3_GCTL_CLK_PIPEHALF (2)
238#define DWC3_GCTL_CLK_MASK (3)
239
240#define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12)
241#define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12)
242#define DWC3_GCTL_PRTCAP_HOST 1
243#define DWC3_GCTL_PRTCAP_DEVICE 2
244#define DWC3_GCTL_PRTCAP_OTG 3
245
246#define DWC3_GCTL_CORESOFTRESET BIT(11)
247#define DWC3_GCTL_SOFITPSYNC BIT(10)
248#define DWC3_GCTL_SCALEDOWN(n) ((n) << 4)
249#define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3)
250#define DWC3_GCTL_DISSCRAMBLE BIT(3)
251#define DWC3_GCTL_U2EXIT_LFPS BIT(2)
252#define DWC3_GCTL_GBLHIBERNATIONEN BIT(1)
253#define DWC3_GCTL_DSBLCLKGTNG BIT(0)
254
255
256#define DWC3_GUCTL_HSTINAUTORETRY BIT(14)
257
258
259#define DWC3_GUCTL1_DEV_DECOUPLE_L1L2_EVT BIT(31)
260#define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS BIT(28)
261#define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW BIT(24)
262#define DWC3_GUCTL1_PARKMODE_DISABLE_SS BIT(17)
263
264
265#define DWC3_GSTS_OTG_IP BIT(10)
266#define DWC3_GSTS_BC_IP BIT(9)
267#define DWC3_GSTS_ADP_IP BIT(8)
268#define DWC3_GSTS_HOST_IP BIT(7)
269#define DWC3_GSTS_DEVICE_IP BIT(6)
270#define DWC3_GSTS_CSR_TIMEOUT BIT(5)
271#define DWC3_GSTS_BUS_ERR_ADDR_VLD BIT(4)
272#define DWC3_GSTS_CURMOD(n) ((n) & 0x3)
273#define DWC3_GSTS_CURMOD_DEVICE 0
274#define DWC3_GSTS_CURMOD_HOST 1
275
276
277#define DWC3_GUSB2PHYCFG_PHYSOFTRST BIT(31)
278#define DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS BIT(30)
279#define DWC3_GUSB2PHYCFG_SUSPHY BIT(6)
280#define DWC3_GUSB2PHYCFG_ULPI_UTMI BIT(4)
281#define DWC3_GUSB2PHYCFG_ENBLSLPM BIT(8)
282#define DWC3_GUSB2PHYCFG_PHYIF(n) (n << 3)
283#define DWC3_GUSB2PHYCFG_PHYIF_MASK DWC3_GUSB2PHYCFG_PHYIF(1)
284#define DWC3_GUSB2PHYCFG_USBTRDTIM(n) (n << 10)
285#define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK DWC3_GUSB2PHYCFG_USBTRDTIM(0xf)
286#define USBTRDTIM_UTMI_8_BIT 9
287#define USBTRDTIM_UTMI_16_BIT 5
288#define UTMI_PHYIF_16_BIT 1
289#define UTMI_PHYIF_8_BIT 0
290
291
292#define DWC3_GUSB2PHYACC_NEWREGREQ BIT(25)
293#define DWC3_GUSB2PHYACC_DONE BIT(24)
294#define DWC3_GUSB2PHYACC_BUSY BIT(23)
295#define DWC3_GUSB2PHYACC_WRITE BIT(22)
296#define DWC3_GUSB2PHYACC_ADDR(n) (n << 16)
297#define DWC3_GUSB2PHYACC_EXTEND_ADDR(n) (n << 8)
298#define DWC3_GUSB2PHYACC_DATA(n) (n & 0xff)
299
300
301#define DWC3_GUSB3PIPECTL_PHYSOFTRST BIT(31)
302#define DWC3_GUSB3PIPECTL_U2SSINP3OK BIT(29)
303#define DWC3_GUSB3PIPECTL_DISRXDETINP3 BIT(28)
304#define DWC3_GUSB3PIPECTL_UX_EXIT_PX BIT(27)
305#define DWC3_GUSB3PIPECTL_REQP1P2P3 BIT(24)
306#define DWC3_GUSB3PIPECTL_DEP1P2P3(n) ((n) << 19)
307#define DWC3_GUSB3PIPECTL_DEP1P2P3_MASK DWC3_GUSB3PIPECTL_DEP1P2P3(7)
308#define DWC3_GUSB3PIPECTL_DEP1P2P3_EN DWC3_GUSB3PIPECTL_DEP1P2P3(1)
309#define DWC3_GUSB3PIPECTL_DEPOCHANGE BIT(18)
310#define DWC3_GUSB3PIPECTL_SUSPHY BIT(17)
311#define DWC3_GUSB3PIPECTL_LFPSFILT BIT(9)
312#define DWC3_GUSB3PIPECTL_RX_DETOPOLL BIT(8)
313#define DWC3_GUSB3PIPECTL_TX_DEEPH_MASK DWC3_GUSB3PIPECTL_TX_DEEPH(3)
314#define DWC3_GUSB3PIPECTL_TX_DEEPH(n) ((n) << 1)
315
316
317#define DWC31_GTXFIFOSIZ_TXFRAMNUM BIT(15)
318#define DWC31_GTXFIFOSIZ_TXFDEP(n) ((n) & 0x7fff)
319#define DWC3_GTXFIFOSIZ_TXFDEP(n) ((n) & 0xffff)
320#define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000)
321
322
323#define DWC31_GRXFIFOSIZ_RXFDEP(n) ((n) & 0x7fff)
324#define DWC3_GRXFIFOSIZ_RXFDEP(n) ((n) & 0xffff)
325
326
327#define DWC3_GEVNTSIZ_INTMASK BIT(31)
328#define DWC3_GEVNTSIZ_SIZE(n) ((n) & 0xffff)
329
330
331#define DWC3_GHWPARAMS0_MODE(n) ((n) & 0x3)
332#define DWC3_GHWPARAMS0_MODE_GADGET 0
333#define DWC3_GHWPARAMS0_MODE_HOST 1
334#define DWC3_GHWPARAMS0_MODE_DRD 2
335#define DWC3_GHWPARAMS0_MBUS_TYPE(n) (((n) >> 3) & 0x7)
336#define DWC3_GHWPARAMS0_SBUS_TYPE(n) (((n) >> 6) & 0x3)
337#define DWC3_GHWPARAMS0_MDWIDTH(n) (((n) >> 8) & 0xff)
338#define DWC3_GHWPARAMS0_SDWIDTH(n) (((n) >> 16) & 0xff)
339#define DWC3_GHWPARAMS0_AWIDTH(n) (((n) >> 24) & 0xff)
340
341
342#define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24)
343#define DWC3_GHWPARAMS1_EN_PWROPT_NO 0
344#define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1
345#define DWC3_GHWPARAMS1_EN_PWROPT_HIB 2
346#define DWC3_GHWPARAMS1_PWROPT(n) ((n) << 24)
347#define DWC3_GHWPARAMS1_PWROPT_MASK DWC3_GHWPARAMS1_PWROPT(3)
348#define DWC3_GHWPARAMS1_ENDBC BIT(31)
349
350
351#define DWC3_GHWPARAMS3_SSPHY_IFC(n) ((n) & 3)
352#define DWC3_GHWPARAMS3_SSPHY_IFC_DIS 0
353#define DWC3_GHWPARAMS3_SSPHY_IFC_GEN1 1
354#define DWC3_GHWPARAMS3_SSPHY_IFC_GEN2 2
355#define DWC3_GHWPARAMS3_HSPHY_IFC(n) (((n) & (3 << 2)) >> 2)
356#define DWC3_GHWPARAMS3_HSPHY_IFC_DIS 0
357#define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI 1
358#define DWC3_GHWPARAMS3_HSPHY_IFC_ULPI 2
359#define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI 3
360#define DWC3_GHWPARAMS3_FSPHY_IFC(n) (((n) & (3 << 4)) >> 4)
361#define DWC3_GHWPARAMS3_FSPHY_IFC_DIS 0
362#define DWC3_GHWPARAMS3_FSPHY_IFC_ENA 1
363
364
365#define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((n) & (0x0f << 13)) >> 13)
366#define DWC3_MAX_HIBER_SCRATCHBUFS 15
367
368
369#define DWC3_GHWPARAMS6_BCSUPPORT BIT(14)
370#define DWC3_GHWPARAMS6_OTG3SUPPORT BIT(13)
371#define DWC3_GHWPARAMS6_ADPSUPPORT BIT(12)
372#define DWC3_GHWPARAMS6_HNPSUPPORT BIT(11)
373#define DWC3_GHWPARAMS6_SRPSUPPORT BIT(10)
374#define DWC3_GHWPARAMS6_EN_FPGA BIT(7)
375
376
377#define DWC3_GHWPARAMS6_MDWIDTH(n) ((n) & (0x3 << 8))
378
379
380#define DWC3_GHWPARAMS7_RAM1_DEPTH(n) ((n) & 0xffff)
381#define DWC3_GHWPARAMS7_RAM2_DEPTH(n) (((n) >> 16) & 0xffff)
382
383
384#define DWC3_GHWPARAMS9_DEV_TXF_FLUSH_BYPASS BIT(0)
385
386
387#define DWC3_GFLADJ_30MHZ_SDBND_SEL BIT(7)
388#define DWC3_GFLADJ_30MHZ_MASK 0x3f
389
390
391#define DWC3_GUCTL_REFCLKPER_MASK 0xffc00000
392#define DWC3_GUCTL_REFCLKPER_SEL 22
393
394
395#define DWC3_GUCTL2_RST_ACTBITLATER BIT(14)
396
397
398#define DWC3_GUCTL3_SPLITDISABLE BIT(14)
399
400
401#define DWC3_DCFG_NUMLANES(n) (((n) & 0x3) << 30)
402
403#define DWC3_DCFG_DEVADDR(addr) ((addr) << 3)
404#define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f)
405
406#define DWC3_DCFG_SPEED_MASK (7 << 0)
407#define DWC3_DCFG_SUPERSPEED_PLUS (5 << 0)
408#define DWC3_DCFG_SUPERSPEED (4 << 0)
409#define DWC3_DCFG_HIGHSPEED (0 << 0)
410#define DWC3_DCFG_FULLSPEED BIT(0)
411
412#define DWC3_DCFG_NUMP_SHIFT 17
413#define DWC3_DCFG_NUMP(n) (((n) >> DWC3_DCFG_NUMP_SHIFT) & 0x1f)
414#define DWC3_DCFG_NUMP_MASK (0x1f << DWC3_DCFG_NUMP_SHIFT)
415#define DWC3_DCFG_LPM_CAP BIT(22)
416#define DWC3_DCFG_IGNSTRMPP BIT(23)
417
418
419#define DWC3_DCTL_RUN_STOP BIT(31)
420#define DWC3_DCTL_CSFTRST BIT(30)
421#define DWC3_DCTL_LSFTRST BIT(29)
422
423#define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24)
424#define DWC3_DCTL_HIRD_THRES(n) ((n) << 24)
425
426#define DWC3_DCTL_APPL1RES BIT(23)
427
428
429#define DWC3_DCTL_TRGTULST_MASK (0x0f << 17)
430#define DWC3_DCTL_TRGTULST(n) ((n) << 17)
431#define DWC3_DCTL_TRGTULST_U2 (DWC3_DCTL_TRGTULST(2))
432#define DWC3_DCTL_TRGTULST_U3 (DWC3_DCTL_TRGTULST(3))
433#define DWC3_DCTL_TRGTULST_SS_DIS (DWC3_DCTL_TRGTULST(4))
434#define DWC3_DCTL_TRGTULST_RX_DET (DWC3_DCTL_TRGTULST(5))
435#define DWC3_DCTL_TRGTULST_SS_INACT (DWC3_DCTL_TRGTULST(6))
436
437
438#define DWC3_DCTL_NYET_THRES(n) (((n) & 0xf) << 20)
439
440#define DWC3_DCTL_KEEP_CONNECT BIT(19)
441#define DWC3_DCTL_L1_HIBER_EN BIT(18)
442#define DWC3_DCTL_CRS BIT(17)
443#define DWC3_DCTL_CSS BIT(16)
444
445#define DWC3_DCTL_INITU2ENA BIT(12)
446#define DWC3_DCTL_ACCEPTU2ENA BIT(11)
447#define DWC3_DCTL_INITU1ENA BIT(10)
448#define DWC3_DCTL_ACCEPTU1ENA BIT(9)
449#define DWC3_DCTL_TSTCTRL_MASK (0xf << 1)
450
451#define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5)
452#define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK)
453
454#define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0))
455#define DWC3_DCTL_ULSTCHNG_SS_DISABLED (DWC3_DCTL_ULSTCHNGREQ(4))
456#define DWC3_DCTL_ULSTCHNG_RX_DETECT (DWC3_DCTL_ULSTCHNGREQ(5))
457#define DWC3_DCTL_ULSTCHNG_SS_INACTIVE (DWC3_DCTL_ULSTCHNGREQ(6))
458#define DWC3_DCTL_ULSTCHNG_RECOVERY (DWC3_DCTL_ULSTCHNGREQ(8))
459#define DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10))
460#define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11))
461
462
463#define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN BIT(12)
464#define DWC3_DEVTEN_EVNTOVERFLOWEN BIT(11)
465#define DWC3_DEVTEN_CMDCMPLTEN BIT(10)
466#define DWC3_DEVTEN_ERRTICERREN BIT(9)
467#define DWC3_DEVTEN_SOFEN BIT(7)
468#define DWC3_DEVTEN_U3L2L1SUSPEN BIT(6)
469#define DWC3_DEVTEN_HIBERNATIONREQEVTEN BIT(5)
470#define DWC3_DEVTEN_WKUPEVTEN BIT(4)
471#define DWC3_DEVTEN_ULSTCNGEN BIT(3)
472#define DWC3_DEVTEN_CONNECTDONEEN BIT(2)
473#define DWC3_DEVTEN_USBRSTEN BIT(1)
474#define DWC3_DEVTEN_DISCONNEVTEN BIT(0)
475
476#define DWC3_DSTS_CONNLANES(n) (((n) >> 30) & 0x3)
477
478
479#define DWC3_DSTS_DCNRD BIT(29)
480
481
482#define DWC3_DSTS_PWRUPREQ BIT(24)
483
484
485#define DWC3_DSTS_RSS BIT(25)
486#define DWC3_DSTS_SSS BIT(24)
487
488#define DWC3_DSTS_COREIDLE BIT(23)
489#define DWC3_DSTS_DEVCTRLHLT BIT(22)
490
491#define DWC3_DSTS_USBLNKST_MASK (0x0f << 18)
492#define DWC3_DSTS_USBLNKST(n) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18)
493
494#define DWC3_DSTS_RXFIFOEMPTY BIT(17)
495
496#define DWC3_DSTS_SOFFN_MASK (0x3fff << 3)
497#define DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3)
498
499#define DWC3_DSTS_CONNECTSPD (7 << 0)
500
501#define DWC3_DSTS_SUPERSPEED_PLUS (5 << 0)
502#define DWC3_DSTS_SUPERSPEED (4 << 0)
503#define DWC3_DSTS_HIGHSPEED (0 << 0)
504#define DWC3_DSTS_FULLSPEED BIT(0)
505
506
507#define DWC3_DGCMD_SET_LMP 0x01
508#define DWC3_DGCMD_SET_PERIODIC_PAR 0x02
509#define DWC3_DGCMD_XMIT_FUNCTION 0x03
510
511
512#define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO 0x04
513#define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI 0x05
514
515#define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09
516#define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a
517#define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c
518#define DWC3_DGCMD_SET_ENDPOINT_PRIME 0x0d
519#define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10
520
521#define DWC3_DGCMD_STATUS(n) (((n) >> 12) & 0x0F)
522#define DWC3_DGCMD_CMDACT BIT(10)
523#define DWC3_DGCMD_CMDIOC BIT(8)
524
525
526#define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT BIT(0)
527#define DWC3_DGCMDPAR_FIFO_NUM(n) ((n) << 0)
528#define DWC3_DGCMDPAR_RX_FIFO (0 << 5)
529#define DWC3_DGCMDPAR_TX_FIFO BIT(5)
530#define DWC3_DGCMDPAR_LOOPBACK_DIS (0 << 0)
531#define DWC3_DGCMDPAR_LOOPBACK_ENA BIT(0)
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533
534#define DWC3_DEPCMD_PARAM_SHIFT 16
535#define DWC3_DEPCMD_PARAM(x) ((x) << DWC3_DEPCMD_PARAM_SHIFT)
536#define DWC3_DEPCMD_GET_RSC_IDX(x) (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f)
537#define DWC3_DEPCMD_STATUS(x) (((x) >> 12) & 0x0F)
538#define DWC3_DEPCMD_HIPRI_FORCERM BIT(11)
539#define DWC3_DEPCMD_CLEARPENDIN BIT(11)
540#define DWC3_DEPCMD_CMDACT BIT(10)
541#define DWC3_DEPCMD_CMDIOC BIT(8)
542
543#define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0)
544#define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0)
545#define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0)
546#define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0)
547#define DWC3_DEPCMD_CLEARSTALL (0x05 << 0)
548#define DWC3_DEPCMD_SETSTALL (0x04 << 0)
549
550#define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0)
551
552#define DWC3_DEPCMD_GETEPSTATE (0x03 << 0)
553#define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0)
554#define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0)
555
556#define DWC3_DEPCMD_CMD(x) ((x) & 0xf)
557
558
559#define DWC3_DALEPENA_EP(n) BIT(n)
560
561#define DWC3_DEPCMD_TYPE_CONTROL 0
562#define DWC3_DEPCMD_TYPE_ISOC 1
563#define DWC3_DEPCMD_TYPE_BULK 2
564#define DWC3_DEPCMD_TYPE_INTR 3
565
566#define DWC3_DEV_IMOD_COUNT_SHIFT 16
567#define DWC3_DEV_IMOD_COUNT_MASK (0xffff << 16)
568#define DWC3_DEV_IMOD_INTERVAL_SHIFT 0
569#define DWC3_DEV_IMOD_INTERVAL_MASK (0xffff << 0)
570
571
572#define DWC3_OCFG_DISPWRCUTTOFF BIT(5)
573#define DWC3_OCFG_HIBDISMASK BIT(4)
574#define DWC3_OCFG_SFTRSTMASK BIT(3)
575#define DWC3_OCFG_OTGVERSION BIT(2)
576#define DWC3_OCFG_HNPCAP BIT(1)
577#define DWC3_OCFG_SRPCAP BIT(0)
578
579
580#define DWC3_OCTL_OTG3GOERR BIT(7)
581#define DWC3_OCTL_PERIMODE BIT(6)
582#define DWC3_OCTL_PRTPWRCTL BIT(5)
583#define DWC3_OCTL_HNPREQ BIT(4)
584#define DWC3_OCTL_SESREQ BIT(3)
585#define DWC3_OCTL_TERMSELIDPULSE BIT(2)
586#define DWC3_OCTL_DEVSETHNPEN BIT(1)
587#define DWC3_OCTL_HSTSETHNPEN BIT(0)
588
589
590#define DWC3_OEVT_DEVICEMODE BIT(31)
591#define DWC3_OEVT_XHCIRUNSTPSET BIT(27)
592#define DWC3_OEVT_DEVRUNSTPSET BIT(26)
593#define DWC3_OEVT_HIBENTRY BIT(25)
594#define DWC3_OEVT_CONIDSTSCHNG BIT(24)
595#define DWC3_OEVT_HRRCONFNOTIF BIT(23)
596#define DWC3_OEVT_HRRINITNOTIF BIT(22)
597#define DWC3_OEVT_ADEVIDLE BIT(21)
598#define DWC3_OEVT_ADEVBHOSTEND BIT(20)
599#define DWC3_OEVT_ADEVHOST BIT(19)
600#define DWC3_OEVT_ADEVHNPCHNG BIT(18)
601#define DWC3_OEVT_ADEVSRPDET BIT(17)
602#define DWC3_OEVT_ADEVSESSENDDET BIT(16)
603#define DWC3_OEVT_BDEVBHOSTEND BIT(11)
604#define DWC3_OEVT_BDEVHNPCHNG BIT(10)
605#define DWC3_OEVT_BDEVSESSVLDDET BIT(9)
606#define DWC3_OEVT_BDEVVBUSCHNG BIT(8)
607#define DWC3_OEVT_BSESSVLD BIT(3)
608#define DWC3_OEVT_HSTNEGSTS BIT(2)
609#define DWC3_OEVT_SESREQSTS BIT(1)
610#define DWC3_OEVT_ERROR BIT(0)
611
612
613#define DWC3_OEVTEN_XHCIRUNSTPSETEN BIT(27)
614#define DWC3_OEVTEN_DEVRUNSTPSETEN BIT(26)
615#define DWC3_OEVTEN_HIBENTRYEN BIT(25)
616#define DWC3_OEVTEN_CONIDSTSCHNGEN BIT(24)
617#define DWC3_OEVTEN_HRRCONFNOTIFEN BIT(23)
618#define DWC3_OEVTEN_HRRINITNOTIFEN BIT(22)
619#define DWC3_OEVTEN_ADEVIDLEEN BIT(21)
620#define DWC3_OEVTEN_ADEVBHOSTENDEN BIT(20)
621#define DWC3_OEVTEN_ADEVHOSTEN BIT(19)
622#define DWC3_OEVTEN_ADEVHNPCHNGEN BIT(18)
623#define DWC3_OEVTEN_ADEVSRPDETEN BIT(17)
624#define DWC3_OEVTEN_ADEVSESSENDDETEN BIT(16)
625#define DWC3_OEVTEN_BDEVBHOSTENDEN BIT(11)
626#define DWC3_OEVTEN_BDEVHNPCHNGEN BIT(10)
627#define DWC3_OEVTEN_BDEVSESSVLDDETEN BIT(9)
628#define DWC3_OEVTEN_BDEVVBUSCHNGEN BIT(8)
629
630
631#define DWC3_OSTS_DEVRUNSTP BIT(13)
632#define DWC3_OSTS_XHCIRUNSTP BIT(12)
633#define DWC3_OSTS_PERIPHERALSTATE BIT(4)
634#define DWC3_OSTS_XHCIPRTPOWER BIT(3)
635#define DWC3_OSTS_BSESVLD BIT(2)
636#define DWC3_OSTS_VBUSVLD BIT(1)
637#define DWC3_OSTS_CONIDSTS BIT(0)
638
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640
641struct dwc3_trb;
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654struct dwc3_event_buffer {
655 void *buf;
656 void *cache;
657 unsigned int length;
658 unsigned int lpos;
659 unsigned int count;
660 unsigned int flags;
661
662#define DWC3_EVENT_PENDING BIT(0)
663
664 dma_addr_t dma;
665
666 struct dwc3 *dwc;
667};
668
669#define DWC3_EP_FLAG_STALLED BIT(0)
670#define DWC3_EP_FLAG_WEDGED BIT(1)
671
672#define DWC3_EP_DIRECTION_TX true
673#define DWC3_EP_DIRECTION_RX false
674
675#define DWC3_TRB_NUM 256
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704struct dwc3_ep {
705 struct usb_ep endpoint;
706 struct list_head cancelled_list;
707 struct list_head pending_list;
708 struct list_head started_list;
709
710 void __iomem *regs;
711
712 struct dwc3_trb *trb_pool;
713 dma_addr_t trb_pool_dma;
714 struct dwc3 *dwc;
715
716 u32 saved_state;
717 unsigned int flags;
718#define DWC3_EP_ENABLED BIT(0)
719#define DWC3_EP_STALL BIT(1)
720#define DWC3_EP_WEDGE BIT(2)
721#define DWC3_EP_TRANSFER_STARTED BIT(3)
722#define DWC3_EP_END_TRANSFER_PENDING BIT(4)
723#define DWC3_EP_PENDING_REQUEST BIT(5)
724#define DWC3_EP_DELAY_START BIT(6)
725#define DWC3_EP_WAIT_TRANSFER_COMPLETE BIT(7)
726#define DWC3_EP_IGNORE_NEXT_NOSTREAM BIT(8)
727#define DWC3_EP_FORCE_RESTART_STREAM BIT(9)
728#define DWC3_EP_FIRST_STREAM_PRIMED BIT(10)
729#define DWC3_EP_PENDING_CLEAR_STALL BIT(11)
730#define DWC3_EP_TXFIFO_RESIZED BIT(12)
731
732
733#define DWC3_EP0_DIR_IN BIT(31)
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743
744 u8 trb_enqueue;
745 u8 trb_dequeue;
746
747 u8 number;
748 u8 type;
749 u8 resource_index;
750 u32 frame_number;
751 u32 interval;
752
753 char name[20];
754
755 unsigned direction:1;
756 unsigned stream_capable:1;
757
758
759 u8 combo_num;
760 int start_cmd_status;
761};
762
763enum dwc3_phy {
764 DWC3_PHY_UNKNOWN = 0,
765 DWC3_PHY_USB3,
766 DWC3_PHY_USB2,
767};
768
769enum dwc3_ep0_next {
770 DWC3_EP0_UNKNOWN = 0,
771 DWC3_EP0_COMPLETE,
772 DWC3_EP0_NRDY_DATA,
773 DWC3_EP0_NRDY_STATUS,
774};
775
776enum dwc3_ep0_state {
777 EP0_UNCONNECTED = 0,
778 EP0_SETUP_PHASE,
779 EP0_DATA_PHASE,
780 EP0_STATUS_PHASE,
781};
782
783enum dwc3_link_state {
784
785 DWC3_LINK_STATE_U0 = 0x00,
786 DWC3_LINK_STATE_U1 = 0x01,
787 DWC3_LINK_STATE_U2 = 0x02,
788 DWC3_LINK_STATE_U3 = 0x03,
789 DWC3_LINK_STATE_SS_DIS = 0x04,
790 DWC3_LINK_STATE_RX_DET = 0x05,
791 DWC3_LINK_STATE_SS_INACT = 0x06,
792 DWC3_LINK_STATE_POLL = 0x07,
793 DWC3_LINK_STATE_RECOV = 0x08,
794 DWC3_LINK_STATE_HRESET = 0x09,
795 DWC3_LINK_STATE_CMPLY = 0x0a,
796 DWC3_LINK_STATE_LPBK = 0x0b,
797 DWC3_LINK_STATE_RESET = 0x0e,
798 DWC3_LINK_STATE_RESUME = 0x0f,
799 DWC3_LINK_STATE_MASK = 0x0f,
800};
801
802
803#define DWC3_TRB_SIZE_MASK (0x00ffffff)
804#define DWC3_TRB_SIZE_LENGTH(n) ((n) & DWC3_TRB_SIZE_MASK)
805#define DWC3_TRB_SIZE_PCM1(n) (((n) & 0x03) << 24)
806#define DWC3_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28)) >> 28)
807
808#define DWC3_TRBSTS_OK 0
809#define DWC3_TRBSTS_MISSED_ISOC 1
810#define DWC3_TRBSTS_SETUP_PENDING 2
811#define DWC3_TRB_STS_XFER_IN_PROG 4
812
813
814#define DWC3_TRB_CTRL_HWO BIT(0)
815#define DWC3_TRB_CTRL_LST BIT(1)
816#define DWC3_TRB_CTRL_CHN BIT(2)
817#define DWC3_TRB_CTRL_CSP BIT(3)
818#define DWC3_TRB_CTRL_TRBCTL(n) (((n) & 0x3f) << 4)
819#define DWC3_TRB_CTRL_ISP_IMI BIT(10)
820#define DWC3_TRB_CTRL_IOC BIT(11)
821#define DWC3_TRB_CTRL_SID_SOFN(n) (((n) & 0xffff) << 14)
822#define DWC3_TRB_CTRL_GET_SID_SOFN(n) (((n) & (0xffff << 14)) >> 14)
823
824#define DWC3_TRBCTL_TYPE(n) ((n) & (0x3f << 4))
825#define DWC3_TRBCTL_NORMAL DWC3_TRB_CTRL_TRBCTL(1)
826#define DWC3_TRBCTL_CONTROL_SETUP DWC3_TRB_CTRL_TRBCTL(2)
827#define DWC3_TRBCTL_CONTROL_STATUS2 DWC3_TRB_CTRL_TRBCTL(3)
828#define DWC3_TRBCTL_CONTROL_STATUS3 DWC3_TRB_CTRL_TRBCTL(4)
829#define DWC3_TRBCTL_CONTROL_DATA DWC3_TRB_CTRL_TRBCTL(5)
830#define DWC3_TRBCTL_ISOCHRONOUS_FIRST DWC3_TRB_CTRL_TRBCTL(6)
831#define DWC3_TRBCTL_ISOCHRONOUS DWC3_TRB_CTRL_TRBCTL(7)
832#define DWC3_TRBCTL_LINK_TRB DWC3_TRB_CTRL_TRBCTL(8)
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841struct dwc3_trb {
842 u32 bpl;
843 u32 bph;
844 u32 size;
845 u32 ctrl;
846} __packed;
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861struct dwc3_hwparams {
862 u32 hwparams0;
863 u32 hwparams1;
864 u32 hwparams2;
865 u32 hwparams3;
866 u32 hwparams4;
867 u32 hwparams5;
868 u32 hwparams6;
869 u32 hwparams7;
870 u32 hwparams8;
871 u32 hwparams9;
872};
873
874
875#define DWC3_MODE(n) ((n) & 0x7)
876
877
878#define DWC3_NUM_INT(n) (((n) & (0x3f << 15)) >> 15)
879
880
881#define DWC3_NUM_IN_EPS_MASK (0x1f << 18)
882#define DWC3_NUM_EPS_MASK (0x3f << 12)
883#define DWC3_NUM_EPS(p) (((p)->hwparams3 & \
884 (DWC3_NUM_EPS_MASK)) >> 12)
885#define DWC3_NUM_IN_EPS(p) (((p)->hwparams3 & \
886 (DWC3_NUM_IN_EPS_MASK)) >> 18)
887
888
889#define DWC3_RAM1_DEPTH(n) ((n) & 0xffff)
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911struct dwc3_request {
912 struct usb_request request;
913 struct list_head list;
914 struct dwc3_ep *dep;
915 struct scatterlist *sg;
916 struct scatterlist *start_sg;
917
918 unsigned int num_pending_sgs;
919 unsigned int num_queued_sgs;
920 unsigned int remaining;
921
922 unsigned int status;
923#define DWC3_REQUEST_STATUS_QUEUED 0
924#define DWC3_REQUEST_STATUS_STARTED 1
925#define DWC3_REQUEST_STATUS_DISCONNECTED 2
926#define DWC3_REQUEST_STATUS_DEQUEUED 3
927#define DWC3_REQUEST_STATUS_STALLED 4
928#define DWC3_REQUEST_STATUS_COMPLETED 5
929#define DWC3_REQUEST_STATUS_UNKNOWN -1
930
931 u8 epnum;
932 struct dwc3_trb *trb;
933 dma_addr_t trb_dma;
934
935 unsigned int num_trbs;
936
937 unsigned int needs_extra_trb:1;
938 unsigned int direction:1;
939 unsigned int mapped:1;
940};
941
942
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944
945
946struct dwc3_scratchpad_array {
947 __le64 dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS];
948};
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1098struct dwc3 {
1099 struct work_struct drd_work;
1100 struct dwc3_trb *ep0_trb;
1101 void *bounce;
1102 void *scratchbuf;
1103 u8 *setup_buf;
1104 dma_addr_t ep0_trb_addr;
1105 dma_addr_t bounce_addr;
1106 dma_addr_t scratch_addr;
1107 struct dwc3_request ep0_usb_req;
1108 struct completion ep0_in_setup;
1109
1110
1111 spinlock_t lock;
1112
1113
1114 struct mutex mutex;
1115
1116 struct device *dev;
1117 struct device *sysdev;
1118
1119 struct platform_device *xhci;
1120 struct resource xhci_resources[DWC3_XHCI_RESOURCES_NUM];
1121
1122 struct dwc3_event_buffer *ev_buf;
1123 struct dwc3_ep *eps[DWC3_ENDPOINTS_NUM];
1124
1125 struct usb_gadget *gadget;
1126 struct usb_gadget_driver *gadget_driver;
1127
1128 struct clk_bulk_data *clks;
1129 int num_clks;
1130
1131 struct reset_control *reset;
1132
1133 struct usb_phy *usb2_phy;
1134 struct usb_phy *usb3_phy;
1135
1136 struct phy *usb2_generic_phy;
1137 struct phy *usb3_generic_phy;
1138
1139 bool phys_ready;
1140
1141 struct ulpi *ulpi;
1142 bool ulpi_ready;
1143
1144 void __iomem *regs;
1145 size_t regs_size;
1146
1147 enum usb_dr_mode dr_mode;
1148 u32 current_dr_role;
1149 u32 desired_dr_role;
1150 struct extcon_dev *edev;
1151 struct notifier_block edev_nb;
1152 enum usb_phy_interface hsphy_mode;
1153 struct usb_role_switch *role_sw;
1154 enum usb_dr_mode role_switch_default_mode;
1155
1156 struct power_supply *usb_psy;
1157
1158 u32 fladj;
1159 u32 ref_clk_per;
1160 u32 irq_gadget;
1161 u32 otg_irq;
1162 u32 current_otg_role;
1163 u32 desired_otg_role;
1164 bool otg_restart_host;
1165 u32 nr_scratch;
1166 u32 u1u2;
1167 u32 maximum_speed;
1168 u32 gadget_max_speed;
1169 enum usb_ssp_rate max_ssp_rate;
1170 enum usb_ssp_rate gadget_ssp_rate;
1171
1172 u32 ip;
1173
1174#define DWC3_IP 0x5533
1175#define DWC31_IP 0x3331
1176#define DWC32_IP 0x3332
1177
1178 u32 revision;
1179
1180#define DWC3_REVISION_ANY 0x0
1181#define DWC3_REVISION_173A 0x5533173a
1182#define DWC3_REVISION_175A 0x5533175a
1183#define DWC3_REVISION_180A 0x5533180a
1184#define DWC3_REVISION_183A 0x5533183a
1185#define DWC3_REVISION_185A 0x5533185a
1186#define DWC3_REVISION_187A 0x5533187a
1187#define DWC3_REVISION_188A 0x5533188a
1188#define DWC3_REVISION_190A 0x5533190a
1189#define DWC3_REVISION_194A 0x5533194a
1190#define DWC3_REVISION_200A 0x5533200a
1191#define DWC3_REVISION_202A 0x5533202a
1192#define DWC3_REVISION_210A 0x5533210a
1193#define DWC3_REVISION_220A 0x5533220a
1194#define DWC3_REVISION_230A 0x5533230a
1195#define DWC3_REVISION_240A 0x5533240a
1196#define DWC3_REVISION_250A 0x5533250a
1197#define DWC3_REVISION_260A 0x5533260a
1198#define DWC3_REVISION_270A 0x5533270a
1199#define DWC3_REVISION_280A 0x5533280a
1200#define DWC3_REVISION_290A 0x5533290a
1201#define DWC3_REVISION_300A 0x5533300a
1202#define DWC3_REVISION_310A 0x5533310a
1203#define DWC3_REVISION_330A 0x5533330a
1204
1205#define DWC31_REVISION_ANY 0x0
1206#define DWC31_REVISION_110A 0x3131302a
1207#define DWC31_REVISION_120A 0x3132302a
1208#define DWC31_REVISION_160A 0x3136302a
1209#define DWC31_REVISION_170A 0x3137302a
1210#define DWC31_REVISION_180A 0x3138302a
1211#define DWC31_REVISION_190A 0x3139302a
1212
1213#define DWC32_REVISION_ANY 0x0
1214#define DWC32_REVISION_100A 0x3130302a
1215
1216 u32 version_type;
1217
1218#define DWC31_VERSIONTYPE_ANY 0x0
1219#define DWC31_VERSIONTYPE_EA01 0x65613031
1220#define DWC31_VERSIONTYPE_EA02 0x65613032
1221#define DWC31_VERSIONTYPE_EA03 0x65613033
1222#define DWC31_VERSIONTYPE_EA04 0x65613034
1223#define DWC31_VERSIONTYPE_EA05 0x65613035
1224#define DWC31_VERSIONTYPE_EA06 0x65613036
1225
1226 enum dwc3_ep0_next ep0_next_event;
1227 enum dwc3_ep0_state ep0state;
1228 enum dwc3_link_state link_state;
1229
1230 u16 u2sel;
1231 u16 u2pel;
1232 u8 u1sel;
1233 u8 u1pel;
1234
1235 u8 speed;
1236
1237 u8 num_eps;
1238
1239 struct dwc3_hwparams hwparams;
1240 struct debugfs_regset32 *regset;
1241
1242 u32 dbg_lsp_select;
1243
1244 u8 test_mode;
1245 u8 test_mode_nr;
1246 u8 lpm_nyet_threshold;
1247 u8 hird_threshold;
1248 u8 rx_thr_num_pkt_prd;
1249 u8 rx_max_burst_prd;
1250 u8 tx_thr_num_pkt_prd;
1251 u8 tx_max_burst_prd;
1252 u8 tx_fifo_resize_max_num;
1253
1254 const char *hsphy_interface;
1255
1256 unsigned connected:1;
1257 unsigned softconnect:1;
1258 unsigned delayed_status:1;
1259 unsigned ep0_bounced:1;
1260 unsigned ep0_expect_in:1;
1261 unsigned has_hibernation:1;
1262 unsigned sysdev_is_parent:1;
1263 unsigned has_lpm_erratum:1;
1264 unsigned is_utmi_l1_suspend:1;
1265 unsigned is_fpga:1;
1266 unsigned pending_events:1;
1267 unsigned do_fifo_resize:1;
1268 unsigned pullups_connected:1;
1269 unsigned setup_packet_pending:1;
1270 unsigned three_stage_setup:1;
1271 unsigned dis_start_transfer_quirk:1;
1272 unsigned usb3_lpm_capable:1;
1273 unsigned usb2_lpm_disable:1;
1274 unsigned usb2_gadget_lpm_disable:1;
1275
1276 unsigned disable_scramble_quirk:1;
1277 unsigned u2exit_lfps_quirk:1;
1278 unsigned u2ss_inp3_quirk:1;
1279 unsigned req_p1p2p3_quirk:1;
1280 unsigned del_p1p2p3_quirk:1;
1281 unsigned del_phy_power_chg_quirk:1;
1282 unsigned lfps_filter_quirk:1;
1283 unsigned rx_detect_poll_quirk:1;
1284 unsigned dis_u3_susphy_quirk:1;
1285 unsigned dis_u2_susphy_quirk:1;
1286 unsigned dis_enblslpm_quirk:1;
1287 unsigned dis_u1_entry_quirk:1;
1288 unsigned dis_u2_entry_quirk:1;
1289 unsigned dis_rxdet_inp3_quirk:1;
1290 unsigned dis_u2_freeclk_exists_quirk:1;
1291 unsigned dis_del_phy_power_chg_quirk:1;
1292 unsigned dis_tx_ipgap_linecheck_quirk:1;
1293 unsigned parkmode_disable_ss_quirk:1;
1294
1295 unsigned tx_de_emphasis_quirk:1;
1296 unsigned tx_de_emphasis:2;
1297
1298 unsigned dis_metastability_quirk:1;
1299
1300 unsigned dis_split_quirk:1;
1301 unsigned async_callbacks:1;
1302
1303 u16 imod_interval;
1304
1305 int max_cfg_eps;
1306 int last_fifo_depth;
1307 int num_ep_resized;
1308};
1309
1310#define INCRX_BURST_MODE 0
1311#define INCRX_UNDEF_LENGTH_BURST_MODE 1
1312
1313#define work_to_dwc(w) (container_of((w), struct dwc3, drd_work))
1314
1315
1316
1317struct dwc3_event_type {
1318 u32 is_devspec:1;
1319 u32 type:7;
1320 u32 reserved8_31:24;
1321} __packed;
1322
1323#define DWC3_DEPEVT_XFERCOMPLETE 0x01
1324#define DWC3_DEPEVT_XFERINPROGRESS 0x02
1325#define DWC3_DEPEVT_XFERNOTREADY 0x03
1326#define DWC3_DEPEVT_RXTXFIFOEVT 0x04
1327#define DWC3_DEPEVT_STREAMEVT 0x06
1328#define DWC3_DEPEVT_EPCMDCMPLT 0x07
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
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1344
1345
1346
1347
1348
1349struct dwc3_event_depevt {
1350 u32 one_bit:1;
1351 u32 endpoint_number:5;
1352 u32 endpoint_event:4;
1353 u32 reserved11_10:2;
1354 u32 status:4;
1355
1356
1357#define DEPEVT_STATUS_TRANSFER_ACTIVE BIT(3)
1358
1359
1360#define DEPEVT_STATUS_BUSERR BIT(0)
1361#define DEPEVT_STATUS_SHORT BIT(1)
1362#define DEPEVT_STATUS_IOC BIT(2)
1363#define DEPEVT_STATUS_LST BIT(3)
1364#define DEPEVT_STATUS_MISSED_ISOC BIT(3)
1365
1366
1367#define DEPEVT_STREAMEVT_FOUND 1
1368#define DEPEVT_STREAMEVT_NOTFOUND 2
1369
1370
1371#define DEPEVT_STREAM_PRIME 0xfffe
1372#define DEPEVT_STREAM_NOSTREAM 0x0
1373
1374
1375#define DEPEVT_STATUS_CONTROL_DATA 1
1376#define DEPEVT_STATUS_CONTROL_STATUS 2
1377#define DEPEVT_STATUS_CONTROL_PHASE(n) ((n) & 3)
1378
1379
1380#define DEPEVT_TRANSFER_NO_RESOURCE 1
1381#define DEPEVT_TRANSFER_BUS_EXPIRY 2
1382
1383 u32 parameters:16;
1384
1385
1386#define DEPEVT_PARAMETER_CMD(n) (((n) & (0xf << 8)) >> 8)
1387} __packed;
1388
1389
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1400
1401
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1409
1410
1411struct dwc3_event_devt {
1412 u32 one_bit:1;
1413 u32 device_event:7;
1414 u32 type:4;
1415 u32 reserved15_12:4;
1416 u32 event_info:9;
1417 u32 reserved31_25:7;
1418} __packed;
1419
1420
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1423
1424
1425
1426
1427struct dwc3_event_gevt {
1428 u32 one_bit:1;
1429 u32 device_event:7;
1430 u32 phy_port_number:4;
1431 u32 reserved31_12:20;
1432} __packed;
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442union dwc3_event {
1443 u32 raw;
1444 struct dwc3_event_type type;
1445 struct dwc3_event_depevt depevt;
1446 struct dwc3_event_devt devt;
1447 struct dwc3_event_gevt gevt;
1448};
1449
1450
1451
1452
1453
1454
1455
1456
1457struct dwc3_gadget_ep_cmd_params {
1458 u32 param2;
1459 u32 param1;
1460 u32 param0;
1461};
1462
1463
1464
1465
1466
1467#define DWC3_HAS_PERIPHERAL BIT(0)
1468#define DWC3_HAS_XHCI BIT(1)
1469#define DWC3_HAS_OTG BIT(3)
1470
1471
1472void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode);
1473void dwc3_set_mode(struct dwc3 *dwc, u32 mode);
1474u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type);
1475
1476#define DWC3_IP_IS(_ip) \
1477 (dwc->ip == _ip##_IP)
1478
1479#define DWC3_VER_IS(_ip, _ver) \
1480 (DWC3_IP_IS(_ip) && dwc->revision == _ip##_REVISION_##_ver)
1481
1482#define DWC3_VER_IS_PRIOR(_ip, _ver) \
1483 (DWC3_IP_IS(_ip) && dwc->revision < _ip##_REVISION_##_ver)
1484
1485#define DWC3_VER_IS_WITHIN(_ip, _from, _to) \
1486 (DWC3_IP_IS(_ip) && \
1487 dwc->revision >= _ip##_REVISION_##_from && \
1488 (!(_ip##_REVISION_##_to) || \
1489 dwc->revision <= _ip##_REVISION_##_to))
1490
1491#define DWC3_VER_TYPE_IS_WITHIN(_ip, _ver, _from, _to) \
1492 (DWC3_VER_IS(_ip, _ver) && \
1493 dwc->version_type >= _ip##_VERSIONTYPE_##_from && \
1494 (!(_ip##_VERSIONTYPE_##_to) || \
1495 dwc->version_type <= _ip##_VERSIONTYPE_##_to))
1496
1497
1498
1499
1500
1501
1502
1503static inline u32 dwc3_mdwidth(struct dwc3 *dwc)
1504{
1505 u32 mdwidth;
1506
1507 mdwidth = DWC3_GHWPARAMS0_MDWIDTH(dwc->hwparams.hwparams0);
1508 if (DWC3_IP_IS(DWC32))
1509 mdwidth += DWC3_GHWPARAMS6_MDWIDTH(dwc->hwparams.hwparams6);
1510
1511 return mdwidth;
1512}
1513
1514bool dwc3_has_imod(struct dwc3 *dwc);
1515
1516int dwc3_event_buffers_setup(struct dwc3 *dwc);
1517void dwc3_event_buffers_cleanup(struct dwc3 *dwc);
1518
1519#if IS_ENABLED(CONFIG_USB_DWC3_HOST) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
1520int dwc3_host_init(struct dwc3 *dwc);
1521void dwc3_host_exit(struct dwc3 *dwc);
1522#else
1523static inline int dwc3_host_init(struct dwc3 *dwc)
1524{ return 0; }
1525static inline void dwc3_host_exit(struct dwc3 *dwc)
1526{ }
1527#endif
1528
1529#if IS_ENABLED(CONFIG_USB_DWC3_GADGET) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
1530int dwc3_gadget_init(struct dwc3 *dwc);
1531void dwc3_gadget_exit(struct dwc3 *dwc);
1532int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode);
1533int dwc3_gadget_get_link_state(struct dwc3 *dwc);
1534int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state);
1535int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned int cmd,
1536 struct dwc3_gadget_ep_cmd_params *params);
1537int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned int cmd,
1538 u32 param);
1539void dwc3_gadget_clear_tx_fifos(struct dwc3 *dwc);
1540#else
1541static inline int dwc3_gadget_init(struct dwc3 *dwc)
1542{ return 0; }
1543static inline void dwc3_gadget_exit(struct dwc3 *dwc)
1544{ }
1545static inline int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
1546{ return 0; }
1547static inline int dwc3_gadget_get_link_state(struct dwc3 *dwc)
1548{ return 0; }
1549static inline int dwc3_gadget_set_link_state(struct dwc3 *dwc,
1550 enum dwc3_link_state state)
1551{ return 0; }
1552
1553static inline int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned int cmd,
1554 struct dwc3_gadget_ep_cmd_params *params)
1555{ return 0; }
1556static inline int dwc3_send_gadget_generic_command(struct dwc3 *dwc,
1557 int cmd, u32 param)
1558{ return 0; }
1559static inline void dwc3_gadget_clear_tx_fifos(struct dwc3 *dwc)
1560{ }
1561#endif
1562
1563#if IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
1564int dwc3_drd_init(struct dwc3 *dwc);
1565void dwc3_drd_exit(struct dwc3 *dwc);
1566void dwc3_otg_init(struct dwc3 *dwc);
1567void dwc3_otg_exit(struct dwc3 *dwc);
1568void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus);
1569void dwc3_otg_host_init(struct dwc3 *dwc);
1570#else
1571static inline int dwc3_drd_init(struct dwc3 *dwc)
1572{ return 0; }
1573static inline void dwc3_drd_exit(struct dwc3 *dwc)
1574{ }
1575static inline void dwc3_otg_init(struct dwc3 *dwc)
1576{ }
1577static inline void dwc3_otg_exit(struct dwc3 *dwc)
1578{ }
1579static inline void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus)
1580{ }
1581static inline void dwc3_otg_host_init(struct dwc3 *dwc)
1582{ }
1583#endif
1584
1585
1586#if !IS_ENABLED(CONFIG_USB_DWC3_HOST)
1587int dwc3_gadget_suspend(struct dwc3 *dwc);
1588int dwc3_gadget_resume(struct dwc3 *dwc);
1589void dwc3_gadget_process_pending_events(struct dwc3 *dwc);
1590#else
1591static inline int dwc3_gadget_suspend(struct dwc3 *dwc)
1592{
1593 return 0;
1594}
1595
1596static inline int dwc3_gadget_resume(struct dwc3 *dwc)
1597{
1598 return 0;
1599}
1600
1601static inline void dwc3_gadget_process_pending_events(struct dwc3 *dwc)
1602{
1603}
1604#endif
1605
1606#if IS_ENABLED(CONFIG_USB_DWC3_ULPI)
1607int dwc3_ulpi_init(struct dwc3 *dwc);
1608void dwc3_ulpi_exit(struct dwc3 *dwc);
1609#else
1610static inline int dwc3_ulpi_init(struct dwc3 *dwc)
1611{ return 0; }
1612static inline void dwc3_ulpi_exit(struct dwc3 *dwc)
1613{ }
1614#endif
1615
1616#endif
1617