1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Copyright (c) 2021 MediaTek Inc. 4 * Author: Chun-Jie Chen <chun-jie.chen@mediatek.com> 5 */ 6 7#ifndef _DT_BINDINGS_CLK_MT8192_H 8#define _DT_BINDINGS_CLK_MT8192_H 9 10/* TOPCKGEN */ 11 12#define CLK_TOP_AXI_SEL 0 13#define CLK_TOP_SPM_SEL 1 14#define CLK_TOP_SCP_SEL 2 15#define CLK_TOP_BUS_AXIMEM_SEL 3 16#define CLK_TOP_DISP_SEL 4 17#define CLK_TOP_MDP_SEL 5 18#define CLK_TOP_IMG1_SEL 6 19#define CLK_TOP_IMG2_SEL 7 20#define CLK_TOP_IPE_SEL 8 21#define CLK_TOP_DPE_SEL 9 22#define CLK_TOP_CAM_SEL 10 23#define CLK_TOP_CCU_SEL 11 24#define CLK_TOP_DSP7_SEL 12 25#define CLK_TOP_MFG_REF_SEL 13 26#define CLK_TOP_MFG_PLL_SEL 14 27#define CLK_TOP_CAMTG_SEL 15 28#define CLK_TOP_CAMTG2_SEL 16 29#define CLK_TOP_CAMTG3_SEL 17 30#define CLK_TOP_CAMTG4_SEL 18 31#define CLK_TOP_CAMTG5_SEL 19 32#define CLK_TOP_CAMTG6_SEL 20 33#define CLK_TOP_UART_SEL 21 34#define CLK_TOP_SPI_SEL 22 35#define CLK_TOP_MSDC50_0_H_SEL 23 36#define CLK_TOP_MSDC50_0_SEL 24 37#define CLK_TOP_MSDC30_1_SEL 25 38#define CLK_TOP_MSDC30_2_SEL 26 39#define CLK_TOP_AUDIO_SEL 27 40#define CLK_TOP_AUD_INTBUS_SEL 28 41#define CLK_TOP_PWRAP_ULPOSC_SEL 29 42#define CLK_TOP_ATB_SEL 30 43#define CLK_TOP_DPI_SEL 31 44#define CLK_TOP_SCAM_SEL 32 45#define CLK_TOP_DISP_PWM_SEL 33 46#define CLK_TOP_USB_TOP_SEL 34 47#define CLK_TOP_SSUSB_XHCI_SEL 35 48#define CLK_TOP_I2C_SEL 36 49#define CLK_TOP_SENINF_SEL 37 50#define CLK_TOP_SENINF1_SEL 38 51#define CLK_TOP_SENINF2_SEL 39 52#define CLK_TOP_SENINF3_SEL 40 53#define CLK_TOP_TL_SEL 41 54#define CLK_TOP_DXCC_SEL 42 55#define CLK_TOP_AUD_ENGEN1_SEL 43 56#define CLK_TOP_AUD_ENGEN2_SEL 44 57#define CLK_TOP_AES_UFSFDE_SEL 45 58#define CLK_TOP_UFS_SEL 46 59#define CLK_TOP_AUD_1_SEL 47 60#define CLK_TOP_AUD_2_SEL 48 61#define CLK_TOP_ADSP_SEL 49 62#define CLK_TOP_DPMAIF_MAIN_SEL 50 63#define CLK_TOP_VENC_SEL 51 64#define CLK_TOP_VDEC_SEL 52 65#define CLK_TOP_CAMTM_SEL 53 66#define CLK_TOP_PWM_SEL 54 67#define CLK_TOP_AUDIO_H_SEL 55 68#define CLK_TOP_SPMI_MST_SEL 56 69#define CLK_TOP_AES_MSDCFDE_SEL 57 70#define CLK_TOP_SFLASH_SEL 58 71#define CLK_TOP_APLL_I2S0_M_SEL 59 72#define CLK_TOP_APLL_I2S1_M_SEL 60 73#define CLK_TOP_APLL_I2S2_M_SEL 61 74#define CLK_TOP_APLL_I2S3_M_SEL 62 75#define CLK_TOP_APLL_I2S4_M_SEL 63 76#define CLK_TOP_APLL_I2S5_M_SEL 64 77#define CLK_TOP_APLL_I2S6_M_SEL 65 78#define CLK_TOP_APLL_I2S7_M_SEL 66 79#define CLK_TOP_APLL_I2S8_M_SEL 67 80#define CLK_TOP_APLL_I2S9_M_SEL 68 81#define CLK_TOP_MAINPLL_D3 69 82#define CLK_TOP_MAINPLL_D4 70 83#define CLK_TOP_MAINPLL_D4_D2 71 84#define CLK_TOP_MAINPLL_D4_D4 72 85#define CLK_TOP_MAINPLL_D4_D8 73 86#define CLK_TOP_MAINPLL_D4_D16 74 87#define CLK_TOP_MAINPLL_D5 75 88#define CLK_TOP_MAINPLL_D5_D2 76 89#define CLK_TOP_MAINPLL_D5_D4 77 90#define CLK_TOP_MAINPLL_D5_D8 78 91#define CLK_TOP_MAINPLL_D6 79 92#define CLK_TOP_MAINPLL_D6_D2 80 93#define CLK_TOP_MAINPLL_D6_D4 81 94#define CLK_TOP_MAINPLL_D7 82 95#define CLK_TOP_MAINPLL_D7_D2 83 96#define CLK_TOP_MAINPLL_D7_D4 84 97#define CLK_TOP_MAINPLL_D7_D8 85 98#define CLK_TOP_UNIVPLL_D3 86 99#define CLK_TOP_UNIVPLL_D4 87 100#define CLK_TOP_UNIVPLL_D4_D2 88 101#define CLK_TOP_UNIVPLL_D4_D4 89 102#define CLK_TOP_UNIVPLL_D4_D8 90 103#define CLK_TOP_UNIVPLL_D5 91 104#define CLK_TOP_UNIVPLL_D5_D2 92 105#define CLK_TOP_UNIVPLL_D5_D4 93 106#define CLK_TOP_UNIVPLL_D5_D8 94 107#define CLK_TOP_UNIVPLL_D6 95 108#define CLK_TOP_UNIVPLL_D6_D2 96 109#define CLK_TOP_UNIVPLL_D6_D4 97 110#define CLK_TOP_UNIVPLL_D6_D8 98 111#define CLK_TOP_UNIVPLL_D6_D16 99 112#define CLK_TOP_UNIVPLL_D7 100 113#define CLK_TOP_APLL1 101 114#define CLK_TOP_APLL1_D2 102 115#define CLK_TOP_APLL1_D4 103 116#define CLK_TOP_APLL1_D8 104 117#define CLK_TOP_APLL2 105 118#define CLK_TOP_APLL2_D2 106 119#define CLK_TOP_APLL2_D4 107 120#define CLK_TOP_APLL2_D8 108 121#define CLK_TOP_MMPLL_D4 109 122#define CLK_TOP_MMPLL_D4_D2 110 123#define CLK_TOP_MMPLL_D5 111 124#define CLK_TOP_MMPLL_D5_D2 112 125#define CLK_TOP_MMPLL_D6 113 126#define CLK_TOP_MMPLL_D6_D2 114 127#define CLK_TOP_MMPLL_D7 115 128#define CLK_TOP_MMPLL_D9 116 129#define CLK_TOP_APUPLL 117 130#define CLK_TOP_NPUPLL 118 131#define CLK_TOP_TVDPLL 119 132#define CLK_TOP_TVDPLL_D2 120 133#define CLK_TOP_TVDPLL_D4 121 134#define CLK_TOP_TVDPLL_D8 122 135#define CLK_TOP_TVDPLL_D16 123 136#define CLK_TOP_MSDCPLL 124 137#define CLK_TOP_MSDCPLL_D2 125 138#define CLK_TOP_MSDCPLL_D4 126 139#define CLK_TOP_ULPOSC 127 140#define CLK_TOP_OSC_D2 128 141#define CLK_TOP_OSC_D4 129 142#define CLK_TOP_OSC_D8 130 143#define CLK_TOP_OSC_D10 131 144#define CLK_TOP_OSC_D16 132 145#define CLK_TOP_OSC_D20 133 146#define CLK_TOP_CSW_F26M_D2 134 147#define CLK_TOP_ADSPPLL 135 148#define CLK_TOP_UNIVPLL_192M 136 149#define CLK_TOP_UNIVPLL_192M_D2 137 150#define CLK_TOP_UNIVPLL_192M_D4 138 151#define CLK_TOP_UNIVPLL_192M_D8 139 152#define CLK_TOP_UNIVPLL_192M_D16 140 153#define CLK_TOP_UNIVPLL_192M_D32 141 154#define CLK_TOP_APLL12_DIV0 142 155#define CLK_TOP_APLL12_DIV1 143 156#define CLK_TOP_APLL12_DIV2 144 157#define CLK_TOP_APLL12_DIV3 145 158#define CLK_TOP_APLL12_DIV4 146 159#define CLK_TOP_APLL12_DIVB 147 160#define CLK_TOP_APLL12_DIV5 148 161#define CLK_TOP_APLL12_DIV6 149 162#define CLK_TOP_APLL12_DIV7 150 163#define CLK_TOP_APLL12_DIV8 151 164#define CLK_TOP_APLL12_DIV9 152 165#define CLK_TOP_SSUSB_TOP_REF 153 166#define CLK_TOP_SSUSB_PHY_REF 154 167#define CLK_TOP_NR_CLK 155 168 169/* INFRACFG */ 170 171#define CLK_INFRA_PMIC_TMR 0 172#define CLK_INFRA_PMIC_AP 1 173#define CLK_INFRA_PMIC_MD 2 174#define CLK_INFRA_PMIC_CONN 3 175#define CLK_INFRA_SCPSYS 4 176#define CLK_INFRA_SEJ 5 177#define CLK_INFRA_APXGPT 6 178#define CLK_INFRA_GCE 7 179#define CLK_INFRA_GCE2 8 180#define CLK_INFRA_THERM 9 181#define CLK_INFRA_I2C0 10 182#define CLK_INFRA_AP_DMA_PSEUDO 11 183#define CLK_INFRA_I2C2 12 184#define CLK_INFRA_I2C3 13 185#define CLK_INFRA_PWM_H 14 186#define CLK_INFRA_PWM1 15 187#define CLK_INFRA_PWM2 16 188#define CLK_INFRA_PWM3 17 189#define CLK_INFRA_PWM4 18 190#define CLK_INFRA_PWM 19 191#define CLK_INFRA_UART0 20 192#define CLK_INFRA_UART1 21 193#define CLK_INFRA_UART2 22 194#define CLK_INFRA_UART3 23 195#define CLK_INFRA_GCE_26M 24 196#define CLK_INFRA_CQ_DMA_FPC 25 197#define CLK_INFRA_BTIF 26 198#define CLK_INFRA_SPI0 27 199#define CLK_INFRA_MSDC0 28 200#define CLK_INFRA_MSDC1 29 201#define CLK_INFRA_MSDC2 30 202#define CLK_INFRA_MSDC0_SRC 31 203#define CLK_INFRA_GCPU 32 204#define CLK_INFRA_TRNG 33 205#define CLK_INFRA_AUXADC 34 206#define CLK_INFRA_CPUM 35 207#define CLK_INFRA_CCIF1_AP 36 208#define CLK_INFRA_CCIF1_MD 37 209#define CLK_INFRA_AUXADC_MD 38 210#define CLK_INFRA_PCIE_TL_26M 39 211#define CLK_INFRA_MSDC1_SRC 40 212#define CLK_INFRA_MSDC2_SRC 41 213#define CLK_INFRA_PCIE_TL_96M 42 214#define CLK_INFRA_PCIE_PL_P_250M 43 215#define CLK_INFRA_DEVICE_APC 44 216#define CLK_INFRA_CCIF_AP 45 217#define CLK_INFRA_DEBUGSYS 46 218#define CLK_INFRA_AUDIO 47 219#define CLK_INFRA_CCIF_MD 48 220#define CLK_INFRA_DXCC_SEC_CORE 49 221#define CLK_INFRA_DXCC_AO 50 222#define CLK_INFRA_DBG_TRACE 51 223#define CLK_INFRA_DEVMPU_B 52 224#define CLK_INFRA_DRAMC_F26M 53 225#define CLK_INFRA_IRTX 54 226#define CLK_INFRA_SSUSB 55 227#define CLK_INFRA_DISP_PWM 56 228#define CLK_INFRA_CLDMA_B 57 229#define CLK_INFRA_AUDIO_26M_B 58 230#define CLK_INFRA_MODEM_TEMP_SHARE 59 231#define CLK_INFRA_SPI1 60 232#define CLK_INFRA_I2C4 61 233#define CLK_INFRA_SPI2 62 234#define CLK_INFRA_SPI3 63 235#define CLK_INFRA_UNIPRO_SYS 64 236#define CLK_INFRA_UNIPRO_TICK 65 237#define CLK_INFRA_UFS_MP_SAP_B 66 238#define CLK_INFRA_MD32_B 67 239#define CLK_INFRA_UNIPRO_MBIST 68 240#define CLK_INFRA_I2C5 69 241#define CLK_INFRA_I2C5_ARBITER 70 242#define CLK_INFRA_I2C5_IMM 71 243#define CLK_INFRA_I2C1_ARBITER 72 244#define CLK_INFRA_I2C1_IMM 73 245#define CLK_INFRA_I2C2_ARBITER 74 246#define CLK_INFRA_I2C2_IMM 75 247#define CLK_INFRA_SPI4 76 248#define CLK_INFRA_SPI5 77 249#define CLK_INFRA_CQ_DMA 78 250#define CLK_INFRA_UFS 79 251#define CLK_INFRA_AES_UFSFDE 80 252#define CLK_INFRA_UFS_TICK 81 253#define CLK_INFRA_SSUSB_XHCI 82 254#define CLK_INFRA_MSDC0_SELF 83 255#define CLK_INFRA_MSDC1_SELF 84 256#define CLK_INFRA_MSDC2_SELF 85 257#define CLK_INFRA_UFS_AXI 86 258#define CLK_INFRA_I2C6 87 259#define CLK_INFRA_AP_MSDC0 88 260#define CLK_INFRA_MD_MSDC0 89 261#define CLK_INFRA_CCIF5_AP 90 262#define CLK_INFRA_CCIF5_MD 91 263#define CLK_INFRA_PCIE_TOP_H_133M 92 264#define CLK_INFRA_FLASHIF_TOP_H_133M 93 265#define CLK_INFRA_PCIE_PERI_26M 94 266#define CLK_INFRA_CCIF2_AP 95 267#define CLK_INFRA_CCIF2_MD 96 268#define CLK_INFRA_CCIF3_AP 97 269#define CLK_INFRA_CCIF3_MD 98 270#define CLK_INFRA_SEJ_F13M 99 271#define CLK_INFRA_AES 100 272#define CLK_INFRA_I2C7 101 273#define CLK_INFRA_I2C8 102 274#define CLK_INFRA_FBIST2FPC 103 275#define CLK_INFRA_DEVICE_APC_SYNC 104 276#define CLK_INFRA_DPMAIF_MAIN 105 277#define CLK_INFRA_PCIE_TL_32K 106 278#define CLK_INFRA_CCIF4_AP 107 279#define CLK_INFRA_CCIF4_MD 108 280#define CLK_INFRA_SPI6 109 281#define CLK_INFRA_SPI7 110 282#define CLK_INFRA_133M 111 283#define CLK_INFRA_66M 112 284#define CLK_INFRA_66M_PERI_BUS 113 285#define CLK_INFRA_FREE_DCM_133M 114 286#define CLK_INFRA_FREE_DCM_66M 115 287#define CLK_INFRA_PERI_BUS_DCM_133M 116 288#define CLK_INFRA_PERI_BUS_DCM_66M 117 289#define CLK_INFRA_FLASHIF_PERI_26M 118 290#define CLK_INFRA_FLASHIF_SFLASH 119 291#define CLK_INFRA_AP_DMA 120 292#define CLK_INFRA_NR_CLK 121 293 294/* PERICFG */ 295 296#define CLK_PERI_PERIAXI 0 297#define CLK_PERI_NR_CLK 1 298 299/* APMIXEDSYS */ 300 301#define CLK_APMIXED_MAINPLL 0 302#define CLK_APMIXED_UNIVPLL 1 303#define CLK_APMIXED_USBPLL 2 304#define CLK_APMIXED_MSDCPLL 3 305#define CLK_APMIXED_MMPLL 4 306#define CLK_APMIXED_ADSPPLL 5 307#define CLK_APMIXED_MFGPLL 6 308#define CLK_APMIXED_TVDPLL 7 309#define CLK_APMIXED_APLL1 8 310#define CLK_APMIXED_APLL2 9 311#define CLK_APMIXED_MIPID26M 10 312#define CLK_APMIXED_NR_CLK 11 313 314/* SCP_ADSP */ 315 316#define CLK_SCP_ADSP_AUDIODSP 0 317#define CLK_SCP_ADSP_NR_CLK 1 318 319/* IMP_IIC_WRAP_C */ 320 321#define CLK_IMP_IIC_WRAP_C_I2C10 0 322#define CLK_IMP_IIC_WRAP_C_I2C11 1 323#define CLK_IMP_IIC_WRAP_C_I2C12 2 324#define CLK_IMP_IIC_WRAP_C_I2C13 3 325#define CLK_IMP_IIC_WRAP_C_NR_CLK 4 326 327/* AUDSYS */ 328 329#define CLK_AUD_AFE 0 330#define CLK_AUD_22M 1 331#define CLK_AUD_24M 2 332#define CLK_AUD_APLL2_TUNER 3 333#define CLK_AUD_APLL_TUNER 4 334#define CLK_AUD_TDM 5 335#define CLK_AUD_ADC 6 336#define CLK_AUD_DAC 7 337#define CLK_AUD_DAC_PREDIS 8 338#define CLK_AUD_TML 9 339#define CLK_AUD_NLE 10 340#define CLK_AUD_I2S1_B 11 341#define CLK_AUD_I2S2_B 12 342#define CLK_AUD_I2S3_B 13 343#define CLK_AUD_I2S4_B 14 344#define CLK_AUD_CONNSYS_I2S_ASRC 15 345#define CLK_AUD_GENERAL1_ASRC 16 346#define CLK_AUD_GENERAL2_ASRC 17 347#define CLK_AUD_DAC_HIRES 18 348#define CLK_AUD_ADC_HIRES 19 349#define CLK_AUD_ADC_HIRES_TML 20 350#define CLK_AUD_ADDA6_ADC 21 351#define CLK_AUD_ADDA6_ADC_HIRES 22 352#define CLK_AUD_3RD_DAC 23 353#define CLK_AUD_3RD_DAC_PREDIS 24 354#define CLK_AUD_3RD_DAC_TML 25 355#define CLK_AUD_3RD_DAC_HIRES 26 356#define CLK_AUD_I2S5_B 27 357#define CLK_AUD_I2S6_B 28 358#define CLK_AUD_I2S7_B 29 359#define CLK_AUD_I2S8_B 30 360#define CLK_AUD_I2S9_B 31 361#define CLK_AUD_NR_CLK 32 362 363/* IMP_IIC_WRAP_E */ 364 365#define CLK_IMP_IIC_WRAP_E_I2C3 0 366#define CLK_IMP_IIC_WRAP_E_NR_CLK 1 367 368/* IMP_IIC_WRAP_S */ 369 370#define CLK_IMP_IIC_WRAP_S_I2C7 0 371#define CLK_IMP_IIC_WRAP_S_I2C8 1 372#define CLK_IMP_IIC_WRAP_S_I2C9 2 373#define CLK_IMP_IIC_WRAP_S_NR_CLK 3 374 375/* IMP_IIC_WRAP_WS */ 376 377#define CLK_IMP_IIC_WRAP_WS_I2C1 0 378#define CLK_IMP_IIC_WRAP_WS_I2C2 1 379#define CLK_IMP_IIC_WRAP_WS_I2C4 2 380#define CLK_IMP_IIC_WRAP_WS_NR_CLK 3 381 382/* IMP_IIC_WRAP_W */ 383 384#define CLK_IMP_IIC_WRAP_W_I2C5 0 385#define CLK_IMP_IIC_WRAP_W_NR_CLK 1 386 387/* IMP_IIC_WRAP_N */ 388 389#define CLK_IMP_IIC_WRAP_N_I2C0 0 390#define CLK_IMP_IIC_WRAP_N_I2C6 1 391#define CLK_IMP_IIC_WRAP_N_NR_CLK 2 392 393/* MSDC_TOP */ 394 395#define CLK_MSDC_TOP_AES_0P 0 396#define CLK_MSDC_TOP_SRC_0P 1 397#define CLK_MSDC_TOP_SRC_1P 2 398#define CLK_MSDC_TOP_SRC_2P 3 399#define CLK_MSDC_TOP_P_MSDC0 4 400#define CLK_MSDC_TOP_P_MSDC1 5 401#define CLK_MSDC_TOP_P_MSDC2 6 402#define CLK_MSDC_TOP_P_CFG 7 403#define CLK_MSDC_TOP_AXI 8 404#define CLK_MSDC_TOP_H_MST_0P 9 405#define CLK_MSDC_TOP_H_MST_1P 10 406#define CLK_MSDC_TOP_H_MST_2P 11 407#define CLK_MSDC_TOP_MEM_OFF_DLY_26M 12 408#define CLK_MSDC_TOP_32K 13 409#define CLK_MSDC_TOP_AHB2AXI_BRG_AXI 14 410#define CLK_MSDC_TOP_NR_CLK 15 411 412/* MSDC */ 413 414#define CLK_MSDC_AXI_WRAP 0 415#define CLK_MSDC_NR_CLK 1 416 417/* MFGCFG */ 418 419#define CLK_MFG_BG3D 0 420#define CLK_MFG_NR_CLK 1 421 422/* MMSYS */ 423 424#define CLK_MM_DISP_MUTEX0 0 425#define CLK_MM_DISP_CONFIG 1 426#define CLK_MM_DISP_OVL0 2 427#define CLK_MM_DISP_RDMA0 3 428#define CLK_MM_DISP_OVL0_2L 4 429#define CLK_MM_DISP_WDMA0 5 430#define CLK_MM_DISP_UFBC_WDMA0 6 431#define CLK_MM_DISP_RSZ0 7 432#define CLK_MM_DISP_AAL0 8 433#define CLK_MM_DISP_CCORR0 9 434#define CLK_MM_DISP_DITHER0 10 435#define CLK_MM_SMI_INFRA 11 436#define CLK_MM_DISP_GAMMA0 12 437#define CLK_MM_DISP_POSTMASK0 13 438#define CLK_MM_DISP_DSC_WRAP0 14 439#define CLK_MM_DSI0 15 440#define CLK_MM_DISP_COLOR0 16 441#define CLK_MM_SMI_COMMON 17 442#define CLK_MM_DISP_FAKE_ENG0 18 443#define CLK_MM_DISP_FAKE_ENG1 19 444#define CLK_MM_MDP_TDSHP4 20 445#define CLK_MM_MDP_RSZ4 21 446#define CLK_MM_MDP_AAL4 22 447#define CLK_MM_MDP_HDR4 23 448#define CLK_MM_MDP_RDMA4 24 449#define CLK_MM_MDP_COLOR4 25 450#define CLK_MM_DISP_Y2R0 26 451#define CLK_MM_SMI_GALS 27 452#define CLK_MM_DISP_OVL2_2L 28 453#define CLK_MM_DISP_RDMA4 29 454#define CLK_MM_DISP_DPI0 30 455#define CLK_MM_SMI_IOMMU 31 456#define CLK_MM_DSI_DSI0 32 457#define CLK_MM_DPI_DPI0 33 458#define CLK_MM_26MHZ 34 459#define CLK_MM_32KHZ 35 460#define CLK_MM_NR_CLK 36 461 462/* IMGSYS */ 463 464#define CLK_IMG_LARB9 0 465#define CLK_IMG_LARB10 1 466#define CLK_IMG_DIP 2 467#define CLK_IMG_GALS 3 468#define CLK_IMG_NR_CLK 4 469 470/* IMGSYS2 */ 471 472#define CLK_IMG2_LARB11 0 473#define CLK_IMG2_LARB12 1 474#define CLK_IMG2_MFB 2 475#define CLK_IMG2_WPE 3 476#define CLK_IMG2_MSS 4 477#define CLK_IMG2_GALS 5 478#define CLK_IMG2_NR_CLK 6 479 480/* VDECSYS_SOC */ 481 482#define CLK_VDEC_SOC_LARB1 0 483#define CLK_VDEC_SOC_LAT 1 484#define CLK_VDEC_SOC_LAT_ACTIVE 2 485#define CLK_VDEC_SOC_VDEC 3 486#define CLK_VDEC_SOC_VDEC_ACTIVE 4 487#define CLK_VDEC_SOC_NR_CLK 5 488 489/* VDECSYS */ 490 491#define CLK_VDEC_LARB1 0 492#define CLK_VDEC_LAT 1 493#define CLK_VDEC_LAT_ACTIVE 2 494#define CLK_VDEC_VDEC 3 495#define CLK_VDEC_ACTIVE 4 496#define CLK_VDEC_NR_CLK 5 497 498/* VENCSYS */ 499 500#define CLK_VENC_SET0_LARB 0 501#define CLK_VENC_SET1_VENC 1 502#define CLK_VENC_SET2_JPGENC 2 503#define CLK_VENC_SET5_GALS 3 504#define CLK_VENC_NR_CLK 4 505 506/* CAMSYS */ 507 508#define CLK_CAM_LARB13 0 509#define CLK_CAM_DFP_VAD 1 510#define CLK_CAM_LARB14 2 511#define CLK_CAM_CAM 3 512#define CLK_CAM_CAMTG 4 513#define CLK_CAM_SENINF 5 514#define CLK_CAM_CAMSV0 6 515#define CLK_CAM_CAMSV1 7 516#define CLK_CAM_CAMSV2 8 517#define CLK_CAM_CAMSV3 9 518#define CLK_CAM_CCU0 10 519#define CLK_CAM_CCU1 11 520#define CLK_CAM_MRAW0 12 521#define CLK_CAM_FAKE_ENG 13 522#define CLK_CAM_CCU_GALS 14 523#define CLK_CAM_CAM2MM_GALS 15 524#define CLK_CAM_NR_CLK 16 525 526/* CAMSYS_RAWA */ 527 528#define CLK_CAM_RAWA_LARBX 0 529#define CLK_CAM_RAWA_CAM 1 530#define CLK_CAM_RAWA_CAMTG 2 531#define CLK_CAM_RAWA_NR_CLK 3 532 533/* CAMSYS_RAWB */ 534 535#define CLK_CAM_RAWB_LARBX 0 536#define CLK_CAM_RAWB_CAM 1 537#define CLK_CAM_RAWB_CAMTG 2 538#define CLK_CAM_RAWB_NR_CLK 3 539 540/* CAMSYS_RAWC */ 541 542#define CLK_CAM_RAWC_LARBX 0 543#define CLK_CAM_RAWC_CAM 1 544#define CLK_CAM_RAWC_CAMTG 2 545#define CLK_CAM_RAWC_NR_CLK 3 546 547/* IPESYS */ 548 549#define CLK_IPE_LARB19 0 550#define CLK_IPE_LARB20 1 551#define CLK_IPE_SMI_SUBCOM 2 552#define CLK_IPE_FD 3 553#define CLK_IPE_FE 4 554#define CLK_IPE_RSC 5 555#define CLK_IPE_DPE 6 556#define CLK_IPE_GALS 7 557#define CLK_IPE_NR_CLK 8 558 559/* MDPSYS */ 560 561#define CLK_MDP_RDMA0 0 562#define CLK_MDP_TDSHP0 1 563#define CLK_MDP_IMG_DL_ASYNC0 2 564#define CLK_MDP_IMG_DL_ASYNC1 3 565#define CLK_MDP_RDMA1 4 566#define CLK_MDP_TDSHP1 5 567#define CLK_MDP_SMI0 6 568#define CLK_MDP_APB_BUS 7 569#define CLK_MDP_WROT0 8 570#define CLK_MDP_RSZ0 9 571#define CLK_MDP_HDR0 10 572#define CLK_MDP_MUTEX0 11 573#define CLK_MDP_WROT1 12 574#define CLK_MDP_RSZ1 13 575#define CLK_MDP_HDR1 14 576#define CLK_MDP_FAKE_ENG0 15 577#define CLK_MDP_AAL0 16 578#define CLK_MDP_AAL1 17 579#define CLK_MDP_COLOR0 18 580#define CLK_MDP_COLOR1 19 581#define CLK_MDP_IMG_DL_RELAY0_ASYNC0 20 582#define CLK_MDP_IMG_DL_RELAY1_ASYNC1 21 583#define CLK_MDP_NR_CLK 22 584 585#endif /* _DT_BINDINGS_CLK_MT8192_H */ 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