LXR linux/sound/pci/hda/hda

   1/* SPDX-License-Identifier: GPL-2.0-or-later */
   2/*
   3 *  Common functionality for the alsa driver code base for HD Audio.
   4 */
   5
   6#ifndef __SOUND_HDA_CONTROLLER_H
   7#define __SOUND_HDA_CONTROLLER_H
   8
   9#include <linux/timecounter.h>
  10#include <linux/interrupt.h>
  11#include <sound/core.h>
  12#include <sound/pcm.h>
  13#include <sound/initval.h>
  14#include <sound/hda_codec.h>
  15#include <sound/hda_register.h>
  16
  17#define AZX_MAX_CODECS          HDA_MAX_CODECS
  18#define AZX_DEFAULT_CODECS      4
  19
  20/* driver quirks (capabilities) */
  21/* bits 0-7 are used for indicating driver type */
  22#define AZX_DCAPS_NO_TCSEL      (1 << 8)        /* No Intel TCSEL bit */
  23#define AZX_DCAPS_NO_MSI        (1 << 9)        /* No MSI support */
  24#define AZX_DCAPS_SNOOP_MASK    (3 << 10)       /* snoop type mask */
  25#define AZX_DCAPS_SNOOP_OFF     (1 << 12)       /* snoop default off */
  26#ifdef CONFIG_SND_HDA_I915
  27#define AZX_DCAPS_I915_COMPONENT (1 << 13)      /* bind with i915 gfx */
  28#else
  29#define AZX_DCAPS_I915_COMPONENT 0              /* NOP */
  30#endif
  31/* 14 unused */
  32#define AZX_DCAPS_CTX_WORKAROUND (1 << 15)      /* X-Fi workaround */
  33#define AZX_DCAPS_POSFIX_LPIB   (1 << 16)       /* Use LPIB as default */
  34#define AZX_DCAPS_AMD_WORKAROUND (1 << 17)      /* AMD-specific workaround */
  35#define AZX_DCAPS_NO_64BIT      (1 << 18)       /* No 64bit address */
  36/* 19 unused */
  37#define AZX_DCAPS_OLD_SSYNC     (1 << 20)       /* Old SSYNC reg for ICH */
  38#define AZX_DCAPS_NO_ALIGN_BUFSIZE (1 << 21)    /* no buffer size alignment */
  39/* 22 unused */
  40#define AZX_DCAPS_4K_BDLE_BOUNDARY (1 << 23)    /* BDLE in 4k boundary */
  41/* 24 unused */
  42#define AZX_DCAPS_COUNT_LPIB_DELAY  (1 << 25)   /* Take LPIB as delay */
  43#define AZX_DCAPS_PM_RUNTIME    (1 << 26)       /* runtime PM support */
  44#define AZX_DCAPS_RETRY_PROBE   (1 << 27)       /* retry probe if no codec is configured */
  45#define AZX_DCAPS_CORBRP_SELF_CLEAR (1 << 28)   /* CORBRP clears itself after reset */
  46#define AZX_DCAPS_NO_MSI64      (1 << 29)       /* Stick to 32-bit MSIs */
  47#define AZX_DCAPS_SEPARATE_STREAM_TAG   (1 << 30) /* capture and playback use separate stream tag */
  48
  49enum {
  50        AZX_SNOOP_TYPE_NONE,
  51        AZX_SNOOP_TYPE_SCH,
  52        AZX_SNOOP_TYPE_ATI,
  53        AZX_SNOOP_TYPE_NVIDIA,
  54};
  55
  56struct azx_dev {
  57        struct hdac_stream core;
  58
  59        unsigned int irq_pending:1;
  60        /*
  61         * For VIA:
  62         *  A flag to ensure DMA position is 0
  63         *  when link position is not greater than FIFO size
  64         */
  65        unsigned int insufficient:1;
  66};
  67
  68#define azx_stream(dev)         (&(dev)->core)
  69#define stream_to_azx_dev(s)    container_of(s, struct azx_dev, core)
  70
  71struct azx;
  72
  73/* Functions to read/write to hda registers. */
  74struct hda_controller_ops {
  75        /* Disable msi if supported, PCI only */
  76        int (*disable_msi_reset_irq)(struct azx *);
  77        /* Check if current position is acceptable */
  78        int (*position_check)(struct azx *chip, struct azx_dev *azx_dev);
  79        /* enable/disable the link power */
  80        int (*link_power)(struct azx *chip, bool enable);
  81};
  82
  83struct azx_pcm {
  84        struct azx *chip;
  85        struct snd_pcm *pcm;
  86        struct hda_codec *codec;
  87        struct hda_pcm *info;
  88        struct list_head list;
  89};
  90
  91typedef unsigned int (*azx_get_pos_callback_t)(struct azx *, struct azx_dev *);
  92typedef int (*azx_get_delay_callback_t)(struct azx *, struct azx_dev *, unsigned int pos);
  93
  94struct azx {
  95        struct hda_bus bus;
  96
  97        struct snd_card *card;
  98        struct pci_dev *pci;
  99        int dev_index;
 100
 101        /* chip type specific */
 102        int driver_type;
 103        unsigned int driver_caps;
 104        int playback_streams;
 105        int playback_index_offset;
 106        int capture_streams;
 107        int capture_index_offset;
 108        int num_streams;
 109        int jackpoll_interval; /* jack poll interval in jiffies */
 110
 111        /* Register interaction. */
 112        const struct hda_controller_ops *ops;
 113
 114        /* position adjustment callbacks */
 115        azx_get_pos_callback_t get_position[2];
 116        azx_get_delay_callback_t get_delay[2];
 117
 118        /* locks */
 119        struct mutex open_mutex; /* Prevents concurrent open/close operations */
 120
 121        /* PCM */
 122        struct list_head pcm_list; /* azx_pcm list */
 123
 124        /* HD codec */
 125        int  codec_probe_mask; /* copied from probe_mask option */
 126        unsigned int beep_mode;
 127
 128#ifdef CONFIG_SND_HDA_PATCH_LOADER
 129        const struct firmware *fw;
 130#endif
 131
 132        /* flags */
 133        int bdl_pos_adj;
 134        unsigned int running:1;
 135        unsigned int fallback_to_single_cmd:1;
 136        unsigned int single_cmd:1;
 137        unsigned int msi:1;
 138        unsigned int probing:1; /* codec probing phase */
 139        unsigned int snoop:1;
 140        unsigned int uc_buffer:1; /* non-cached pages for stream buffers */
 141        unsigned int align_buffer_size:1;
 142        unsigned int disabled:1; /* disabled by vga_switcheroo */
 143        unsigned int pm_prepared:1;
 144
 145        /* GTS present */
 146        unsigned int gts_present:1;
 147
 148#ifdef CONFIG_SND_HDA_DSP_LOADER
 149        struct azx_dev saved_azx_dev;
 150#endif
 151};
 152
 153#define azx_bus(chip)   (&(chip)->bus.core)
 154#define bus_to_azx(_bus)        container_of(_bus, struct azx, bus.core)
 155
 156static inline bool azx_snoop(struct azx *chip)
 157{
 158        return !IS_ENABLED(CONFIG_X86) || chip->snoop;
 159}
 160
 161/*
 162 * macros for easy use
 163 */
 164
 165#define azx_writel(chip, reg, value) \
 166        snd_hdac_chip_writel(azx_bus(chip), reg, value)
 167#define azx_readl(chip, reg) \
 168        snd_hdac_chip_readl(azx_bus(chip), reg)
 169#define azx_writew(chip, reg, value) \
 170        snd_hdac_chip_writew(azx_bus(chip), reg, value)
 171#define azx_readw(chip, reg) \
 172        snd_hdac_chip_readw(azx_bus(chip), reg)
 173#define azx_writeb(chip, reg, value) \
 174        snd_hdac_chip_writeb(azx_bus(chip), reg, value)
 175#define azx_readb(chip, reg) \
 176        snd_hdac_chip_readb(azx_bus(chip), reg)
 177
 178#define azx_has_pm_runtime(chip) \
 179        ((chip)->driver_caps & AZX_DCAPS_PM_RUNTIME)
 180
 181/* PCM setup */
 182static inline struct azx_dev *get_azx_dev(struct snd_pcm_substream *substream)
 183{
 184        return substream->runtime->private_data;
 185}
 186unsigned int azx_get_position(struct azx *chip, struct azx_dev *azx_dev);
 187unsigned int azx_get_pos_lpib(struct azx *chip, struct azx_dev *azx_dev);
 188unsigned int azx_get_pos_posbuf(struct azx *chip, struct azx_dev *azx_dev);
 189
 190/* Stream control. */
 191void azx_stop_all_streams(struct azx *chip);
 192
 193/* Allocation functions. */
 194#define azx_alloc_stream_pages(chip) \
 195        snd_hdac_bus_alloc_stream_pages(azx_bus(chip))
 196#define azx_free_stream_pages(chip) \
 197        snd_hdac_bus_free_stream_pages(azx_bus(chip))
 198
 199/* Low level azx interface */
 200void azx_init_chip(struct azx *chip, bool full_reset);
 201void azx_stop_chip(struct azx *chip);
 202#define azx_enter_link_reset(chip) \
 203        snd_hdac_bus_enter_link_reset(azx_bus(chip))
 204irqreturn_t azx_interrupt(int irq, void *dev_id);
 205
 206/* Codec interface */
 207int azx_bus_init(struct azx *chip, const char *model);
 208int azx_probe_codecs(struct azx *chip, unsigned int max_slots);
 209int azx_codec_configure(struct azx *chip);
 210int azx_init_streams(struct azx *chip);
 211void azx_free_streams(struct azx *chip);
 212
 213#endif /* __SOUND_HDA_CONTROLLER_H */
 214