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58#include <linux/delay.h>
59#include <linux/gfp.h>
60#include <linux/init.h>
61#include <linux/interrupt.h>
62#include <linux/pci.h>
63#include <linux/module.h>
64#include <linux/io.h>
65
66#include <sound/core.h>
67#include <sound/info.h>
68#include <sound/control.h>
69#include <sound/pcm.h>
70#include <sound/pcm_params.h>
71#include <sound/pcm-indirect.h>
72#include <sound/asoundef.h>
73#include <sound/initval.h>
74
75static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
76static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
77static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
78static bool fullduplex[SNDRV_CARDS];
79
80module_param_array(index, int, NULL, 0444);
81MODULE_PARM_DESC(index, "Index value for RME Digi32 soundcard.");
82module_param_array(id, charp, NULL, 0444);
83MODULE_PARM_DESC(id, "ID string for RME Digi32 soundcard.");
84module_param_array(enable, bool, NULL, 0444);
85MODULE_PARM_DESC(enable, "Enable RME Digi32 soundcard.");
86module_param_array(fullduplex, bool, NULL, 0444);
87MODULE_PARM_DESC(fullduplex, "Support full-duplex mode.");
88MODULE_AUTHOR("Martin Langer <martin-langer@gmx.de>, Pilo Chambert <pilo.c@wanadoo.fr>");
89MODULE_DESCRIPTION("RME Digi32, Digi32/8, Digi32 PRO");
90MODULE_LICENSE("GPL");
91
92
93#define RME32_SPDIF_NCHANNELS 2
94
95
96#define RME32_BUFFER_SIZE 0x20000
97
98
99#define RME32_IO_SIZE 0x30000
100
101
102#define RME32_IO_DATA_BUFFER 0x0
103#define RME32_IO_CONTROL_REGISTER 0x20000
104#define RME32_IO_GET_POS 0x20000
105#define RME32_IO_CONFIRM_ACTION_IRQ 0x20004
106#define RME32_IO_RESET_POS 0x20100
107
108
109#define RME32_WCR_START (1 << 0)
110#define RME32_WCR_MONO (1 << 1)
111
112
113
114
115
116
117
118#define RME32_WCR_MODE24 (1 << 2)
119#define RME32_WCR_SEL (1 << 3)
120#define RME32_WCR_FREQ_0 (1 << 4)
121#define RME32_WCR_FREQ_1 (1 << 5)
122#define RME32_WCR_INP_0 (1 << 6)
123#define RME32_WCR_INP_1 (1 << 7)
124#define RME32_WCR_RESET (1 << 8)
125#define RME32_WCR_MUTE (1 << 9)
126#define RME32_WCR_PRO (1 << 10)
127#define RME32_WCR_DS_BM (1 << 11)
128#define RME32_WCR_ADAT (1 << 12)
129#define RME32_WCR_AUTOSYNC (1 << 13)
130#define RME32_WCR_PD (1 << 14)
131#define RME32_WCR_EMP (1 << 15)
132
133#define RME32_WCR_BITPOS_FREQ_0 4
134#define RME32_WCR_BITPOS_FREQ_1 5
135#define RME32_WCR_BITPOS_INP_0 6
136#define RME32_WCR_BITPOS_INP_1 7
137
138
139#define RME32_RCR_AUDIO_ADDR_MASK 0x1ffff
140#define RME32_RCR_LOCK (1 << 23)
141#define RME32_RCR_ERF (1 << 26)
142#define RME32_RCR_FREQ_0 (1 << 27)
143#define RME32_RCR_FREQ_1 (1 << 28)
144#define RME32_RCR_FREQ_2 (1 << 29)
145#define RME32_RCR_KMODE (1 << 30)
146#define RME32_RCR_IRQ (1 << 31)
147
148#define RME32_RCR_BITPOS_F0 27
149#define RME32_RCR_BITPOS_F1 28
150#define RME32_RCR_BITPOS_F2 29
151
152
153#define RME32_INPUT_OPTICAL 0
154#define RME32_INPUT_COAXIAL 1
155#define RME32_INPUT_INTERNAL 2
156#define RME32_INPUT_XLR 3
157
158
159#define RME32_CLOCKMODE_SLAVE 0
160#define RME32_CLOCKMODE_MASTER_32 1
161#define RME32_CLOCKMODE_MASTER_44 2
162#define RME32_CLOCKMODE_MASTER_48 3
163
164
165#define RME32_BLOCK_SIZE 8192
166
167
168#define RME32_MID_BUFFER_SIZE (1024*1024)
169
170
171#define RME32_32_REVISION 192
172#define RME32_328_REVISION_OLD 100
173#define RME32_328_REVISION_NEW 101
174#define RME32_PRO_REVISION_WITH_8412 192
175#define RME32_PRO_REVISION_WITH_8414 150
176
177
178struct rme32 {
179 spinlock_t lock;
180 int irq;
181 unsigned long port;
182 void __iomem *iobase;
183
184 u32 wcreg;
185 u32 wcreg_spdif;
186 u32 wcreg_spdif_stream;
187 u32 rcreg;
188
189 u8 rev;
190
191 struct snd_pcm_substream *playback_substream;
192 struct snd_pcm_substream *capture_substream;
193
194 int playback_frlog;
195 int capture_frlog;
196
197 size_t playback_periodsize;
198 size_t capture_periodsize;
199
200 unsigned int fullduplex_mode;
201 int running;
202
203 struct snd_pcm_indirect playback_pcm;
204 struct snd_pcm_indirect capture_pcm;
205
206 struct snd_card *card;
207 struct snd_pcm *spdif_pcm;
208 struct snd_pcm *adat_pcm;
209 struct pci_dev *pci;
210 struct snd_kcontrol *spdif_ctl;
211};
212
213static const struct pci_device_id snd_rme32_ids[] = {
214 {PCI_VDEVICE(XILINX_RME, PCI_DEVICE_ID_RME_DIGI32), 0,},
215 {PCI_VDEVICE(XILINX_RME, PCI_DEVICE_ID_RME_DIGI32_8), 0,},
216 {PCI_VDEVICE(XILINX_RME, PCI_DEVICE_ID_RME_DIGI32_PRO), 0,},
217 {0,}
218};
219
220MODULE_DEVICE_TABLE(pci, snd_rme32_ids);
221
222#define RME32_ISWORKING(rme32) ((rme32)->wcreg & RME32_WCR_START)
223#define RME32_PRO_WITH_8414(rme32) ((rme32)->pci->device == PCI_DEVICE_ID_RME_DIGI32_PRO && (rme32)->rev == RME32_PRO_REVISION_WITH_8414)
224
225static int snd_rme32_playback_prepare(struct snd_pcm_substream *substream);
226
227static int snd_rme32_capture_prepare(struct snd_pcm_substream *substream);
228
229static int snd_rme32_pcm_trigger(struct snd_pcm_substream *substream, int cmd);
230
231static void snd_rme32_proc_init(struct rme32 * rme32);
232
233static int snd_rme32_create_switches(struct snd_card *card, struct rme32 * rme32);
234
235static inline unsigned int snd_rme32_pcm_byteptr(struct rme32 * rme32)
236{
237 return (readl(rme32->iobase + RME32_IO_GET_POS)
238 & RME32_RCR_AUDIO_ADDR_MASK);
239}
240
241
242static int snd_rme32_playback_silence(struct snd_pcm_substream *substream,
243 int channel, unsigned long pos,
244 unsigned long count)
245{
246 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
247
248 memset_io(rme32->iobase + RME32_IO_DATA_BUFFER + pos, 0, count);
249 return 0;
250}
251
252
253static int snd_rme32_playback_copy(struct snd_pcm_substream *substream,
254 int channel, unsigned long pos,
255 void __user *src, unsigned long count)
256{
257 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
258
259 if (copy_from_user_toio(rme32->iobase + RME32_IO_DATA_BUFFER + pos,
260 src, count))
261 return -EFAULT;
262 return 0;
263}
264
265static int snd_rme32_playback_copy_kernel(struct snd_pcm_substream *substream,
266 int channel, unsigned long pos,
267 void *src, unsigned long count)
268{
269 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
270
271 memcpy_toio(rme32->iobase + RME32_IO_DATA_BUFFER + pos, src, count);
272 return 0;
273}
274
275
276static int snd_rme32_capture_copy(struct snd_pcm_substream *substream,
277 int channel, unsigned long pos,
278 void __user *dst, unsigned long count)
279{
280 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
281
282 if (copy_to_user_fromio(dst,
283 rme32->iobase + RME32_IO_DATA_BUFFER + pos,
284 count))
285 return -EFAULT;
286 return 0;
287}
288
289static int snd_rme32_capture_copy_kernel(struct snd_pcm_substream *substream,
290 int channel, unsigned long pos,
291 void *dst, unsigned long count)
292{
293 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
294
295 memcpy_fromio(dst, rme32->iobase + RME32_IO_DATA_BUFFER + pos, count);
296 return 0;
297}
298
299
300
301
302static const struct snd_pcm_hardware snd_rme32_spdif_info = {
303 .info = (SNDRV_PCM_INFO_MMAP_IOMEM |
304 SNDRV_PCM_INFO_MMAP_VALID |
305 SNDRV_PCM_INFO_INTERLEAVED |
306 SNDRV_PCM_INFO_PAUSE |
307 SNDRV_PCM_INFO_SYNC_START |
308 SNDRV_PCM_INFO_SYNC_APPLPTR),
309 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
310 SNDRV_PCM_FMTBIT_S32_LE),
311 .rates = (SNDRV_PCM_RATE_32000 |
312 SNDRV_PCM_RATE_44100 |
313 SNDRV_PCM_RATE_48000),
314 .rate_min = 32000,
315 .rate_max = 48000,
316 .channels_min = 2,
317 .channels_max = 2,
318 .buffer_bytes_max = RME32_BUFFER_SIZE,
319 .period_bytes_min = RME32_BLOCK_SIZE,
320 .period_bytes_max = RME32_BLOCK_SIZE,
321 .periods_min = RME32_BUFFER_SIZE / RME32_BLOCK_SIZE,
322 .periods_max = RME32_BUFFER_SIZE / RME32_BLOCK_SIZE,
323 .fifo_size = 0,
324};
325
326
327
328
329static const struct snd_pcm_hardware snd_rme32_adat_info =
330{
331 .info = (SNDRV_PCM_INFO_MMAP_IOMEM |
332 SNDRV_PCM_INFO_MMAP_VALID |
333 SNDRV_PCM_INFO_INTERLEAVED |
334 SNDRV_PCM_INFO_PAUSE |
335 SNDRV_PCM_INFO_SYNC_START |
336 SNDRV_PCM_INFO_SYNC_APPLPTR),
337 .formats= SNDRV_PCM_FMTBIT_S16_LE,
338 .rates = (SNDRV_PCM_RATE_44100 |
339 SNDRV_PCM_RATE_48000),
340 .rate_min = 44100,
341 .rate_max = 48000,
342 .channels_min = 8,
343 .channels_max = 8,
344 .buffer_bytes_max = RME32_BUFFER_SIZE,
345 .period_bytes_min = RME32_BLOCK_SIZE,
346 .period_bytes_max = RME32_BLOCK_SIZE,
347 .periods_min = RME32_BUFFER_SIZE / RME32_BLOCK_SIZE,
348 .periods_max = RME32_BUFFER_SIZE / RME32_BLOCK_SIZE,
349 .fifo_size = 0,
350};
351
352
353
354
355static const struct snd_pcm_hardware snd_rme32_spdif_fd_info = {
356 .info = (SNDRV_PCM_INFO_MMAP |
357 SNDRV_PCM_INFO_MMAP_VALID |
358 SNDRV_PCM_INFO_INTERLEAVED |
359 SNDRV_PCM_INFO_PAUSE |
360 SNDRV_PCM_INFO_SYNC_START |
361 SNDRV_PCM_INFO_SYNC_APPLPTR),
362 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
363 SNDRV_PCM_FMTBIT_S32_LE),
364 .rates = (SNDRV_PCM_RATE_32000 |
365 SNDRV_PCM_RATE_44100 |
366 SNDRV_PCM_RATE_48000),
367 .rate_min = 32000,
368 .rate_max = 48000,
369 .channels_min = 2,
370 .channels_max = 2,
371 .buffer_bytes_max = RME32_MID_BUFFER_SIZE,
372 .period_bytes_min = RME32_BLOCK_SIZE,
373 .period_bytes_max = RME32_BLOCK_SIZE,
374 .periods_min = 2,
375 .periods_max = RME32_MID_BUFFER_SIZE / RME32_BLOCK_SIZE,
376 .fifo_size = 0,
377};
378
379
380
381
382static const struct snd_pcm_hardware snd_rme32_adat_fd_info =
383{
384 .info = (SNDRV_PCM_INFO_MMAP |
385 SNDRV_PCM_INFO_MMAP_VALID |
386 SNDRV_PCM_INFO_INTERLEAVED |
387 SNDRV_PCM_INFO_PAUSE |
388 SNDRV_PCM_INFO_SYNC_START |
389 SNDRV_PCM_INFO_SYNC_APPLPTR),
390 .formats= SNDRV_PCM_FMTBIT_S16_LE,
391 .rates = (SNDRV_PCM_RATE_44100 |
392 SNDRV_PCM_RATE_48000),
393 .rate_min = 44100,
394 .rate_max = 48000,
395 .channels_min = 8,
396 .channels_max = 8,
397 .buffer_bytes_max = RME32_MID_BUFFER_SIZE,
398 .period_bytes_min = RME32_BLOCK_SIZE,
399 .period_bytes_max = RME32_BLOCK_SIZE,
400 .periods_min = 2,
401 .periods_max = RME32_MID_BUFFER_SIZE / RME32_BLOCK_SIZE,
402 .fifo_size = 0,
403};
404
405static void snd_rme32_reset_dac(struct rme32 *rme32)
406{
407 writel(rme32->wcreg | RME32_WCR_PD,
408 rme32->iobase + RME32_IO_CONTROL_REGISTER);
409 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
410}
411
412static int snd_rme32_playback_getrate(struct rme32 * rme32)
413{
414 int rate;
415
416 rate = ((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_0) & 1) +
417 (((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_1) & 1) << 1);
418 switch (rate) {
419 case 1:
420 rate = 32000;
421 break;
422 case 2:
423 rate = 44100;
424 break;
425 case 3:
426 rate = 48000;
427 break;
428 default:
429 return -1;
430 }
431 return (rme32->wcreg & RME32_WCR_DS_BM) ? rate << 1 : rate;
432}
433
434static int snd_rme32_capture_getrate(struct rme32 * rme32, int *is_adat)
435{
436 int n;
437
438 *is_adat = 0;
439 if (rme32->rcreg & RME32_RCR_LOCK) {
440
441 *is_adat = 1;
442 }
443 if (rme32->rcreg & RME32_RCR_ERF) {
444 return -1;
445 }
446
447
448 n = ((rme32->rcreg >> RME32_RCR_BITPOS_F0) & 1) +
449 (((rme32->rcreg >> RME32_RCR_BITPOS_F1) & 1) << 1) +
450 (((rme32->rcreg >> RME32_RCR_BITPOS_F2) & 1) << 2);
451
452 if (RME32_PRO_WITH_8414(rme32))
453 switch (n) {
454 case 0:
455 case 1:
456 case 2:
457 return -1;
458 case 3:
459 return 96000;
460 case 4:
461 return 88200;
462 case 5:
463 return 48000;
464 case 6:
465 return 44100;
466 case 7:
467 return 32000;
468 default:
469 return -1;
470 }
471 else
472 switch (n) {
473 case 0:
474 return -1;
475 case 1:
476 return 48000;
477 case 2:
478 return 44100;
479 case 3:
480 return 32000;
481 case 4:
482 return 48000;
483 case 5:
484 return 44100;
485 case 6:
486 return 44056;
487 case 7:
488 return 32000;
489 default:
490 break;
491 }
492 return -1;
493}
494
495static int snd_rme32_playback_setrate(struct rme32 * rme32, int rate)
496{
497 int ds;
498
499 ds = rme32->wcreg & RME32_WCR_DS_BM;
500 switch (rate) {
501 case 32000:
502 rme32->wcreg &= ~RME32_WCR_DS_BM;
503 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) &
504 ~RME32_WCR_FREQ_1;
505 break;
506 case 44100:
507 rme32->wcreg &= ~RME32_WCR_DS_BM;
508 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_1) &
509 ~RME32_WCR_FREQ_0;
510 break;
511 case 48000:
512 rme32->wcreg &= ~RME32_WCR_DS_BM;
513 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) |
514 RME32_WCR_FREQ_1;
515 break;
516 case 64000:
517 if (rme32->pci->device != PCI_DEVICE_ID_RME_DIGI32_PRO)
518 return -EINVAL;
519 rme32->wcreg |= RME32_WCR_DS_BM;
520 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) &
521 ~RME32_WCR_FREQ_1;
522 break;
523 case 88200:
524 if (rme32->pci->device != PCI_DEVICE_ID_RME_DIGI32_PRO)
525 return -EINVAL;
526 rme32->wcreg |= RME32_WCR_DS_BM;
527 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_1) &
528 ~RME32_WCR_FREQ_0;
529 break;
530 case 96000:
531 if (rme32->pci->device != PCI_DEVICE_ID_RME_DIGI32_PRO)
532 return -EINVAL;
533 rme32->wcreg |= RME32_WCR_DS_BM;
534 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) |
535 RME32_WCR_FREQ_1;
536 break;
537 default:
538 return -EINVAL;
539 }
540 if ((!ds && rme32->wcreg & RME32_WCR_DS_BM) ||
541 (ds && !(rme32->wcreg & RME32_WCR_DS_BM)))
542 {
543
544 snd_rme32_reset_dac(rme32);
545 } else {
546 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
547 }
548 return 0;
549}
550
551static int snd_rme32_setclockmode(struct rme32 * rme32, int mode)
552{
553 switch (mode) {
554 case RME32_CLOCKMODE_SLAVE:
555
556 rme32->wcreg = (rme32->wcreg & ~RME32_WCR_FREQ_0) &
557 ~RME32_WCR_FREQ_1;
558 break;
559 case RME32_CLOCKMODE_MASTER_32:
560
561 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) &
562 ~RME32_WCR_FREQ_1;
563 break;
564 case RME32_CLOCKMODE_MASTER_44:
565
566 rme32->wcreg = (rme32->wcreg & ~RME32_WCR_FREQ_0) |
567 RME32_WCR_FREQ_1;
568 break;
569 case RME32_CLOCKMODE_MASTER_48:
570
571 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) |
572 RME32_WCR_FREQ_1;
573 break;
574 default:
575 return -EINVAL;
576 }
577 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
578 return 0;
579}
580
581static int snd_rme32_getclockmode(struct rme32 * rme32)
582{
583 return ((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_0) & 1) +
584 (((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_1) & 1) << 1);
585}
586
587static int snd_rme32_setinputtype(struct rme32 * rme32, int type)
588{
589 switch (type) {
590 case RME32_INPUT_OPTICAL:
591 rme32->wcreg = (rme32->wcreg & ~RME32_WCR_INP_0) &
592 ~RME32_WCR_INP_1;
593 break;
594 case RME32_INPUT_COAXIAL:
595 rme32->wcreg = (rme32->wcreg | RME32_WCR_INP_0) &
596 ~RME32_WCR_INP_1;
597 break;
598 case RME32_INPUT_INTERNAL:
599 rme32->wcreg = (rme32->wcreg & ~RME32_WCR_INP_0) |
600 RME32_WCR_INP_1;
601 break;
602 case RME32_INPUT_XLR:
603 rme32->wcreg = (rme32->wcreg | RME32_WCR_INP_0) |
604 RME32_WCR_INP_1;
605 break;
606 default:
607 return -EINVAL;
608 }
609 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
610 return 0;
611}
612
613static int snd_rme32_getinputtype(struct rme32 * rme32)
614{
615 return ((rme32->wcreg >> RME32_WCR_BITPOS_INP_0) & 1) +
616 (((rme32->wcreg >> RME32_WCR_BITPOS_INP_1) & 1) << 1);
617}
618
619static void
620snd_rme32_setframelog(struct rme32 * rme32, int n_channels, int is_playback)
621{
622 int frlog;
623
624 if (n_channels == 2) {
625 frlog = 1;
626 } else {
627
628 frlog = 3;
629 }
630 if (is_playback) {
631 frlog += (rme32->wcreg & RME32_WCR_MODE24) ? 2 : 1;
632 rme32->playback_frlog = frlog;
633 } else {
634 frlog += (rme32->wcreg & RME32_WCR_MODE24) ? 2 : 1;
635 rme32->capture_frlog = frlog;
636 }
637}
638
639static int snd_rme32_setformat(struct rme32 *rme32, snd_pcm_format_t format)
640{
641 switch (format) {
642 case SNDRV_PCM_FORMAT_S16_LE:
643 rme32->wcreg &= ~RME32_WCR_MODE24;
644 break;
645 case SNDRV_PCM_FORMAT_S32_LE:
646 rme32->wcreg |= RME32_WCR_MODE24;
647 break;
648 default:
649 return -EINVAL;
650 }
651 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
652 return 0;
653}
654
655static int
656snd_rme32_playback_hw_params(struct snd_pcm_substream *substream,
657 struct snd_pcm_hw_params *params)
658{
659 int err, rate, dummy;
660 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
661 struct snd_pcm_runtime *runtime = substream->runtime;
662
663 if (!rme32->fullduplex_mode) {
664 runtime->dma_area = (void __force *)(rme32->iobase +
665 RME32_IO_DATA_BUFFER);
666 runtime->dma_addr = rme32->port + RME32_IO_DATA_BUFFER;
667 runtime->dma_bytes = RME32_BUFFER_SIZE;
668 }
669
670 spin_lock_irq(&rme32->lock);
671 rate = 0;
672 if (rme32->rcreg & RME32_RCR_KMODE)
673 rate = snd_rme32_capture_getrate(rme32, &dummy);
674 if (rate > 0) {
675
676 if ((int)params_rate(params) != rate) {
677 spin_unlock_irq(&rme32->lock);
678 return -EIO;
679 }
680 } else {
681 err = snd_rme32_playback_setrate(rme32, params_rate(params));
682 if (err < 0) {
683 spin_unlock_irq(&rme32->lock);
684 return err;
685 }
686 }
687 err = snd_rme32_setformat(rme32, params_format(params));
688 if (err < 0) {
689 spin_unlock_irq(&rme32->lock);
690 return err;
691 }
692
693 snd_rme32_setframelog(rme32, params_channels(params), 1);
694 if (rme32->capture_periodsize != 0) {
695 if (params_period_size(params) << rme32->playback_frlog != rme32->capture_periodsize) {
696 spin_unlock_irq(&rme32->lock);
697 return -EBUSY;
698 }
699 }
700 rme32->playback_periodsize = params_period_size(params) << rme32->playback_frlog;
701
702 if ((rme32->wcreg & RME32_WCR_ADAT) == 0) {
703 rme32->wcreg &= ~(RME32_WCR_PRO | RME32_WCR_EMP);
704 rme32->wcreg |= rme32->wcreg_spdif_stream;
705 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
706 }
707 spin_unlock_irq(&rme32->lock);
708
709 return 0;
710}
711
712static int
713snd_rme32_capture_hw_params(struct snd_pcm_substream *substream,
714 struct snd_pcm_hw_params *params)
715{
716 int err, isadat, rate;
717 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
718 struct snd_pcm_runtime *runtime = substream->runtime;
719
720 if (!rme32->fullduplex_mode) {
721 runtime->dma_area = (void __force *)rme32->iobase +
722 RME32_IO_DATA_BUFFER;
723 runtime->dma_addr = rme32->port + RME32_IO_DATA_BUFFER;
724 runtime->dma_bytes = RME32_BUFFER_SIZE;
725 }
726
727 spin_lock_irq(&rme32->lock);
728
729 rme32->wcreg |= RME32_WCR_AUTOSYNC;
730 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
731
732 err = snd_rme32_setformat(rme32, params_format(params));
733 if (err < 0) {
734 spin_unlock_irq(&rme32->lock);
735 return err;
736 }
737 err = snd_rme32_playback_setrate(rme32, params_rate(params));
738 if (err < 0) {
739 spin_unlock_irq(&rme32->lock);
740 return err;
741 }
742 rate = snd_rme32_capture_getrate(rme32, &isadat);
743 if (rate > 0) {
744 if ((int)params_rate(params) != rate) {
745 spin_unlock_irq(&rme32->lock);
746 return -EIO;
747 }
748 if ((isadat && runtime->hw.channels_min == 2) ||
749 (!isadat && runtime->hw.channels_min == 8)) {
750 spin_unlock_irq(&rme32->lock);
751 return -EIO;
752 }
753 }
754
755 rme32->wcreg &= ~RME32_WCR_AUTOSYNC;
756 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
757
758 snd_rme32_setframelog(rme32, params_channels(params), 0);
759 if (rme32->playback_periodsize != 0) {
760 if (params_period_size(params) << rme32->capture_frlog !=
761 rme32->playback_periodsize) {
762 spin_unlock_irq(&rme32->lock);
763 return -EBUSY;
764 }
765 }
766 rme32->capture_periodsize =
767 params_period_size(params) << rme32->capture_frlog;
768 spin_unlock_irq(&rme32->lock);
769
770 return 0;
771}
772
773static void snd_rme32_pcm_start(struct rme32 * rme32, int from_pause)
774{
775 if (!from_pause) {
776 writel(0, rme32->iobase + RME32_IO_RESET_POS);
777 }
778
779 rme32->wcreg |= RME32_WCR_START;
780 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
781}
782
783static void snd_rme32_pcm_stop(struct rme32 * rme32, int to_pause)
784{
785
786
787
788
789 rme32->rcreg = readl(rme32->iobase + RME32_IO_CONTROL_REGISTER);
790 if (rme32->rcreg & RME32_RCR_IRQ) {
791 writel(0, rme32->iobase + RME32_IO_CONFIRM_ACTION_IRQ);
792 }
793 rme32->wcreg &= ~RME32_WCR_START;
794 if (rme32->wcreg & RME32_WCR_SEL)
795 rme32->wcreg |= RME32_WCR_MUTE;
796 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
797 if (! to_pause)
798 writel(0, rme32->iobase + RME32_IO_RESET_POS);
799}
800
801static irqreturn_t snd_rme32_interrupt(int irq, void *dev_id)
802{
803 struct rme32 *rme32 = (struct rme32 *) dev_id;
804
805 rme32->rcreg = readl(rme32->iobase + RME32_IO_CONTROL_REGISTER);
806 if (!(rme32->rcreg & RME32_RCR_IRQ)) {
807 return IRQ_NONE;
808 } else {
809 if (rme32->capture_substream) {
810 snd_pcm_period_elapsed(rme32->capture_substream);
811 }
812 if (rme32->playback_substream) {
813 snd_pcm_period_elapsed(rme32->playback_substream);
814 }
815 writel(0, rme32->iobase + RME32_IO_CONFIRM_ACTION_IRQ);
816 }
817 return IRQ_HANDLED;
818}
819
820static const unsigned int period_bytes[] = { RME32_BLOCK_SIZE };
821
822static const struct snd_pcm_hw_constraint_list hw_constraints_period_bytes = {
823 .count = ARRAY_SIZE(period_bytes),
824 .list = period_bytes,
825 .mask = 0
826};
827
828static void snd_rme32_set_buffer_constraint(struct rme32 *rme32, struct snd_pcm_runtime *runtime)
829{
830 if (! rme32->fullduplex_mode) {
831 snd_pcm_hw_constraint_single(runtime,
832 SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
833 RME32_BUFFER_SIZE);
834 snd_pcm_hw_constraint_list(runtime, 0,
835 SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
836 &hw_constraints_period_bytes);
837 }
838}
839
840static int snd_rme32_playback_spdif_open(struct snd_pcm_substream *substream)
841{
842 int rate, dummy;
843 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
844 struct snd_pcm_runtime *runtime = substream->runtime;
845
846 snd_pcm_set_sync(substream);
847
848 spin_lock_irq(&rme32->lock);
849 if (rme32->playback_substream != NULL) {
850 spin_unlock_irq(&rme32->lock);
851 return -EBUSY;
852 }
853 rme32->wcreg &= ~RME32_WCR_ADAT;
854 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
855 rme32->playback_substream = substream;
856 spin_unlock_irq(&rme32->lock);
857
858 if (rme32->fullduplex_mode)
859 runtime->hw = snd_rme32_spdif_fd_info;
860 else
861 runtime->hw = snd_rme32_spdif_info;
862 if (rme32->pci->device == PCI_DEVICE_ID_RME_DIGI32_PRO) {
863 runtime->hw.rates |= SNDRV_PCM_RATE_64000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000;
864 runtime->hw.rate_max = 96000;
865 }
866 rate = 0;
867 if (rme32->rcreg & RME32_RCR_KMODE)
868 rate = snd_rme32_capture_getrate(rme32, &dummy);
869 if (rate > 0) {
870
871 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
872 runtime->hw.rate_min = rate;
873 runtime->hw.rate_max = rate;
874 }
875
876 snd_rme32_set_buffer_constraint(rme32, runtime);
877
878 rme32->wcreg_spdif_stream = rme32->wcreg_spdif;
879 rme32->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
880 snd_ctl_notify(rme32->card, SNDRV_CTL_EVENT_MASK_VALUE |
881 SNDRV_CTL_EVENT_MASK_INFO, &rme32->spdif_ctl->id);
882 return 0;
883}
884
885static int snd_rme32_capture_spdif_open(struct snd_pcm_substream *substream)
886{
887 int isadat, rate;
888 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
889 struct snd_pcm_runtime *runtime = substream->runtime;
890
891 snd_pcm_set_sync(substream);
892
893 spin_lock_irq(&rme32->lock);
894 if (rme32->capture_substream != NULL) {
895 spin_unlock_irq(&rme32->lock);
896 return -EBUSY;
897 }
898 rme32->capture_substream = substream;
899 spin_unlock_irq(&rme32->lock);
900
901 if (rme32->fullduplex_mode)
902 runtime->hw = snd_rme32_spdif_fd_info;
903 else
904 runtime->hw = snd_rme32_spdif_info;
905 if (RME32_PRO_WITH_8414(rme32)) {
906 runtime->hw.rates |= SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000;
907 runtime->hw.rate_max = 96000;
908 }
909 rate = snd_rme32_capture_getrate(rme32, &isadat);
910 if (rate > 0) {
911 if (isadat) {
912 return -EIO;
913 }
914 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
915 runtime->hw.rate_min = rate;
916 runtime->hw.rate_max = rate;
917 }
918
919 snd_rme32_set_buffer_constraint(rme32, runtime);
920
921 return 0;
922}
923
924static int
925snd_rme32_playback_adat_open(struct snd_pcm_substream *substream)
926{
927 int rate, dummy;
928 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
929 struct snd_pcm_runtime *runtime = substream->runtime;
930
931 snd_pcm_set_sync(substream);
932
933 spin_lock_irq(&rme32->lock);
934 if (rme32->playback_substream != NULL) {
935 spin_unlock_irq(&rme32->lock);
936 return -EBUSY;
937 }
938 rme32->wcreg |= RME32_WCR_ADAT;
939 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
940 rme32->playback_substream = substream;
941 spin_unlock_irq(&rme32->lock);
942
943 if (rme32->fullduplex_mode)
944 runtime->hw = snd_rme32_adat_fd_info;
945 else
946 runtime->hw = snd_rme32_adat_info;
947 rate = 0;
948 if (rme32->rcreg & RME32_RCR_KMODE)
949 rate = snd_rme32_capture_getrate(rme32, &dummy);
950 if (rate > 0) {
951
952 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
953 runtime->hw.rate_min = rate;
954 runtime->hw.rate_max = rate;
955 }
956
957 snd_rme32_set_buffer_constraint(rme32, runtime);
958 return 0;
959}
960
961static int
962snd_rme32_capture_adat_open(struct snd_pcm_substream *substream)
963{
964 int isadat, rate;
965 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
966 struct snd_pcm_runtime *runtime = substream->runtime;
967
968 if (rme32->fullduplex_mode)
969 runtime->hw = snd_rme32_adat_fd_info;
970 else
971 runtime->hw = snd_rme32_adat_info;
972 rate = snd_rme32_capture_getrate(rme32, &isadat);
973 if (rate > 0) {
974 if (!isadat) {
975 return -EIO;
976 }
977 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
978 runtime->hw.rate_min = rate;
979 runtime->hw.rate_max = rate;
980 }
981
982 snd_pcm_set_sync(substream);
983
984 spin_lock_irq(&rme32->lock);
985 if (rme32->capture_substream != NULL) {
986 spin_unlock_irq(&rme32->lock);
987 return -EBUSY;
988 }
989 rme32->capture_substream = substream;
990 spin_unlock_irq(&rme32->lock);
991
992 snd_rme32_set_buffer_constraint(rme32, runtime);
993 return 0;
994}
995
996static int snd_rme32_playback_close(struct snd_pcm_substream *substream)
997{
998 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
999 int spdif = 0;
1000
1001 spin_lock_irq(&rme32->lock);
1002 rme32->playback_substream = NULL;
1003 rme32->playback_periodsize = 0;
1004 spdif = (rme32->wcreg & RME32_WCR_ADAT) == 0;
1005 spin_unlock_irq(&rme32->lock);
1006 if (spdif) {
1007 rme32->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1008 snd_ctl_notify(rme32->card, SNDRV_CTL_EVENT_MASK_VALUE |
1009 SNDRV_CTL_EVENT_MASK_INFO,
1010 &rme32->spdif_ctl->id);
1011 }
1012 return 0;
1013}
1014
1015static int snd_rme32_capture_close(struct snd_pcm_substream *substream)
1016{
1017 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1018
1019 spin_lock_irq(&rme32->lock);
1020 rme32->capture_substream = NULL;
1021 rme32->capture_periodsize = 0;
1022 spin_unlock_irq(&rme32->lock);
1023 return 0;
1024}
1025
1026static int snd_rme32_playback_prepare(struct snd_pcm_substream *substream)
1027{
1028 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1029
1030 spin_lock_irq(&rme32->lock);
1031 if (rme32->fullduplex_mode) {
1032 memset(&rme32->playback_pcm, 0, sizeof(rme32->playback_pcm));
1033 rme32->playback_pcm.hw_buffer_size = RME32_BUFFER_SIZE;
1034 rme32->playback_pcm.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
1035 } else {
1036 writel(0, rme32->iobase + RME32_IO_RESET_POS);
1037 }
1038 if (rme32->wcreg & RME32_WCR_SEL)
1039 rme32->wcreg &= ~RME32_WCR_MUTE;
1040 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
1041 spin_unlock_irq(&rme32->lock);
1042 return 0;
1043}
1044
1045static int snd_rme32_capture_prepare(struct snd_pcm_substream *substream)
1046{
1047 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1048
1049 spin_lock_irq(&rme32->lock);
1050 if (rme32->fullduplex_mode) {
1051 memset(&rme32->capture_pcm, 0, sizeof(rme32->capture_pcm));
1052 rme32->capture_pcm.hw_buffer_size = RME32_BUFFER_SIZE;
1053 rme32->capture_pcm.hw_queue_size = RME32_BUFFER_SIZE / 2;
1054 rme32->capture_pcm.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
1055 } else {
1056 writel(0, rme32->iobase + RME32_IO_RESET_POS);
1057 }
1058 spin_unlock_irq(&rme32->lock);
1059 return 0;
1060}
1061
1062static int
1063snd_rme32_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1064{
1065 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1066 struct snd_pcm_substream *s;
1067
1068 spin_lock(&rme32->lock);
1069 snd_pcm_group_for_each_entry(s, substream) {
1070 if (s != rme32->playback_substream &&
1071 s != rme32->capture_substream)
1072 continue;
1073 switch (cmd) {
1074 case SNDRV_PCM_TRIGGER_START:
1075 rme32->running |= (1 << s->stream);
1076 if (rme32->fullduplex_mode) {
1077
1078 if (s == rme32->playback_substream) {
1079 rme32->playback_pcm.hw_io =
1080 rme32->playback_pcm.hw_data = snd_rme32_pcm_byteptr(rme32);
1081 } else {
1082 rme32->capture_pcm.hw_io =
1083 rme32->capture_pcm.hw_data = snd_rme32_pcm_byteptr(rme32);
1084 }
1085 }
1086 break;
1087 case SNDRV_PCM_TRIGGER_STOP:
1088 rme32->running &= ~(1 << s->stream);
1089 break;
1090 }
1091 snd_pcm_trigger_done(s, substream);
1092 }
1093
1094 switch (cmd) {
1095 case SNDRV_PCM_TRIGGER_START:
1096 if (rme32->running && ! RME32_ISWORKING(rme32))
1097 snd_rme32_pcm_start(rme32, 0);
1098 break;
1099 case SNDRV_PCM_TRIGGER_STOP:
1100 if (! rme32->running && RME32_ISWORKING(rme32))
1101 snd_rme32_pcm_stop(rme32, 0);
1102 break;
1103 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1104 if (rme32->running && RME32_ISWORKING(rme32))
1105 snd_rme32_pcm_stop(rme32, 1);
1106 break;
1107 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1108 if (rme32->running && ! RME32_ISWORKING(rme32))
1109 snd_rme32_pcm_start(rme32, 1);
1110 break;
1111 }
1112 spin_unlock(&rme32->lock);
1113 return 0;
1114}
1115
1116
1117static snd_pcm_uframes_t
1118snd_rme32_playback_pointer(struct snd_pcm_substream *substream)
1119{
1120 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1121 return snd_rme32_pcm_byteptr(rme32) >> rme32->playback_frlog;
1122}
1123
1124static snd_pcm_uframes_t
1125snd_rme32_capture_pointer(struct snd_pcm_substream *substream)
1126{
1127 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1128 return snd_rme32_pcm_byteptr(rme32) >> rme32->capture_frlog;
1129}
1130
1131
1132
1133static void snd_rme32_pb_trans_copy(struct snd_pcm_substream *substream,
1134 struct snd_pcm_indirect *rec, size_t bytes)
1135{
1136 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1137 memcpy_toio(rme32->iobase + RME32_IO_DATA_BUFFER + rec->hw_data,
1138 substream->runtime->dma_area + rec->sw_data, bytes);
1139}
1140
1141static int snd_rme32_playback_fd_ack(struct snd_pcm_substream *substream)
1142{
1143 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1144 struct snd_pcm_indirect *rec, *cprec;
1145
1146 rec = &rme32->playback_pcm;
1147 cprec = &rme32->capture_pcm;
1148 spin_lock(&rme32->lock);
1149 rec->hw_queue_size = RME32_BUFFER_SIZE;
1150 if (rme32->running & (1 << SNDRV_PCM_STREAM_CAPTURE))
1151 rec->hw_queue_size -= cprec->hw_ready;
1152 spin_unlock(&rme32->lock);
1153 return snd_pcm_indirect_playback_transfer(substream, rec,
1154 snd_rme32_pb_trans_copy);
1155}
1156
1157static void snd_rme32_cp_trans_copy(struct snd_pcm_substream *substream,
1158 struct snd_pcm_indirect *rec, size_t bytes)
1159{
1160 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1161 memcpy_fromio(substream->runtime->dma_area + rec->sw_data,
1162 rme32->iobase + RME32_IO_DATA_BUFFER + rec->hw_data,
1163 bytes);
1164}
1165
1166static int snd_rme32_capture_fd_ack(struct snd_pcm_substream *substream)
1167{
1168 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1169 return snd_pcm_indirect_capture_transfer(substream, &rme32->capture_pcm,
1170 snd_rme32_cp_trans_copy);
1171}
1172
1173static snd_pcm_uframes_t
1174snd_rme32_playback_fd_pointer(struct snd_pcm_substream *substream)
1175{
1176 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1177 return snd_pcm_indirect_playback_pointer(substream, &rme32->playback_pcm,
1178 snd_rme32_pcm_byteptr(rme32));
1179}
1180
1181static snd_pcm_uframes_t
1182snd_rme32_capture_fd_pointer(struct snd_pcm_substream *substream)
1183{
1184 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1185 return snd_pcm_indirect_capture_pointer(substream, &rme32->capture_pcm,
1186 snd_rme32_pcm_byteptr(rme32));
1187}
1188
1189
1190static const struct snd_pcm_ops snd_rme32_playback_spdif_ops = {
1191 .open = snd_rme32_playback_spdif_open,
1192 .close = snd_rme32_playback_close,
1193 .hw_params = snd_rme32_playback_hw_params,
1194 .prepare = snd_rme32_playback_prepare,
1195 .trigger = snd_rme32_pcm_trigger,
1196 .pointer = snd_rme32_playback_pointer,
1197 .copy_user = snd_rme32_playback_copy,
1198 .copy_kernel = snd_rme32_playback_copy_kernel,
1199 .fill_silence = snd_rme32_playback_silence,
1200 .mmap = snd_pcm_lib_mmap_iomem,
1201};
1202
1203static const struct snd_pcm_ops snd_rme32_capture_spdif_ops = {
1204 .open = snd_rme32_capture_spdif_open,
1205 .close = snd_rme32_capture_close,
1206 .hw_params = snd_rme32_capture_hw_params,
1207 .prepare = snd_rme32_capture_prepare,
1208 .trigger = snd_rme32_pcm_trigger,
1209 .pointer = snd_rme32_capture_pointer,
1210 .copy_user = snd_rme32_capture_copy,
1211 .copy_kernel = snd_rme32_capture_copy_kernel,
1212 .mmap = snd_pcm_lib_mmap_iomem,
1213};
1214
1215static const struct snd_pcm_ops snd_rme32_playback_adat_ops = {
1216 .open = snd_rme32_playback_adat_open,
1217 .close = snd_rme32_playback_close,
1218 .hw_params = snd_rme32_playback_hw_params,
1219 .prepare = snd_rme32_playback_prepare,
1220 .trigger = snd_rme32_pcm_trigger,
1221 .pointer = snd_rme32_playback_pointer,
1222 .copy_user = snd_rme32_playback_copy,
1223 .copy_kernel = snd_rme32_playback_copy_kernel,
1224 .fill_silence = snd_rme32_playback_silence,
1225 .mmap = snd_pcm_lib_mmap_iomem,
1226};
1227
1228static const struct snd_pcm_ops snd_rme32_capture_adat_ops = {
1229 .open = snd_rme32_capture_adat_open,
1230 .close = snd_rme32_capture_close,
1231 .hw_params = snd_rme32_capture_hw_params,
1232 .prepare = snd_rme32_capture_prepare,
1233 .trigger = snd_rme32_pcm_trigger,
1234 .pointer = snd_rme32_capture_pointer,
1235 .copy_user = snd_rme32_capture_copy,
1236 .copy_kernel = snd_rme32_capture_copy_kernel,
1237 .mmap = snd_pcm_lib_mmap_iomem,
1238};
1239
1240
1241static const struct snd_pcm_ops snd_rme32_playback_spdif_fd_ops = {
1242 .open = snd_rme32_playback_spdif_open,
1243 .close = snd_rme32_playback_close,
1244 .hw_params = snd_rme32_playback_hw_params,
1245 .prepare = snd_rme32_playback_prepare,
1246 .trigger = snd_rme32_pcm_trigger,
1247 .pointer = snd_rme32_playback_fd_pointer,
1248 .ack = snd_rme32_playback_fd_ack,
1249};
1250
1251static const struct snd_pcm_ops snd_rme32_capture_spdif_fd_ops = {
1252 .open = snd_rme32_capture_spdif_open,
1253 .close = snd_rme32_capture_close,
1254 .hw_params = snd_rme32_capture_hw_params,
1255 .prepare = snd_rme32_capture_prepare,
1256 .trigger = snd_rme32_pcm_trigger,
1257 .pointer = snd_rme32_capture_fd_pointer,
1258 .ack = snd_rme32_capture_fd_ack,
1259};
1260
1261static const struct snd_pcm_ops snd_rme32_playback_adat_fd_ops = {
1262 .open = snd_rme32_playback_adat_open,
1263 .close = snd_rme32_playback_close,
1264 .hw_params = snd_rme32_playback_hw_params,
1265 .prepare = snd_rme32_playback_prepare,
1266 .trigger = snd_rme32_pcm_trigger,
1267 .pointer = snd_rme32_playback_fd_pointer,
1268 .ack = snd_rme32_playback_fd_ack,
1269};
1270
1271static const struct snd_pcm_ops snd_rme32_capture_adat_fd_ops = {
1272 .open = snd_rme32_capture_adat_open,
1273 .close = snd_rme32_capture_close,
1274 .hw_params = snd_rme32_capture_hw_params,
1275 .prepare = snd_rme32_capture_prepare,
1276 .trigger = snd_rme32_pcm_trigger,
1277 .pointer = snd_rme32_capture_fd_pointer,
1278 .ack = snd_rme32_capture_fd_ack,
1279};
1280
1281static void snd_rme32_free(struct rme32 *rme32)
1282{
1283 if (rme32->irq >= 0)
1284 snd_rme32_pcm_stop(rme32, 0);
1285}
1286
1287static void snd_rme32_free_spdif_pcm(struct snd_pcm *pcm)
1288{
1289 struct rme32 *rme32 = (struct rme32 *) pcm->private_data;
1290 rme32->spdif_pcm = NULL;
1291}
1292
1293static void
1294snd_rme32_free_adat_pcm(struct snd_pcm *pcm)
1295{
1296 struct rme32 *rme32 = (struct rme32 *) pcm->private_data;
1297 rme32->adat_pcm = NULL;
1298}
1299
1300static int snd_rme32_create(struct rme32 *rme32)
1301{
1302 struct pci_dev *pci = rme32->pci;
1303 int err;
1304
1305 rme32->irq = -1;
1306 spin_lock_init(&rme32->lock);
1307
1308 err = pcim_enable_device(pci);
1309 if (err < 0)
1310 return err;
1311
1312 err = pci_request_regions(pci, "RME32");
1313 if (err < 0)
1314 return err;
1315 rme32->port = pci_resource_start(rme32->pci, 0);
1316
1317 rme32->iobase = devm_ioremap(&pci->dev, rme32->port, RME32_IO_SIZE);
1318 if (!rme32->iobase) {
1319 dev_err(rme32->card->dev,
1320 "unable to remap memory region 0x%lx-0x%lx\n",
1321 rme32->port, rme32->port + RME32_IO_SIZE - 1);
1322 return -ENOMEM;
1323 }
1324
1325 if (devm_request_irq(&pci->dev, pci->irq, snd_rme32_interrupt,
1326 IRQF_SHARED, KBUILD_MODNAME, rme32)) {
1327 dev_err(rme32->card->dev, "unable to grab IRQ %d\n", pci->irq);
1328 return -EBUSY;
1329 }
1330 rme32->irq = pci->irq;
1331 rme32->card->sync_irq = rme32->irq;
1332
1333
1334 pci_read_config_byte(pci, 8, &rme32->rev);
1335
1336
1337 err = snd_pcm_new(rme32->card, "Digi32 IEC958", 0, 1, 1, &rme32->spdif_pcm);
1338 if (err < 0)
1339 return err;
1340 rme32->spdif_pcm->private_data = rme32;
1341 rme32->spdif_pcm->private_free = snd_rme32_free_spdif_pcm;
1342 strcpy(rme32->spdif_pcm->name, "Digi32 IEC958");
1343 if (rme32->fullduplex_mode) {
1344 snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_PLAYBACK,
1345 &snd_rme32_playback_spdif_fd_ops);
1346 snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_CAPTURE,
1347 &snd_rme32_capture_spdif_fd_ops);
1348 snd_pcm_set_managed_buffer_all(rme32->spdif_pcm, SNDRV_DMA_TYPE_CONTINUOUS,
1349 NULL, 0, RME32_MID_BUFFER_SIZE);
1350 rme32->spdif_pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
1351 } else {
1352 snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_PLAYBACK,
1353 &snd_rme32_playback_spdif_ops);
1354 snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_CAPTURE,
1355 &snd_rme32_capture_spdif_ops);
1356 rme32->spdif_pcm->info_flags = SNDRV_PCM_INFO_HALF_DUPLEX;
1357 }
1358
1359
1360 if ((pci->device == PCI_DEVICE_ID_RME_DIGI32) ||
1361 (pci->device == PCI_DEVICE_ID_RME_DIGI32_PRO)) {
1362
1363 rme32->adat_pcm = NULL;
1364 }
1365 else {
1366 err = snd_pcm_new(rme32->card, "Digi32 ADAT", 1,
1367 1, 1, &rme32->adat_pcm);
1368 if (err < 0)
1369 return err;
1370 rme32->adat_pcm->private_data = rme32;
1371 rme32->adat_pcm->private_free = snd_rme32_free_adat_pcm;
1372 strcpy(rme32->adat_pcm->name, "Digi32 ADAT");
1373 if (rme32->fullduplex_mode) {
1374 snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_PLAYBACK,
1375 &snd_rme32_playback_adat_fd_ops);
1376 snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_CAPTURE,
1377 &snd_rme32_capture_adat_fd_ops);
1378 snd_pcm_set_managed_buffer_all(rme32->adat_pcm, SNDRV_DMA_TYPE_CONTINUOUS,
1379 NULL,
1380 0, RME32_MID_BUFFER_SIZE);
1381 rme32->adat_pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
1382 } else {
1383 snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_PLAYBACK,
1384 &snd_rme32_playback_adat_ops);
1385 snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_CAPTURE,
1386 &snd_rme32_capture_adat_ops);
1387 rme32->adat_pcm->info_flags = SNDRV_PCM_INFO_HALF_DUPLEX;
1388 }
1389 }
1390
1391
1392 rme32->playback_periodsize = 0;
1393 rme32->capture_periodsize = 0;
1394
1395
1396 snd_rme32_pcm_stop(rme32, 0);
1397
1398
1399 snd_rme32_reset_dac(rme32);
1400
1401
1402 writel(0, rme32->iobase + RME32_IO_RESET_POS);
1403
1404
1405 rme32->wcreg = RME32_WCR_SEL |
1406 RME32_WCR_INP_0 |
1407 RME32_WCR_MUTE;
1408 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
1409
1410
1411
1412 err = snd_rme32_create_switches(rme32->card, rme32);
1413 if (err < 0)
1414 return err;
1415
1416
1417 snd_rme32_proc_init(rme32);
1418
1419 rme32->capture_substream = NULL;
1420 rme32->playback_substream = NULL;
1421
1422 return 0;
1423}
1424
1425
1426
1427
1428
1429static void
1430snd_rme32_proc_read(struct snd_info_entry * entry, struct snd_info_buffer *buffer)
1431{
1432 int n;
1433 struct rme32 *rme32 = (struct rme32 *) entry->private_data;
1434
1435 rme32->rcreg = readl(rme32->iobase + RME32_IO_CONTROL_REGISTER);
1436
1437 snd_iprintf(buffer, rme32->card->longname);
1438 snd_iprintf(buffer, " (index #%d)\n", rme32->card->number + 1);
1439
1440 snd_iprintf(buffer, "\nGeneral settings\n");
1441 if (rme32->fullduplex_mode)
1442 snd_iprintf(buffer, " Full-duplex mode\n");
1443 else
1444 snd_iprintf(buffer, " Half-duplex mode\n");
1445 if (RME32_PRO_WITH_8414(rme32)) {
1446 snd_iprintf(buffer, " receiver: CS8414\n");
1447 } else {
1448 snd_iprintf(buffer, " receiver: CS8412\n");
1449 }
1450 if (rme32->wcreg & RME32_WCR_MODE24) {
1451 snd_iprintf(buffer, " format: 24 bit");
1452 } else {
1453 snd_iprintf(buffer, " format: 16 bit");
1454 }
1455 if (rme32->wcreg & RME32_WCR_MONO) {
1456 snd_iprintf(buffer, ", Mono\n");
1457 } else {
1458 snd_iprintf(buffer, ", Stereo\n");
1459 }
1460
1461 snd_iprintf(buffer, "\nInput settings\n");
1462 switch (snd_rme32_getinputtype(rme32)) {
1463 case RME32_INPUT_OPTICAL:
1464 snd_iprintf(buffer, " input: optical");
1465 break;
1466 case RME32_INPUT_COAXIAL:
1467 snd_iprintf(buffer, " input: coaxial");
1468 break;
1469 case RME32_INPUT_INTERNAL:
1470 snd_iprintf(buffer, " input: internal");
1471 break;
1472 case RME32_INPUT_XLR:
1473 snd_iprintf(buffer, " input: XLR");
1474 break;
1475 }
1476 if (snd_rme32_capture_getrate(rme32, &n) < 0) {
1477 snd_iprintf(buffer, "\n sample rate: no valid signal\n");
1478 } else {
1479 if (n) {
1480 snd_iprintf(buffer, " (8 channels)\n");
1481 } else {
1482 snd_iprintf(buffer, " (2 channels)\n");
1483 }
1484 snd_iprintf(buffer, " sample rate: %d Hz\n",
1485 snd_rme32_capture_getrate(rme32, &n));
1486 }
1487
1488 snd_iprintf(buffer, "\nOutput settings\n");
1489 if (rme32->wcreg & RME32_WCR_SEL) {
1490 snd_iprintf(buffer, " output signal: normal playback");
1491 } else {
1492 snd_iprintf(buffer, " output signal: same as input");
1493 }
1494 if (rme32->wcreg & RME32_WCR_MUTE) {
1495 snd_iprintf(buffer, " (muted)\n");
1496 } else {
1497 snd_iprintf(buffer, "\n");
1498 }
1499
1500
1501 if (!
1502 ((!(rme32->wcreg & RME32_WCR_FREQ_0))
1503 && (!(rme32->wcreg & RME32_WCR_FREQ_1)))) {
1504 snd_iprintf(buffer, " sample rate: %d Hz\n",
1505 snd_rme32_playback_getrate(rme32));
1506 }
1507 if (rme32->rcreg & RME32_RCR_KMODE) {
1508 snd_iprintf(buffer, " sample clock source: AutoSync\n");
1509 } else {
1510 snd_iprintf(buffer, " sample clock source: Internal\n");
1511 }
1512 if (rme32->wcreg & RME32_WCR_PRO) {
1513 snd_iprintf(buffer, " format: AES/EBU (professional)\n");
1514 } else {
1515 snd_iprintf(buffer, " format: IEC958 (consumer)\n");
1516 }
1517 if (rme32->wcreg & RME32_WCR_EMP) {
1518 snd_iprintf(buffer, " emphasis: on\n");
1519 } else {
1520 snd_iprintf(buffer, " emphasis: off\n");
1521 }
1522}
1523
1524static void snd_rme32_proc_init(struct rme32 *rme32)
1525{
1526 snd_card_ro_proc_new(rme32->card, "rme32", rme32, snd_rme32_proc_read);
1527}
1528
1529
1530
1531
1532
1533#define snd_rme32_info_loopback_control snd_ctl_boolean_mono_info
1534
1535static int
1536snd_rme32_get_loopback_control(struct snd_kcontrol *kcontrol,
1537 struct snd_ctl_elem_value *ucontrol)
1538{
1539 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1540
1541 spin_lock_irq(&rme32->lock);
1542 ucontrol->value.integer.value[0] =
1543 rme32->wcreg & RME32_WCR_SEL ? 0 : 1;
1544 spin_unlock_irq(&rme32->lock);
1545 return 0;
1546}
1547static int
1548snd_rme32_put_loopback_control(struct snd_kcontrol *kcontrol,
1549 struct snd_ctl_elem_value *ucontrol)
1550{
1551 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1552 unsigned int val;
1553 int change;
1554
1555 val = ucontrol->value.integer.value[0] ? 0 : RME32_WCR_SEL;
1556 spin_lock_irq(&rme32->lock);
1557 val = (rme32->wcreg & ~RME32_WCR_SEL) | val;
1558 change = val != rme32->wcreg;
1559 if (ucontrol->value.integer.value[0])
1560 val &= ~RME32_WCR_MUTE;
1561 else
1562 val |= RME32_WCR_MUTE;
1563 rme32->wcreg = val;
1564 writel(val, rme32->iobase + RME32_IO_CONTROL_REGISTER);
1565 spin_unlock_irq(&rme32->lock);
1566 return change;
1567}
1568
1569static int
1570snd_rme32_info_inputtype_control(struct snd_kcontrol *kcontrol,
1571 struct snd_ctl_elem_info *uinfo)
1572{
1573 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1574 static const char * const texts[4] = {
1575 "Optical", "Coaxial", "Internal", "XLR"
1576 };
1577 int num_items;
1578
1579 switch (rme32->pci->device) {
1580 case PCI_DEVICE_ID_RME_DIGI32:
1581 case PCI_DEVICE_ID_RME_DIGI32_8:
1582 num_items = 3;
1583 break;
1584 case PCI_DEVICE_ID_RME_DIGI32_PRO:
1585 num_items = 4;
1586 break;
1587 default:
1588 snd_BUG();
1589 return -EINVAL;
1590 }
1591 return snd_ctl_enum_info(uinfo, 1, num_items, texts);
1592}
1593static int
1594snd_rme32_get_inputtype_control(struct snd_kcontrol *kcontrol,
1595 struct snd_ctl_elem_value *ucontrol)
1596{
1597 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1598 unsigned int items = 3;
1599
1600 spin_lock_irq(&rme32->lock);
1601 ucontrol->value.enumerated.item[0] = snd_rme32_getinputtype(rme32);
1602
1603 switch (rme32->pci->device) {
1604 case PCI_DEVICE_ID_RME_DIGI32:
1605 case PCI_DEVICE_ID_RME_DIGI32_8:
1606 items = 3;
1607 break;
1608 case PCI_DEVICE_ID_RME_DIGI32_PRO:
1609 items = 4;
1610 break;
1611 default:
1612 snd_BUG();
1613 break;
1614 }
1615 if (ucontrol->value.enumerated.item[0] >= items) {
1616 ucontrol->value.enumerated.item[0] = items - 1;
1617 }
1618
1619 spin_unlock_irq(&rme32->lock);
1620 return 0;
1621}
1622static int
1623snd_rme32_put_inputtype_control(struct snd_kcontrol *kcontrol,
1624 struct snd_ctl_elem_value *ucontrol)
1625{
1626 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1627 unsigned int val;
1628 int change, items = 3;
1629
1630 switch (rme32->pci->device) {
1631 case PCI_DEVICE_ID_RME_DIGI32:
1632 case PCI_DEVICE_ID_RME_DIGI32_8:
1633 items = 3;
1634 break;
1635 case PCI_DEVICE_ID_RME_DIGI32_PRO:
1636 items = 4;
1637 break;
1638 default:
1639 snd_BUG();
1640 break;
1641 }
1642 val = ucontrol->value.enumerated.item[0] % items;
1643
1644 spin_lock_irq(&rme32->lock);
1645 change = val != (unsigned int)snd_rme32_getinputtype(rme32);
1646 snd_rme32_setinputtype(rme32, val);
1647 spin_unlock_irq(&rme32->lock);
1648 return change;
1649}
1650
1651static int
1652snd_rme32_info_clockmode_control(struct snd_kcontrol *kcontrol,
1653 struct snd_ctl_elem_info *uinfo)
1654{
1655 static const char * const texts[4] = { "AutoSync",
1656 "Internal 32.0kHz",
1657 "Internal 44.1kHz",
1658 "Internal 48.0kHz" };
1659
1660 return snd_ctl_enum_info(uinfo, 1, 4, texts);
1661}
1662static int
1663snd_rme32_get_clockmode_control(struct snd_kcontrol *kcontrol,
1664 struct snd_ctl_elem_value *ucontrol)
1665{
1666 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1667
1668 spin_lock_irq(&rme32->lock);
1669 ucontrol->value.enumerated.item[0] = snd_rme32_getclockmode(rme32);
1670 spin_unlock_irq(&rme32->lock);
1671 return 0;
1672}
1673static int
1674snd_rme32_put_clockmode_control(struct snd_kcontrol *kcontrol,
1675 struct snd_ctl_elem_value *ucontrol)
1676{
1677 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1678 unsigned int val;
1679 int change;
1680
1681 val = ucontrol->value.enumerated.item[0] % 3;
1682 spin_lock_irq(&rme32->lock);
1683 change = val != (unsigned int)snd_rme32_getclockmode(rme32);
1684 snd_rme32_setclockmode(rme32, val);
1685 spin_unlock_irq(&rme32->lock);
1686 return change;
1687}
1688
1689static u32 snd_rme32_convert_from_aes(struct snd_aes_iec958 * aes)
1690{
1691 u32 val = 0;
1692 val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? RME32_WCR_PRO : 0;
1693 if (val & RME32_WCR_PRO)
1694 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? RME32_WCR_EMP : 0;
1695 else
1696 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? RME32_WCR_EMP : 0;
1697 return val;
1698}
1699
1700static void snd_rme32_convert_to_aes(struct snd_aes_iec958 * aes, u32 val)
1701{
1702 aes->status[0] = ((val & RME32_WCR_PRO) ? IEC958_AES0_PROFESSIONAL : 0);
1703 if (val & RME32_WCR_PRO)
1704 aes->status[0] |= (val & RME32_WCR_EMP) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
1705 else
1706 aes->status[0] |= (val & RME32_WCR_EMP) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
1707}
1708
1709static int snd_rme32_control_spdif_info(struct snd_kcontrol *kcontrol,
1710 struct snd_ctl_elem_info *uinfo)
1711{
1712 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1713 uinfo->count = 1;
1714 return 0;
1715}
1716
1717static int snd_rme32_control_spdif_get(struct snd_kcontrol *kcontrol,
1718 struct snd_ctl_elem_value *ucontrol)
1719{
1720 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1721
1722 snd_rme32_convert_to_aes(&ucontrol->value.iec958,
1723 rme32->wcreg_spdif);
1724 return 0;
1725}
1726
1727static int snd_rme32_control_spdif_put(struct snd_kcontrol *kcontrol,
1728 struct snd_ctl_elem_value *ucontrol)
1729{
1730 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1731 int change;
1732 u32 val;
1733
1734 val = snd_rme32_convert_from_aes(&ucontrol->value.iec958);
1735 spin_lock_irq(&rme32->lock);
1736 change = val != rme32->wcreg_spdif;
1737 rme32->wcreg_spdif = val;
1738 spin_unlock_irq(&rme32->lock);
1739 return change;
1740}
1741
1742static int snd_rme32_control_spdif_stream_info(struct snd_kcontrol *kcontrol,
1743 struct snd_ctl_elem_info *uinfo)
1744{
1745 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1746 uinfo->count = 1;
1747 return 0;
1748}
1749
1750static int snd_rme32_control_spdif_stream_get(struct snd_kcontrol *kcontrol,
1751 struct snd_ctl_elem_value *
1752 ucontrol)
1753{
1754 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1755
1756 snd_rme32_convert_to_aes(&ucontrol->value.iec958,
1757 rme32->wcreg_spdif_stream);
1758 return 0;
1759}
1760
1761static int snd_rme32_control_spdif_stream_put(struct snd_kcontrol *kcontrol,
1762 struct snd_ctl_elem_value *
1763 ucontrol)
1764{
1765 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1766 int change;
1767 u32 val;
1768
1769 val = snd_rme32_convert_from_aes(&ucontrol->value.iec958);
1770 spin_lock_irq(&rme32->lock);
1771 change = val != rme32->wcreg_spdif_stream;
1772 rme32->wcreg_spdif_stream = val;
1773 rme32->wcreg &= ~(RME32_WCR_PRO | RME32_WCR_EMP);
1774 rme32->wcreg |= val;
1775 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
1776 spin_unlock_irq(&rme32->lock);
1777 return change;
1778}
1779
1780static int snd_rme32_control_spdif_mask_info(struct snd_kcontrol *kcontrol,
1781 struct snd_ctl_elem_info *uinfo)
1782{
1783 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1784 uinfo->count = 1;
1785 return 0;
1786}
1787
1788static int snd_rme32_control_spdif_mask_get(struct snd_kcontrol *kcontrol,
1789 struct snd_ctl_elem_value *
1790 ucontrol)
1791{
1792 ucontrol->value.iec958.status[0] = kcontrol->private_value;
1793 return 0;
1794}
1795
1796static const struct snd_kcontrol_new snd_rme32_controls[] = {
1797 {
1798 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1799 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
1800 .info = snd_rme32_control_spdif_info,
1801 .get = snd_rme32_control_spdif_get,
1802 .put = snd_rme32_control_spdif_put
1803 },
1804 {
1805 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
1806 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1807 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, PCM_STREAM),
1808 .info = snd_rme32_control_spdif_stream_info,
1809 .get = snd_rme32_control_spdif_stream_get,
1810 .put = snd_rme32_control_spdif_stream_put
1811 },
1812 {
1813 .access = SNDRV_CTL_ELEM_ACCESS_READ,
1814 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1815 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, CON_MASK),
1816 .info = snd_rme32_control_spdif_mask_info,
1817 .get = snd_rme32_control_spdif_mask_get,
1818 .private_value = IEC958_AES0_PROFESSIONAL | IEC958_AES0_CON_EMPHASIS
1819 },
1820 {
1821 .access = SNDRV_CTL_ELEM_ACCESS_READ,
1822 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1823 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, PRO_MASK),
1824 .info = snd_rme32_control_spdif_mask_info,
1825 .get = snd_rme32_control_spdif_mask_get,
1826 .private_value = IEC958_AES0_PROFESSIONAL | IEC958_AES0_PRO_EMPHASIS
1827 },
1828 {
1829 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1830 .name = "Input Connector",
1831 .info = snd_rme32_info_inputtype_control,
1832 .get = snd_rme32_get_inputtype_control,
1833 .put = snd_rme32_put_inputtype_control
1834 },
1835 {
1836 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1837 .name = "Loopback Input",
1838 .info = snd_rme32_info_loopback_control,
1839 .get = snd_rme32_get_loopback_control,
1840 .put = snd_rme32_put_loopback_control
1841 },
1842 {
1843 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1844 .name = "Sample Clock Source",
1845 .info = snd_rme32_info_clockmode_control,
1846 .get = snd_rme32_get_clockmode_control,
1847 .put = snd_rme32_put_clockmode_control
1848 }
1849};
1850
1851static int snd_rme32_create_switches(struct snd_card *card, struct rme32 * rme32)
1852{
1853 int idx, err;
1854 struct snd_kcontrol *kctl;
1855
1856 for (idx = 0; idx < (int)ARRAY_SIZE(snd_rme32_controls); idx++) {
1857 kctl = snd_ctl_new1(&snd_rme32_controls[idx], rme32);
1858 err = snd_ctl_add(card, kctl);
1859 if (err < 0)
1860 return err;
1861 if (idx == 1)
1862 rme32->spdif_ctl = kctl;
1863 }
1864
1865 return 0;
1866}
1867
1868
1869
1870
1871
1872static void snd_rme32_card_free(struct snd_card *card)
1873{
1874 snd_rme32_free(card->private_data);
1875}
1876
1877static int
1878snd_rme32_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
1879{
1880 static int dev;
1881 struct rme32 *rme32;
1882 struct snd_card *card;
1883 int err;
1884
1885 if (dev >= SNDRV_CARDS) {
1886 return -ENODEV;
1887 }
1888 if (!enable[dev]) {
1889 dev++;
1890 return -ENOENT;
1891 }
1892
1893 err = snd_devm_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
1894 sizeof(*rme32), &card);
1895 if (err < 0)
1896 return err;
1897 card->private_free = snd_rme32_card_free;
1898 rme32 = (struct rme32 *) card->private_data;
1899 rme32->card = card;
1900 rme32->pci = pci;
1901 if (fullduplex[dev])
1902 rme32->fullduplex_mode = 1;
1903 err = snd_rme32_create(rme32);
1904 if (err < 0)
1905 return err;
1906
1907 strcpy(card->driver, "Digi32");
1908 switch (rme32->pci->device) {
1909 case PCI_DEVICE_ID_RME_DIGI32:
1910 strcpy(card->shortname, "RME Digi32");
1911 break;
1912 case PCI_DEVICE_ID_RME_DIGI32_8:
1913 strcpy(card->shortname, "RME Digi32/8");
1914 break;
1915 case PCI_DEVICE_ID_RME_DIGI32_PRO:
1916 strcpy(card->shortname, "RME Digi32 PRO");
1917 break;
1918 }
1919 sprintf(card->longname, "%s (Rev. %d) at 0x%lx, irq %d",
1920 card->shortname, rme32->rev, rme32->port, rme32->irq);
1921
1922 err = snd_card_register(card);
1923 if (err < 0)
1924 return err;
1925 pci_set_drvdata(pci, card);
1926 dev++;
1927 return 0;
1928}
1929
1930static struct pci_driver rme32_driver = {
1931 .name = KBUILD_MODNAME,
1932 .id_table = snd_rme32_ids,
1933 .probe = snd_rme32_probe,
1934};
1935
1936module_pci_driver(rme32_driver);
1937
