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7
8
9#include <linux/delay.h>
10#include <linux/init.h>
11#include <linux/interrupt.h>
12#include <linux/pci.h>
13#include <linux/module.h>
14#include <linux/io.h>
15#include <linux/nospec.h>
16
17#include <sound/core.h>
18#include <sound/control.h>
19#include <sound/pcm.h>
20#include <sound/info.h>
21#include <sound/asoundef.h>
22#include <sound/initval.h>
23
24#include <asm/current.h>
25
26static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
27static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
28static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
29static bool precise_ptr[SNDRV_CARDS];
30
31module_param_array(index, int, NULL, 0444);
32MODULE_PARM_DESC(index, "Index value for RME Digi9652 (Hammerfall) soundcard.");
33module_param_array(id, charp, NULL, 0444);
34MODULE_PARM_DESC(id, "ID string for RME Digi9652 (Hammerfall) soundcard.");
35module_param_array(enable, bool, NULL, 0444);
36MODULE_PARM_DESC(enable, "Enable/disable specific RME96{52,36} soundcards.");
37module_param_array(precise_ptr, bool, NULL, 0444);
38MODULE_PARM_DESC(precise_ptr, "Enable precise pointer (doesn't work reliably).");
39MODULE_AUTHOR("Paul Davis <pbd@op.net>, Winfried Ritsch");
40MODULE_DESCRIPTION("RME Digi9652/Digi9636");
41MODULE_LICENSE("GPL");
42
43
44
45
46
47
48
49
50
51
52#define RME9652_NCHANNELS 26
53#define RME9636_NCHANNELS 18
54
55
56
57#define RME9652_SYNC_FROM_SPDIF 0
58#define RME9652_SYNC_FROM_ADAT1 1
59#define RME9652_SYNC_FROM_ADAT2 2
60#define RME9652_SYNC_FROM_ADAT3 3
61
62
63
64#define RME9652_SPDIFIN_OPTICAL 0
65#define RME9652_SPDIFIN_COAXIAL 1
66#define RME9652_SPDIFIN_INTERN 2
67
68
69
70#define RME9652_IRQ (1<<0)
71#define RME9652_lock_2 (1<<1)
72#define RME9652_lock_1 (1<<2)
73#define RME9652_lock_0 (1<<3)
74#define RME9652_fs48 (1<<4)
75#define RME9652_wsel_rd (1<<5)
76
77#define RME9652_sync_2 (1<<16)
78#define RME9652_sync_1 (1<<17)
79#define RME9652_sync_0 (1<<18)
80#define RME9652_DS_rd (1<<19)
81#define RME9652_tc_busy (1<<20)
82#define RME9652_tc_out (1<<21)
83#define RME9652_F_0 (1<<22)
84#define RME9652_F_1 (1<<23)
85#define RME9652_F_2 (1<<24)
86#define RME9652_ERF (1<<25)
87#define RME9652_buffer_id (1<<26)
88#define RME9652_tc_valid (1<<27)
89#define RME9652_SPDIF_READ (1<<28)
90
91#define RME9652_sync (RME9652_sync_0|RME9652_sync_1|RME9652_sync_2)
92#define RME9652_lock (RME9652_lock_0|RME9652_lock_1|RME9652_lock_2)
93#define RME9652_F (RME9652_F_0|RME9652_F_1|RME9652_F_2)
94#define rme9652_decode_spdif_rate(x) ((x)>>22)
95
96
97
98#define RME9652_buf_pos 0x000FFC0
99
100
101
102
103
104#define RME9652_REV15_buf_pos(x) ((((x)&0xE0000000)>>26)|((x)&RME9652_buf_pos))
105
106
107
108
109
110#define RME9652_IO_EXTENT 1024
111
112#define RME9652_init_buffer 0
113#define RME9652_play_buffer 32
114#define RME9652_rec_buffer 36
115#define RME9652_control_register 64
116#define RME9652_irq_clear 96
117#define RME9652_time_code 100
118#define RME9652_thru_base 128
119
120
121
122
123
124
125
126#define RME9652_status_register 0
127
128
129
130
131#define RME9652_start_bit (1<<0)
132
133#define RME9652_Master (1<<4)
134#define RME9652_IE (1<<5)
135#define RME9652_freq (1<<6)
136#define RME9652_freq1 (1<<7)
137#define RME9652_DS (1<<8)
138#define RME9652_PRO (1<<9)
139#define RME9652_EMP (1<<10)
140#define RME9652_Dolby (1<<11)
141#define RME9652_opt_out (1<<12)
142#define RME9652_wsel (1<<13)
143#define RME9652_inp_0 (1<<14)
144#define RME9652_inp_1 (1<<15)
145#define RME9652_SyncPref_ADAT2 (1<<16)
146#define RME9652_SyncPref_ADAT3 (1<<17)
147#define RME9652_SPDIF_RESET (1<<18)
148#define RME9652_SPDIF_SELECT (1<<19)
149#define RME9652_SPDIF_CLOCK (1<<20)
150#define RME9652_SPDIF_WRITE (1<<21)
151#define RME9652_ADAT1_INTERNAL (1<<22)
152
153
154
155#define RME9652_latency 0x0e
156#define rme9652_encode_latency(x) (((x)&0x7)<<1)
157#define rme9652_decode_latency(x) (((x)>>1)&0x7)
158#define rme9652_running_double_speed(s) ((s)->control_register & RME9652_DS)
159#define RME9652_inp (RME9652_inp_0|RME9652_inp_1)
160#define rme9652_encode_spdif_in(x) (((x)&0x3)<<14)
161#define rme9652_decode_spdif_in(x) (((x)>>14)&0x3)
162
163#define RME9652_SyncPref_Mask (RME9652_SyncPref_ADAT2|RME9652_SyncPref_ADAT3)
164#define RME9652_SyncPref_ADAT1 0
165#define RME9652_SyncPref_SPDIF (RME9652_SyncPref_ADAT2|RME9652_SyncPref_ADAT3)
166
167
168
169#define RME9652_CHANNEL_BUFFER_SAMPLES (16*1024)
170#define RME9652_CHANNEL_BUFFER_BYTES (4*RME9652_CHANNEL_BUFFER_SAMPLES)
171
172
173
174
175
176
177
178
179
180
181#define RME9652_DMA_AREA_BYTES ((RME9652_NCHANNELS+1) * RME9652_CHANNEL_BUFFER_BYTES)
182#define RME9652_DMA_AREA_KILOBYTES (RME9652_DMA_AREA_BYTES/1024)
183
184struct snd_rme9652 {
185 int dev;
186
187 spinlock_t lock;
188 int irq;
189 unsigned long port;
190 void __iomem *iobase;
191
192 int precise_ptr;
193
194 u32 control_register;
195 u32 thru_bits;
196
197 u32 creg_spdif;
198 u32 creg_spdif_stream;
199
200 char *card_name;
201
202 size_t hw_offsetmask;
203 size_t prev_hw_offset;
204 size_t max_jitter;
205
206 size_t period_bytes;
207
208 unsigned char ds_channels;
209 unsigned char ss_channels;
210
211
212
213
214 struct snd_dma_buffer playback_dma_buf;
215 struct snd_dma_buffer capture_dma_buf;
216
217 unsigned char *capture_buffer;
218 unsigned char *playback_buffer;
219
220 pid_t capture_pid;
221 pid_t playback_pid;
222
223 struct snd_pcm_substream *capture_substream;
224 struct snd_pcm_substream *playback_substream;
225 int running;
226
227 int passthru;
228 int hw_rev;
229
230 int last_spdif_sample_rate;
231 int last_adat_sample_rate;
232
233 const char *channel_map;
234
235 struct snd_card *card;
236 struct snd_pcm *pcm;
237 struct pci_dev *pci;
238 struct snd_kcontrol *spdif_ctl;
239
240};
241
242
243
244
245
246
247
248
249
250static const char channel_map_9652_ss[26] = {
251 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
252 18, 19, 20, 21, 22, 23, 24, 25
253};
254
255static const char channel_map_9636_ss[26] = {
256 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
257
258 24, 25,
259
260 -1, -1, -1, -1, -1, -1, -1, -1
261};
262
263static const char channel_map_9652_ds[26] = {
264
265 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23,
266
267 24, 25,
268
269 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
270};
271
272static const char channel_map_9636_ds[26] = {
273
274 1, 3, 5, 7, 9, 11, 13, 15,
275
276 24, 25,
277
278 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
279};
280
281static struct snd_dma_buffer *
282snd_hammerfall_get_buffer(struct pci_dev *pci, size_t size)
283{
284 return snd_devm_alloc_pages(&pci->dev, SNDRV_DMA_TYPE_DEV, size);
285}
286
287static const struct pci_device_id snd_rme9652_ids[] = {
288 {
289 .vendor = 0x10ee,
290 .device = 0x3fc4,
291 .subvendor = PCI_ANY_ID,
292 .subdevice = PCI_ANY_ID,
293 },
294 { 0, },
295};
296
297MODULE_DEVICE_TABLE(pci, snd_rme9652_ids);
298
299static inline void rme9652_write(struct snd_rme9652 *rme9652, int reg, int val)
300{
301 writel(val, rme9652->iobase + reg);
302}
303
304static inline unsigned int rme9652_read(struct snd_rme9652 *rme9652, int reg)
305{
306 return readl(rme9652->iobase + reg);
307}
308
309static inline int snd_rme9652_use_is_exclusive(struct snd_rme9652 *rme9652)
310{
311 unsigned long flags;
312 int ret = 1;
313
314 spin_lock_irqsave(&rme9652->lock, flags);
315 if ((rme9652->playback_pid != rme9652->capture_pid) &&
316 (rme9652->playback_pid >= 0) && (rme9652->capture_pid >= 0)) {
317 ret = 0;
318 }
319 spin_unlock_irqrestore(&rme9652->lock, flags);
320 return ret;
321}
322
323static inline int rme9652_adat_sample_rate(struct snd_rme9652 *rme9652)
324{
325 if (rme9652_running_double_speed(rme9652)) {
326 return (rme9652_read(rme9652, RME9652_status_register) &
327 RME9652_fs48) ? 96000 : 88200;
328 } else {
329 return (rme9652_read(rme9652, RME9652_status_register) &
330 RME9652_fs48) ? 48000 : 44100;
331 }
332}
333
334static inline void rme9652_compute_period_size(struct snd_rme9652 *rme9652)
335{
336 unsigned int i;
337
338 i = rme9652->control_register & RME9652_latency;
339 rme9652->period_bytes = 1 << ((rme9652_decode_latency(i) + 8));
340 rme9652->hw_offsetmask =
341 (rme9652->period_bytes * 2 - 1) & RME9652_buf_pos;
342 rme9652->max_jitter = 80;
343}
344
345static snd_pcm_uframes_t rme9652_hw_pointer(struct snd_rme9652 *rme9652)
346{
347 int status;
348 unsigned int offset, frag;
349 snd_pcm_uframes_t period_size = rme9652->period_bytes / 4;
350 snd_pcm_sframes_t delta;
351
352 status = rme9652_read(rme9652, RME9652_status_register);
353 if (!rme9652->precise_ptr)
354 return (status & RME9652_buffer_id) ? period_size : 0;
355 offset = status & RME9652_buf_pos;
356
357
358
359
360
361 delta = rme9652->prev_hw_offset - offset;
362 delta &= 0xffff;
363 if (delta <= (snd_pcm_sframes_t)rme9652->max_jitter * 4)
364 offset = rme9652->prev_hw_offset;
365 else
366 rme9652->prev_hw_offset = offset;
367 offset &= rme9652->hw_offsetmask;
368 offset /= 4;
369 frag = status & RME9652_buffer_id;
370
371 if (offset < period_size) {
372 if (offset > rme9652->max_jitter) {
373 if (frag)
374 dev_err(rme9652->card->dev,
375 "Unexpected hw_pointer position (bufid == 0): status: %x offset: %d\n",
376 status, offset);
377 } else if (!frag)
378 return 0;
379 offset -= rme9652->max_jitter;
380 if ((int)offset < 0)
381 offset += period_size * 2;
382 } else {
383 if (offset > period_size + rme9652->max_jitter) {
384 if (!frag)
385 dev_err(rme9652->card->dev,
386 "Unexpected hw_pointer position (bufid == 1): status: %x offset: %d\n",
387 status, offset);
388 } else if (frag)
389 return period_size;
390 offset -= rme9652->max_jitter;
391 }
392
393 return offset;
394}
395
396static inline void rme9652_reset_hw_pointer(struct snd_rme9652 *rme9652)
397{
398 int i;
399
400
401
402
403
404
405
406 for (i = 0; i < 8; i++) {
407 rme9652_write(rme9652, i * 4, 0);
408 udelay(10);
409 }
410 rme9652->prev_hw_offset = 0;
411}
412
413static inline void rme9652_start(struct snd_rme9652 *s)
414{
415 s->control_register |= (RME9652_IE | RME9652_start_bit);
416 rme9652_write(s, RME9652_control_register, s->control_register);
417}
418
419static inline void rme9652_stop(struct snd_rme9652 *s)
420{
421 s->control_register &= ~(RME9652_start_bit | RME9652_IE);
422 rme9652_write(s, RME9652_control_register, s->control_register);
423}
424
425static int rme9652_set_interrupt_interval(struct snd_rme9652 *s,
426 unsigned int frames)
427{
428 int restart = 0;
429 int n;
430
431 spin_lock_irq(&s->lock);
432
433 restart = s->running;
434 if (restart)
435 rme9652_stop(s);
436
437 frames >>= 7;
438 n = 0;
439 while (frames) {
440 n++;
441 frames >>= 1;
442 }
443
444 s->control_register &= ~RME9652_latency;
445 s->control_register |= rme9652_encode_latency(n);
446
447 rme9652_write(s, RME9652_control_register, s->control_register);
448
449 rme9652_compute_period_size(s);
450
451 if (restart)
452 rme9652_start(s);
453
454 spin_unlock_irq(&s->lock);
455
456 return 0;
457}
458
459static int rme9652_set_rate(struct snd_rme9652 *rme9652, int rate)
460{
461 int restart;
462 int reject_if_open = 0;
463 int xrate;
464
465 if (!snd_rme9652_use_is_exclusive (rme9652)) {
466 return -EBUSY;
467 }
468
469
470
471
472
473
474
475
476
477
478
479
480 spin_lock_irq(&rme9652->lock);
481 xrate = rme9652_adat_sample_rate(rme9652);
482
483 switch (rate) {
484 case 44100:
485 if (xrate > 48000) {
486 reject_if_open = 1;
487 }
488 rate = 0;
489 break;
490 case 48000:
491 if (xrate > 48000) {
492 reject_if_open = 1;
493 }
494 rate = RME9652_freq;
495 break;
496 case 88200:
497 if (xrate < 48000) {
498 reject_if_open = 1;
499 }
500 rate = RME9652_DS;
501 break;
502 case 96000:
503 if (xrate < 48000) {
504 reject_if_open = 1;
505 }
506 rate = RME9652_DS | RME9652_freq;
507 break;
508 default:
509 spin_unlock_irq(&rme9652->lock);
510 return -EINVAL;
511 }
512
513 if (reject_if_open && (rme9652->capture_pid >= 0 || rme9652->playback_pid >= 0)) {
514 spin_unlock_irq(&rme9652->lock);
515 return -EBUSY;
516 }
517
518 restart = rme9652->running;
519 if (restart)
520 rme9652_stop(rme9652);
521 rme9652->control_register &= ~(RME9652_freq | RME9652_DS);
522 rme9652->control_register |= rate;
523 rme9652_write(rme9652, RME9652_control_register, rme9652->control_register);
524
525 if (restart)
526 rme9652_start(rme9652);
527
528 if (rate & RME9652_DS) {
529 if (rme9652->ss_channels == RME9652_NCHANNELS) {
530 rme9652->channel_map = channel_map_9652_ds;
531 } else {
532 rme9652->channel_map = channel_map_9636_ds;
533 }
534 } else {
535 if (rme9652->ss_channels == RME9652_NCHANNELS) {
536 rme9652->channel_map = channel_map_9652_ss;
537 } else {
538 rme9652->channel_map = channel_map_9636_ss;
539 }
540 }
541
542 spin_unlock_irq(&rme9652->lock);
543 return 0;
544}
545
546static void rme9652_set_thru(struct snd_rme9652 *rme9652, int channel, int enable)
547{
548 int i;
549
550 rme9652->passthru = 0;
551
552 if (channel < 0) {
553
554
555
556 if (enable) {
557 for (i = 0; i < RME9652_NCHANNELS; i++) {
558 rme9652->thru_bits |= (1 << i);
559 rme9652_write(rme9652, RME9652_thru_base + i * 4, 1);
560 }
561 } else {
562 for (i = 0; i < RME9652_NCHANNELS; i++) {
563 rme9652->thru_bits &= ~(1 << i);
564 rme9652_write(rme9652, RME9652_thru_base + i * 4, 0);
565 }
566 }
567
568 } else {
569 int mapped_channel;
570
571 mapped_channel = rme9652->channel_map[channel];
572
573 if (enable) {
574 rme9652->thru_bits |= (1 << mapped_channel);
575 } else {
576 rme9652->thru_bits &= ~(1 << mapped_channel);
577 }
578
579 rme9652_write(rme9652,
580 RME9652_thru_base + mapped_channel * 4,
581 enable ? 1 : 0);
582 }
583}
584
585static int rme9652_set_passthru(struct snd_rme9652 *rme9652, int onoff)
586{
587 if (onoff) {
588 rme9652_set_thru(rme9652, -1, 1);
589
590
591
592
593
594 rme9652->control_register =
595 RME9652_inp_0 |
596 rme9652_encode_latency(7) |
597 RME9652_start_bit;
598
599 rme9652_reset_hw_pointer(rme9652);
600
601 rme9652_write(rme9652, RME9652_control_register,
602 rme9652->control_register);
603 rme9652->passthru = 1;
604 } else {
605 rme9652_set_thru(rme9652, -1, 0);
606 rme9652_stop(rme9652);
607 rme9652->passthru = 0;
608 }
609
610 return 0;
611}
612
613static void rme9652_spdif_set_bit (struct snd_rme9652 *rme9652, int mask, int onoff)
614{
615 if (onoff)
616 rme9652->control_register |= mask;
617 else
618 rme9652->control_register &= ~mask;
619
620 rme9652_write(rme9652, RME9652_control_register, rme9652->control_register);
621}
622
623static void rme9652_spdif_write_byte (struct snd_rme9652 *rme9652, const int val)
624{
625 long mask;
626 long i;
627
628 for (i = 0, mask = 0x80; i < 8; i++, mask >>= 1) {
629 if (val & mask)
630 rme9652_spdif_set_bit (rme9652, RME9652_SPDIF_WRITE, 1);
631 else
632 rme9652_spdif_set_bit (rme9652, RME9652_SPDIF_WRITE, 0);
633
634 rme9652_spdif_set_bit (rme9652, RME9652_SPDIF_CLOCK, 1);
635 rme9652_spdif_set_bit (rme9652, RME9652_SPDIF_CLOCK, 0);
636 }
637}
638
639static int rme9652_spdif_read_byte (struct snd_rme9652 *rme9652)
640{
641 long mask;
642 long val;
643 long i;
644
645 val = 0;
646
647 for (i = 0, mask = 0x80; i < 8; i++, mask >>= 1) {
648 rme9652_spdif_set_bit (rme9652, RME9652_SPDIF_CLOCK, 1);
649 if (rme9652_read (rme9652, RME9652_status_register) & RME9652_SPDIF_READ)
650 val |= mask;
651 rme9652_spdif_set_bit (rme9652, RME9652_SPDIF_CLOCK, 0);
652 }
653
654 return val;
655}
656
657static void rme9652_write_spdif_codec (struct snd_rme9652 *rme9652, const int address, const int data)
658{
659 rme9652_spdif_set_bit (rme9652, RME9652_SPDIF_SELECT, 1);
660 rme9652_spdif_write_byte (rme9652, 0x20);
661 rme9652_spdif_write_byte (rme9652, address);
662 rme9652_spdif_write_byte (rme9652, data);
663 rme9652_spdif_set_bit (rme9652, RME9652_SPDIF_SELECT, 0);
664}
665
666
667static int rme9652_spdif_read_codec (struct snd_rme9652 *rme9652, const int address)
668{
669 int ret;
670
671 rme9652_spdif_set_bit (rme9652, RME9652_SPDIF_SELECT, 1);
672 rme9652_spdif_write_byte (rme9652, 0x20);
673 rme9652_spdif_write_byte (rme9652, address);
674 rme9652_spdif_set_bit (rme9652, RME9652_SPDIF_SELECT, 0);
675 rme9652_spdif_set_bit (rme9652, RME9652_SPDIF_SELECT, 1);
676
677 rme9652_spdif_write_byte (rme9652, 0x21);
678 ret = rme9652_spdif_read_byte (rme9652);
679 rme9652_spdif_set_bit (rme9652, RME9652_SPDIF_SELECT, 0);
680
681 return ret;
682}
683
684static void rme9652_initialize_spdif_receiver (struct snd_rme9652 *rme9652)
685{
686
687
688 rme9652->control_register |= RME9652_SPDIF_RESET;
689
690 rme9652_write_spdif_codec (rme9652, 4, 0x40);
691 rme9652_write_spdif_codec (rme9652, 17, 0x13);
692 rme9652_write_spdif_codec (rme9652, 6, 0x02);
693}
694
695static inline int rme9652_spdif_sample_rate(struct snd_rme9652 *s)
696{
697 unsigned int rate_bits;
698
699 if (rme9652_read(s, RME9652_status_register) & RME9652_ERF) {
700 return -1;
701 }
702
703 if (s->hw_rev == 15) {
704
705 int x, y, ret;
706
707 x = rme9652_spdif_read_codec (s, 30);
708
709 if (x != 0)
710 y = 48000 * 64 / x;
711 else
712 y = 0;
713
714 if (y > 30400 && y < 33600) ret = 32000;
715 else if (y > 41900 && y < 46000) ret = 44100;
716 else if (y > 46000 && y < 50400) ret = 48000;
717 else if (y > 60800 && y < 67200) ret = 64000;
718 else if (y > 83700 && y < 92000) ret = 88200;
719 else if (y > 92000 && y < 100000) ret = 96000;
720 else ret = 0;
721 return ret;
722 }
723
724 rate_bits = rme9652_read(s, RME9652_status_register) & RME9652_F;
725
726 switch (rme9652_decode_spdif_rate(rate_bits)) {
727 case 0x7:
728 return 32000;
729
730 case 0x6:
731 return 44100;
732
733 case 0x5:
734 return 48000;
735
736 case 0x4:
737 return 88200;
738
739 case 0x3:
740 return 96000;
741
742 case 0x0:
743 return 64000;
744
745 default:
746 dev_err(s->card->dev,
747 "%s: unknown S/PDIF input rate (bits = 0x%x)\n",
748 s->card_name, rate_bits);
749 return 0;
750 }
751}
752
753
754
755
756
757static u32 snd_rme9652_convert_from_aes(struct snd_aes_iec958 *aes)
758{
759 u32 val = 0;
760 val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? RME9652_PRO : 0;
761 val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? RME9652_Dolby : 0;
762 if (val & RME9652_PRO)
763 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? RME9652_EMP : 0;
764 else
765 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? RME9652_EMP : 0;
766 return val;
767}
768
769static void snd_rme9652_convert_to_aes(struct snd_aes_iec958 *aes, u32 val)
770{
771 aes->status[0] = ((val & RME9652_PRO) ? IEC958_AES0_PROFESSIONAL : 0) |
772 ((val & RME9652_Dolby) ? IEC958_AES0_NONAUDIO : 0);
773 if (val & RME9652_PRO)
774 aes->status[0] |= (val & RME9652_EMP) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
775 else
776 aes->status[0] |= (val & RME9652_EMP) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
777}
778
779static int snd_rme9652_control_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
780{
781 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
782 uinfo->count = 1;
783 return 0;
784}
785
786static int snd_rme9652_control_spdif_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
787{
788 struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);
789
790 snd_rme9652_convert_to_aes(&ucontrol->value.iec958, rme9652->creg_spdif);
791 return 0;
792}
793
794static int snd_rme9652_control_spdif_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
795{
796 struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);
797 int change;
798 u32 val;
799
800 val = snd_rme9652_convert_from_aes(&ucontrol->value.iec958);
801 spin_lock_irq(&rme9652->lock);
802 change = val != rme9652->creg_spdif;
803 rme9652->creg_spdif = val;
804 spin_unlock_irq(&rme9652->lock);
805 return change;
806}
807
808static int snd_rme9652_control_spdif_stream_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
809{
810 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
811 uinfo->count = 1;
812 return 0;
813}
814
815static int snd_rme9652_control_spdif_stream_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
816{
817 struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);
818
819 snd_rme9652_convert_to_aes(&ucontrol->value.iec958, rme9652->creg_spdif_stream);
820 return 0;
821}
822
823static int snd_rme9652_control_spdif_stream_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
824{
825 struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);
826 int change;
827 u32 val;
828
829 val = snd_rme9652_convert_from_aes(&ucontrol->value.iec958);
830 spin_lock_irq(&rme9652->lock);
831 change = val != rme9652->creg_spdif_stream;
832 rme9652->creg_spdif_stream = val;
833 rme9652->control_register &= ~(RME9652_PRO | RME9652_Dolby | RME9652_EMP);
834 rme9652_write(rme9652, RME9652_control_register, rme9652->control_register |= val);
835 spin_unlock_irq(&rme9652->lock);
836 return change;
837}
838
839static int snd_rme9652_control_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
840{
841 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
842 uinfo->count = 1;
843 return 0;
844}
845
846static int snd_rme9652_control_spdif_mask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
847{
848 ucontrol->value.iec958.status[0] = kcontrol->private_value;
849 return 0;
850}
851
852#define RME9652_ADAT1_IN(xname, xindex) \
853{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
854 .info = snd_rme9652_info_adat1_in, \
855 .get = snd_rme9652_get_adat1_in, \
856 .put = snd_rme9652_put_adat1_in }
857
858static unsigned int rme9652_adat1_in(struct snd_rme9652 *rme9652)
859{
860 if (rme9652->control_register & RME9652_ADAT1_INTERNAL)
861 return 1;
862 return 0;
863}
864
865static int rme9652_set_adat1_input(struct snd_rme9652 *rme9652, int internal)
866{
867 int restart = 0;
868
869 if (internal) {
870 rme9652->control_register |= RME9652_ADAT1_INTERNAL;
871 } else {
872 rme9652->control_register &= ~RME9652_ADAT1_INTERNAL;
873 }
874
875
876
877 restart = rme9652->running;
878 if (restart)
879 rme9652_stop(rme9652);
880
881 rme9652_write(rme9652, RME9652_control_register, rme9652->control_register);
882
883 if (restart)
884 rme9652_start(rme9652);
885
886 return 0;
887}
888
889static int snd_rme9652_info_adat1_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
890{
891 static const char * const texts[2] = {"ADAT1", "Internal"};
892
893 return snd_ctl_enum_info(uinfo, 1, 2, texts);
894}
895
896static int snd_rme9652_get_adat1_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
897{
898 struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);
899
900 spin_lock_irq(&rme9652->lock);
901 ucontrol->value.enumerated.item[0] = rme9652_adat1_in(rme9652);
902 spin_unlock_irq(&rme9652->lock);
903 return 0;
904}
905
906static int snd_rme9652_put_adat1_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
907{
908 struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);
909 int change;
910 unsigned int val;
911
912 if (!snd_rme9652_use_is_exclusive(rme9652))
913 return -EBUSY;
914 val = ucontrol->value.enumerated.item[0] % 2;
915 spin_lock_irq(&rme9652->lock);
916 change = val != rme9652_adat1_in(rme9652);
917 if (change)
918 rme9652_set_adat1_input(rme9652, val);
919 spin_unlock_irq(&rme9652->lock);
920 return change;
921}
922
923#define RME9652_SPDIF_IN(xname, xindex) \
924{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
925 .info = snd_rme9652_info_spdif_in, \
926 .get = snd_rme9652_get_spdif_in, .put = snd_rme9652_put_spdif_in }
927
928static unsigned int rme9652_spdif_in(struct snd_rme9652 *rme9652)
929{
930 return rme9652_decode_spdif_in(rme9652->control_register &
931 RME9652_inp);
932}
933
934static int rme9652_set_spdif_input(struct snd_rme9652 *rme9652, int in)
935{
936 int restart = 0;
937
938 rme9652->control_register &= ~RME9652_inp;
939 rme9652->control_register |= rme9652_encode_spdif_in(in);
940
941 restart = rme9652->running;
942 if (restart)
943 rme9652_stop(rme9652);
944
945 rme9652_write(rme9652, RME9652_control_register, rme9652->control_register);
946
947 if (restart)
948 rme9652_start(rme9652);
949
950 return 0;
951}
952
953static int snd_rme9652_info_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
954{
955 static const char * const texts[3] = {"ADAT1", "Coaxial", "Internal"};
956
957 return snd_ctl_enum_info(uinfo, 1, 3, texts);
958}
959
960static int snd_rme9652_get_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
961{
962 struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);
963
964 spin_lock_irq(&rme9652->lock);
965 ucontrol->value.enumerated.item[0] = rme9652_spdif_in(rme9652);
966 spin_unlock_irq(&rme9652->lock);
967 return 0;
968}
969
970static int snd_rme9652_put_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
971{
972 struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);
973 int change;
974 unsigned int val;
975
976 if (!snd_rme9652_use_is_exclusive(rme9652))
977 return -EBUSY;
978 val = ucontrol->value.enumerated.item[0] % 3;
979 spin_lock_irq(&rme9652->lock);
980 change = val != rme9652_spdif_in(rme9652);
981 if (change)
982 rme9652_set_spdif_input(rme9652, val);
983 spin_unlock_irq(&rme9652->lock);
984 return change;
985}
986
987#define RME9652_SPDIF_OUT(xname, xindex) \
988{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
989 .info = snd_rme9652_info_spdif_out, \
990 .get = snd_rme9652_get_spdif_out, .put = snd_rme9652_put_spdif_out }
991
992static int rme9652_spdif_out(struct snd_rme9652 *rme9652)
993{
994 return (rme9652->control_register & RME9652_opt_out) ? 1 : 0;
995}
996
997static int rme9652_set_spdif_output(struct snd_rme9652 *rme9652, int out)
998{
999 int restart = 0;
1000
1001 if (out) {
1002 rme9652->control_register |= RME9652_opt_out;
1003 } else {
1004 rme9652->control_register &= ~RME9652_opt_out;
1005 }
1006
1007 restart = rme9652->running;
1008 if (restart)
1009 rme9652_stop(rme9652);
1010
1011 rme9652_write(rme9652, RME9652_control_register, rme9652->control_register);
1012
1013 if (restart)
1014 rme9652_start(rme9652);
1015
1016 return 0;
1017}
1018
1019#define snd_rme9652_info_spdif_out snd_ctl_boolean_mono_info
1020
1021static int snd_rme9652_get_spdif_out(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1022{
1023 struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);
1024
1025 spin_lock_irq(&rme9652->lock);
1026 ucontrol->value.integer.value[0] = rme9652_spdif_out(rme9652);
1027 spin_unlock_irq(&rme9652->lock);
1028 return 0;
1029}
1030
1031static int snd_rme9652_put_spdif_out(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1032{
1033 struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);
1034 int change;
1035 unsigned int val;
1036
1037 if (!snd_rme9652_use_is_exclusive(rme9652))
1038 return -EBUSY;
1039 val = ucontrol->value.integer.value[0] & 1;
1040 spin_lock_irq(&rme9652->lock);
1041 change = (int)val != rme9652_spdif_out(rme9652);
1042 rme9652_set_spdif_output(rme9652, val);
1043 spin_unlock_irq(&rme9652->lock);
1044 return change;
1045}
1046
1047#define RME9652_SYNC_MODE(xname, xindex) \
1048{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
1049 .info = snd_rme9652_info_sync_mode, \
1050 .get = snd_rme9652_get_sync_mode, .put = snd_rme9652_put_sync_mode }
1051
1052static int rme9652_sync_mode(struct snd_rme9652 *rme9652)
1053{
1054 if (rme9652->control_register & RME9652_wsel) {
1055 return 2;
1056 } else if (rme9652->control_register & RME9652_Master) {
1057 return 1;
1058 } else {
1059 return 0;
1060 }
1061}
1062
1063static int rme9652_set_sync_mode(struct snd_rme9652 *rme9652, int mode)
1064{
1065 int restart = 0;
1066
1067 switch (mode) {
1068 case 0:
1069 rme9652->control_register &=
1070 ~(RME9652_Master | RME9652_wsel);
1071 break;
1072 case 1:
1073 rme9652->control_register =
1074 (rme9652->control_register & ~RME9652_wsel) | RME9652_Master;
1075 break;
1076 case 2:
1077 rme9652->control_register |=
1078 (RME9652_Master | RME9652_wsel);
1079 break;
1080 }
1081
1082 restart = rme9652->running;
1083 if (restart)
1084 rme9652_stop(rme9652);
1085
1086 rme9652_write(rme9652, RME9652_control_register, rme9652->control_register);
1087
1088 if (restart)
1089 rme9652_start(rme9652);
1090
1091 return 0;
1092}
1093
1094static int snd_rme9652_info_sync_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1095{
1096 static const char * const texts[3] = {
1097 "AutoSync", "Master", "Word Clock"
1098 };
1099
1100 return snd_ctl_enum_info(uinfo, 1, 3, texts);
1101}
1102
1103static int snd_rme9652_get_sync_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1104{
1105 struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);
1106
1107 spin_lock_irq(&rme9652->lock);
1108 ucontrol->value.enumerated.item[0] = rme9652_sync_mode(rme9652);
1109 spin_unlock_irq(&rme9652->lock);
1110 return 0;
1111}
1112
1113static int snd_rme9652_put_sync_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1114{
1115 struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);
1116 int change;
1117 unsigned int val;
1118
1119 val = ucontrol->value.enumerated.item[0] % 3;
1120 spin_lock_irq(&rme9652->lock);
1121 change = (int)val != rme9652_sync_mode(rme9652);
1122 rme9652_set_sync_mode(rme9652, val);
1123 spin_unlock_irq(&rme9652->lock);
1124 return change;
1125}
1126
1127#define RME9652_SYNC_PREF(xname, xindex) \
1128{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
1129 .info = snd_rme9652_info_sync_pref, \
1130 .get = snd_rme9652_get_sync_pref, .put = snd_rme9652_put_sync_pref }
1131
1132static int rme9652_sync_pref(struct snd_rme9652 *rme9652)
1133{
1134 switch (rme9652->control_register & RME9652_SyncPref_Mask) {
1135 case RME9652_SyncPref_ADAT1:
1136 return RME9652_SYNC_FROM_ADAT1;
1137 case RME9652_SyncPref_ADAT2:
1138 return RME9652_SYNC_FROM_ADAT2;
1139 case RME9652_SyncPref_ADAT3:
1140 return RME9652_SYNC_FROM_ADAT3;
1141 case RME9652_SyncPref_SPDIF:
1142 return RME9652_SYNC_FROM_SPDIF;
1143 }
1144
1145 return 0;
1146}
1147
1148static int rme9652_set_sync_pref(struct snd_rme9652 *rme9652, int pref)
1149{
1150 int restart;
1151
1152 rme9652->control_register &= ~RME9652_SyncPref_Mask;
1153 switch (pref) {
1154 case RME9652_SYNC_FROM_ADAT1:
1155 rme9652->control_register |= RME9652_SyncPref_ADAT1;
1156 break;
1157 case RME9652_SYNC_FROM_ADAT2:
1158 rme9652->control_register |= RME9652_SyncPref_ADAT2;
1159 break;
1160 case RME9652_SYNC_FROM_ADAT3:
1161 rme9652->control_register |= RME9652_SyncPref_ADAT3;
1162 break;
1163 case RME9652_SYNC_FROM_SPDIF:
1164 rme9652->control_register |= RME9652_SyncPref_SPDIF;
1165 break;
1166 }
1167
1168 restart = rme9652->running;
1169 if (restart)
1170 rme9652_stop(rme9652);
1171
1172 rme9652_write(rme9652, RME9652_control_register, rme9652->control_register);
1173
1174 if (restart)
1175 rme9652_start(rme9652);
1176
1177 return 0;
1178}
1179
1180static int snd_rme9652_info_sync_pref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1181{
1182 static const char * const texts[4] = {
1183 "IEC958 In", "ADAT1 In", "ADAT2 In", "ADAT3 In"
1184 };
1185 struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);
1186
1187 return snd_ctl_enum_info(uinfo, 1,
1188 rme9652->ss_channels == RME9652_NCHANNELS ? 4 : 3,
1189 texts);
1190}
1191
1192static int snd_rme9652_get_sync_pref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1193{
1194 struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);
1195
1196 spin_lock_irq(&rme9652->lock);
1197 ucontrol->value.enumerated.item[0] = rme9652_sync_pref(rme9652);
1198 spin_unlock_irq(&rme9652->lock);
1199 return 0;
1200}
1201
1202static int snd_rme9652_put_sync_pref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1203{
1204 struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);
1205 int change, max;
1206 unsigned int val;
1207
1208 if (!snd_rme9652_use_is_exclusive(rme9652))
1209 return -EBUSY;
1210 max = rme9652->ss_channels == RME9652_NCHANNELS ? 4 : 3;
1211 val = ucontrol->value.enumerated.item[0] % max;
1212 spin_lock_irq(&rme9652->lock);
1213 change = (int)val != rme9652_sync_pref(rme9652);
1214 rme9652_set_sync_pref(rme9652, val);
1215 spin_unlock_irq(&rme9652->lock);
1216 return change;
1217}
1218
1219static int snd_rme9652_info_thru(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1220{
1221 struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);
1222 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1223 uinfo->count = rme9652->ss_channels;
1224 uinfo->value.integer.min = 0;
1225 uinfo->value.integer.max = 1;
1226 return 0;
1227}
1228
1229static int snd_rme9652_get_thru(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1230{
1231 struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);
1232 unsigned int k;
1233 u32 thru_bits = rme9652->thru_bits;
1234
1235 for (k = 0; k < rme9652->ss_channels; ++k) {
1236 ucontrol->value.integer.value[k] = !!(thru_bits & (1 << k));
1237 }
1238 return 0;
1239}
1240
1241static int snd_rme9652_put_thru(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1242{
1243 struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);
1244 int change;
1245 unsigned int chn;
1246 u32 thru_bits = 0;
1247
1248 if (!snd_rme9652_use_is_exclusive(rme9652))
1249 return -EBUSY;
1250
1251 for (chn = 0; chn < rme9652->ss_channels; ++chn) {
1252 if (ucontrol->value.integer.value[chn])
1253 thru_bits |= 1 << chn;
1254 }
1255
1256 spin_lock_irq(&rme9652->lock);
1257 change = thru_bits ^ rme9652->thru_bits;
1258 if (change) {
1259 for (chn = 0; chn < rme9652->ss_channels; ++chn) {
1260 if (!(change & (1 << chn)))
1261 continue;
1262 rme9652_set_thru(rme9652,chn,thru_bits&(1<<chn));
1263 }
1264 }
1265 spin_unlock_irq(&rme9652->lock);
1266 return !!change;
1267}
1268
1269#define RME9652_PASSTHRU(xname, xindex) \
1270{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
1271 .info = snd_rme9652_info_passthru, \
1272 .put = snd_rme9652_put_passthru, \
1273 .get = snd_rme9652_get_passthru }
1274
1275#define snd_rme9652_info_passthru snd_ctl_boolean_mono_info
1276
1277static int snd_rme9652_get_passthru(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1278{
1279 struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);
1280
1281 spin_lock_irq(&rme9652->lock);
1282 ucontrol->value.integer.value[0] = rme9652->passthru;
1283 spin_unlock_irq(&rme9652->lock);
1284 return 0;
1285}
1286
1287static int snd_rme9652_put_passthru(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1288{
1289 struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);
1290 int change;
1291 unsigned int val;
1292 int err = 0;
1293
1294 if (!snd_rme9652_use_is_exclusive(rme9652))
1295 return -EBUSY;
1296
1297 val = ucontrol->value.integer.value[0] & 1;
1298 spin_lock_irq(&rme9652->lock);
1299 change = (ucontrol->value.integer.value[0] != rme9652->passthru);
1300 if (change)
1301 err = rme9652_set_passthru(rme9652, val);
1302 spin_unlock_irq(&rme9652->lock);
1303 return err ? err : change;
1304}
1305
1306
1307
1308#define RME9652_SPDIF_RATE(xname, xindex) \
1309{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
1310 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
1311 .info = snd_rme9652_info_spdif_rate, \
1312 .get = snd_rme9652_get_spdif_rate }
1313
1314static int snd_rme9652_info_spdif_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1315{
1316 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1317 uinfo->count = 1;
1318 uinfo->value.integer.min = 0;
1319 uinfo->value.integer.max = 96000;
1320 return 0;
1321}
1322
1323static int snd_rme9652_get_spdif_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1324{
1325 struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);
1326
1327 spin_lock_irq(&rme9652->lock);
1328 ucontrol->value.integer.value[0] = rme9652_spdif_sample_rate(rme9652);
1329 spin_unlock_irq(&rme9652->lock);
1330 return 0;
1331}
1332
1333#define RME9652_ADAT_SYNC(xname, xindex, xidx) \
1334{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
1335 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
1336 .info = snd_rme9652_info_adat_sync, \
1337 .get = snd_rme9652_get_adat_sync, .private_value = xidx }
1338
1339static int snd_rme9652_info_adat_sync(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1340{
1341 static const char * const texts[4] = {
1342 "No Lock", "Lock", "No Lock Sync", "Lock Sync"
1343 };
1344
1345 return snd_ctl_enum_info(uinfo, 1, 4, texts);
1346}
1347
1348static int snd_rme9652_get_adat_sync(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1349{
1350 struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);
1351 unsigned int mask1, mask2, val;
1352
1353 switch (kcontrol->private_value) {
1354 case 0: mask1 = RME9652_lock_0; mask2 = RME9652_sync_0; break;
1355 case 1: mask1 = RME9652_lock_1; mask2 = RME9652_sync_1; break;
1356 case 2: mask1 = RME9652_lock_2; mask2 = RME9652_sync_2; break;
1357 default: return -EINVAL;
1358 }
1359 val = rme9652_read(rme9652, RME9652_status_register);
1360 ucontrol->value.enumerated.item[0] = (val & mask1) ? 1 : 0;
1361 ucontrol->value.enumerated.item[0] |= (val & mask2) ? 2 : 0;
1362 return 0;
1363}
1364
1365#define RME9652_TC_VALID(xname, xindex) \
1366{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
1367 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
1368 .info = snd_rme9652_info_tc_valid, \
1369 .get = snd_rme9652_get_tc_valid }
1370
1371#define snd_rme9652_info_tc_valid snd_ctl_boolean_mono_info
1372
1373static int snd_rme9652_get_tc_valid(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1374{
1375 struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);
1376
1377 ucontrol->value.integer.value[0] =
1378 (rme9652_read(rme9652, RME9652_status_register) & RME9652_tc_valid) ? 1 : 0;
1379 return 0;
1380}
1381
1382#ifdef ALSA_HAS_STANDARD_WAY_OF_RETURNING_TIMECODE
1383
1384
1385
1386static int snd_rme9652_get_tc_value(void *private_data,
1387 snd_kswitch_t *kswitch,
1388 snd_switch_t *uswitch)
1389{
1390 struct snd_rme9652 *s = (struct snd_rme9652 *) private_data;
1391 u32 value;
1392 int i;
1393
1394 uswitch->type = SNDRV_SW_TYPE_DWORD;
1395
1396 if ((rme9652_read(s, RME9652_status_register) &
1397 RME9652_tc_valid) == 0) {
1398 uswitch->value.data32[0] = 0;
1399 return 0;
1400 }
1401
1402
1403
1404 rme9652_write(s, RME9652_time_code, 0);
1405
1406
1407
1408 for (i = 0; i < 50; i++) {
1409 if (!(rme9652_read(s, i * 4) & RME9652_tc_busy))
1410 break;
1411 }
1412
1413 if (!(rme9652_read(s, i * 4) & RME9652_tc_busy)) {
1414 return -EIO;
1415 }
1416
1417 value = 0;
1418
1419 for (i = 0; i < 32; i++) {
1420 value >>= 1;
1421
1422 if (rme9652_read(s, i * 4) & RME9652_tc_out)
1423 value |= 0x80000000;
1424 }
1425
1426 if (value > 2 * 60 * 48000) {
1427 value -= 2 * 60 * 48000;
1428 } else {
1429 value = 0;
1430 }
1431
1432 uswitch->value.data32[0] = value;
1433
1434 return 0;
1435}
1436
1437#endif
1438
1439static const struct snd_kcontrol_new snd_rme9652_controls[] = {
1440{
1441 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1442 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
1443 .info = snd_rme9652_control_spdif_info,
1444 .get = snd_rme9652_control_spdif_get,
1445 .put = snd_rme9652_control_spdif_put,
1446},
1447{
1448 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
1449 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1450 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
1451 .info = snd_rme9652_control_spdif_stream_info,
1452 .get = snd_rme9652_control_spdif_stream_get,
1453 .put = snd_rme9652_control_spdif_stream_put,
1454},
1455{
1456 .access = SNDRV_CTL_ELEM_ACCESS_READ,
1457 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1458 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
1459 .info = snd_rme9652_control_spdif_mask_info,
1460 .get = snd_rme9652_control_spdif_mask_get,
1461 .private_value = IEC958_AES0_NONAUDIO |
1462 IEC958_AES0_PROFESSIONAL |
1463 IEC958_AES0_CON_EMPHASIS,
1464},
1465{
1466 .access = SNDRV_CTL_ELEM_ACCESS_READ,
1467 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1468 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK),
1469 .info = snd_rme9652_control_spdif_mask_info,
1470 .get = snd_rme9652_control_spdif_mask_get,
1471 .private_value = IEC958_AES0_NONAUDIO |
1472 IEC958_AES0_PROFESSIONAL |
1473 IEC958_AES0_PRO_EMPHASIS,
1474},
1475RME9652_SPDIF_IN("IEC958 Input Connector", 0),
1476RME9652_SPDIF_OUT("IEC958 Output also on ADAT1", 0),
1477RME9652_SYNC_MODE("Sync Mode", 0),
1478RME9652_SYNC_PREF("Preferred Sync Source", 0),
1479{
1480 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1481 .name = "Channels Thru",
1482 .index = 0,
1483 .info = snd_rme9652_info_thru,
1484 .get = snd_rme9652_get_thru,
1485 .put = snd_rme9652_put_thru,
1486},
1487RME9652_SPDIF_RATE("IEC958 Sample Rate", 0),
1488RME9652_ADAT_SYNC("ADAT1 Sync Check", 0, 0),
1489RME9652_ADAT_SYNC("ADAT2 Sync Check", 0, 1),
1490RME9652_TC_VALID("Timecode Valid", 0),
1491RME9652_PASSTHRU("Passthru", 0)
1492};
1493
1494static const struct snd_kcontrol_new snd_rme9652_adat3_check =
1495RME9652_ADAT_SYNC("ADAT3 Sync Check", 0, 2);
1496
1497static const struct snd_kcontrol_new snd_rme9652_adat1_input =
1498RME9652_ADAT1_IN("ADAT1 Input Source", 0);
1499
1500static int snd_rme9652_create_controls(struct snd_card *card, struct snd_rme9652 *rme9652)
1501{
1502 unsigned int idx;
1503 int err;
1504 struct snd_kcontrol *kctl;
1505
1506 for (idx = 0; idx < ARRAY_SIZE(snd_rme9652_controls); idx++) {
1507 kctl = snd_ctl_new1(&snd_rme9652_controls[idx], rme9652);
1508 err = snd_ctl_add(card, kctl);
1509 if (err < 0)
1510 return err;
1511 if (idx == 1)
1512 rme9652->spdif_ctl = kctl;
1513 }
1514
1515 if (rme9652->ss_channels == RME9652_NCHANNELS) {
1516 kctl = snd_ctl_new1(&snd_rme9652_adat3_check, rme9652);
1517 err = snd_ctl_add(card, kctl);
1518 if (err < 0)
1519 return err;
1520 }
1521
1522 if (rme9652->hw_rev >= 15) {
1523 kctl = snd_ctl_new1(&snd_rme9652_adat1_input, rme9652);
1524 err = snd_ctl_add(card, kctl);
1525 if (err < 0)
1526 return err;
1527 }
1528
1529 return 0;
1530}
1531
1532
1533
1534
1535
1536static void
1537snd_rme9652_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
1538{
1539 struct snd_rme9652 *rme9652 = (struct snd_rme9652 *) entry->private_data;
1540 u32 thru_bits = rme9652->thru_bits;
1541 int show_auto_sync_source = 0;
1542 int i;
1543 unsigned int status;
1544 int x;
1545
1546 status = rme9652_read(rme9652, RME9652_status_register);
1547
1548 snd_iprintf(buffer, "%s (Card #%d)\n", rme9652->card_name, rme9652->card->number + 1);
1549 snd_iprintf(buffer, "Buffers: capture %p playback %p\n",
1550 rme9652->capture_buffer, rme9652->playback_buffer);
1551 snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
1552 rme9652->irq, rme9652->port, (unsigned long)rme9652->iobase);
1553 snd_iprintf(buffer, "Control register: %x\n", rme9652->control_register);
1554
1555 snd_iprintf(buffer, "\n");
1556
1557 x = 1 << (6 + rme9652_decode_latency(rme9652->control_register &
1558 RME9652_latency));
1559
1560 snd_iprintf(buffer, "Latency: %d samples (2 periods of %lu bytes)\n",
1561 x, (unsigned long) rme9652->period_bytes);
1562 snd_iprintf(buffer, "Hardware pointer (frames): %ld\n",
1563 rme9652_hw_pointer(rme9652));
1564 snd_iprintf(buffer, "Passthru: %s\n",
1565 rme9652->passthru ? "yes" : "no");
1566
1567 if ((rme9652->control_register & (RME9652_Master | RME9652_wsel)) == 0) {
1568 snd_iprintf(buffer, "Clock mode: autosync\n");
1569 show_auto_sync_source = 1;
1570 } else if (rme9652->control_register & RME9652_wsel) {
1571 if (status & RME9652_wsel_rd) {
1572 snd_iprintf(buffer, "Clock mode: word clock\n");
1573 } else {
1574 snd_iprintf(buffer, "Clock mode: word clock (no signal)\n");
1575 }
1576 } else {
1577 snd_iprintf(buffer, "Clock mode: master\n");
1578 }
1579
1580 if (show_auto_sync_source) {
1581 switch (rme9652->control_register & RME9652_SyncPref_Mask) {
1582 case RME9652_SyncPref_ADAT1:
1583 snd_iprintf(buffer, "Pref. sync source: ADAT1\n");
1584 break;
1585 case RME9652_SyncPref_ADAT2:
1586 snd_iprintf(buffer, "Pref. sync source: ADAT2\n");
1587 break;
1588 case RME9652_SyncPref_ADAT3:
1589 snd_iprintf(buffer, "Pref. sync source: ADAT3\n");
1590 break;
1591 case RME9652_SyncPref_SPDIF:
1592 snd_iprintf(buffer, "Pref. sync source: IEC958\n");
1593 break;
1594 default:
1595 snd_iprintf(buffer, "Pref. sync source: ???\n");
1596 }
1597 }
1598
1599 if (rme9652->hw_rev >= 15)
1600 snd_iprintf(buffer, "\nADAT1 Input source: %s\n",
1601 (rme9652->control_register & RME9652_ADAT1_INTERNAL) ?
1602 "Internal" : "ADAT1 optical");
1603
1604 snd_iprintf(buffer, "\n");
1605
1606 switch (rme9652_decode_spdif_in(rme9652->control_register &
1607 RME9652_inp)) {
1608 case RME9652_SPDIFIN_OPTICAL:
1609 snd_iprintf(buffer, "IEC958 input: ADAT1\n");
1610 break;
1611 case RME9652_SPDIFIN_COAXIAL:
1612 snd_iprintf(buffer, "IEC958 input: Coaxial\n");
1613 break;
1614 case RME9652_SPDIFIN_INTERN:
1615 snd_iprintf(buffer, "IEC958 input: Internal\n");
1616 break;
1617 default:
1618 snd_iprintf(buffer, "IEC958 input: ???\n");
1619 break;
1620 }
1621
1622 if (rme9652->control_register & RME9652_opt_out) {
1623 snd_iprintf(buffer, "IEC958 output: Coaxial & ADAT1\n");
1624 } else {
1625 snd_iprintf(buffer, "IEC958 output: Coaxial only\n");
1626 }
1627
1628 if (rme9652->control_register & RME9652_PRO) {
1629 snd_iprintf(buffer, "IEC958 quality: Professional\n");
1630 } else {
1631 snd_iprintf(buffer, "IEC958 quality: Consumer\n");
1632 }
1633
1634 if (rme9652->control_register & RME9652_EMP) {
1635 snd_iprintf(buffer, "IEC958 emphasis: on\n");
1636 } else {
1637 snd_iprintf(buffer, "IEC958 emphasis: off\n");
1638 }
1639
1640 if (rme9652->control_register & RME9652_Dolby) {
1641 snd_iprintf(buffer, "IEC958 Dolby: on\n");
1642 } else {
1643 snd_iprintf(buffer, "IEC958 Dolby: off\n");
1644 }
1645
1646 i = rme9652_spdif_sample_rate(rme9652);
1647
1648 if (i < 0) {
1649 snd_iprintf(buffer,
1650 "IEC958 sample rate: error flag set\n");
1651 } else if (i == 0) {
1652 snd_iprintf(buffer, "IEC958 sample rate: undetermined\n");
1653 } else {
1654 snd_iprintf(buffer, "IEC958 sample rate: %d\n", i);
1655 }
1656
1657 snd_iprintf(buffer, "\n");
1658
1659 snd_iprintf(buffer, "ADAT Sample rate: %dHz\n",
1660 rme9652_adat_sample_rate(rme9652));
1661
1662
1663
1664 x = status & RME9652_sync_0;
1665 if (status & RME9652_lock_0) {
1666 snd_iprintf(buffer, "ADAT1: %s\n", x ? "Sync" : "Lock");
1667 } else {
1668 snd_iprintf(buffer, "ADAT1: No Lock\n");
1669 }
1670
1671 x = status & RME9652_sync_1;
1672 if (status & RME9652_lock_1) {
1673 snd_iprintf(buffer, "ADAT2: %s\n", x ? "Sync" : "Lock");
1674 } else {
1675 snd_iprintf(buffer, "ADAT2: No Lock\n");
1676 }
1677
1678 x = status & RME9652_sync_2;
1679 if (status & RME9652_lock_2) {
1680 snd_iprintf(buffer, "ADAT3: %s\n", x ? "Sync" : "Lock");
1681 } else {
1682 snd_iprintf(buffer, "ADAT3: No Lock\n");
1683 }
1684
1685 snd_iprintf(buffer, "\n");
1686
1687 snd_iprintf(buffer, "Timecode signal: %s\n",
1688 (status & RME9652_tc_valid) ? "yes" : "no");
1689
1690
1691
1692 snd_iprintf(buffer, "Punch Status:\n\n");
1693
1694 for (i = 0; i < rme9652->ss_channels; i++) {
1695 if (thru_bits & (1 << i)) {
1696 snd_iprintf(buffer, "%2d: on ", i + 1);
1697 } else {
1698 snd_iprintf(buffer, "%2d: off ", i + 1);
1699 }
1700
1701 if (((i + 1) % 8) == 0) {
1702 snd_iprintf(buffer, "\n");
1703 }
1704 }
1705
1706 snd_iprintf(buffer, "\n");
1707}
1708
1709static void snd_rme9652_proc_init(struct snd_rme9652 *rme9652)
1710{
1711 snd_card_ro_proc_new(rme9652->card, "rme9652", rme9652,
1712 snd_rme9652_proc_read);
1713}
1714
1715static void snd_rme9652_card_free(struct snd_card *card)
1716{
1717 struct snd_rme9652 *rme9652 = (struct snd_rme9652 *) card->private_data;
1718
1719 if (rme9652->irq >= 0)
1720 rme9652_stop(rme9652);
1721}
1722
1723static int snd_rme9652_initialize_memory(struct snd_rme9652 *rme9652)
1724{
1725 struct snd_dma_buffer *capture_dma, *playback_dma;
1726
1727 capture_dma = snd_hammerfall_get_buffer(rme9652->pci, RME9652_DMA_AREA_BYTES);
1728 playback_dma = snd_hammerfall_get_buffer(rme9652->pci, RME9652_DMA_AREA_BYTES);
1729 if (!capture_dma || !playback_dma) {
1730 dev_err(rme9652->card->dev,
1731 "%s: no buffers available\n", rme9652->card_name);
1732 return -ENOMEM;
1733 }
1734
1735
1736 rme9652->capture_dma_buf = *capture_dma;
1737 rme9652->playback_dma_buf = *playback_dma;
1738
1739
1740 rme9652->capture_dma_buf.addr = ALIGN(capture_dma->addr, 0x10000ul);
1741 rme9652->playback_dma_buf.addr = ALIGN(playback_dma->addr, 0x10000ul);
1742
1743
1744 rme9652_write(rme9652, RME9652_rec_buffer, rme9652->capture_dma_buf.addr);
1745 rme9652_write(rme9652, RME9652_play_buffer, rme9652->playback_dma_buf.addr);
1746
1747 rme9652->capture_dma_buf.area += rme9652->capture_dma_buf.addr - capture_dma->addr;
1748 rme9652->playback_dma_buf.area += rme9652->playback_dma_buf.addr - playback_dma->addr;
1749 rme9652->capture_buffer = rme9652->capture_dma_buf.area;
1750 rme9652->playback_buffer = rme9652->playback_dma_buf.area;
1751
1752 return 0;
1753}
1754
1755static void snd_rme9652_set_defaults(struct snd_rme9652 *rme9652)
1756{
1757 unsigned int k;
1758
1759
1760
1761
1762
1763
1764
1765
1766
1767
1768
1769
1770
1771
1772
1773
1774
1775 rme9652->control_register =
1776 RME9652_inp_0 | rme9652_encode_latency(7);
1777
1778 rme9652_write(rme9652, RME9652_control_register, rme9652->control_register);
1779
1780 rme9652_reset_hw_pointer(rme9652);
1781 rme9652_compute_period_size(rme9652);
1782
1783
1784
1785 for (k = 0; k < RME9652_NCHANNELS; ++k)
1786 rme9652_write(rme9652, RME9652_thru_base + k * 4, 0);
1787
1788 rme9652->thru_bits = 0;
1789 rme9652->passthru = 0;
1790
1791
1792
1793 rme9652_set_rate(rme9652, 48000);
1794}
1795
1796static irqreturn_t snd_rme9652_interrupt(int irq, void *dev_id)
1797{
1798 struct snd_rme9652 *rme9652 = (struct snd_rme9652 *) dev_id;
1799
1800 if (!(rme9652_read(rme9652, RME9652_status_register) & RME9652_IRQ)) {
1801 return IRQ_NONE;
1802 }
1803
1804 rme9652_write(rme9652, RME9652_irq_clear, 0);
1805
1806 if (rme9652->capture_substream) {
1807 snd_pcm_period_elapsed(rme9652->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream);
1808 }
1809
1810 if (rme9652->playback_substream) {
1811 snd_pcm_period_elapsed(rme9652->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream);
1812 }
1813 return IRQ_HANDLED;
1814}
1815
1816static snd_pcm_uframes_t snd_rme9652_hw_pointer(struct snd_pcm_substream *substream)
1817{
1818 struct snd_rme9652 *rme9652 = snd_pcm_substream_chip(substream);
1819 return rme9652_hw_pointer(rme9652);
1820}
1821
1822static char *rme9652_channel_buffer_location(struct snd_rme9652 *rme9652,
1823 int stream,
1824 int channel)
1825
1826{
1827 int mapped_channel;
1828
1829 if (snd_BUG_ON(channel < 0 || channel >= RME9652_NCHANNELS))
1830 return NULL;
1831
1832 mapped_channel = rme9652->channel_map[channel];
1833 if (mapped_channel < 0)
1834 return NULL;
1835
1836 if (stream == SNDRV_PCM_STREAM_CAPTURE) {
1837 return rme9652->capture_buffer +
1838 (mapped_channel * RME9652_CHANNEL_BUFFER_BYTES);
1839 } else {
1840 return rme9652->playback_buffer +
1841 (mapped_channel * RME9652_CHANNEL_BUFFER_BYTES);
1842 }
1843}
1844
1845static int snd_rme9652_playback_copy(struct snd_pcm_substream *substream,
1846 int channel, unsigned long pos,
1847 void __user *src, unsigned long count)
1848{
1849 struct snd_rme9652 *rme9652 = snd_pcm_substream_chip(substream);
1850 char *channel_buf;
1851
1852 if (snd_BUG_ON(pos + count > RME9652_CHANNEL_BUFFER_BYTES))
1853 return -EINVAL;
1854
1855 channel_buf = rme9652_channel_buffer_location (rme9652,
1856 substream->pstr->stream,
1857 channel);
1858 if (snd_BUG_ON(!channel_buf))
1859 return -EIO;
1860 if (copy_from_user(channel_buf + pos, src, count))
1861 return -EFAULT;
1862 return 0;
1863}
1864
1865static int snd_rme9652_playback_copy_kernel(struct snd_pcm_substream *substream,
1866 int channel, unsigned long pos,
1867 void *src, unsigned long count)
1868{
1869 struct snd_rme9652 *rme9652 = snd_pcm_substream_chip(substream);
1870 char *channel_buf;
1871
1872 channel_buf = rme9652_channel_buffer_location(rme9652,
1873 substream->pstr->stream,
1874 channel);
1875 if (snd_BUG_ON(!channel_buf))
1876 return -EIO;
1877 memcpy(channel_buf + pos, src, count);
1878 return 0;
1879}
1880
1881static int snd_rme9652_capture_copy(struct snd_pcm_substream *substream,
1882 int channel, unsigned long pos,
1883 void __user *dst, unsigned long count)
1884{
1885 struct snd_rme9652 *rme9652 = snd_pcm_substream_chip(substream);
1886 char *channel_buf;
1887
1888 if (snd_BUG_ON(pos + count > RME9652_CHANNEL_BUFFER_BYTES))
1889 return -EINVAL;
1890
1891 channel_buf = rme9652_channel_buffer_location (rme9652,
1892 substream->pstr->stream,
1893 channel);
1894 if (snd_BUG_ON(!channel_buf))
1895 return -EIO;
1896 if (copy_to_user(dst, channel_buf + pos, count))
1897 return -EFAULT;
1898 return 0;
1899}
1900
1901static int snd_rme9652_capture_copy_kernel(struct snd_pcm_substream *substream,
1902 int channel, unsigned long pos,
1903 void *dst, unsigned long count)
1904{
1905 struct snd_rme9652 *rme9652 = snd_pcm_substream_chip(substream);
1906 char *channel_buf;
1907
1908 channel_buf = rme9652_channel_buffer_location(rme9652,
1909 substream->pstr->stream,
1910 channel);
1911 if (snd_BUG_ON(!channel_buf))
1912 return -EIO;
1913 memcpy(dst, channel_buf + pos, count);
1914 return 0;
1915}
1916
1917static int snd_rme9652_hw_silence(struct snd_pcm_substream *substream,
1918 int channel, unsigned long pos,
1919 unsigned long count)
1920{
1921 struct snd_rme9652 *rme9652 = snd_pcm_substream_chip(substream);
1922 char *channel_buf;
1923
1924 channel_buf = rme9652_channel_buffer_location (rme9652,
1925 substream->pstr->stream,
1926 channel);
1927 if (snd_BUG_ON(!channel_buf))
1928 return -EIO;
1929 memset(channel_buf + pos, 0, count);
1930 return 0;
1931}
1932
1933static int snd_rme9652_reset(struct snd_pcm_substream *substream)
1934{
1935 struct snd_pcm_runtime *runtime = substream->runtime;
1936 struct snd_rme9652 *rme9652 = snd_pcm_substream_chip(substream);
1937 struct snd_pcm_substream *other;
1938 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1939 other = rme9652->capture_substream;
1940 else
1941 other = rme9652->playback_substream;
1942 if (rme9652->running)
1943 runtime->status->hw_ptr = rme9652_hw_pointer(rme9652);
1944 else
1945 runtime->status->hw_ptr = 0;
1946 if (other) {
1947 struct snd_pcm_substream *s;
1948 struct snd_pcm_runtime *oruntime = other->runtime;
1949 snd_pcm_group_for_each_entry(s, substream) {
1950 if (s == other) {
1951 oruntime->status->hw_ptr = runtime->status->hw_ptr;
1952 break;
1953 }
1954 }
1955 }
1956 return 0;
1957}
1958
1959static int snd_rme9652_hw_params(struct snd_pcm_substream *substream,
1960 struct snd_pcm_hw_params *params)
1961{
1962 struct snd_rme9652 *rme9652 = snd_pcm_substream_chip(substream);
1963 int err;
1964 pid_t this_pid;
1965 pid_t other_pid;
1966
1967 spin_lock_irq(&rme9652->lock);
1968
1969 if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1970 rme9652->control_register &= ~(RME9652_PRO | RME9652_Dolby | RME9652_EMP);
1971 rme9652_write(rme9652, RME9652_control_register, rme9652->control_register |= rme9652->creg_spdif_stream);
1972 this_pid = rme9652->playback_pid;
1973 other_pid = rme9652->capture_pid;
1974 } else {
1975 this_pid = rme9652->capture_pid;
1976 other_pid = rme9652->playback_pid;
1977 }
1978
1979 if ((other_pid > 0) && (this_pid != other_pid)) {
1980
1981
1982
1983
1984
1985
1986 if ((int)params_rate(params) !=
1987 rme9652_adat_sample_rate(rme9652)) {
1988 spin_unlock_irq(&rme9652->lock);
1989 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
1990 return -EBUSY;
1991 }
1992
1993 if (params_period_size(params) != rme9652->period_bytes / 4) {
1994 spin_unlock_irq(&rme9652->lock);
1995 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
1996 return -EBUSY;
1997 }
1998
1999
2000
2001 spin_unlock_irq(&rme9652->lock);
2002 return 0;
2003
2004 } else {
2005 spin_unlock_irq(&rme9652->lock);
2006 }
2007
2008
2009
2010
2011 err = rme9652_set_rate(rme9652, params_rate(params));
2012 if (err < 0) {
2013 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
2014 return err;
2015 }
2016
2017 err = rme9652_set_interrupt_interval(rme9652, params_period_size(params));
2018 if (err < 0) {
2019 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
2020 return err;
2021 }
2022
2023 return 0;
2024}
2025
2026static int snd_rme9652_channel_info(struct snd_pcm_substream *substream,
2027 struct snd_pcm_channel_info *info)
2028{
2029 struct snd_rme9652 *rme9652 = snd_pcm_substream_chip(substream);
2030 int chn;
2031
2032 if (snd_BUG_ON(info->channel >= RME9652_NCHANNELS))
2033 return -EINVAL;
2034
2035 chn = rme9652->channel_map[array_index_nospec(info->channel,
2036 RME9652_NCHANNELS)];
2037 if (chn < 0)
2038 return -EINVAL;
2039
2040 info->offset = chn * RME9652_CHANNEL_BUFFER_BYTES;
2041 info->first = 0;
2042 info->step = 32;
2043 return 0;
2044}
2045
2046static int snd_rme9652_ioctl(struct snd_pcm_substream *substream,
2047 unsigned int cmd, void *arg)
2048{
2049 switch (cmd) {
2050 case SNDRV_PCM_IOCTL1_RESET:
2051 {
2052 return snd_rme9652_reset(substream);
2053 }
2054 case SNDRV_PCM_IOCTL1_CHANNEL_INFO:
2055 {
2056 struct snd_pcm_channel_info *info = arg;
2057 return snd_rme9652_channel_info(substream, info);
2058 }
2059 default:
2060 break;
2061 }
2062
2063 return snd_pcm_lib_ioctl(substream, cmd, arg);
2064}
2065
2066static void rme9652_silence_playback(struct snd_rme9652 *rme9652)
2067{
2068 memset(rme9652->playback_buffer, 0, RME9652_DMA_AREA_BYTES);
2069}
2070
2071static int snd_rme9652_trigger(struct snd_pcm_substream *substream,
2072 int cmd)
2073{
2074 struct snd_rme9652 *rme9652 = snd_pcm_substream_chip(substream);
2075 struct snd_pcm_substream *other;
2076 int running;
2077 spin_lock(&rme9652->lock);
2078 running = rme9652->running;
2079 switch (cmd) {
2080 case SNDRV_PCM_TRIGGER_START:
2081 running |= 1 << substream->stream;
2082 break;
2083 case SNDRV_PCM_TRIGGER_STOP:
2084 running &= ~(1 << substream->stream);
2085 break;
2086 default:
2087 snd_BUG();
2088 spin_unlock(&rme9652->lock);
2089 return -EINVAL;
2090 }
2091 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
2092 other = rme9652->capture_substream;
2093 else
2094 other = rme9652->playback_substream;
2095
2096 if (other) {
2097 struct snd_pcm_substream *s;
2098 snd_pcm_group_for_each_entry(s, substream) {
2099 if (s == other) {
2100 snd_pcm_trigger_done(s, substream);
2101 if (cmd == SNDRV_PCM_TRIGGER_START)
2102 running |= 1 << s->stream;
2103 else
2104 running &= ~(1 << s->stream);
2105 goto _ok;
2106 }
2107 }
2108 if (cmd == SNDRV_PCM_TRIGGER_START) {
2109 if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK)) &&
2110 substream->stream == SNDRV_PCM_STREAM_CAPTURE)
2111 rme9652_silence_playback(rme9652);
2112 } else {
2113 if (running &&
2114 substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
2115 rme9652_silence_playback(rme9652);
2116 }
2117 } else {
2118 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
2119 rme9652_silence_playback(rme9652);
2120 }
2121 _ok:
2122 snd_pcm_trigger_done(substream, substream);
2123 if (!rme9652->running && running)
2124 rme9652_start(rme9652);
2125 else if (rme9652->running && !running)
2126 rme9652_stop(rme9652);
2127 rme9652->running = running;
2128 spin_unlock(&rme9652->lock);
2129
2130 return 0;
2131}
2132
2133static int snd_rme9652_prepare(struct snd_pcm_substream *substream)
2134{
2135 struct snd_rme9652 *rme9652 = snd_pcm_substream_chip(substream);
2136 unsigned long flags;
2137
2138 spin_lock_irqsave(&rme9652->lock, flags);
2139 if (!rme9652->running)
2140 rme9652_reset_hw_pointer(rme9652);
2141 spin_unlock_irqrestore(&rme9652->lock, flags);
2142 return 0;
2143}
2144
2145static const struct snd_pcm_hardware snd_rme9652_playback_subinfo =
2146{
2147 .info = (SNDRV_PCM_INFO_MMAP |
2148 SNDRV_PCM_INFO_MMAP_VALID |
2149 SNDRV_PCM_INFO_NONINTERLEAVED |
2150 SNDRV_PCM_INFO_SYNC_START |
2151 SNDRV_PCM_INFO_DOUBLE),
2152 .formats = SNDRV_PCM_FMTBIT_S32_LE,
2153 .rates = (SNDRV_PCM_RATE_44100 |
2154 SNDRV_PCM_RATE_48000 |
2155 SNDRV_PCM_RATE_88200 |
2156 SNDRV_PCM_RATE_96000),
2157 .rate_min = 44100,
2158 .rate_max = 96000,
2159 .channels_min = 10,
2160 .channels_max = 26,
2161 .buffer_bytes_max = RME9652_CHANNEL_BUFFER_BYTES * 26,
2162 .period_bytes_min = (64 * 4) * 10,
2163 .period_bytes_max = (8192 * 4) * 26,
2164 .periods_min = 2,
2165 .periods_max = 2,
2166 .fifo_size = 0,
2167};
2168
2169static const struct snd_pcm_hardware snd_rme9652_capture_subinfo =
2170{
2171 .info = (SNDRV_PCM_INFO_MMAP |
2172 SNDRV_PCM_INFO_MMAP_VALID |
2173 SNDRV_PCM_INFO_NONINTERLEAVED |
2174 SNDRV_PCM_INFO_SYNC_START),
2175 .formats = SNDRV_PCM_FMTBIT_S32_LE,
2176 .rates = (SNDRV_PCM_RATE_44100 |
2177 SNDRV_PCM_RATE_48000 |
2178 SNDRV_PCM_RATE_88200 |
2179 SNDRV_PCM_RATE_96000),
2180 .rate_min = 44100,
2181 .rate_max = 96000,
2182 .channels_min = 10,
2183 .channels_max = 26,
2184 .buffer_bytes_max = RME9652_CHANNEL_BUFFER_BYTES *26,
2185 .period_bytes_min = (64 * 4) * 10,
2186 .period_bytes_max = (8192 * 4) * 26,
2187 .periods_min = 2,
2188 .periods_max = 2,
2189 .fifo_size = 0,
2190};
2191
2192static const unsigned int period_sizes[] = { 64, 128, 256, 512, 1024, 2048, 4096, 8192 };
2193
2194static const struct snd_pcm_hw_constraint_list hw_constraints_period_sizes = {
2195 .count = ARRAY_SIZE(period_sizes),
2196 .list = period_sizes,
2197 .mask = 0
2198};
2199
2200static int snd_rme9652_hw_rule_channels(struct snd_pcm_hw_params *params,
2201 struct snd_pcm_hw_rule *rule)
2202{
2203 struct snd_rme9652 *rme9652 = rule->private;
2204 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
2205 unsigned int list[2] = { rme9652->ds_channels, rme9652->ss_channels };
2206 return snd_interval_list(c, 2, list, 0);
2207}
2208
2209static int snd_rme9652_hw_rule_channels_rate(struct snd_pcm_hw_params *params,
2210 struct snd_pcm_hw_rule *rule)
2211{
2212 struct snd_rme9652 *rme9652 = rule->private;
2213 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
2214 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
2215 if (r->min > 48000) {
2216 struct snd_interval t = {
2217 .min = rme9652->ds_channels,
2218 .max = rme9652->ds_channels,
2219 .integer = 1,
2220 };
2221 return snd_interval_refine(c, &t);
2222 } else if (r->max < 88200) {
2223 struct snd_interval t = {
2224 .min = rme9652->ss_channels,
2225 .max = rme9652->ss_channels,
2226 .integer = 1,
2227 };
2228 return snd_interval_refine(c, &t);
2229 }
2230 return 0;
2231}
2232
2233static int snd_rme9652_hw_rule_rate_channels(struct snd_pcm_hw_params *params,
2234 struct snd_pcm_hw_rule *rule)
2235{
2236 struct snd_rme9652 *rme9652 = rule->private;
2237 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
2238 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
2239 if (c->min >= rme9652->ss_channels) {
2240 struct snd_interval t = {
2241 .min = 44100,
2242 .max = 48000,
2243 .integer = 1,
2244 };
2245 return snd_interval_refine(r, &t);
2246 } else if (c->max <= rme9652->ds_channels) {
2247 struct snd_interval t = {
2248 .min = 88200,
2249 .max = 96000,
2250 .integer = 1,
2251 };
2252 return snd_interval_refine(r, &t);
2253 }
2254 return 0;
2255}
2256
2257static int snd_rme9652_playback_open(struct snd_pcm_substream *substream)
2258{
2259 struct snd_rme9652 *rme9652 = snd_pcm_substream_chip(substream);
2260 struct snd_pcm_runtime *runtime = substream->runtime;
2261
2262 spin_lock_irq(&rme9652->lock);
2263
2264 snd_pcm_set_sync(substream);
2265
2266 runtime->hw = snd_rme9652_playback_subinfo;
2267 snd_pcm_set_runtime_buffer(substream, &rme9652->playback_dma_buf);
2268
2269 if (rme9652->capture_substream == NULL) {
2270 rme9652_stop(rme9652);
2271 rme9652_set_thru(rme9652, -1, 0);
2272 }
2273
2274 rme9652->playback_pid = current->pid;
2275 rme9652->playback_substream = substream;
2276
2277 spin_unlock_irq(&rme9652->lock);
2278
2279 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
2280 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hw_constraints_period_sizes);
2281 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
2282 snd_rme9652_hw_rule_channels, rme9652,
2283 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
2284 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
2285 snd_rme9652_hw_rule_channels_rate, rme9652,
2286 SNDRV_PCM_HW_PARAM_RATE, -1);
2287 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
2288 snd_rme9652_hw_rule_rate_channels, rme9652,
2289 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
2290
2291 rme9652->creg_spdif_stream = rme9652->creg_spdif;
2292 rme9652->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
2293 snd_ctl_notify(rme9652->card, SNDRV_CTL_EVENT_MASK_VALUE |
2294 SNDRV_CTL_EVENT_MASK_INFO, &rme9652->spdif_ctl->id);
2295 return 0;
2296}
2297
2298static int snd_rme9652_playback_release(struct snd_pcm_substream *substream)
2299{
2300 struct snd_rme9652 *rme9652 = snd_pcm_substream_chip(substream);
2301
2302 spin_lock_irq(&rme9652->lock);
2303
2304 rme9652->playback_pid = -1;
2305 rme9652->playback_substream = NULL;
2306
2307 spin_unlock_irq(&rme9652->lock);
2308
2309 rme9652->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
2310 snd_ctl_notify(rme9652->card, SNDRV_CTL_EVENT_MASK_VALUE |
2311 SNDRV_CTL_EVENT_MASK_INFO, &rme9652->spdif_ctl->id);
2312 return 0;
2313}
2314
2315
2316static int snd_rme9652_capture_open(struct snd_pcm_substream *substream)
2317{
2318 struct snd_rme9652 *rme9652 = snd_pcm_substream_chip(substream);
2319 struct snd_pcm_runtime *runtime = substream->runtime;
2320
2321 spin_lock_irq(&rme9652->lock);
2322
2323 snd_pcm_set_sync(substream);
2324
2325 runtime->hw = snd_rme9652_capture_subinfo;
2326 snd_pcm_set_runtime_buffer(substream, &rme9652->capture_dma_buf);
2327
2328 if (rme9652->playback_substream == NULL) {
2329 rme9652_stop(rme9652);
2330 rme9652_set_thru(rme9652, -1, 0);
2331 }
2332
2333 rme9652->capture_pid = current->pid;
2334 rme9652->capture_substream = substream;
2335
2336 spin_unlock_irq(&rme9652->lock);
2337
2338 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
2339 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hw_constraints_period_sizes);
2340 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
2341 snd_rme9652_hw_rule_channels, rme9652,
2342 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
2343 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
2344 snd_rme9652_hw_rule_channels_rate, rme9652,
2345 SNDRV_PCM_HW_PARAM_RATE, -1);
2346 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
2347 snd_rme9652_hw_rule_rate_channels, rme9652,
2348 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
2349 return 0;
2350}
2351
2352static int snd_rme9652_capture_release(struct snd_pcm_substream *substream)
2353{
2354 struct snd_rme9652 *rme9652 = snd_pcm_substream_chip(substream);
2355
2356 spin_lock_irq(&rme9652->lock);
2357
2358 rme9652->capture_pid = -1;
2359 rme9652->capture_substream = NULL;
2360
2361 spin_unlock_irq(&rme9652->lock);
2362 return 0;
2363}
2364
2365static const struct snd_pcm_ops snd_rme9652_playback_ops = {
2366 .open = snd_rme9652_playback_open,
2367 .close = snd_rme9652_playback_release,
2368 .ioctl = snd_rme9652_ioctl,
2369 .hw_params = snd_rme9652_hw_params,
2370 .prepare = snd_rme9652_prepare,
2371 .trigger = snd_rme9652_trigger,
2372 .pointer = snd_rme9652_hw_pointer,
2373 .copy_user = snd_rme9652_playback_copy,
2374 .copy_kernel = snd_rme9652_playback_copy_kernel,
2375 .fill_silence = snd_rme9652_hw_silence,
2376};
2377
2378static const struct snd_pcm_ops snd_rme9652_capture_ops = {
2379 .open = snd_rme9652_capture_open,
2380 .close = snd_rme9652_capture_release,
2381 .ioctl = snd_rme9652_ioctl,
2382 .hw_params = snd_rme9652_hw_params,
2383 .prepare = snd_rme9652_prepare,
2384 .trigger = snd_rme9652_trigger,
2385 .pointer = snd_rme9652_hw_pointer,
2386 .copy_user = snd_rme9652_capture_copy,
2387 .copy_kernel = snd_rme9652_capture_copy_kernel,
2388};
2389
2390static int snd_rme9652_create_pcm(struct snd_card *card,
2391 struct snd_rme9652 *rme9652)
2392{
2393 struct snd_pcm *pcm;
2394 int err;
2395
2396 err = snd_pcm_new(card, rme9652->card_name, 0, 1, 1, &pcm);
2397 if (err < 0)
2398 return err;
2399
2400 rme9652->pcm = pcm;
2401 pcm->private_data = rme9652;
2402 strcpy(pcm->name, rme9652->card_name);
2403
2404 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_rme9652_playback_ops);
2405 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_rme9652_capture_ops);
2406
2407 pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
2408
2409 return 0;
2410}
2411
2412static int snd_rme9652_create(struct snd_card *card,
2413 struct snd_rme9652 *rme9652,
2414 int precise_ptr)
2415{
2416 struct pci_dev *pci = rme9652->pci;
2417 int err;
2418 int status;
2419 unsigned short rev;
2420
2421 rme9652->irq = -1;
2422 rme9652->card = card;
2423
2424 pci_read_config_word(rme9652->pci, PCI_CLASS_REVISION, &rev);
2425
2426 switch (rev & 0xff) {
2427 case 3:
2428 case 4:
2429 case 8:
2430 case 9:
2431 break;
2432
2433 default:
2434
2435 return -ENODEV;
2436 }
2437
2438 err = pcim_enable_device(pci);
2439 if (err < 0)
2440 return err;
2441
2442 spin_lock_init(&rme9652->lock);
2443
2444 err = pci_request_regions(pci, "rme9652");
2445 if (err < 0)
2446 return err;
2447 rme9652->port = pci_resource_start(pci, 0);
2448 rme9652->iobase = devm_ioremap(&pci->dev, rme9652->port, RME9652_IO_EXTENT);
2449 if (rme9652->iobase == NULL) {
2450 dev_err(card->dev, "unable to remap region 0x%lx-0x%lx\n",
2451 rme9652->port, rme9652->port + RME9652_IO_EXTENT - 1);
2452 return -EBUSY;
2453 }
2454
2455 if (devm_request_irq(&pci->dev, pci->irq, snd_rme9652_interrupt,
2456 IRQF_SHARED, KBUILD_MODNAME, rme9652)) {
2457 dev_err(card->dev, "unable to request IRQ %d\n", pci->irq);
2458 return -EBUSY;
2459 }
2460 rme9652->irq = pci->irq;
2461 card->sync_irq = rme9652->irq;
2462 rme9652->precise_ptr = precise_ptr;
2463
2464
2465
2466
2467
2468
2469 status = rme9652_read(rme9652, RME9652_status_register);
2470 if (rme9652_decode_spdif_rate(status&RME9652_F) == 1) {
2471 rme9652->hw_rev = 15;
2472 } else {
2473 rme9652->hw_rev = 11;
2474 }
2475
2476
2477
2478
2479
2480
2481
2482
2483 switch (rev) {
2484 case 8:
2485 strcpy(card->driver, "RME9636");
2486 if (rme9652->hw_rev == 15) {
2487 rme9652->card_name = "RME Digi9636 (Rev 1.5)";
2488 } else {
2489 rme9652->card_name = "RME Digi9636";
2490 }
2491 rme9652->ss_channels = RME9636_NCHANNELS;
2492 break;
2493 case 9:
2494 strcpy(card->driver, "RME9636");
2495 rme9652->card_name = "RME Digi9636 (Rev G)";
2496 rme9652->ss_channels = RME9636_NCHANNELS;
2497 break;
2498 case 4:
2499 strcpy(card->driver, "RME9652");
2500 rme9652->card_name = "RME Digi9652 (Rev G)";
2501 rme9652->ss_channels = RME9652_NCHANNELS;
2502 break;
2503 case 3:
2504 strcpy(card->driver, "RME9652");
2505 if (rme9652->hw_rev == 15) {
2506 rme9652->card_name = "RME Digi9652 (Rev 1.5)";
2507 } else {
2508 rme9652->card_name = "RME Digi9652";
2509 }
2510 rme9652->ss_channels = RME9652_NCHANNELS;
2511 break;
2512 }
2513
2514 rme9652->ds_channels = (rme9652->ss_channels - 2) / 2 + 2;
2515
2516 pci_set_master(rme9652->pci);
2517
2518 err = snd_rme9652_initialize_memory(rme9652);
2519 if (err < 0)
2520 return err;
2521
2522 err = snd_rme9652_create_pcm(card, rme9652);
2523 if (err < 0)
2524 return err;
2525
2526 err = snd_rme9652_create_controls(card, rme9652);
2527 if (err < 0)
2528 return err;
2529
2530 snd_rme9652_proc_init(rme9652);
2531
2532 rme9652->last_spdif_sample_rate = -1;
2533 rme9652->last_adat_sample_rate = -1;
2534 rme9652->playback_pid = -1;
2535 rme9652->capture_pid = -1;
2536 rme9652->capture_substream = NULL;
2537 rme9652->playback_substream = NULL;
2538
2539 snd_rme9652_set_defaults(rme9652);
2540
2541 if (rme9652->hw_rev == 15) {
2542 rme9652_initialize_spdif_receiver (rme9652);
2543 }
2544
2545 return 0;
2546}
2547
2548static int snd_rme9652_probe(struct pci_dev *pci,
2549 const struct pci_device_id *pci_id)
2550{
2551 static int dev;
2552 struct snd_rme9652 *rme9652;
2553 struct snd_card *card;
2554 int err;
2555
2556 if (dev >= SNDRV_CARDS)
2557 return -ENODEV;
2558 if (!enable[dev]) {
2559 dev++;
2560 return -ENOENT;
2561 }
2562
2563 err = snd_devm_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2564 sizeof(struct snd_rme9652), &card);
2565
2566 if (err < 0)
2567 return err;
2568
2569 rme9652 = (struct snd_rme9652 *) card->private_data;
2570 card->private_free = snd_rme9652_card_free;
2571 rme9652->dev = dev;
2572 rme9652->pci = pci;
2573 err = snd_rme9652_create(card, rme9652, precise_ptr[dev]);
2574 if (err)
2575 return err;
2576
2577 strcpy(card->shortname, rme9652->card_name);
2578
2579 sprintf(card->longname, "%s at 0x%lx, irq %d",
2580 card->shortname, rme9652->port, rme9652->irq);
2581 err = snd_card_register(card);
2582 if (err)
2583 return err;
2584 pci_set_drvdata(pci, card);
2585 dev++;
2586 return 0;
2587}
2588
2589static struct pci_driver rme9652_driver = {
2590 .name = KBUILD_MODNAME,
2591 .id_table = snd_rme9652_ids,
2592 .probe = snd_rme9652_probe,
2593};
2594
2595module_pci_driver(rme9652_driver);
2596