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10#include <linux/acpi.h>
11#include <linux/clk.h>
12#include <linux/delay.h>
13#include <linux/init.h>
14#include <linux/i2c.h>
15#include <linux/module.h>
16#include <linux/math64.h>
17#include <linux/regmap.h>
18#include <linux/slab.h>
19#include <sound/core.h>
20#include <sound/initval.h>
21#include <sound/jack.h>
22#include <sound/pcm.h>
23#include <sound/pcm_params.h>
24#include <sound/soc.h>
25#include <sound/tlv.h>
26#include "nau8821.h"
27
28#define NAU_FREF_MAX 13500000
29#define NAU_FVCO_MAX 100000000
30#define NAU_FVCO_MIN 90000000
31
32
33#define CLK_DA_AD_MAX 6144000
34
35static int nau8821_configure_sysclk(struct nau8821 *nau8821,
36 int clk_id, unsigned int freq);
37
38struct nau8821_fll {
39 int mclk_src;
40 int ratio;
41 int fll_frac;
42 int fll_int;
43 int clk_ref_div;
44};
45
46struct nau8821_fll_attr {
47 unsigned int param;
48 unsigned int val;
49};
50
51
52static const struct nau8821_fll_attr mclk_src_scaling[] = {
53 { 1, 0x0 },
54 { 2, 0x2 },
55 { 4, 0x3 },
56 { 8, 0x4 },
57 { 16, 0x5 },
58 { 32, 0x6 },
59 { 3, 0x7 },
60 { 6, 0xa },
61 { 12, 0xb },
62 { 24, 0xc },
63 { 48, 0xd },
64 { 96, 0xe },
65 { 5, 0xf },
66};
67
68
69static const struct nau8821_fll_attr fll_ratio[] = {
70 { 512000, 0x01 },
71 { 256000, 0x02 },
72 { 128000, 0x04 },
73 { 64000, 0x08 },
74 { 32000, 0x10 },
75 { 8000, 0x20 },
76 { 4000, 0x40 },
77};
78
79static const struct nau8821_fll_attr fll_pre_scalar[] = {
80 { 0, 0x0 },
81 { 1, 0x1 },
82 { 2, 0x2 },
83 { 3, 0x3 },
84};
85
86
87struct nau8821_osr_attr {
88 unsigned int osr;
89 unsigned int clk_src;
90};
91
92static const struct nau8821_osr_attr osr_dac_sel[] = {
93 { 64, 2 },
94 { 256, 0 },
95 { 128, 1 },
96 { 0, 0 },
97 { 32, 3 },
98};
99
100static const struct nau8821_osr_attr osr_adc_sel[] = {
101 { 32, 3 },
102 { 64, 2 },
103 { 128, 1 },
104 { 256, 0 },
105};
106
107struct nau8821_dmic_speed {
108 unsigned int param;
109 unsigned int val;
110};
111
112static const struct nau8821_dmic_speed dmic_speed_sel[] = {
113 { 0, 0x0 },
114 { 1, 0x1 },
115 { 2, 0x2 },
116 { 3, 0x3 },
117};
118
119static const struct reg_default nau8821_reg_defaults[] = {
120 { NAU8821_R01_ENA_CTRL, 0x00ff },
121 { NAU8821_R03_CLK_DIVIDER, 0x0050 },
122 { NAU8821_R04_FLL1, 0x0 },
123 { NAU8821_R05_FLL2, 0x00bc },
124 { NAU8821_R06_FLL3, 0x0008 },
125 { NAU8821_R07_FLL4, 0x0010 },
126 { NAU8821_R08_FLL5, 0x4000 },
127 { NAU8821_R09_FLL6, 0x6900 },
128 { NAU8821_R0A_FLL7, 0x0031 },
129 { NAU8821_R0B_FLL8, 0x26e9 },
130 { NAU8821_R0D_JACK_DET_CTRL, 0x0 },
131 { NAU8821_R0F_INTERRUPT_MASK, 0x0 },
132 { NAU8821_R12_INTERRUPT_DIS_CTRL, 0xffff },
133 { NAU8821_R13_DMIC_CTRL, 0x0 },
134 { NAU8821_R1A_GPIO12_CTRL, 0x0 },
135 { NAU8821_R1B_TDM_CTRL, 0x0 },
136 { NAU8821_R1C_I2S_PCM_CTRL1, 0x000a },
137 { NAU8821_R1D_I2S_PCM_CTRL2, 0x8010 },
138 { NAU8821_R1E_LEFT_TIME_SLOT, 0x0 },
139 { NAU8821_R1F_RIGHT_TIME_SLOT, 0x0 },
140 { NAU8821_R21_BIQ0_COF1, 0x0 },
141 { NAU8821_R22_BIQ0_COF2, 0x0 },
142 { NAU8821_R23_BIQ0_COF3, 0x0 },
143 { NAU8821_R24_BIQ0_COF4, 0x0 },
144 { NAU8821_R25_BIQ0_COF5, 0x0 },
145 { NAU8821_R26_BIQ0_COF6, 0x0 },
146 { NAU8821_R27_BIQ0_COF7, 0x0 },
147 { NAU8821_R28_BIQ0_COF8, 0x0 },
148 { NAU8821_R29_BIQ0_COF9, 0x0 },
149 { NAU8821_R2A_BIQ0_COF10, 0x0 },
150 { NAU8821_R2B_ADC_RATE, 0x0002 },
151 { NAU8821_R2C_DAC_CTRL1, 0x0082 },
152 { NAU8821_R2D_DAC_CTRL2, 0x0 },
153 { NAU8821_R2F_DAC_DGAIN_CTRL, 0x0 },
154 { NAU8821_R30_ADC_DGAIN_CTRL, 0x0 },
155 { NAU8821_R31_MUTE_CTRL, 0x0 },
156 { NAU8821_R32_HSVOL_CTRL, 0x0 },
157 { NAU8821_R34_DACR_CTRL, 0xcfcf },
158 { NAU8821_R35_ADC_DGAIN_CTRL1, 0xcfcf },
159 { NAU8821_R36_ADC_DRC_KNEE_IP12, 0x1486 },
160 { NAU8821_R37_ADC_DRC_KNEE_IP34, 0x0f12 },
161 { NAU8821_R38_ADC_DRC_SLOPES, 0x25ff },
162 { NAU8821_R39_ADC_DRC_ATKDCY, 0x3457 },
163 { NAU8821_R3A_DAC_DRC_KNEE_IP12, 0x1486 },
164 { NAU8821_R3B_DAC_DRC_KNEE_IP34, 0x0f12 },
165 { NAU8821_R3C_DAC_DRC_SLOPES, 0x25f9 },
166 { NAU8821_R3D_DAC_DRC_ATKDCY, 0x3457 },
167 { NAU8821_R41_BIQ1_COF1, 0x0 },
168 { NAU8821_R42_BIQ1_COF2, 0x0 },
169 { NAU8821_R43_BIQ1_COF3, 0x0 },
170 { NAU8821_R44_BIQ1_COF4, 0x0 },
171 { NAU8821_R45_BIQ1_COF5, 0x0 },
172 { NAU8821_R46_BIQ1_COF6, 0x0 },
173 { NAU8821_R47_BIQ1_COF7, 0x0 },
174 { NAU8821_R48_BIQ1_COF8, 0x0 },
175 { NAU8821_R49_BIQ1_COF9, 0x0 },
176 { NAU8821_R4A_BIQ1_COF10, 0x0 },
177 { NAU8821_R4B_CLASSG_CTRL, 0x0 },
178 { NAU8821_R4C_IMM_MODE_CTRL, 0x0 },
179 { NAU8821_R4D_IMM_RMS_L, 0x0 },
180 { NAU8821_R53_OTPDOUT_1, 0xaad8 },
181 { NAU8821_R54_OTPDOUT_2, 0x0002 },
182 { NAU8821_R55_MISC_CTRL, 0x0 },
183 { NAU8821_R66_BIAS_ADJ, 0x0 },
184 { NAU8821_R68_TRIM_SETTINGS, 0x0 },
185 { NAU8821_R69_ANALOG_CONTROL_1, 0x0 },
186 { NAU8821_R6A_ANALOG_CONTROL_2, 0x0 },
187 { NAU8821_R6B_PGA_MUTE, 0x0 },
188 { NAU8821_R71_ANALOG_ADC_1, 0x0011 },
189 { NAU8821_R72_ANALOG_ADC_2, 0x0020 },
190 { NAU8821_R73_RDAC, 0x0008 },
191 { NAU8821_R74_MIC_BIAS, 0x0006 },
192 { NAU8821_R76_BOOST, 0x0 },
193 { NAU8821_R77_FEPGA, 0x0 },
194 { NAU8821_R7E_PGA_GAIN, 0x0 },
195 { NAU8821_R7F_POWER_UP_CONTROL, 0x0 },
196 { NAU8821_R80_CHARGE_PUMP, 0x0 },
197};
198
199static bool nau8821_readable_reg(struct device *dev, unsigned int reg)
200{
201 switch (reg) {
202 case NAU8821_R00_RESET ... NAU8821_R01_ENA_CTRL:
203 case NAU8821_R03_CLK_DIVIDER ... NAU8821_R0B_FLL8:
204 case NAU8821_R0D_JACK_DET_CTRL:
205 case NAU8821_R0F_INTERRUPT_MASK ... NAU8821_R13_DMIC_CTRL:
206 case NAU8821_R1A_GPIO12_CTRL ... NAU8821_R1F_RIGHT_TIME_SLOT:
207 case NAU8821_R21_BIQ0_COF1 ... NAU8821_R2D_DAC_CTRL2:
208 case NAU8821_R2F_DAC_DGAIN_CTRL ... NAU8821_R32_HSVOL_CTRL:
209 case NAU8821_R34_DACR_CTRL ... NAU8821_R3D_DAC_DRC_ATKDCY:
210 case NAU8821_R41_BIQ1_COF1 ... NAU8821_R4F_FUSE_CTRL3:
211 case NAU8821_R51_FUSE_CTRL1:
212 case NAU8821_R53_OTPDOUT_1 ... NAU8821_R55_MISC_CTRL:
213 case NAU8821_R58_I2C_DEVICE_ID ... NAU8821_R5A_SOFTWARE_RST:
214 case NAU8821_R66_BIAS_ADJ:
215 case NAU8821_R68_TRIM_SETTINGS ... NAU8821_R6B_PGA_MUTE:
216 case NAU8821_R71_ANALOG_ADC_1 ... NAU8821_R74_MIC_BIAS:
217 case NAU8821_R76_BOOST ... NAU8821_R77_FEPGA:
218 case NAU8821_R7E_PGA_GAIN ... NAU8821_R82_GENERAL_STATUS:
219 return true;
220 default:
221 return false;
222 }
223}
224
225static bool nau8821_writeable_reg(struct device *dev, unsigned int reg)
226{
227 switch (reg) {
228 case NAU8821_R00_RESET ... NAU8821_R01_ENA_CTRL:
229 case NAU8821_R03_CLK_DIVIDER ... NAU8821_R0B_FLL8:
230 case NAU8821_R0D_JACK_DET_CTRL:
231 case NAU8821_R0F_INTERRUPT_MASK:
232 case NAU8821_R11_INT_CLR_KEY_STATUS ... NAU8821_R13_DMIC_CTRL:
233 case NAU8821_R1A_GPIO12_CTRL ... NAU8821_R1F_RIGHT_TIME_SLOT:
234 case NAU8821_R21_BIQ0_COF1 ... NAU8821_R2D_DAC_CTRL2:
235 case NAU8821_R2F_DAC_DGAIN_CTRL ... NAU8821_R32_HSVOL_CTRL:
236 case NAU8821_R34_DACR_CTRL ... NAU8821_R3D_DAC_DRC_ATKDCY:
237 case NAU8821_R41_BIQ1_COF1 ... NAU8821_R4C_IMM_MODE_CTRL:
238 case NAU8821_R4E_FUSE_CTRL2 ... NAU8821_R4F_FUSE_CTRL3:
239 case NAU8821_R51_FUSE_CTRL1:
240 case NAU8821_R55_MISC_CTRL:
241 case NAU8821_R5A_SOFTWARE_RST:
242 case NAU8821_R66_BIAS_ADJ:
243 case NAU8821_R68_TRIM_SETTINGS ... NAU8821_R6B_PGA_MUTE:
244 case NAU8821_R71_ANALOG_ADC_1 ... NAU8821_R74_MIC_BIAS:
245 case NAU8821_R76_BOOST ... NAU8821_R77_FEPGA:
246 case NAU8821_R7E_PGA_GAIN ... NAU8821_R80_CHARGE_PUMP:
247 return true;
248 default:
249 return false;
250 }
251}
252
253static bool nau8821_volatile_reg(struct device *dev, unsigned int reg)
254{
255 switch (reg) {
256 case NAU8821_R00_RESET:
257 case NAU8821_R10_IRQ_STATUS ... NAU8821_R11_INT_CLR_KEY_STATUS:
258 case NAU8821_R21_BIQ0_COF1 ... NAU8821_R2A_BIQ0_COF10:
259 case NAU8821_R41_BIQ1_COF1 ... NAU8821_R4A_BIQ1_COF10:
260 case NAU8821_R4D_IMM_RMS_L:
261 case NAU8821_R53_OTPDOUT_1 ... NAU8821_R54_OTPDOUT_2:
262 case NAU8821_R58_I2C_DEVICE_ID ... NAU8821_R5A_SOFTWARE_RST:
263 case NAU8821_R81_CHARGE_PUMP_INPUT_READ ... NAU8821_R82_GENERAL_STATUS:
264 return true;
265 default:
266 return false;
267 }
268}
269
270static int nau8821_biq_coeff_get(struct snd_kcontrol *kcontrol,
271 struct snd_ctl_elem_value *ucontrol)
272{
273 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
274 struct soc_bytes_ext *params = (void *)kcontrol->private_value;
275
276 if (!component->regmap)
277 return -EINVAL;
278
279 regmap_raw_read(component->regmap, NAU8821_R21_BIQ0_COF1,
280 ucontrol->value.bytes.data, params->max);
281
282 return 0;
283}
284
285static int nau8821_biq_coeff_put(struct snd_kcontrol *kcontrol,
286 struct snd_ctl_elem_value *ucontrol)
287{
288 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
289 struct soc_bytes_ext *params = (void *)kcontrol->private_value;
290 void *data;
291
292 if (!component->regmap)
293 return -EINVAL;
294
295 data = kmemdup(ucontrol->value.bytes.data,
296 params->max, GFP_KERNEL | GFP_DMA);
297 if (!data)
298 return -ENOMEM;
299
300 regmap_raw_write(component->regmap, NAU8821_R21_BIQ0_COF1,
301 data, params->max);
302
303 kfree(data);
304
305 return 0;
306}
307
308static const char * const nau8821_adc_decimation[] = {
309 "32", "64", "128", "256" };
310
311static const struct soc_enum nau8821_adc_decimation_enum =
312 SOC_ENUM_SINGLE(NAU8821_R2B_ADC_RATE, NAU8821_ADC_SYNC_DOWN_SFT,
313 ARRAY_SIZE(nau8821_adc_decimation), nau8821_adc_decimation);
314
315static const char * const nau8821_dac_oversampl[] = {
316 "64", "256", "128", "", "32" };
317
318static const struct soc_enum nau8821_dac_oversampl_enum =
319 SOC_ENUM_SINGLE(NAU8821_R2C_DAC_CTRL1, NAU8821_DAC_OVERSAMPLE_SFT,
320 ARRAY_SIZE(nau8821_dac_oversampl), nau8821_dac_oversampl);
321
322static const DECLARE_TLV_DB_MINMAX_MUTE(adc_vol_tlv, -6600, 2400);
323static const DECLARE_TLV_DB_MINMAX_MUTE(sidetone_vol_tlv, -4200, 0);
324static const DECLARE_TLV_DB_MINMAX(hp_vol_tlv, -900, 0);
325static const DECLARE_TLV_DB_SCALE(playback_vol_tlv, -6600, 50, 1);
326static const DECLARE_TLV_DB_MINMAX(fepga_gain_tlv, -100, 3600);
327static const DECLARE_TLV_DB_MINMAX_MUTE(crosstalk_vol_tlv, -7000, 2400);
328
329static const struct snd_kcontrol_new nau8821_controls[] = {
330 SOC_DOUBLE_TLV("Mic Volume", NAU8821_R35_ADC_DGAIN_CTRL1,
331 NAU8821_ADCL_CH_VOL_SFT, NAU8821_ADCR_CH_VOL_SFT,
332 0xff, 0, adc_vol_tlv),
333 SOC_DOUBLE_TLV("Headphone Bypass Volume", NAU8821_R30_ADC_DGAIN_CTRL,
334 12, 8, 0x0f, 0, sidetone_vol_tlv),
335 SOC_DOUBLE_TLV("Headphone Volume", NAU8821_R32_HSVOL_CTRL,
336 NAU8821_HPL_VOL_SFT, NAU8821_HPR_VOL_SFT, 0x3, 1, hp_vol_tlv),
337 SOC_DOUBLE_TLV("Digital Playback Volume", NAU8821_R34_DACR_CTRL,
338 NAU8821_DACL_CH_VOL_SFT, NAU8821_DACR_CH_VOL_SFT,
339 0xcf, 0, playback_vol_tlv),
340 SOC_DOUBLE_TLV("Frontend PGA Volume", NAU8821_R7E_PGA_GAIN,
341 NAU8821_PGA_GAIN_L_SFT, NAU8821_PGA_GAIN_R_SFT,
342 37, 0, fepga_gain_tlv),
343 SOC_DOUBLE_TLV("Headphone Crosstalk Volume",
344 NAU8821_R2F_DAC_DGAIN_CTRL,
345 0, 8, 0xff, 0, crosstalk_vol_tlv),
346
347 SOC_ENUM("ADC Decimation Rate", nau8821_adc_decimation_enum),
348 SOC_ENUM("DAC Oversampling Rate", nau8821_dac_oversampl_enum),
349 SND_SOC_BYTES_EXT("BIQ Coefficients", 20,
350 nau8821_biq_coeff_get, nau8821_biq_coeff_put),
351 SOC_SINGLE("ADC Phase Switch", NAU8821_R1B_TDM_CTRL,
352 NAU8821_ADCPHS_SFT, 1, 0),
353};
354
355static const struct snd_kcontrol_new nau8821_dmic_mode_switch =
356 SOC_DAPM_SINGLE("Switch", NAU8821_R13_DMIC_CTRL,
357 NAU8821_DMIC_EN_SFT, 1, 0);
358
359static int dmic_clock_control(struct snd_soc_dapm_widget *w,
360 struct snd_kcontrol *k, int event)
361{
362 struct snd_soc_component *component =
363 snd_soc_dapm_to_component(w->dapm);
364 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
365 int i, speed_selection = -1, clk_adc_src, clk_adc;
366 unsigned int clk_divider_r03;
367
368
369
370
371
372 regmap_read(nau8821->regmap, NAU8821_R03_CLK_DIVIDER,
373 &clk_divider_r03);
374 clk_adc_src = (clk_divider_r03 & NAU8821_CLK_ADC_SRC_MASK)
375 >> NAU8821_CLK_ADC_SRC_SFT;
376 clk_adc = (nau8821->fs * 256) >> clk_adc_src;
377
378 for (i = 0 ; i < 4 ; i++)
379 if ((clk_adc >> dmic_speed_sel[i].param) <=
380 nau8821->dmic_clk_threshold) {
381 speed_selection = dmic_speed_sel[i].val;
382 break;
383 }
384 if (i == 4)
385 return -EINVAL;
386
387 dev_dbg(nau8821->dev,
388 "clk_adc=%d, dmic_clk_threshold = %d, param=%d, val = %d\n",
389 clk_adc, nau8821->dmic_clk_threshold,
390 dmic_speed_sel[i].param, dmic_speed_sel[i].val);
391 regmap_update_bits(nau8821->regmap, NAU8821_R13_DMIC_CTRL,
392 NAU8821_DMIC_SRC_MASK,
393 (speed_selection << NAU8821_DMIC_SRC_SFT));
394
395 return 0;
396}
397
398static int nau8821_left_adc_event(struct snd_soc_dapm_widget *w,
399 struct snd_kcontrol *kcontrol, int event)
400{
401 struct snd_soc_component *component =
402 snd_soc_dapm_to_component(w->dapm);
403 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
404
405 switch (event) {
406 case SND_SOC_DAPM_POST_PMU:
407 msleep(125);
408 regmap_update_bits(nau8821->regmap, NAU8821_R01_ENA_CTRL,
409 NAU8821_EN_ADCL, NAU8821_EN_ADCL);
410 break;
411 case SND_SOC_DAPM_POST_PMD:
412 regmap_update_bits(nau8821->regmap,
413 NAU8821_R01_ENA_CTRL, NAU8821_EN_ADCL, 0);
414 break;
415 default:
416 return -EINVAL;
417 }
418
419 return 0;
420}
421
422static int nau8821_right_adc_event(struct snd_soc_dapm_widget *w,
423 struct snd_kcontrol *kcontrol, int event)
424{
425 struct snd_soc_component *component =
426 snd_soc_dapm_to_component(w->dapm);
427 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
428
429 switch (event) {
430 case SND_SOC_DAPM_POST_PMU:
431 msleep(125);
432 regmap_update_bits(nau8821->regmap, NAU8821_R01_ENA_CTRL,
433 NAU8821_EN_ADCR, NAU8821_EN_ADCR);
434 break;
435 case SND_SOC_DAPM_POST_PMD:
436 regmap_update_bits(nau8821->regmap,
437 NAU8821_R01_ENA_CTRL, NAU8821_EN_ADCR, 0);
438 break;
439 default:
440 return -EINVAL;
441 }
442
443 return 0;
444}
445
446static int nau8821_pump_event(struct snd_soc_dapm_widget *w,
447 struct snd_kcontrol *kcontrol, int event)
448{
449 struct snd_soc_component *component =
450 snd_soc_dapm_to_component(w->dapm);
451 struct nau8821 *nau8821 =
452 snd_soc_component_get_drvdata(component);
453
454 switch (event) {
455 case SND_SOC_DAPM_POST_PMU:
456
457 msleep(20);
458 regmap_update_bits(nau8821->regmap, NAU8821_R80_CHARGE_PUMP,
459 NAU8821_JAMNODCLOW, NAU8821_JAMNODCLOW);
460 break;
461 case SND_SOC_DAPM_PRE_PMD:
462 regmap_update_bits(nau8821->regmap, NAU8821_R80_CHARGE_PUMP,
463 NAU8821_JAMNODCLOW, 0);
464 break;
465 default:
466 return -EINVAL;
467 }
468
469 return 0;
470}
471
472static int nau8821_output_dac_event(struct snd_soc_dapm_widget *w,
473 struct snd_kcontrol *kcontrol, int event)
474{
475 struct snd_soc_component *component =
476 snd_soc_dapm_to_component(w->dapm);
477 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
478
479 switch (event) {
480 case SND_SOC_DAPM_PRE_PMU:
481
482 regmap_update_bits(nau8821->regmap, NAU8821_R66_BIAS_ADJ,
483 NAU8821_BIAS_TESTDAC_EN, 0);
484 break;
485 case SND_SOC_DAPM_POST_PMD:
486 regmap_update_bits(nau8821->regmap, NAU8821_R66_BIAS_ADJ,
487 NAU8821_BIAS_TESTDAC_EN, NAU8821_BIAS_TESTDAC_EN);
488 break;
489 default:
490 return -EINVAL;
491 }
492
493 return 0;
494}
495
496static const struct snd_soc_dapm_widget nau8821_dapm_widgets[] = {
497 SND_SOC_DAPM_SUPPLY("MICBIAS", NAU8821_R74_MIC_BIAS,
498 NAU8821_MICBIAS_POWERUP_SFT, 0, NULL, 0),
499 SND_SOC_DAPM_SUPPLY("DMIC Clock", SND_SOC_NOPM, 0, 0,
500 dmic_clock_control, SND_SOC_DAPM_POST_PMU),
501 SND_SOC_DAPM_ADC("ADCL Power", NULL, NAU8821_R72_ANALOG_ADC_2,
502 NAU8821_POWERUP_ADCL_SFT, 0),
503 SND_SOC_DAPM_ADC("ADCR Power", NULL, NAU8821_R72_ANALOG_ADC_2,
504 NAU8821_POWERUP_ADCR_SFT, 0),
505 SND_SOC_DAPM_PGA_S("Frontend PGA L", 1, NAU8821_R7F_POWER_UP_CONTROL,
506 NAU8821_PUP_PGA_L_SFT, 0, NULL, 0),
507 SND_SOC_DAPM_PGA_S("Frontend PGA R", 1, NAU8821_R7F_POWER_UP_CONTROL,
508 NAU8821_PUP_PGA_R_SFT, 0, NULL, 0),
509 SND_SOC_DAPM_PGA_S("ADCL Digital path", 0, NAU8821_R01_ENA_CTRL,
510 NAU8821_EN_ADCL_SFT, 0, nau8821_left_adc_event,
511 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
512 SND_SOC_DAPM_PGA_S("ADCR Digital path", 0, NAU8821_R01_ENA_CTRL,
513 NAU8821_EN_ADCR_SFT, 0, nau8821_right_adc_event,
514 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
515 SND_SOC_DAPM_SWITCH("DMIC Enable", SND_SOC_NOPM,
516 0, 0, &nau8821_dmic_mode_switch),
517 SND_SOC_DAPM_AIF_OUT("AIFTX", "Capture", 0, NAU8821_R1D_I2S_PCM_CTRL2,
518 NAU8821_I2S_TRISTATE_SFT, 1),
519 SND_SOC_DAPM_AIF_IN("AIFRX", "Playback", 0, SND_SOC_NOPM, 0, 0),
520
521 SND_SOC_DAPM_PGA_S("ADACL", 2, NAU8821_R73_RDAC,
522 NAU8821_DACL_EN_SFT, 0, NULL, 0),
523 SND_SOC_DAPM_PGA_S("ADACR", 2, NAU8821_R73_RDAC,
524 NAU8821_DACR_EN_SFT, 0, NULL, 0),
525 SND_SOC_DAPM_PGA_S("ADACL Clock", 3, NAU8821_R73_RDAC,
526 NAU8821_DACL_CLK_EN_SFT, 0, NULL, 0),
527 SND_SOC_DAPM_PGA_S("ADACR Clock", 3, NAU8821_R73_RDAC,
528 NAU8821_DACR_CLK_EN_SFT, 0, NULL, 0),
529 SND_SOC_DAPM_DAC("DDACR", NULL, NAU8821_R01_ENA_CTRL,
530 NAU8821_EN_DACR_SFT, 0),
531 SND_SOC_DAPM_DAC("DDACL", NULL, NAU8821_R01_ENA_CTRL,
532 NAU8821_EN_DACL_SFT, 0),
533 SND_SOC_DAPM_PGA_S("HP amp L", 0, NAU8821_R4B_CLASSG_CTRL,
534 NAU8821_CLASSG_LDAC_EN_SFT, 0, NULL, 0),
535 SND_SOC_DAPM_PGA_S("HP amp R", 0, NAU8821_R4B_CLASSG_CTRL,
536 NAU8821_CLASSG_RDAC_EN_SFT, 0, NULL, 0),
537 SND_SOC_DAPM_PGA_S("Charge Pump", 1, NAU8821_R80_CHARGE_PUMP,
538 NAU8821_CHANRGE_PUMP_EN_SFT, 0, nau8821_pump_event,
539 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
540 SND_SOC_DAPM_PGA_S("Output Driver R Stage 1", 4,
541 NAU8821_R7F_POWER_UP_CONTROL,
542 NAU8821_PUP_INTEG_R_SFT, 0, NULL, 0),
543 SND_SOC_DAPM_PGA_S("Output Driver L Stage 1", 4,
544 NAU8821_R7F_POWER_UP_CONTROL,
545 NAU8821_PUP_INTEG_L_SFT, 0, NULL, 0),
546 SND_SOC_DAPM_PGA_S("Output Driver R Stage 2", 5,
547 NAU8821_R7F_POWER_UP_CONTROL,
548 NAU8821_PUP_DRV_INSTG_R_SFT, 0, NULL, 0),
549 SND_SOC_DAPM_PGA_S("Output Driver L Stage 2", 5,
550 NAU8821_R7F_POWER_UP_CONTROL,
551 NAU8821_PUP_DRV_INSTG_L_SFT, 0, NULL, 0),
552 SND_SOC_DAPM_PGA_S("Output Driver R Stage 3", 6,
553 NAU8821_R7F_POWER_UP_CONTROL,
554 NAU8821_PUP_MAIN_DRV_R_SFT, 0, NULL, 0),
555 SND_SOC_DAPM_PGA_S("Output Driver L Stage 3", 6,
556 NAU8821_R7F_POWER_UP_CONTROL,
557 NAU8821_PUP_MAIN_DRV_L_SFT, 0, NULL, 0),
558 SND_SOC_DAPM_PGA_S("Output DACL", 7,
559 NAU8821_R80_CHARGE_PUMP, NAU8821_POWER_DOWN_DACL_SFT,
560 0, nau8821_output_dac_event,
561 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
562 SND_SOC_DAPM_PGA_S("Output DACR", 7,
563 NAU8821_R80_CHARGE_PUMP, NAU8821_POWER_DOWN_DACR_SFT,
564 0, nau8821_output_dac_event,
565 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
566
567
568 SND_SOC_DAPM_PGA_S("HPOL Pulldown", 8,
569 NAU8821_R0D_JACK_DET_CTRL,
570 NAU8821_SPKR_DWN1L_SFT, 0, NULL, 0),
571 SND_SOC_DAPM_PGA_S("HPOR Pulldown", 8,
572 NAU8821_R0D_JACK_DET_CTRL,
573 NAU8821_SPKR_DWN1R_SFT, 0, NULL, 0),
574
575
576 SND_SOC_DAPM_PGA_S("HP Boost Driver", 9,
577 NAU8821_R76_BOOST, NAU8821_HP_BOOST_DIS_SFT, 1, NULL, 0),
578 SND_SOC_DAPM_PGA("Class G", NAU8821_R4B_CLASSG_CTRL,
579 NAU8821_CLASSG_EN_SFT, 0, NULL, 0),
580
581 SND_SOC_DAPM_INPUT("MICL"),
582 SND_SOC_DAPM_INPUT("MICR"),
583 SND_SOC_DAPM_INPUT("DMIC"),
584 SND_SOC_DAPM_OUTPUT("HPOL"),
585 SND_SOC_DAPM_OUTPUT("HPOR"),
586};
587
588static const struct snd_soc_dapm_route nau8821_dapm_routes[] = {
589 {"DMIC Enable", "Switch", "DMIC"},
590 {"DMIC Enable", NULL, "DMIC Clock"},
591
592 {"Frontend PGA L", NULL, "MICL"},
593 {"Frontend PGA R", NULL, "MICR"},
594 {"Frontend PGA L", NULL, "MICBIAS"},
595 {"Frontend PGA R", NULL, "MICBIAS"},
596
597 {"ADCL Power", NULL, "Frontend PGA L"},
598 {"ADCR Power", NULL, "Frontend PGA R"},
599
600 {"ADCL Digital path", NULL, "ADCL Power"},
601 {"ADCR Digital path", NULL, "ADCR Power"},
602 {"ADCL Digital path", NULL, "DMIC Enable"},
603 {"ADCR Digital path", NULL, "DMIC Enable"},
604
605 {"AIFTX", NULL, "ADCL Digital path"},
606 {"AIFTX", NULL, "ADCR Digital path"},
607
608 {"DDACL", NULL, "AIFRX"},
609 {"DDACR", NULL, "AIFRX"},
610
611 {"HP amp L", NULL, "DDACL"},
612 {"HP amp R", NULL, "DDACR"},
613
614 {"Charge Pump", NULL, "HP amp L"},
615 {"Charge Pump", NULL, "HP amp R"},
616
617 {"ADACL", NULL, "Charge Pump"},
618 {"ADACR", NULL, "Charge Pump"},
619 {"ADACL Clock", NULL, "ADACL"},
620 {"ADACR Clock", NULL, "ADACR"},
621
622 {"Output Driver L Stage 1", NULL, "ADACL Clock"},
623 {"Output Driver R Stage 1", NULL, "ADACR Clock"},
624 {"Output Driver L Stage 2", NULL, "Output Driver L Stage 1"},
625 {"Output Driver R Stage 2", NULL, "Output Driver R Stage 1"},
626 {"Output Driver L Stage 3", NULL, "Output Driver L Stage 2"},
627 {"Output Driver R Stage 3", NULL, "Output Driver R Stage 2"},
628 {"Output DACL", NULL, "Output Driver L Stage 3"},
629 {"Output DACR", NULL, "Output Driver R Stage 3"},
630
631 {"HPOL Pulldown", NULL, "Output DACL"},
632 {"HPOR Pulldown", NULL, "Output DACR"},
633 {"HP Boost Driver", NULL, "HPOL Pulldown"},
634 {"HP Boost Driver", NULL, "HPOR Pulldown"},
635
636 {"Class G", NULL, "HP Boost Driver"},
637 {"HPOL", NULL, "Class G"},
638 {"HPOR", NULL, "Class G"},
639};
640
641static int nau8821_clock_check(struct nau8821 *nau8821,
642 int stream, int rate, int osr)
643{
644 int osrate = 0;
645
646 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
647 if (osr >= ARRAY_SIZE(osr_dac_sel))
648 return -EINVAL;
649 osrate = osr_dac_sel[osr].osr;
650 } else {
651 if (osr >= ARRAY_SIZE(osr_adc_sel))
652 return -EINVAL;
653 osrate = osr_adc_sel[osr].osr;
654 }
655
656 if (!osrate || rate * osrate > CLK_DA_AD_MAX) {
657 dev_err(nau8821->dev,
658 "exceed the maximum frequency of CLK_ADC or CLK_DAC");
659 return -EINVAL;
660 }
661
662 return 0;
663}
664
665static int nau8821_hw_params(struct snd_pcm_substream *substream,
666 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
667{
668 struct snd_soc_component *component = dai->component;
669 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
670 unsigned int val_len = 0, osr, ctrl_val, bclk_fs, clk_div;
671
672 nau8821->fs = params_rate(params);
673
674
675
676
677
678
679 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
680 regmap_read(nau8821->regmap, NAU8821_R2C_DAC_CTRL1, &osr);
681 osr &= NAU8821_DAC_OVERSAMPLE_MASK;
682 if (nau8821_clock_check(nau8821, substream->stream,
683 nau8821->fs, osr)) {
684 return -EINVAL;
685 }
686 regmap_update_bits(nau8821->regmap, NAU8821_R03_CLK_DIVIDER,
687 NAU8821_CLK_DAC_SRC_MASK,
688 osr_dac_sel[osr].clk_src << NAU8821_CLK_DAC_SRC_SFT);
689 } else {
690 regmap_read(nau8821->regmap, NAU8821_R2B_ADC_RATE, &osr);
691 osr &= NAU8821_ADC_SYNC_DOWN_MASK;
692 if (nau8821_clock_check(nau8821, substream->stream,
693 nau8821->fs, osr)) {
694 return -EINVAL;
695 }
696 regmap_update_bits(nau8821->regmap, NAU8821_R03_CLK_DIVIDER,
697 NAU8821_CLK_ADC_SRC_MASK,
698 osr_adc_sel[osr].clk_src << NAU8821_CLK_ADC_SRC_SFT);
699 }
700
701
702 regmap_read(nau8821->regmap, NAU8821_R1D_I2S_PCM_CTRL2, &ctrl_val);
703 if (ctrl_val & NAU8821_I2S_MS_MASTER) {
704
705 bclk_fs = snd_soc_params_to_bclk(params) / nau8821->fs;
706 if (bclk_fs <= 32)
707 clk_div = 3;
708 else if (bclk_fs <= 64)
709 clk_div = 2;
710 else if (bclk_fs <= 128)
711 clk_div = 1;
712 else {
713 return -EINVAL;
714 }
715 regmap_update_bits(nau8821->regmap, NAU8821_R1D_I2S_PCM_CTRL2,
716 NAU8821_I2S_LRC_DIV_MASK | NAU8821_I2S_BLK_DIV_MASK,
717 (clk_div << NAU8821_I2S_LRC_DIV_SFT) | clk_div);
718 }
719
720 switch (params_width(params)) {
721 case 16:
722 val_len |= NAU8821_I2S_DL_16;
723 break;
724 case 20:
725 val_len |= NAU8821_I2S_DL_20;
726 break;
727 case 24:
728 val_len |= NAU8821_I2S_DL_24;
729 break;
730 case 32:
731 val_len |= NAU8821_I2S_DL_32;
732 break;
733 default:
734 return -EINVAL;
735 }
736
737 regmap_update_bits(nau8821->regmap, NAU8821_R1C_I2S_PCM_CTRL1,
738 NAU8821_I2S_DL_MASK, val_len);
739
740 return 0;
741}
742
743static int nau8821_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
744{
745 struct snd_soc_component *component = codec_dai->component;
746 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
747 unsigned int ctrl1_val = 0, ctrl2_val = 0;
748
749 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
750 case SND_SOC_DAIFMT_CBP_CFP:
751 ctrl2_val |= NAU8821_I2S_MS_MASTER;
752 break;
753 case SND_SOC_DAIFMT_CBC_CFC:
754 break;
755 default:
756 return -EINVAL;
757 }
758
759 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
760 case SND_SOC_DAIFMT_NB_NF:
761 break;
762 case SND_SOC_DAIFMT_IB_NF:
763 ctrl1_val |= NAU8821_I2S_BP_INV;
764 break;
765 default:
766 return -EINVAL;
767 }
768
769 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
770 case SND_SOC_DAIFMT_I2S:
771 ctrl1_val |= NAU8821_I2S_DF_I2S;
772 break;
773 case SND_SOC_DAIFMT_LEFT_J:
774 ctrl1_val |= NAU8821_I2S_DF_LEFT;
775 break;
776 case SND_SOC_DAIFMT_RIGHT_J:
777 ctrl1_val |= NAU8821_I2S_DF_RIGTH;
778 break;
779 case SND_SOC_DAIFMT_DSP_A:
780 ctrl1_val |= NAU8821_I2S_DF_PCM_AB;
781 break;
782 case SND_SOC_DAIFMT_DSP_B:
783 ctrl1_val |= NAU8821_I2S_DF_PCM_AB;
784 ctrl1_val |= NAU8821_I2S_PCMB_EN;
785 break;
786 default:
787 return -EINVAL;
788 }
789
790 regmap_update_bits(nau8821->regmap, NAU8821_R1C_I2S_PCM_CTRL1,
791 NAU8821_I2S_DL_MASK | NAU8821_I2S_DF_MASK |
792 NAU8821_I2S_BP_MASK | NAU8821_I2S_PCMB_MASK, ctrl1_val);
793 regmap_update_bits(nau8821->regmap, NAU8821_R1D_I2S_PCM_CTRL2,
794 NAU8821_I2S_MS_MASK, ctrl2_val);
795
796 return 0;
797}
798
799static int nau8821_digital_mute(struct snd_soc_dai *dai, int mute,
800 int direction)
801{
802 struct snd_soc_component *component = dai->component;
803 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
804 unsigned int val = 0;
805
806 if (mute)
807 val = NAU8821_DAC_SOFT_MUTE;
808
809 return regmap_update_bits(nau8821->regmap,
810 NAU8821_R31_MUTE_CTRL, NAU8821_DAC_SOFT_MUTE, val);
811}
812
813static const struct snd_soc_dai_ops nau8821_dai_ops = {
814 .hw_params = nau8821_hw_params,
815 .set_fmt = nau8821_set_dai_fmt,
816 .mute_stream = nau8821_digital_mute,
817};
818
819#define NAU8821_RATES SNDRV_PCM_RATE_8000_192000
820#define NAU8821_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \
821 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
822
823static struct snd_soc_dai_driver nau8821_dai = {
824 .name = NUVOTON_CODEC_DAI,
825 .playback = {
826 .stream_name = "Playback",
827 .channels_min = 1,
828 .channels_max = 2,
829 .rates = NAU8821_RATES,
830 .formats = NAU8821_FORMATS,
831 },
832 .capture = {
833 .stream_name = "Capture",
834 .channels_min = 1,
835 .channels_max = 2,
836 .rates = NAU8821_RATES,
837 .formats = NAU8821_FORMATS,
838 },
839 .ops = &nau8821_dai_ops,
840};
841
842
843static bool nau8821_is_jack_inserted(struct regmap *regmap)
844{
845 bool active_high, is_high;
846 int status, jkdet;
847
848 regmap_read(regmap, NAU8821_R0D_JACK_DET_CTRL, &jkdet);
849 active_high = jkdet & NAU8821_JACK_POLARITY;
850 regmap_read(regmap, NAU8821_R82_GENERAL_STATUS, &status);
851 is_high = status & NAU8821_GPIO2_IN;
852
853
854
855 return active_high == is_high;
856}
857
858static void nau8821_int_status_clear_all(struct regmap *regmap)
859{
860 int active_irq, clear_irq, i;
861
862
863
864
865 regmap_read(regmap, NAU8821_R10_IRQ_STATUS, &active_irq);
866 for (i = 0; i < NAU8821_REG_DATA_LEN; i++) {
867 clear_irq = (0x1 << i);
868 if (active_irq & clear_irq)
869 regmap_write(regmap,
870 NAU8821_R11_INT_CLR_KEY_STATUS, clear_irq);
871 }
872}
873
874static void nau8821_eject_jack(struct nau8821 *nau8821)
875{
876 struct snd_soc_dapm_context *dapm = nau8821->dapm;
877 struct regmap *regmap = nau8821->regmap;
878 struct snd_soc_component *component = snd_soc_dapm_to_component(dapm);
879
880
881 regmap_update_bits(regmap, NAU8821_R74_MIC_BIAS,
882 NAU8821_MICBIAS_JKR2, 0);
883
884 regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL,
885 NAU8821_SPKR_DWN1R | NAU8821_SPKR_DWN1L, 0);
886 snd_soc_component_disable_pin(component, "MICBIAS");
887 snd_soc_dapm_sync(dapm);
888
889
890 nau8821_int_status_clear_all(regmap);
891
892
893
894
895 regmap_update_bits(regmap, NAU8821_R12_INTERRUPT_DIS_CTRL,
896 NAU8821_IRQ_EJECT_DIS | NAU8821_IRQ_INSERT_DIS,
897 NAU8821_IRQ_EJECT_DIS);
898
899 regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK,
900 NAU8821_IRQ_EJECT_EN | NAU8821_IRQ_INSERT_EN,
901 NAU8821_IRQ_EJECT_EN);
902
903 regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL,
904 NAU8821_JACK_DET_DB_BYPASS, NAU8821_JACK_DET_DB_BYPASS);
905
906
907 if (dapm->bias_level < SND_SOC_BIAS_PREPARE)
908 nau8821_configure_sysclk(nau8821, NAU8821_CLK_DIS, 0);
909
910
911 regmap_update_bits(regmap, NAU8821_R2B_ADC_RATE,
912 NAU8821_ADC_R_SRC_EN, 0);
913}
914
915static void nau8821_jdet_work(struct work_struct *work)
916{
917 struct nau8821 *nau8821 =
918 container_of(work, struct nau8821, jdet_work);
919 struct snd_soc_dapm_context *dapm = nau8821->dapm;
920 struct snd_soc_component *component = snd_soc_dapm_to_component(dapm);
921 struct regmap *regmap = nau8821->regmap;
922 int jack_status_reg, mic_detected, event = 0, event_mask = 0;
923
924 snd_soc_component_force_enable_pin(component, "MICBIAS");
925 snd_soc_dapm_sync(dapm);
926 msleep(20);
927
928 regmap_read(regmap, NAU8821_R58_I2C_DEVICE_ID, &jack_status_reg);
929 mic_detected = !(jack_status_reg & NAU8821_KEYDET);
930 if (mic_detected) {
931 dev_dbg(nau8821->dev, "Headset connected\n");
932 event |= SND_JACK_HEADSET;
933
934
935 regmap_update_bits(regmap, NAU8821_R74_MIC_BIAS,
936 NAU8821_MICBIAS_JKR2, NAU8821_MICBIAS_JKR2);
937
938
939
940 regmap_update_bits(regmap, NAU8821_R2B_ADC_RATE,
941 NAU8821_ADC_R_SRC_EN, NAU8821_ADC_R_SRC_EN);
942 } else {
943 dev_dbg(nau8821->dev, "Headphone connected\n");
944 event |= SND_JACK_HEADPHONE;
945 snd_soc_component_disable_pin(component, "MICBIAS");
946 snd_soc_dapm_sync(dapm);
947 }
948 event_mask |= SND_JACK_HEADSET;
949 snd_soc_jack_report(nau8821->jack, event, event_mask);
950}
951
952
953static void nau8821_setup_inserted_irq(struct nau8821 *nau8821)
954{
955 struct regmap *regmap = nau8821->regmap;
956
957
958 if (nau8821->dapm->bias_level < SND_SOC_BIAS_PREPARE)
959 nau8821_configure_sysclk(nau8821, NAU8821_CLK_INTERNAL, 0);
960
961
962
963
964
965
966 regmap_update_bits(regmap, NAU8821_R1D_I2S_PCM_CTRL2,
967 NAU8821_I2S_MS_MASK, NAU8821_I2S_MS_MASTER);
968 regmap_update_bits(regmap, NAU8821_R1D_I2S_PCM_CTRL2,
969 NAU8821_I2S_MS_MASK, NAU8821_I2S_MS_SLAVE);
970
971
972 regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL,
973 NAU8821_JACK_DET_DB_BYPASS, 0);
974
975 regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK,
976 NAU8821_IRQ_EJECT_EN, 0);
977 regmap_update_bits(regmap, NAU8821_R12_INTERRUPT_DIS_CTRL,
978 NAU8821_IRQ_EJECT_DIS, 0);
979}
980
981static irqreturn_t nau8821_interrupt(int irq, void *data)
982{
983 struct nau8821 *nau8821 = (struct nau8821 *)data;
984 struct regmap *regmap = nau8821->regmap;
985 int active_irq, clear_irq = 0, event = 0, event_mask = 0;
986
987 if (regmap_read(regmap, NAU8821_R10_IRQ_STATUS, &active_irq)) {
988 dev_err(nau8821->dev, "failed to read irq status\n");
989 return IRQ_NONE;
990 }
991
992 dev_dbg(nau8821->dev, "IRQ %d\n", active_irq);
993
994 if ((active_irq & NAU8821_JACK_EJECT_IRQ_MASK) ==
995 NAU8821_JACK_EJECT_DETECTED) {
996 regmap_update_bits(regmap, NAU8821_R71_ANALOG_ADC_1,
997 NAU8821_MICDET_MASK, NAU8821_MICDET_DIS);
998 nau8821_eject_jack(nau8821);
999 event_mask |= SND_JACK_HEADSET;
1000 clear_irq = NAU8821_JACK_EJECT_IRQ_MASK;
1001 } else if ((active_irq & NAU8821_JACK_INSERT_IRQ_MASK) ==
1002 NAU8821_JACK_INSERT_DETECTED) {
1003 regmap_update_bits(regmap, NAU8821_R71_ANALOG_ADC_1,
1004 NAU8821_MICDET_MASK, NAU8821_MICDET_EN);
1005 if (nau8821_is_jack_inserted(regmap)) {
1006
1007 cancel_work_sync(&nau8821->jdet_work);
1008 schedule_work(&nau8821->jdet_work);
1009
1010 regmap_update_bits(regmap,
1011 NAU8821_R12_INTERRUPT_DIS_CTRL,
1012 NAU8821_IRQ_INSERT_DIS,
1013 NAU8821_IRQ_INSERT_DIS);
1014 regmap_update_bits(regmap,
1015 NAU8821_R0F_INTERRUPT_MASK,
1016 NAU8821_IRQ_INSERT_EN,
1017 NAU8821_IRQ_INSERT_EN);
1018 nau8821_setup_inserted_irq(nau8821);
1019 } else {
1020 dev_warn(nau8821->dev,
1021 "Inserted IRQ fired but not connected\n");
1022 nau8821_eject_jack(nau8821);
1023 }
1024 }
1025
1026 if (!clear_irq)
1027 clear_irq = active_irq;
1028
1029 regmap_write(regmap, NAU8821_R11_INT_CLR_KEY_STATUS, clear_irq);
1030
1031 if (event_mask)
1032 snd_soc_jack_report(nau8821->jack, event, event_mask);
1033
1034 return IRQ_HANDLED;
1035}
1036
1037static const struct regmap_config nau8821_regmap_config = {
1038 .val_bits = NAU8821_REG_DATA_LEN,
1039 .reg_bits = NAU8821_REG_ADDR_LEN,
1040
1041 .max_register = NAU8821_REG_MAX,
1042 .readable_reg = nau8821_readable_reg,
1043 .writeable_reg = nau8821_writeable_reg,
1044 .volatile_reg = nau8821_volatile_reg,
1045
1046 .cache_type = REGCACHE_RBTREE,
1047 .reg_defaults = nau8821_reg_defaults,
1048 .num_reg_defaults = ARRAY_SIZE(nau8821_reg_defaults),
1049};
1050
1051static int nau8821_component_probe(struct snd_soc_component *component)
1052{
1053 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
1054 struct snd_soc_dapm_context *dapm =
1055 snd_soc_component_get_dapm(component);
1056
1057 nau8821->dapm = dapm;
1058
1059 return 0;
1060}
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072static int nau8821_calc_fll_param(unsigned int fll_in,
1073 unsigned int fs, struct nau8821_fll *fll_param)
1074{
1075 u64 fvco, fvco_max;
1076 unsigned int fref, i, fvco_sel;
1077
1078
1079
1080
1081
1082 for (i = 0; i < ARRAY_SIZE(fll_pre_scalar); i++) {
1083 fref = fll_in >> fll_pre_scalar[i].param;
1084 if (fref <= NAU_FREF_MAX)
1085 break;
1086 }
1087 if (i == ARRAY_SIZE(fll_pre_scalar))
1088 return -EINVAL;
1089 fll_param->clk_ref_div = fll_pre_scalar[i].val;
1090
1091
1092 for (i = 0; i < ARRAY_SIZE(fll_ratio); i++) {
1093 if (fref >= fll_ratio[i].param)
1094 break;
1095 }
1096 if (i == ARRAY_SIZE(fll_ratio))
1097 return -EINVAL;
1098 fll_param->ratio = fll_ratio[i].val;
1099
1100
1101
1102
1103
1104
1105 fvco_max = 0;
1106 fvco_sel = ARRAY_SIZE(mclk_src_scaling);
1107 for (i = 0; i < ARRAY_SIZE(mclk_src_scaling); i++) {
1108 fvco = 256ULL * fs * 2 * mclk_src_scaling[i].param;
1109 if (fvco > NAU_FVCO_MIN && fvco < NAU_FVCO_MAX &&
1110 fvco_max < fvco) {
1111 fvco_max = fvco;
1112 fvco_sel = i;
1113 }
1114 }
1115 if (ARRAY_SIZE(mclk_src_scaling) == fvco_sel)
1116 return -EINVAL;
1117 fll_param->mclk_src = mclk_src_scaling[fvco_sel].val;
1118
1119
1120
1121
1122 fvco = div_u64(fvco_max << 24, fref * fll_param->ratio);
1123 fll_param->fll_int = (fvco >> 24) & 0x3ff;
1124 fll_param->fll_frac = fvco & 0xffffff;
1125
1126 return 0;
1127}
1128
1129static void nau8821_fll_apply(struct nau8821 *nau8821,
1130 struct nau8821_fll *fll_param)
1131{
1132 struct regmap *regmap = nau8821->regmap;
1133
1134 regmap_update_bits(regmap, NAU8821_R03_CLK_DIVIDER,
1135 NAU8821_CLK_SRC_MASK | NAU8821_CLK_MCLK_SRC_MASK,
1136 NAU8821_CLK_SRC_MCLK | fll_param->mclk_src);
1137
1138 regmap_update_bits(regmap, NAU8821_R04_FLL1,
1139 NAU8821_FLL_RATIO_MASK | NAU8821_ICTRL_LATCH_MASK,
1140 fll_param->ratio | (0x6 << NAU8821_ICTRL_LATCH_SFT));
1141
1142 regmap_write(regmap, NAU8821_R0A_FLL7,
1143 (fll_param->fll_frac >> 16) & 0xff);
1144 regmap_write(regmap, NAU8821_R0B_FLL8, fll_param->fll_frac & 0xffff);
1145
1146 regmap_update_bits(regmap, NAU8821_R06_FLL3,
1147 NAU8821_FLL_INTEGER_MASK, fll_param->fll_int);
1148
1149 regmap_update_bits(regmap, NAU8821_R07_FLL4,
1150 NAU8821_HIGHBW_EN | NAU8821_FLL_REF_DIV_MASK,
1151 NAU8821_HIGHBW_EN |
1152 (fll_param->clk_ref_div << NAU8821_FLL_REF_DIV_SFT));
1153
1154 regmap_update_bits(regmap, NAU8821_R08_FLL5,
1155 NAU8821_FLL_CLK_SW_MASK, NAU8821_FLL_CLK_SW_REF);
1156
1157 regmap_update_bits(regmap,
1158 NAU8821_R09_FLL6, NAU8821_DCO_EN, 0);
1159 if (fll_param->fll_frac) {
1160
1161 regmap_update_bits(regmap, NAU8821_R08_FLL5,
1162 NAU8821_FLL_PDB_DAC_EN | NAU8821_FLL_LOOP_FTR_EN |
1163 NAU8821_FLL_FTR_SW_MASK,
1164 NAU8821_FLL_PDB_DAC_EN | NAU8821_FLL_LOOP_FTR_EN |
1165 NAU8821_FLL_FTR_SW_FILTER);
1166 regmap_update_bits(regmap, NAU8821_R09_FLL6,
1167 NAU8821_SDM_EN | NAU8821_CUTOFF500,
1168 NAU8821_SDM_EN | NAU8821_CUTOFF500);
1169 } else {
1170
1171 regmap_update_bits(regmap, NAU8821_R08_FLL5,
1172 NAU8821_FLL_PDB_DAC_EN | NAU8821_FLL_LOOP_FTR_EN |
1173 NAU8821_FLL_FTR_SW_MASK, NAU8821_FLL_FTR_SW_ACCU);
1174 regmap_update_bits(regmap, NAU8821_R09_FLL6,
1175 NAU8821_SDM_EN | NAU8821_CUTOFF500, 0);
1176 }
1177}
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192static int nau8821_set_fll(struct snd_soc_component *component,
1193 int pll_id, int source, unsigned int freq_in, unsigned int freq_out)
1194{
1195 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
1196 struct nau8821_fll fll_set_param, *fll_param = &fll_set_param;
1197 int ret, fs;
1198
1199 fs = freq_out >> 8;
1200 ret = nau8821_calc_fll_param(freq_in, fs, fll_param);
1201 if (ret) {
1202 dev_err(nau8821->dev,
1203 "Unsupported input clock %d to output clock %d\n",
1204 freq_in, freq_out);
1205 return ret;
1206 }
1207 dev_dbg(nau8821->dev,
1208 "mclk_src=%x ratio=%x fll_frac=%x fll_int=%x clk_ref_div=%x\n",
1209 fll_param->mclk_src, fll_param->ratio, fll_param->fll_frac,
1210 fll_param->fll_int, fll_param->clk_ref_div);
1211
1212 nau8821_fll_apply(nau8821, fll_param);
1213 mdelay(2);
1214 regmap_update_bits(nau8821->regmap, NAU8821_R03_CLK_DIVIDER,
1215 NAU8821_CLK_SRC_MASK, NAU8821_CLK_SRC_VCO);
1216
1217 return 0;
1218}
1219
1220static void nau8821_configure_mclk_as_sysclk(struct regmap *regmap)
1221{
1222 regmap_update_bits(regmap, NAU8821_R03_CLK_DIVIDER,
1223 NAU8821_CLK_SRC_MASK, NAU8821_CLK_SRC_MCLK);
1224 regmap_update_bits(regmap, NAU8821_R09_FLL6,
1225 NAU8821_DCO_EN, 0);
1226
1227 regmap_update_bits(regmap, NAU8821_R04_FLL1,
1228 NAU8821_ICTRL_LATCH_MASK, 0);
1229}
1230
1231static int nau8821_configure_sysclk(struct nau8821 *nau8821,
1232 int clk_id, unsigned int freq)
1233{
1234 struct regmap *regmap = nau8821->regmap;
1235
1236 switch (clk_id) {
1237 case NAU8821_CLK_DIS:
1238
1239 nau8821_configure_mclk_as_sysclk(regmap);
1240 break;
1241 case NAU8821_CLK_MCLK:
1242 nau8821_configure_mclk_as_sysclk(regmap);
1243
1244 regmap_update_bits(regmap, NAU8821_R03_CLK_DIVIDER,
1245 NAU8821_CLK_MCLK_SRC_MASK, 0);
1246 break;
1247 case NAU8821_CLK_INTERNAL:
1248 if (nau8821_is_jack_inserted(regmap)) {
1249 regmap_update_bits(regmap, NAU8821_R09_FLL6,
1250 NAU8821_DCO_EN, NAU8821_DCO_EN);
1251 regmap_update_bits(regmap, NAU8821_R03_CLK_DIVIDER,
1252 NAU8821_CLK_SRC_MASK, NAU8821_CLK_SRC_VCO);
1253
1254
1255
1256 regmap_update_bits(regmap, NAU8821_R03_CLK_DIVIDER,
1257 NAU8821_CLK_MCLK_SRC_MASK, 0xf);
1258 regmap_update_bits(regmap, NAU8821_R04_FLL1,
1259 NAU8821_ICTRL_LATCH_MASK |
1260 NAU8821_FLL_RATIO_MASK, 0x10);
1261 regmap_update_bits(regmap, NAU8821_R09_FLL6,
1262 NAU8821_SDM_EN, NAU8821_SDM_EN);
1263 }
1264 break;
1265 case NAU8821_CLK_FLL_MCLK:
1266
1267
1268
1269
1270 regmap_update_bits(regmap, NAU8821_R06_FLL3,
1271 NAU8821_FLL_CLK_SRC_MASK | NAU8821_GAIN_ERR_MASK,
1272 NAU8821_FLL_CLK_SRC_MCLK | 0);
1273 break;
1274 case NAU8821_CLK_FLL_BLK:
1275
1276
1277
1278
1279
1280
1281 regmap_update_bits(regmap, NAU8821_R06_FLL3,
1282 NAU8821_FLL_CLK_SRC_MASK | NAU8821_GAIN_ERR_MASK,
1283 NAU8821_FLL_CLK_SRC_BLK |
1284 (0xf << NAU8821_GAIN_ERR_SFT));
1285 break;
1286 case NAU8821_CLK_FLL_FS:
1287
1288
1289
1290
1291
1292
1293 regmap_update_bits(regmap, NAU8821_R06_FLL3,
1294 NAU8821_FLL_CLK_SRC_MASK | NAU8821_GAIN_ERR_MASK,
1295 NAU8821_FLL_CLK_SRC_FS |
1296 (0xf << NAU8821_GAIN_ERR_SFT));
1297 break;
1298 default:
1299 dev_err(nau8821->dev, "Invalid clock id (%d)\n", clk_id);
1300 return -EINVAL;
1301 }
1302 nau8821->clk_id = clk_id;
1303 dev_dbg(nau8821->dev, "Sysclk is %dHz and clock id is %d\n", freq,
1304 nau8821->clk_id);
1305
1306 return 0;
1307}
1308
1309static int nau8821_set_sysclk(struct snd_soc_component *component, int clk_id,
1310 int source, unsigned int freq, int dir)
1311{
1312 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
1313
1314 return nau8821_configure_sysclk(nau8821, clk_id, freq);
1315}
1316
1317static int nau8821_resume_setup(struct nau8821 *nau8821)
1318{
1319 struct regmap *regmap = nau8821->regmap;
1320
1321
1322 nau8821_configure_sysclk(nau8821, NAU8821_CLK_DIS, 0);
1323 if (nau8821->irq) {
1324
1325 nau8821_int_status_clear_all(regmap);
1326
1327
1328
1329
1330 regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK,
1331 NAU8821_IRQ_EJECT_EN | NAU8821_IRQ_INSERT_EN, 0);
1332 regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL,
1333 NAU8821_JACK_DET_DB_BYPASS,
1334 NAU8821_JACK_DET_DB_BYPASS);
1335 regmap_update_bits(regmap, NAU8821_R12_INTERRUPT_DIS_CTRL,
1336 NAU8821_IRQ_INSERT_DIS | NAU8821_IRQ_EJECT_DIS, 0);
1337 }
1338
1339 return 0;
1340}
1341
1342static int nau8821_set_bias_level(struct snd_soc_component *component,
1343 enum snd_soc_bias_level level)
1344{
1345 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
1346 struct regmap *regmap = nau8821->regmap;
1347
1348 switch (level) {
1349 case SND_SOC_BIAS_ON:
1350 break;
1351
1352 case SND_SOC_BIAS_PREPARE:
1353 break;
1354
1355 case SND_SOC_BIAS_STANDBY:
1356
1357 if (snd_soc_component_get_bias_level(component) ==
1358 SND_SOC_BIAS_OFF)
1359 nau8821_resume_setup(nau8821);
1360 break;
1361
1362 case SND_SOC_BIAS_OFF:
1363
1364 regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL,
1365 NAU8821_SPKR_DWN1R | NAU8821_SPKR_DWN1L, 0);
1366 if (nau8821->irq) {
1367
1368
1369
1370 regmap_update_bits(regmap, NAU8821_R74_MIC_BIAS,
1371 NAU8821_MICBIAS_JKR2, 0);
1372
1373
1374
1375
1376 regmap_write(regmap,
1377 NAU8821_R12_INTERRUPT_DIS_CTRL, 0xffff);
1378 regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK,
1379 NAU8821_IRQ_EJECT_EN | NAU8821_IRQ_INSERT_EN,
1380 NAU8821_IRQ_EJECT_EN | NAU8821_IRQ_INSERT_EN);
1381 }
1382 break;
1383 default:
1384 break;
1385 }
1386
1387 return 0;
1388}
1389
1390static int __maybe_unused nau8821_suspend(struct snd_soc_component *component)
1391{
1392 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
1393
1394 if (nau8821->irq)
1395 disable_irq(nau8821->irq);
1396 snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF);
1397
1398 snd_soc_component_disable_pin(component, "MICBIAS");
1399 snd_soc_dapm_sync(nau8821->dapm);
1400 regcache_cache_only(nau8821->regmap, true);
1401 regcache_mark_dirty(nau8821->regmap);
1402
1403 return 0;
1404}
1405
1406static int __maybe_unused nau8821_resume(struct snd_soc_component *component)
1407{
1408 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
1409
1410 regcache_cache_only(nau8821->regmap, false);
1411 regcache_sync(nau8821->regmap);
1412 if (nau8821->irq)
1413 enable_irq(nau8821->irq);
1414
1415 return 0;
1416}
1417
1418static const struct snd_soc_component_driver nau8821_component_driver = {
1419 .probe = nau8821_component_probe,
1420 .set_sysclk = nau8821_set_sysclk,
1421 .set_pll = nau8821_set_fll,
1422 .set_bias_level = nau8821_set_bias_level,
1423 .suspend = nau8821_suspend,
1424 .resume = nau8821_resume,
1425 .controls = nau8821_controls,
1426 .num_controls = ARRAY_SIZE(nau8821_controls),
1427 .dapm_widgets = nau8821_dapm_widgets,
1428 .num_dapm_widgets = ARRAY_SIZE(nau8821_dapm_widgets),
1429 .dapm_routes = nau8821_dapm_routes,
1430 .num_dapm_routes = ARRAY_SIZE(nau8821_dapm_routes),
1431 .suspend_bias_off = 1,
1432 .non_legacy_dai_naming = 1,
1433 .idle_bias_on = 1,
1434 .use_pmdown_time = 1,
1435 .endianness = 1,
1436};
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448int nau8821_enable_jack_detect(struct snd_soc_component *component,
1449 struct snd_soc_jack *jack)
1450{
1451 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
1452 int ret;
1453
1454 nau8821->jack = jack;
1455
1456 INIT_WORK(&nau8821->jdet_work, nau8821_jdet_work);
1457 ret = devm_request_threaded_irq(nau8821->dev, nau8821->irq, NULL,
1458 nau8821_interrupt, IRQF_TRIGGER_LOW | IRQF_ONESHOT,
1459 "nau8821", nau8821);
1460 if (ret) {
1461 dev_err(nau8821->dev, "Cannot request irq %d (%d)\n",
1462 nau8821->irq, ret);
1463 return ret;
1464 }
1465
1466 return ret;
1467}
1468EXPORT_SYMBOL_GPL(nau8821_enable_jack_detect);
1469
1470static void nau8821_reset_chip(struct regmap *regmap)
1471{
1472 regmap_write(regmap, NAU8821_R00_RESET, 0xffff);
1473 regmap_write(regmap, NAU8821_R00_RESET, 0xffff);
1474}
1475
1476static void nau8821_print_device_properties(struct nau8821 *nau8821)
1477{
1478 struct device *dev = nau8821->dev;
1479
1480 dev_dbg(dev, "jkdet-enable: %d\n", nau8821->jkdet_enable);
1481 dev_dbg(dev, "jkdet-pull-enable: %d\n", nau8821->jkdet_pull_enable);
1482 dev_dbg(dev, "jkdet-pull-up: %d\n", nau8821->jkdet_pull_up);
1483 dev_dbg(dev, "jkdet-polarity: %d\n", nau8821->jkdet_polarity);
1484 dev_dbg(dev, "micbias-voltage: %d\n", nau8821->micbias_voltage);
1485 dev_dbg(dev, "vref-impedance: %d\n", nau8821->vref_impedance);
1486 dev_dbg(dev, "jack-insert-debounce: %d\n",
1487 nau8821->jack_insert_debounce);
1488 dev_dbg(dev, "jack-eject-debounce: %d\n",
1489 nau8821->jack_eject_debounce);
1490 dev_dbg(dev, "dmic-clk-threshold: %d\n",
1491 nau8821->dmic_clk_threshold);
1492}
1493
1494static int nau8821_read_device_properties(struct device *dev,
1495 struct nau8821 *nau8821)
1496{
1497 int ret;
1498
1499 nau8821->jkdet_enable = device_property_read_bool(dev,
1500 "nuvoton,jkdet-enable");
1501 nau8821->jkdet_pull_enable = device_property_read_bool(dev,
1502 "nuvoton,jkdet-pull-enable");
1503 nau8821->jkdet_pull_up = device_property_read_bool(dev,
1504 "nuvoton,jkdet-pull-up");
1505 ret = device_property_read_u32(dev, "nuvoton,jkdet-polarity",
1506 &nau8821->jkdet_polarity);
1507 if (ret)
1508 nau8821->jkdet_polarity = 1;
1509 ret = device_property_read_u32(dev, "nuvoton,micbias-voltage",
1510 &nau8821->micbias_voltage);
1511 if (ret)
1512 nau8821->micbias_voltage = 6;
1513 ret = device_property_read_u32(dev, "nuvoton,vref-impedance",
1514 &nau8821->vref_impedance);
1515 if (ret)
1516 nau8821->vref_impedance = 2;
1517 ret = device_property_read_u32(dev, "nuvoton,jack-insert-debounce",
1518 &nau8821->jack_insert_debounce);
1519 if (ret)
1520 nau8821->jack_insert_debounce = 7;
1521 ret = device_property_read_u32(dev, "nuvoton,jack-eject-debounce",
1522 &nau8821->jack_eject_debounce);
1523 if (ret)
1524 nau8821->jack_eject_debounce = 0;
1525 ret = device_property_read_u32(dev, "nuvoton,dmic-clk-threshold",
1526 &nau8821->dmic_clk_threshold);
1527 if (ret)
1528 nau8821->dmic_clk_threshold = 3072000;
1529
1530 return 0;
1531}
1532
1533static void nau8821_init_regs(struct nau8821 *nau8821)
1534{
1535 struct regmap *regmap = nau8821->regmap;
1536
1537
1538 regmap_update_bits(regmap, NAU8821_R66_BIAS_ADJ,
1539 NAU8821_BIAS_VMID, NAU8821_BIAS_VMID);
1540 regmap_update_bits(regmap, NAU8821_R76_BOOST,
1541 NAU8821_GLOBAL_BIAS_EN, NAU8821_GLOBAL_BIAS_EN);
1542
1543
1544
1545
1546
1547 regmap_update_bits(regmap, NAU8821_R66_BIAS_ADJ,
1548 NAU8821_BIAS_VMID_SEL_MASK | NAU8821_BIAS_TESTDAC_EN,
1549 (nau8821->vref_impedance << NAU8821_BIAS_VMID_SEL_SFT) |
1550 NAU8821_BIAS_TESTDAC_EN);
1551
1552 regmap_update_bits(regmap, NAU8821_R1E_LEFT_TIME_SLOT,
1553 NAU8821_DIS_FS_SHORT_DET, NAU8821_DIS_FS_SHORT_DET);
1554
1555 regmap_update_bits(regmap, NAU8821_R76_BOOST,
1556 NAU8821_PRECHARGE_DIS | NAU8821_HP_BOOST_DIS |
1557 NAU8821_HP_BOOST_G_DIS | NAU8821_SHORT_SHUTDOWN_EN,
1558 NAU8821_PRECHARGE_DIS | NAU8821_HP_BOOST_DIS |
1559 NAU8821_HP_BOOST_G_DIS | NAU8821_SHORT_SHUTDOWN_EN);
1560
1561 regmap_update_bits(regmap, NAU8821_R4B_CLASSG_CTRL,
1562 NAU8821_CLASSG_TIMER_MASK,
1563 0x20 << NAU8821_CLASSG_TIMER_SFT);
1564
1565 regmap_update_bits(regmap, NAU8821_R6A_ANALOG_CONTROL_2,
1566 NAU8821_HP_NON_CLASSG_CURRENT_2xADJ |
1567 NAU8821_DAC_CAPACITOR_MSB | NAU8821_DAC_CAPACITOR_LSB,
1568 NAU8821_HP_NON_CLASSG_CURRENT_2xADJ |
1569 NAU8821_DAC_CAPACITOR_MSB | NAU8821_DAC_CAPACITOR_LSB);
1570
1571 regmap_update_bits(regmap, NAU8821_R80_CHARGE_PUMP,
1572 NAU8821_POWER_DOWN_DACR | NAU8821_POWER_DOWN_DACL, 0);
1573
1574 regmap_update_bits(regmap, NAU8821_R73_RDAC,
1575 NAU8821_DAC_CLK_DELAY_MASK | NAU8821_DAC_VREF_MASK,
1576 (0x2 << NAU8821_DAC_CLK_DELAY_SFT) |
1577 (0x3 << NAU8821_DAC_VREF_SFT));
1578
1579 regmap_update_bits(regmap, NAU8821_R74_MIC_BIAS,
1580 NAU8821_MICBIAS_VOLTAGE_MASK, nau8821->micbias_voltage);
1581
1582
1583
1584 regmap_update_bits(regmap, NAU8821_R2B_ADC_RATE,
1585 NAU8821_ADC_SYNC_DOWN_MASK, NAU8821_ADC_SYNC_DOWN_64);
1586 regmap_update_bits(regmap, NAU8821_R2C_DAC_CTRL1,
1587 NAU8821_DAC_OVERSAMPLE_MASK, NAU8821_DAC_OVERSAMPLE_64);
1588}
1589
1590static int nau8821_setup_irq(struct nau8821 *nau8821)
1591{
1592 struct regmap *regmap = nau8821->regmap;
1593
1594
1595 regmap_update_bits(regmap, NAU8821_R1A_GPIO12_CTRL,
1596 NAU8821_JKDET_OUTPUT_EN,
1597 nau8821->jkdet_enable ? 0 : NAU8821_JKDET_OUTPUT_EN);
1598 regmap_update_bits(regmap, NAU8821_R1A_GPIO12_CTRL,
1599 NAU8821_JKDET_PULL_EN,
1600 nau8821->jkdet_pull_enable ? 0 : NAU8821_JKDET_PULL_EN);
1601 regmap_update_bits(regmap, NAU8821_R1A_GPIO12_CTRL,
1602 NAU8821_JKDET_PULL_UP,
1603 nau8821->jkdet_pull_up ? NAU8821_JKDET_PULL_UP : 0);
1604 regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL,
1605 NAU8821_JACK_POLARITY,
1606
1607 nau8821->jkdet_polarity ? 0 : NAU8821_JACK_POLARITY);
1608 regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL,
1609 NAU8821_JACK_INSERT_DEBOUNCE_MASK,
1610 nau8821->jack_insert_debounce <<
1611 NAU8821_JACK_INSERT_DEBOUNCE_SFT);
1612 regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL,
1613 NAU8821_JACK_EJECT_DEBOUNCE_MASK,
1614 nau8821->jack_eject_debounce <<
1615 NAU8821_JACK_EJECT_DEBOUNCE_SFT);
1616
1617 regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK,
1618 NAU8821_IRQ_PIN_PULL_UP | NAU8821_IRQ_PIN_PULL_EN |
1619 NAU8821_IRQ_OUTPUT_EN, NAU8821_IRQ_PIN_PULL_UP |
1620 NAU8821_IRQ_PIN_PULL_EN | NAU8821_IRQ_OUTPUT_EN);
1621
1622
1623 regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK, 0x3f5, 0x3f5);
1624
1625 return 0;
1626}
1627
1628static int nau8821_i2c_probe(struct i2c_client *i2c,
1629 const struct i2c_device_id *id)
1630{
1631 struct device *dev = &i2c->dev;
1632 struct nau8821 *nau8821 = dev_get_platdata(&i2c->dev);
1633 int ret, value;
1634
1635 if (!nau8821) {
1636 nau8821 = devm_kzalloc(dev, sizeof(*nau8821), GFP_KERNEL);
1637 if (!nau8821)
1638 return -ENOMEM;
1639 nau8821_read_device_properties(dev, nau8821);
1640 }
1641 i2c_set_clientdata(i2c, nau8821);
1642
1643 nau8821->regmap = devm_regmap_init_i2c(i2c, &nau8821_regmap_config);
1644 if (IS_ERR(nau8821->regmap))
1645 return PTR_ERR(nau8821->regmap);
1646
1647 nau8821->dev = dev;
1648 nau8821->irq = i2c->irq;
1649 nau8821_print_device_properties(nau8821);
1650
1651 nau8821_reset_chip(nau8821->regmap);
1652 ret = regmap_read(nau8821->regmap, NAU8821_R58_I2C_DEVICE_ID, &value);
1653 if (ret) {
1654 dev_err(dev, "Failed to read device id (%d)\n", ret);
1655 return ret;
1656 }
1657 nau8821_init_regs(nau8821);
1658
1659 if (i2c->irq)
1660 nau8821_setup_irq(nau8821);
1661
1662 ret = devm_snd_soc_register_component(&i2c->dev,
1663 &nau8821_component_driver, &nau8821_dai, 1);
1664
1665 return ret;
1666}
1667
1668static int nau8821_i2c_remove(struct i2c_client *i2c_client)
1669{
1670 struct nau8821 *nau8821 = i2c_get_clientdata(i2c_client);
1671
1672 devm_free_irq(nau8821->dev, nau8821->irq, nau8821);
1673
1674 return 0;
1675}
1676
1677static const struct i2c_device_id nau8821_i2c_ids[] = {
1678 { "nau8821", 0 },
1679 { }
1680};
1681MODULE_DEVICE_TABLE(i2c, nau8821_i2c_ids);
1682
1683#ifdef CONFIG_OF
1684static const struct of_device_id nau8821_of_ids[] = {
1685 { .compatible = "nuvoton,nau8821", },
1686 {}
1687};
1688MODULE_DEVICE_TABLE(of, nau8821_of_ids);
1689#endif
1690
1691#ifdef CONFIG_ACPI
1692static const struct acpi_device_id nau8821_acpi_match[] = {
1693 { "NVTN2020", 0 },
1694 {},
1695};
1696MODULE_DEVICE_TABLE(acpi, nau8821_acpi_match);
1697#endif
1698
1699static struct i2c_driver nau8821_driver = {
1700 .driver = {
1701 .name = "nau8821",
1702 .of_match_table = of_match_ptr(nau8821_of_ids),
1703 .acpi_match_table = ACPI_PTR(nau8821_acpi_match),
1704 },
1705 .probe = nau8821_i2c_probe,
1706 .remove = nau8821_i2c_remove,
1707 .id_table = nau8821_i2c_ids,
1708};
1709module_i2c_driver(nau8821_driver);
1710
1711MODULE_DESCRIPTION("ASoC nau8821 driver");
1712MODULE_AUTHOR("John Hsu <kchsu0@nuvoton.com>");
1713MODULE_AUTHOR("Seven Lee <wtli@nuvoton.com>");
1714MODULE_LICENSE("GPL");
1715
