1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * tegra210_admaif.h - Tegra ADMAIF registers 4 * 5 * Copyright (c) 2020 NVIDIA CORPORATION. All rights reserved. 6 * 7 */ 8 9#ifndef __TEGRA_ADMAIF_H__ 10#define __TEGRA_ADMAIF_H__ 11 12#define TEGRA_ADMAIF_CHANNEL_REG_STRIDE 0x40 13/* Tegra210 specific */ 14#define TEGRA210_ADMAIF_LAST_REG 0x75f 15#define TEGRA210_ADMAIF_CHANNEL_COUNT 10 16#define TEGRA210_ADMAIF_RX_BASE 0x0 17#define TEGRA210_ADMAIF_TX_BASE 0x300 18#define TEGRA210_ADMAIF_GLOBAL_BASE 0x700 19/* Tegra186 specific */ 20#define TEGRA186_ADMAIF_LAST_REG 0xd5f 21#define TEGRA186_ADMAIF_CHANNEL_COUNT 20 22#define TEGRA186_ADMAIF_RX_BASE 0x0 23#define TEGRA186_ADMAIF_TX_BASE 0x500 24#define TEGRA186_ADMAIF_GLOBAL_BASE 0xd00 25/* Global registers */ 26#define TEGRA_ADMAIF_GLOBAL_ENABLE 0x0 27#define TEGRA_ADMAIF_GLOBAL_CG_0 0x8 28#define TEGRA_ADMAIF_GLOBAL_STATUS 0x10 29#define TEGRA_ADMAIF_GLOBAL_RX_ENABLE_STATUS 0x20 30#define TEGRA_ADMAIF_GLOBAL_TX_ENABLE_STATUS 0x24 31/* RX channel registers */ 32#define TEGRA_ADMAIF_RX_ENABLE 0x0 33#define TEGRA_ADMAIF_RX_SOFT_RESET 0x4 34#define TEGRA_ADMAIF_RX_STATUS 0xc 35#define TEGRA_ADMAIF_RX_INT_STATUS 0x10 36#define TEGRA_ADMAIF_RX_INT_MASK 0x14 37#define TEGRA_ADMAIF_RX_INT_SET 0x18 38#define TEGRA_ADMAIF_RX_INT_CLEAR 0x1c 39#define TEGRA_ADMAIF_CH_ACIF_RX_CTRL 0x20 40#define TEGRA_ADMAIF_RX_FIFO_CTRL 0x28 41#define TEGRA_ADMAIF_RX_FIFO_READ 0x2c 42/* TX channel registers */ 43#define TEGRA_ADMAIF_TX_ENABLE 0x0 44#define TEGRA_ADMAIF_TX_SOFT_RESET 0x4 45#define TEGRA_ADMAIF_TX_STATUS 0xc 46#define TEGRA_ADMAIF_TX_INT_STATUS 0x10 47#define TEGRA_ADMAIF_TX_INT_MASK 0x14 48#define TEGRA_ADMAIF_TX_INT_SET 0x18 49#define TEGRA_ADMAIF_TX_INT_CLEAR 0x1c 50#define TEGRA_ADMAIF_CH_ACIF_TX_CTRL 0x20 51#define TEGRA_ADMAIF_TX_FIFO_CTRL 0x28 52#define TEGRA_ADMAIF_TX_FIFO_WRITE 0x2c 53/* Bit fields */ 54#define PACK8_EN_SHIFT 31 55#define PACK8_EN_MASK BIT(PACK8_EN_SHIFT) 56#define PACK8_EN BIT(PACK8_EN_SHIFT) 57#define PACK16_EN_SHIFT 30 58#define PACK16_EN_MASK BIT(PACK16_EN_SHIFT) 59#define PACK16_EN BIT(PACK16_EN_SHIFT) 60#define TX_ENABLE_SHIFT 0 61#define TX_ENABLE_MASK BIT(TX_ENABLE_SHIFT) 62#define TX_ENABLE BIT(TX_ENABLE_SHIFT) 63#define RX_ENABLE_SHIFT 0 64#define RX_ENABLE_MASK BIT(RX_ENABLE_SHIFT) 65#define RX_ENABLE BIT(RX_ENABLE_SHIFT) 66#define SW_RESET_MASK 1 67#define SW_RESET 1 68/* Default values - Tegra210 */ 69#define TEGRA210_ADMAIF_RX1_FIFO_CTRL_REG_DEFAULT 0x00000300 70#define TEGRA210_ADMAIF_RX2_FIFO_CTRL_REG_DEFAULT 0x00000304 71#define TEGRA210_ADMAIF_RX3_FIFO_CTRL_REG_DEFAULT 0x00000208 72#define TEGRA210_ADMAIF_RX4_FIFO_CTRL_REG_DEFAULT 0x0000020b 73#define TEGRA210_ADMAIF_RX5_FIFO_CTRL_REG_DEFAULT 0x0000020e 74#define TEGRA210_ADMAIF_RX6_FIFO_CTRL_REG_DEFAULT 0x00000211 75#define TEGRA210_ADMAIF_RX7_FIFO_CTRL_REG_DEFAULT 0x00000214 76#define TEGRA210_ADMAIF_RX8_FIFO_CTRL_REG_DEFAULT 0x00000217 77#define TEGRA210_ADMAIF_RX9_FIFO_CTRL_REG_DEFAULT 0x0000021a 78#define TEGRA210_ADMAIF_RX10_FIFO_CTRL_REG_DEFAULT 0x0000021d 79#define TEGRA210_ADMAIF_TX1_FIFO_CTRL_REG_DEFAULT 0x02000300 80#define TEGRA210_ADMAIF_TX2_FIFO_CTRL_REG_DEFAULT 0x02000304 81#define TEGRA210_ADMAIF_TX3_FIFO_CTRL_REG_DEFAULT 0x01800208 82#define TEGRA210_ADMAIF_TX4_FIFO_CTRL_REG_DEFAULT 0x0180020b 83#define TEGRA210_ADMAIF_TX5_FIFO_CTRL_REG_DEFAULT 0x0180020e 84#define TEGRA210_ADMAIF_TX6_FIFO_CTRL_REG_DEFAULT 0x01800211 85#define TEGRA210_ADMAIF_TX7_FIFO_CTRL_REG_DEFAULT 0x01800214 86#define TEGRA210_ADMAIF_TX8_FIFO_CTRL_REG_DEFAULT 0x01800217 87#define TEGRA210_ADMAIF_TX9_FIFO_CTRL_REG_DEFAULT 0x0180021a 88#define TEGRA210_ADMAIF_TX10_FIFO_CTRL_REG_DEFAULT 0x0180021d 89/* Default values - Tegra186 */ 90#define TEGRA186_ADMAIF_RX1_FIFO_CTRL_REG_DEFAULT 0x00000300 91#define TEGRA186_ADMAIF_RX2_FIFO_CTRL_REG_DEFAULT 0x00000304 92#define TEGRA186_ADMAIF_RX3_FIFO_CTRL_REG_DEFAULT 0x00000308 93#define TEGRA186_ADMAIF_RX4_FIFO_CTRL_REG_DEFAULT 0x0000030c 94#define TEGRA186_ADMAIF_RX5_FIFO_CTRL_REG_DEFAULT 0x00000210 95#define TEGRA186_ADMAIF_RX6_FIFO_CTRL_REG_DEFAULT 0x00000213 96#define TEGRA186_ADMAIF_RX7_FIFO_CTRL_REG_DEFAULT 0x00000216 97#define TEGRA186_ADMAIF_RX8_FIFO_CTRL_REG_DEFAULT 0x00000219 98#define TEGRA186_ADMAIF_RX9_FIFO_CTRL_REG_DEFAULT 0x0000021c 99#define TEGRA186_ADMAIF_RX10_FIFO_CTRL_REG_DEFAULT 0x0000021f 100#define TEGRA186_ADMAIF_RX11_FIFO_CTRL_REG_DEFAULT 0x00000222 101#define TEGRA186_ADMAIF_RX12_FIFO_CTRL_REG_DEFAULT 0x00000225 102#define TEGRA186_ADMAIF_RX13_FIFO_CTRL_REG_DEFAULT 0x00000228 103#define TEGRA186_ADMAIF_RX14_FIFO_CTRL_REG_DEFAULT 0x0000022b 104#define TEGRA186_ADMAIF_RX15_FIFO_CTRL_REG_DEFAULT 0x0000022e 105#define TEGRA186_ADMAIF_RX16_FIFO_CTRL_REG_DEFAULT 0x00000231 106#define TEGRA186_ADMAIF_RX17_FIFO_CTRL_REG_DEFAULT 0x00000234 107#define TEGRA186_ADMAIF_RX18_FIFO_CTRL_REG_DEFAULT 0x00000237 108#define TEGRA186_ADMAIF_RX19_FIFO_CTRL_REG_DEFAULT 0x0000023a 109#define TEGRA186_ADMAIF_RX20_FIFO_CTRL_REG_DEFAULT 0x0000023d 110#define TEGRA186_ADMAIF_TX1_FIFO_CTRL_REG_DEFAULT 0x02000300 111#define TEGRA186_ADMAIF_TX2_FIFO_CTRL_REG_DEFAULT 0x02000304 112#define TEGRA186_ADMAIF_TX3_FIFO_CTRL_REG_DEFAULT 0x02000308 113#define TEGRA186_ADMAIF_TX4_FIFO_CTRL_REG_DEFAULT 0x0200030c 114#define TEGRA186_ADMAIF_TX5_FIFO_CTRL_REG_DEFAULT 0x01800210 115#define TEGRA186_ADMAIF_TX6_FIFO_CTRL_REG_DEFAULT 0x01800213 116#define TEGRA186_ADMAIF_TX7_FIFO_CTRL_REG_DEFAULT 0x01800216 117#define TEGRA186_ADMAIF_TX8_FIFO_CTRL_REG_DEFAULT 0x01800219 118#define TEGRA186_ADMAIF_TX9_FIFO_CTRL_REG_DEFAULT 0x0180021c 119#define TEGRA186_ADMAIF_TX10_FIFO_CTRL_REG_DEFAULT 0x0180021f 120#define TEGRA186_ADMAIF_TX11_FIFO_CTRL_REG_DEFAULT 0x01800222 121#define TEGRA186_ADMAIF_TX12_FIFO_CTRL_REG_DEFAULT 0x01800225 122#define TEGRA186_ADMAIF_TX13_FIFO_CTRL_REG_DEFAULT 0x01800228 123#define TEGRA186_ADMAIF_TX14_FIFO_CTRL_REG_DEFAULT 0x0180022b 124#define TEGRA186_ADMAIF_TX15_FIFO_CTRL_REG_DEFAULT 0x0180022e 125#define TEGRA186_ADMAIF_TX16_FIFO_CTRL_REG_DEFAULT 0x01800231 126#define TEGRA186_ADMAIF_TX17_FIFO_CTRL_REG_DEFAULT 0x01800234 127#define TEGRA186_ADMAIF_TX18_FIFO_CTRL_REG_DEFAULT 0x01800237 128#define TEGRA186_ADMAIF_TX19_FIFO_CTRL_REG_DEFAULT 0x0180023a 129#define TEGRA186_ADMAIF_TX20_FIFO_CTRL_REG_DEFAULT 0x0180023d 130 131enum { 132 DATA_8BIT, 133 DATA_16BIT, 134 DATA_32BIT 135}; 136 137enum { 138 ADMAIF_RX_PATH, 139 ADMAIF_TX_PATH, 140 ADMAIF_PATHS, 141}; 142 143struct tegra_admaif_soc_data { 144 const struct snd_soc_component_driver *cmpnt; 145 const struct regmap_config *regmap_conf; 146 struct snd_soc_dai_driver *dais; 147 unsigned int global_base; 148 unsigned int tx_base; 149 unsigned int rx_base; 150 unsigned int num_ch; 151}; 152 153struct tegra_admaif { 154 struct snd_dmaengine_dai_dma_data *capture_dma_data; 155 struct snd_dmaengine_dai_dma_data *playback_dma_data; 156 const struct tegra_admaif_soc_data *soc_data; 157 unsigned int *mono_to_stereo[ADMAIF_PATHS]; 158 unsigned int *stereo_to_mono[ADMAIF_PATHS]; 159 struct regmap *regmap; 160}; 161 162#endif 163