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9#include <linux/bpf.h>
10#include <linux/bitops.h>
11#include <linux/compiler.h>
12#include <linux/errno.h>
13#include <linux/filter.h>
14#include <linux/netdevice.h>
15#include <linux/string.h>
16#include <linux/slab.h>
17#include <linux/if_vlan.h>
18
19#include <asm/cacheflush.h>
20#include <asm/hwcap.h>
21#include <asm/opcodes.h>
22#include <asm/system_info.h>
23
24#include "bpf_jit_32.h"
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76
77#define CALLEE_MASK (1 << ARM_R4 | 1 << ARM_R5 | 1 << ARM_R6 | \
78 1 << ARM_R7 | 1 << ARM_R8 | 1 << ARM_R9 | \
79 1 << ARM_FP)
80#define CALLEE_PUSH_MASK (CALLEE_MASK | 1 << ARM_LR)
81#define CALLEE_POP_MASK (CALLEE_MASK | 1 << ARM_PC)
82
83#define CALLER_MASK (1 << ARM_R0 | 1 << ARM_R1 | 1 << ARM_R2 | 1 << ARM_R3)
84
85enum {
86
87 BPF_R2_HI,
88 BPF_R2_LO,
89 BPF_R3_HI,
90 BPF_R3_LO,
91 BPF_R4_HI,
92 BPF_R4_LO,
93 BPF_R5_HI,
94 BPF_R5_LO,
95 BPF_R7_HI,
96 BPF_R7_LO,
97 BPF_R8_HI,
98 BPF_R8_LO,
99 BPF_R9_HI,
100 BPF_R9_LO,
101 BPF_FP_HI,
102 BPF_FP_LO,
103 BPF_TC_HI,
104 BPF_TC_LO,
105 BPF_AX_HI,
106 BPF_AX_LO,
107
108
109
110
111 BPF_JIT_SCRATCH_REGS,
112};
113
114
115
116
117
118#define STACK_OFFSET(k) (-4 - (k) * 4)
119#define SCRATCH_SIZE (BPF_JIT_SCRATCH_REGS * 4)
120
121#ifdef CONFIG_FRAME_POINTER
122#define EBPF_SCRATCH_TO_ARM_FP(x) ((x) - 4 * hweight16(CALLEE_PUSH_MASK) - 4)
123#else
124#define EBPF_SCRATCH_TO_ARM_FP(x) (x)
125#endif
126
127#define TMP_REG_1 (MAX_BPF_JIT_REG + 0)
128#define TMP_REG_2 (MAX_BPF_JIT_REG + 1)
129#define TCALL_CNT (MAX_BPF_JIT_REG + 2)
130
131#define FLAG_IMM_OVERFLOW (1 << 0)
132
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146
147
148static const s8 bpf2a32[][2] = {
149
150 [BPF_REG_0] = {ARM_R1, ARM_R0},
151
152 [BPF_REG_1] = {ARM_R3, ARM_R2},
153
154 [BPF_REG_2] = {STACK_OFFSET(BPF_R2_HI), STACK_OFFSET(BPF_R2_LO)},
155 [BPF_REG_3] = {STACK_OFFSET(BPF_R3_HI), STACK_OFFSET(BPF_R3_LO)},
156 [BPF_REG_4] = {STACK_OFFSET(BPF_R4_HI), STACK_OFFSET(BPF_R4_LO)},
157 [BPF_REG_5] = {STACK_OFFSET(BPF_R5_HI), STACK_OFFSET(BPF_R5_LO)},
158
159 [BPF_REG_6] = {ARM_R5, ARM_R4},
160
161 [BPF_REG_7] = {STACK_OFFSET(BPF_R7_HI), STACK_OFFSET(BPF_R7_LO)},
162 [BPF_REG_8] = {STACK_OFFSET(BPF_R8_HI), STACK_OFFSET(BPF_R8_LO)},
163 [BPF_REG_9] = {STACK_OFFSET(BPF_R9_HI), STACK_OFFSET(BPF_R9_LO)},
164
165 [BPF_REG_FP] = {STACK_OFFSET(BPF_FP_HI), STACK_OFFSET(BPF_FP_LO)},
166
167
168
169 [TMP_REG_1] = {ARM_R7, ARM_R6},
170 [TMP_REG_2] = {ARM_R9, ARM_R8},
171
172 [TCALL_CNT] = {STACK_OFFSET(BPF_TC_HI), STACK_OFFSET(BPF_TC_LO)},
173
174
175
176 [BPF_REG_AX] = {STACK_OFFSET(BPF_AX_HI), STACK_OFFSET(BPF_AX_LO)},
177};
178
179#define dst_lo dst[1]
180#define dst_hi dst[0]
181#define src_lo src[1]
182#define src_hi src[0]
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199
200struct jit_ctx {
201 const struct bpf_prog *prog;
202 unsigned int idx;
203 unsigned int prologue_bytes;
204 unsigned int epilogue_offset;
205 unsigned int cpu_architecture;
206 u32 flags;
207 u32 *offsets;
208 u32 *target;
209 u32 stack_size;
210#if __LINUX_ARM_ARCH__ < 7
211 u16 epilogue_bytes;
212 u16 imm_count;
213 u32 *imms;
214#endif
215};
216
217
218
219
220
221static u32 jit_udiv32(u32 dividend, u32 divisor)
222{
223 return dividend / divisor;
224}
225
226static u32 jit_mod32(u32 dividend, u32 divisor)
227{
228 return dividend % divisor;
229}
230
231static inline void _emit(int cond, u32 inst, struct jit_ctx *ctx)
232{
233 inst |= (cond << 28);
234 inst = __opcode_to_mem_arm(inst);
235
236 if (ctx->target != NULL)
237 ctx->target[ctx->idx] = inst;
238
239 ctx->idx++;
240}
241
242
243
244
245static inline void emit(u32 inst, struct jit_ctx *ctx)
246{
247 _emit(ARM_COND_AL, inst, ctx);
248}
249
250
251
252
253
254
255
256#define imm12val(v, s) (rol32(v, (s)) | (s) << 7)
257#define const_imm8m(x) \
258 ({ int r; \
259 u32 v = (x); \
260 if (!(v & ~0x000000ff)) \
261 r = imm12val(v, 0); \
262 else if (!(v & ~0xc000003f)) \
263 r = imm12val(v, 2); \
264 else if (!(v & ~0xf000000f)) \
265 r = imm12val(v, 4); \
266 else if (!(v & ~0xfc000003)) \
267 r = imm12val(v, 6); \
268 else if (!(v & ~0xff000000)) \
269 r = imm12val(v, 8); \
270 else if (!(v & ~0x3fc00000)) \
271 r = imm12val(v, 10); \
272 else if (!(v & ~0x0ff00000)) \
273 r = imm12val(v, 12); \
274 else if (!(v & ~0x03fc0000)) \
275 r = imm12val(v, 14); \
276 else if (!(v & ~0x00ff0000)) \
277 r = imm12val(v, 16); \
278 else if (!(v & ~0x003fc000)) \
279 r = imm12val(v, 18); \
280 else if (!(v & ~0x000ff000)) \
281 r = imm12val(v, 20); \
282 else if (!(v & ~0x0003fc00)) \
283 r = imm12val(v, 22); \
284 else if (!(v & ~0x0000ff00)) \
285 r = imm12val(v, 24); \
286 else if (!(v & ~0x00003fc0)) \
287 r = imm12val(v, 26); \
288 else if (!(v & ~0x00000ff0)) \
289 r = imm12val(v, 28); \
290 else if (!(v & ~0x000003fc)) \
291 r = imm12val(v, 30); \
292 else \
293 r = -1; \
294 r; })
295
296
297
298
299static int imm8m(u32 x)
300{
301 u32 rot;
302
303 for (rot = 0; rot < 16; rot++)
304 if ((x & ~ror32(0xff, 2 * rot)) == 0)
305 return rol32(x, 2 * rot) | (rot << 8);
306 return -1;
307}
308
309#define imm8m(x) (__builtin_constant_p(x) ? const_imm8m(x) : imm8m(x))
310
311static u32 arm_bpf_ldst_imm12(u32 op, u8 rt, u8 rn, s16 imm12)
312{
313 op |= rt << 12 | rn << 16;
314 if (imm12 >= 0)
315 op |= ARM_INST_LDST__U;
316 else
317 imm12 = -imm12;
318 return op | (imm12 & ARM_INST_LDST__IMM12);
319}
320
321static u32 arm_bpf_ldst_imm8(u32 op, u8 rt, u8 rn, s16 imm8)
322{
323 op |= rt << 12 | rn << 16;
324 if (imm8 >= 0)
325 op |= ARM_INST_LDST__U;
326 else
327 imm8 = -imm8;
328 return op | (imm8 & 0xf0) << 4 | (imm8 & 0x0f);
329}
330
331#define ARM_LDR_I(rt, rn, off) arm_bpf_ldst_imm12(ARM_INST_LDR_I, rt, rn, off)
332#define ARM_LDRB_I(rt, rn, off) arm_bpf_ldst_imm12(ARM_INST_LDRB_I, rt, rn, off)
333#define ARM_LDRD_I(rt, rn, off) arm_bpf_ldst_imm8(ARM_INST_LDRD_I, rt, rn, off)
334#define ARM_LDRH_I(rt, rn, off) arm_bpf_ldst_imm8(ARM_INST_LDRH_I, rt, rn, off)
335
336#define ARM_STR_I(rt, rn, off) arm_bpf_ldst_imm12(ARM_INST_STR_I, rt, rn, off)
337#define ARM_STRB_I(rt, rn, off) arm_bpf_ldst_imm12(ARM_INST_STRB_I, rt, rn, off)
338#define ARM_STRD_I(rt, rn, off) arm_bpf_ldst_imm8(ARM_INST_STRD_I, rt, rn, off)
339#define ARM_STRH_I(rt, rn, off) arm_bpf_ldst_imm8(ARM_INST_STRH_I, rt, rn, off)
340
341
342
343
344static void jit_fill_hole(void *area, unsigned int size)
345{
346 u32 *ptr;
347
348 for (ptr = area; size >= sizeof(u32); size -= sizeof(u32))
349 *ptr++ = __opcode_to_mem_arm(ARM_INST_UDF);
350}
351
352#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5)
353
354#define STACK_ALIGNMENT 8
355#else
356
357#define STACK_ALIGNMENT 4
358#endif
359
360
361#define _STACK_SIZE (ctx->prog->aux->stack_depth + SCRATCH_SIZE)
362#define STACK_SIZE ALIGN(_STACK_SIZE, STACK_ALIGNMENT)
363
364#if __LINUX_ARM_ARCH__ < 7
365
366static u16 imm_offset(u32 k, struct jit_ctx *ctx)
367{
368 unsigned int i = 0, offset;
369 u16 imm;
370
371
372 if (ctx->target == NULL) {
373 ctx->imm_count++;
374 return 0;
375 }
376
377 while ((i < ctx->imm_count) && ctx->imms[i]) {
378 if (ctx->imms[i] == k)
379 break;
380 i++;
381 }
382
383 if (ctx->imms[i] == 0)
384 ctx->imms[i] = k;
385
386
387 offset = ctx->offsets[ctx->prog->len - 1] * 4;
388 offset += ctx->prologue_bytes;
389 offset += ctx->epilogue_bytes;
390 offset += i * 4;
391
392 ctx->target[offset / 4] = k;
393
394
395 imm = offset - (8 + ctx->idx * 4);
396
397 if (imm & ~0xfff) {
398
399
400
401
402 ctx->flags |= FLAG_IMM_OVERFLOW;
403 return 0;
404 }
405
406 return imm;
407}
408
409#endif
410
411static inline int bpf2a32_offset(int bpf_to, int bpf_from,
412 const struct jit_ctx *ctx) {
413 int to, from;
414
415 if (ctx->target == NULL)
416 return 0;
417 to = ctx->offsets[bpf_to];
418 from = ctx->offsets[bpf_from];
419
420 return to - from - 1;
421}
422
423
424
425
426static inline void emit_mov_i_no8m(const u8 rd, u32 val, struct jit_ctx *ctx)
427{
428#if __LINUX_ARM_ARCH__ < 7
429 emit(ARM_LDR_I(rd, ARM_PC, imm_offset(val, ctx)), ctx);
430#else
431 emit(ARM_MOVW(rd, val & 0xffff), ctx);
432 if (val > 0xffff)
433 emit(ARM_MOVT(rd, val >> 16), ctx);
434#endif
435}
436
437static inline void emit_mov_i(const u8 rd, u32 val, struct jit_ctx *ctx)
438{
439 int imm12 = imm8m(val);
440
441 if (imm12 >= 0)
442 emit(ARM_MOV_I(rd, imm12), ctx);
443 else
444 emit_mov_i_no8m(rd, val, ctx);
445}
446
447static void emit_bx_r(u8 tgt_reg, struct jit_ctx *ctx)
448{
449 if (elf_hwcap & HWCAP_THUMB)
450 emit(ARM_BX(tgt_reg), ctx);
451 else
452 emit(ARM_MOV_R(ARM_PC, tgt_reg), ctx);
453}
454
455static inline void emit_blx_r(u8 tgt_reg, struct jit_ctx *ctx)
456{
457#if __LINUX_ARM_ARCH__ < 5
458 emit(ARM_MOV_R(ARM_LR, ARM_PC), ctx);
459 emit_bx_r(tgt_reg, ctx);
460#else
461 emit(ARM_BLX_R(tgt_reg), ctx);
462#endif
463}
464
465static inline int epilogue_offset(const struct jit_ctx *ctx)
466{
467 int to, from;
468
469 if (ctx->target == NULL)
470 return 0;
471 to = ctx->epilogue_offset;
472 from = ctx->idx;
473
474 return to - from - 2;
475}
476
477static inline void emit_udivmod(u8 rd, u8 rm, u8 rn, struct jit_ctx *ctx, u8 op)
478{
479 const int exclude_mask = BIT(ARM_R0) | BIT(ARM_R1);
480 const s8 *tmp = bpf2a32[TMP_REG_1];
481
482#if __LINUX_ARM_ARCH__ == 7
483 if (elf_hwcap & HWCAP_IDIVA) {
484 if (op == BPF_DIV)
485 emit(ARM_UDIV(rd, rm, rn), ctx);
486 else {
487 emit(ARM_UDIV(ARM_IP, rm, rn), ctx);
488 emit(ARM_MLS(rd, rn, ARM_IP, rm), ctx);
489 }
490 return;
491 }
492#endif
493
494
495
496
497
498
499
500
501
502 if (rn != ARM_R1) {
503 emit(ARM_MOV_R(tmp[0], ARM_R1), ctx);
504 emit(ARM_MOV_R(ARM_R1, rn), ctx);
505 }
506 if (rm != ARM_R0) {
507 emit(ARM_MOV_R(tmp[1], ARM_R0), ctx);
508 emit(ARM_MOV_R(ARM_R0, rm), ctx);
509 }
510
511
512 emit(ARM_PUSH(CALLER_MASK & ~exclude_mask), ctx);
513
514
515 emit_mov_i(ARM_IP, op == BPF_DIV ?
516 (u32)jit_udiv32 : (u32)jit_mod32, ctx);
517 emit_blx_r(ARM_IP, ctx);
518
519
520 emit(ARM_POP(CALLER_MASK & ~exclude_mask), ctx);
521
522
523 if (rd != ARM_R0)
524 emit(ARM_MOV_R(rd, ARM_R0), ctx);
525
526
527 if (rn != ARM_R1)
528 emit(ARM_MOV_R(ARM_R1, tmp[0]), ctx);
529 if (rm != ARM_R0)
530 emit(ARM_MOV_R(ARM_R0, tmp[1]), ctx);
531}
532
533
534static bool is_stacked(s8 reg)
535{
536 return reg < 0;
537}
538
539
540
541
542
543static s8 arm_bpf_get_reg32(s8 reg, s8 tmp, struct jit_ctx *ctx)
544{
545 if (is_stacked(reg)) {
546 emit(ARM_LDR_I(tmp, ARM_FP, EBPF_SCRATCH_TO_ARM_FP(reg)), ctx);
547 reg = tmp;
548 }
549 return reg;
550}
551
552static const s8 *arm_bpf_get_reg64(const s8 *reg, const s8 *tmp,
553 struct jit_ctx *ctx)
554{
555 if (is_stacked(reg[1])) {
556 if (__LINUX_ARM_ARCH__ >= 6 ||
557 ctx->cpu_architecture >= CPU_ARCH_ARMv5TE) {
558 emit(ARM_LDRD_I(tmp[1], ARM_FP,
559 EBPF_SCRATCH_TO_ARM_FP(reg[1])), ctx);
560 } else {
561 emit(ARM_LDR_I(tmp[1], ARM_FP,
562 EBPF_SCRATCH_TO_ARM_FP(reg[1])), ctx);
563 emit(ARM_LDR_I(tmp[0], ARM_FP,
564 EBPF_SCRATCH_TO_ARM_FP(reg[0])), ctx);
565 }
566 reg = tmp;
567 }
568 return reg;
569}
570
571
572
573
574
575static void arm_bpf_put_reg32(s8 reg, s8 src, struct jit_ctx *ctx)
576{
577 if (is_stacked(reg))
578 emit(ARM_STR_I(src, ARM_FP, EBPF_SCRATCH_TO_ARM_FP(reg)), ctx);
579 else if (reg != src)
580 emit(ARM_MOV_R(reg, src), ctx);
581}
582
583static void arm_bpf_put_reg64(const s8 *reg, const s8 *src,
584 struct jit_ctx *ctx)
585{
586 if (is_stacked(reg[1])) {
587 if (__LINUX_ARM_ARCH__ >= 6 ||
588 ctx->cpu_architecture >= CPU_ARCH_ARMv5TE) {
589 emit(ARM_STRD_I(src[1], ARM_FP,
590 EBPF_SCRATCH_TO_ARM_FP(reg[1])), ctx);
591 } else {
592 emit(ARM_STR_I(src[1], ARM_FP,
593 EBPF_SCRATCH_TO_ARM_FP(reg[1])), ctx);
594 emit(ARM_STR_I(src[0], ARM_FP,
595 EBPF_SCRATCH_TO_ARM_FP(reg[0])), ctx);
596 }
597 } else {
598 if (reg[1] != src[1])
599 emit(ARM_MOV_R(reg[1], src[1]), ctx);
600 if (reg[0] != src[0])
601 emit(ARM_MOV_R(reg[0], src[0]), ctx);
602 }
603}
604
605static inline void emit_a32_mov_i(const s8 dst, const u32 val,
606 struct jit_ctx *ctx)
607{
608 const s8 *tmp = bpf2a32[TMP_REG_1];
609
610 if (is_stacked(dst)) {
611 emit_mov_i(tmp[1], val, ctx);
612 arm_bpf_put_reg32(dst, tmp[1], ctx);
613 } else {
614 emit_mov_i(dst, val, ctx);
615 }
616}
617
618static void emit_a32_mov_i64(const s8 dst[], u64 val, struct jit_ctx *ctx)
619{
620 const s8 *tmp = bpf2a32[TMP_REG_1];
621 const s8 *rd = is_stacked(dst_lo) ? tmp : dst;
622
623 emit_mov_i(rd[1], (u32)val, ctx);
624 emit_mov_i(rd[0], val >> 32, ctx);
625
626 arm_bpf_put_reg64(dst, rd, ctx);
627}
628
629
630static inline void emit_a32_mov_se_i64(const bool is64, const s8 dst[],
631 const u32 val, struct jit_ctx *ctx) {
632 u64 val64 = val;
633
634 if (is64 && (val & (1<<31)))
635 val64 |= 0xffffffff00000000ULL;
636 emit_a32_mov_i64(dst, val64, ctx);
637}
638
639static inline void emit_a32_add_r(const u8 dst, const u8 src,
640 const bool is64, const bool hi,
641 struct jit_ctx *ctx) {
642
643
644
645
646
647
648 if (!hi && is64)
649 emit(ARM_ADDS_R(dst, dst, src), ctx);
650 else if (hi && is64)
651 emit(ARM_ADC_R(dst, dst, src), ctx);
652 else
653 emit(ARM_ADD_R(dst, dst, src), ctx);
654}
655
656static inline void emit_a32_sub_r(const u8 dst, const u8 src,
657 const bool is64, const bool hi,
658 struct jit_ctx *ctx) {
659
660
661
662
663
664
665 if (!hi && is64)
666 emit(ARM_SUBS_R(dst, dst, src), ctx);
667 else if (hi && is64)
668 emit(ARM_SBC_R(dst, dst, src), ctx);
669 else
670 emit(ARM_SUB_R(dst, dst, src), ctx);
671}
672
673static inline void emit_alu_r(const u8 dst, const u8 src, const bool is64,
674 const bool hi, const u8 op, struct jit_ctx *ctx){
675 switch (BPF_OP(op)) {
676
677 case BPF_ADD:
678 emit_a32_add_r(dst, src, is64, hi, ctx);
679 break;
680
681 case BPF_SUB:
682 emit_a32_sub_r(dst, src, is64, hi, ctx);
683 break;
684
685 case BPF_OR:
686 emit(ARM_ORR_R(dst, dst, src), ctx);
687 break;
688
689 case BPF_AND:
690 emit(ARM_AND_R(dst, dst, src), ctx);
691 break;
692
693 case BPF_XOR:
694 emit(ARM_EOR_R(dst, dst, src), ctx);
695 break;
696
697 case BPF_MUL:
698 emit(ARM_MUL(dst, dst, src), ctx);
699 break;
700
701 case BPF_LSH:
702 emit(ARM_LSL_R(dst, dst, src), ctx);
703 break;
704
705 case BPF_RSH:
706 emit(ARM_LSR_R(dst, dst, src), ctx);
707 break;
708
709 case BPF_ARSH:
710 emit(ARM_MOV_SR(dst, dst, SRTYPE_ASR, src), ctx);
711 break;
712 }
713}
714
715
716
717
718static inline void emit_a32_alu_r(const s8 dst, const s8 src,
719 struct jit_ctx *ctx, const bool is64,
720 const bool hi, const u8 op) {
721 const s8 *tmp = bpf2a32[TMP_REG_1];
722 s8 rn, rd;
723
724 rn = arm_bpf_get_reg32(src, tmp[1], ctx);
725 rd = arm_bpf_get_reg32(dst, tmp[0], ctx);
726
727 emit_alu_r(rd, rn, is64, hi, op, ctx);
728 arm_bpf_put_reg32(dst, rd, ctx);
729}
730
731
732static inline void emit_a32_alu_r64(const bool is64, const s8 dst[],
733 const s8 src[], struct jit_ctx *ctx,
734 const u8 op) {
735 const s8 *tmp = bpf2a32[TMP_REG_1];
736 const s8 *tmp2 = bpf2a32[TMP_REG_2];
737 const s8 *rd;
738
739 rd = arm_bpf_get_reg64(dst, tmp, ctx);
740 if (is64) {
741 const s8 *rs;
742
743 rs = arm_bpf_get_reg64(src, tmp2, ctx);
744
745
746 emit_alu_r(rd[1], rs[1], true, false, op, ctx);
747 emit_alu_r(rd[0], rs[0], true, true, op, ctx);
748 } else {
749 s8 rs;
750
751 rs = arm_bpf_get_reg32(src_lo, tmp2[1], ctx);
752
753
754 emit_alu_r(rd[1], rs, true, false, op, ctx);
755 if (!ctx->prog->aux->verifier_zext)
756 emit_a32_mov_i(rd[0], 0, ctx);
757 }
758
759 arm_bpf_put_reg64(dst, rd, ctx);
760}
761
762
763static inline void emit_a32_mov_r(const s8 dst, const s8 src,
764 struct jit_ctx *ctx) {
765 const s8 *tmp = bpf2a32[TMP_REG_1];
766 s8 rt;
767
768 rt = arm_bpf_get_reg32(src, tmp[0], ctx);
769 arm_bpf_put_reg32(dst, rt, ctx);
770}
771
772
773static inline void emit_a32_mov_r64(const bool is64, const s8 dst[],
774 const s8 src[],
775 struct jit_ctx *ctx) {
776 if (!is64) {
777 emit_a32_mov_r(dst_lo, src_lo, ctx);
778 if (!ctx->prog->aux->verifier_zext)
779
780 emit_a32_mov_i(dst_hi, 0, ctx);
781 } else if (__LINUX_ARM_ARCH__ < 6 &&
782 ctx->cpu_architecture < CPU_ARCH_ARMv5TE) {
783
784 emit_a32_mov_r(dst_lo, src_lo, ctx);
785 emit_a32_mov_r(dst_hi, src_hi, ctx);
786 } else if (is_stacked(src_lo) && is_stacked(dst_lo)) {
787 const u8 *tmp = bpf2a32[TMP_REG_1];
788
789 emit(ARM_LDRD_I(tmp[1], ARM_FP, EBPF_SCRATCH_TO_ARM_FP(src_lo)), ctx);
790 emit(ARM_STRD_I(tmp[1], ARM_FP, EBPF_SCRATCH_TO_ARM_FP(dst_lo)), ctx);
791 } else if (is_stacked(src_lo)) {
792 emit(ARM_LDRD_I(dst[1], ARM_FP, EBPF_SCRATCH_TO_ARM_FP(src_lo)), ctx);
793 } else if (is_stacked(dst_lo)) {
794 emit(ARM_STRD_I(src[1], ARM_FP, EBPF_SCRATCH_TO_ARM_FP(dst_lo)), ctx);
795 } else {
796 emit(ARM_MOV_R(dst[0], src[0]), ctx);
797 emit(ARM_MOV_R(dst[1], src[1]), ctx);
798 }
799}
800
801
802static inline void emit_a32_alu_i(const s8 dst, const u32 val,
803 struct jit_ctx *ctx, const u8 op) {
804 const s8 *tmp = bpf2a32[TMP_REG_1];
805 s8 rd;
806
807 rd = arm_bpf_get_reg32(dst, tmp[0], ctx);
808
809
810 switch (op) {
811 case BPF_LSH:
812 emit(ARM_LSL_I(rd, rd, val), ctx);
813 break;
814 case BPF_RSH:
815 emit(ARM_LSR_I(rd, rd, val), ctx);
816 break;
817 case BPF_ARSH:
818 emit(ARM_ASR_I(rd, rd, val), ctx);
819 break;
820 case BPF_NEG:
821 emit(ARM_RSB_I(rd, rd, val), ctx);
822 break;
823 }
824
825 arm_bpf_put_reg32(dst, rd, ctx);
826}
827
828
829static inline void emit_a32_neg64(const s8 dst[],
830 struct jit_ctx *ctx){
831 const s8 *tmp = bpf2a32[TMP_REG_1];
832 const s8 *rd;
833
834
835 rd = arm_bpf_get_reg64(dst, tmp, ctx);
836
837
838 emit(ARM_RSBS_I(rd[1], rd[1], 0), ctx);
839 emit(ARM_RSC_I(rd[0], rd[0], 0), ctx);
840
841 arm_bpf_put_reg64(dst, rd, ctx);
842}
843
844
845static inline void emit_a32_lsh_r64(const s8 dst[], const s8 src[],
846 struct jit_ctx *ctx) {
847 const s8 *tmp = bpf2a32[TMP_REG_1];
848 const s8 *tmp2 = bpf2a32[TMP_REG_2];
849 const s8 *rd;
850 s8 rt;
851
852
853 rt = arm_bpf_get_reg32(src_lo, tmp2[1], ctx);
854 rd = arm_bpf_get_reg64(dst, tmp, ctx);
855
856
857 emit(ARM_SUB_I(ARM_IP, rt, 32), ctx);
858 emit(ARM_RSB_I(tmp2[0], rt, 32), ctx);
859 emit(ARM_MOV_SR(ARM_LR, rd[0], SRTYPE_ASL, rt), ctx);
860 emit(ARM_ORR_SR(ARM_LR, ARM_LR, rd[1], SRTYPE_ASL, ARM_IP), ctx);
861 emit(ARM_ORR_SR(ARM_IP, ARM_LR, rd[1], SRTYPE_LSR, tmp2[0]), ctx);
862 emit(ARM_MOV_SR(ARM_LR, rd[1], SRTYPE_ASL, rt), ctx);
863
864 arm_bpf_put_reg32(dst_lo, ARM_LR, ctx);
865 arm_bpf_put_reg32(dst_hi, ARM_IP, ctx);
866}
867
868
869static inline void emit_a32_arsh_r64(const s8 dst[], const s8 src[],
870 struct jit_ctx *ctx) {
871 const s8 *tmp = bpf2a32[TMP_REG_1];
872 const s8 *tmp2 = bpf2a32[TMP_REG_2];
873 const s8 *rd;
874 s8 rt;
875
876
877 rt = arm_bpf_get_reg32(src_lo, tmp2[1], ctx);
878 rd = arm_bpf_get_reg64(dst, tmp, ctx);
879
880
881 emit(ARM_RSB_I(ARM_IP, rt, 32), ctx);
882 emit(ARM_SUBS_I(tmp2[0], rt, 32), ctx);
883 emit(ARM_MOV_SR(ARM_LR, rd[1], SRTYPE_LSR, rt), ctx);
884 emit(ARM_ORR_SR(ARM_LR, ARM_LR, rd[0], SRTYPE_ASL, ARM_IP), ctx);
885 _emit(ARM_COND_PL,
886 ARM_ORR_SR(ARM_LR, ARM_LR, rd[0], SRTYPE_ASR, tmp2[0]), ctx);
887 emit(ARM_MOV_SR(ARM_IP, rd[0], SRTYPE_ASR, rt), ctx);
888
889 arm_bpf_put_reg32(dst_lo, ARM_LR, ctx);
890 arm_bpf_put_reg32(dst_hi, ARM_IP, ctx);
891}
892
893
894static inline void emit_a32_rsh_r64(const s8 dst[], const s8 src[],
895 struct jit_ctx *ctx) {
896 const s8 *tmp = bpf2a32[TMP_REG_1];
897 const s8 *tmp2 = bpf2a32[TMP_REG_2];
898 const s8 *rd;
899 s8 rt;
900
901
902 rt = arm_bpf_get_reg32(src_lo, tmp2[1], ctx);
903 rd = arm_bpf_get_reg64(dst, tmp, ctx);
904
905
906 emit(ARM_RSB_I(ARM_IP, rt, 32), ctx);
907 emit(ARM_SUBS_I(tmp2[0], rt, 32), ctx);
908 emit(ARM_MOV_SR(ARM_LR, rd[1], SRTYPE_LSR, rt), ctx);
909 emit(ARM_ORR_SR(ARM_LR, ARM_LR, rd[0], SRTYPE_ASL, ARM_IP), ctx);
910 emit(ARM_ORR_SR(ARM_LR, ARM_LR, rd[0], SRTYPE_LSR, tmp2[0]), ctx);
911 emit(ARM_MOV_SR(ARM_IP, rd[0], SRTYPE_LSR, rt), ctx);
912
913 arm_bpf_put_reg32(dst_lo, ARM_LR, ctx);
914 arm_bpf_put_reg32(dst_hi, ARM_IP, ctx);
915}
916
917
918static inline void emit_a32_lsh_i64(const s8 dst[],
919 const u32 val, struct jit_ctx *ctx){
920 const s8 *tmp = bpf2a32[TMP_REG_1];
921 const s8 *tmp2 = bpf2a32[TMP_REG_2];
922 const s8 *rd;
923
924
925 rd = arm_bpf_get_reg64(dst, tmp, ctx);
926
927
928 if (val < 32) {
929 emit(ARM_MOV_SI(tmp2[0], rd[0], SRTYPE_ASL, val), ctx);
930 emit(ARM_ORR_SI(rd[0], tmp2[0], rd[1], SRTYPE_LSR, 32 - val), ctx);
931 emit(ARM_MOV_SI(rd[1], rd[1], SRTYPE_ASL, val), ctx);
932 } else {
933 if (val == 32)
934 emit(ARM_MOV_R(rd[0], rd[1]), ctx);
935 else
936 emit(ARM_MOV_SI(rd[0], rd[1], SRTYPE_ASL, val - 32), ctx);
937 emit(ARM_EOR_R(rd[1], rd[1], rd[1]), ctx);
938 }
939
940 arm_bpf_put_reg64(dst, rd, ctx);
941}
942
943
944static inline void emit_a32_rsh_i64(const s8 dst[],
945 const u32 val, struct jit_ctx *ctx) {
946 const s8 *tmp = bpf2a32[TMP_REG_1];
947 const s8 *tmp2 = bpf2a32[TMP_REG_2];
948 const s8 *rd;
949
950
951 rd = arm_bpf_get_reg64(dst, tmp, ctx);
952
953
954 if (val == 0) {
955
956
957
958 } else if (val < 32) {
959 emit(ARM_MOV_SI(tmp2[1], rd[1], SRTYPE_LSR, val), ctx);
960 emit(ARM_ORR_SI(rd[1], tmp2[1], rd[0], SRTYPE_ASL, 32 - val), ctx);
961 emit(ARM_MOV_SI(rd[0], rd[0], SRTYPE_LSR, val), ctx);
962 } else if (val == 32) {
963 emit(ARM_MOV_R(rd[1], rd[0]), ctx);
964 emit(ARM_MOV_I(rd[0], 0), ctx);
965 } else {
966 emit(ARM_MOV_SI(rd[1], rd[0], SRTYPE_LSR, val - 32), ctx);
967 emit(ARM_MOV_I(rd[0], 0), ctx);
968 }
969
970 arm_bpf_put_reg64(dst, rd, ctx);
971}
972
973
974static inline void emit_a32_arsh_i64(const s8 dst[],
975 const u32 val, struct jit_ctx *ctx){
976 const s8 *tmp = bpf2a32[TMP_REG_1];
977 const s8 *tmp2 = bpf2a32[TMP_REG_2];
978 const s8 *rd;
979
980
981 rd = arm_bpf_get_reg64(dst, tmp, ctx);
982
983
984 if (val == 0) {
985
986
987
988 } else if (val < 32) {
989 emit(ARM_MOV_SI(tmp2[1], rd[1], SRTYPE_LSR, val), ctx);
990 emit(ARM_ORR_SI(rd[1], tmp2[1], rd[0], SRTYPE_ASL, 32 - val), ctx);
991 emit(ARM_MOV_SI(rd[0], rd[0], SRTYPE_ASR, val), ctx);
992 } else if (val == 32) {
993 emit(ARM_MOV_R(rd[1], rd[0]), ctx);
994 emit(ARM_MOV_SI(rd[0], rd[0], SRTYPE_ASR, 31), ctx);
995 } else {
996 emit(ARM_MOV_SI(rd[1], rd[0], SRTYPE_ASR, val - 32), ctx);
997 emit(ARM_MOV_SI(rd[0], rd[0], SRTYPE_ASR, 31), ctx);
998 }
999
1000 arm_bpf_put_reg64(dst, rd, ctx);
1001}
1002
1003static inline void emit_a32_mul_r64(const s8 dst[], const s8 src[],
1004 struct jit_ctx *ctx) {
1005 const s8 *tmp = bpf2a32[TMP_REG_1];
1006 const s8 *tmp2 = bpf2a32[TMP_REG_2];
1007 const s8 *rd, *rt;
1008
1009
1010 rd = arm_bpf_get_reg64(dst, tmp, ctx);
1011 rt = arm_bpf_get_reg64(src, tmp2, ctx);
1012
1013
1014 emit(ARM_MUL(ARM_IP, rd[1], rt[0]), ctx);
1015 emit(ARM_MUL(ARM_LR, rd[0], rt[1]), ctx);
1016 emit(ARM_ADD_R(ARM_LR, ARM_IP, ARM_LR), ctx);
1017
1018 emit(ARM_UMULL(ARM_IP, rd[0], rd[1], rt[1]), ctx);
1019 emit(ARM_ADD_R(rd[0], ARM_LR, rd[0]), ctx);
1020
1021 arm_bpf_put_reg32(dst_lo, ARM_IP, ctx);
1022 arm_bpf_put_reg32(dst_hi, rd[0], ctx);
1023}
1024
1025static bool is_ldst_imm(s16 off, const u8 size)
1026{
1027 s16 off_max = 0;
1028
1029 switch (size) {
1030 case BPF_B:
1031 case BPF_W:
1032 off_max = 0xfff;
1033 break;
1034 case BPF_H:
1035 off_max = 0xff;
1036 break;
1037 case BPF_DW:
1038
1039 off_max = 0xfff - 4;
1040 break;
1041 }
1042 return -off_max <= off && off <= off_max;
1043}
1044
1045
1046static inline void emit_str_r(const s8 dst, const s8 src[],
1047 s16 off, struct jit_ctx *ctx, const u8 sz){
1048 const s8 *tmp = bpf2a32[TMP_REG_1];
1049 s8 rd;
1050
1051 rd = arm_bpf_get_reg32(dst, tmp[1], ctx);
1052
1053 if (!is_ldst_imm(off, sz)) {
1054 emit_a32_mov_i(tmp[0], off, ctx);
1055 emit(ARM_ADD_R(tmp[0], tmp[0], rd), ctx);
1056 rd = tmp[0];
1057 off = 0;
1058 }
1059 switch (sz) {
1060 case BPF_B:
1061
1062 emit(ARM_STRB_I(src_lo, rd, off), ctx);
1063 break;
1064 case BPF_H:
1065
1066 emit(ARM_STRH_I(src_lo, rd, off), ctx);
1067 break;
1068 case BPF_W:
1069
1070 emit(ARM_STR_I(src_lo, rd, off), ctx);
1071 break;
1072 case BPF_DW:
1073
1074 emit(ARM_STR_I(src_lo, rd, off), ctx);
1075 emit(ARM_STR_I(src_hi, rd, off + 4), ctx);
1076 break;
1077 }
1078}
1079
1080
1081static inline void emit_ldx_r(const s8 dst[], const s8 src,
1082 s16 off, struct jit_ctx *ctx, const u8 sz){
1083 const s8 *tmp = bpf2a32[TMP_REG_1];
1084 const s8 *rd = is_stacked(dst_lo) ? tmp : dst;
1085 s8 rm = src;
1086
1087 if (!is_ldst_imm(off, sz)) {
1088 emit_a32_mov_i(tmp[0], off, ctx);
1089 emit(ARM_ADD_R(tmp[0], tmp[0], src), ctx);
1090 rm = tmp[0];
1091 off = 0;
1092 } else if (rd[1] == rm) {
1093 emit(ARM_MOV_R(tmp[0], rm), ctx);
1094 rm = tmp[0];
1095 }
1096 switch (sz) {
1097 case BPF_B:
1098
1099 emit(ARM_LDRB_I(rd[1], rm, off), ctx);
1100 if (!ctx->prog->aux->verifier_zext)
1101 emit_a32_mov_i(rd[0], 0, ctx);
1102 break;
1103 case BPF_H:
1104
1105 emit(ARM_LDRH_I(rd[1], rm, off), ctx);
1106 if (!ctx->prog->aux->verifier_zext)
1107 emit_a32_mov_i(rd[0], 0, ctx);
1108 break;
1109 case BPF_W:
1110
1111 emit(ARM_LDR_I(rd[1], rm, off), ctx);
1112 if (!ctx->prog->aux->verifier_zext)
1113 emit_a32_mov_i(rd[0], 0, ctx);
1114 break;
1115 case BPF_DW:
1116
1117 emit(ARM_LDR_I(rd[1], rm, off), ctx);
1118 emit(ARM_LDR_I(rd[0], rm, off + 4), ctx);
1119 break;
1120 }
1121 arm_bpf_put_reg64(dst, rd, ctx);
1122}
1123
1124
1125static inline void emit_ar_r(const u8 rd, const u8 rt, const u8 rm,
1126 const u8 rn, struct jit_ctx *ctx, u8 op,
1127 bool is_jmp64) {
1128 switch (op) {
1129 case BPF_JSET:
1130 if (is_jmp64) {
1131 emit(ARM_AND_R(ARM_IP, rt, rn), ctx);
1132 emit(ARM_AND_R(ARM_LR, rd, rm), ctx);
1133 emit(ARM_ORRS_R(ARM_IP, ARM_LR, ARM_IP), ctx);
1134 } else {
1135 emit(ARM_ANDS_R(ARM_IP, rt, rn), ctx);
1136 }
1137 break;
1138 case BPF_JEQ:
1139 case BPF_JNE:
1140 case BPF_JGT:
1141 case BPF_JGE:
1142 case BPF_JLE:
1143 case BPF_JLT:
1144 if (is_jmp64) {
1145 emit(ARM_CMP_R(rd, rm), ctx);
1146
1147 _emit(ARM_COND_EQ, ARM_CMP_R(rt, rn), ctx);
1148 } else {
1149 emit(ARM_CMP_R(rt, rn), ctx);
1150 }
1151 break;
1152 case BPF_JSLE:
1153 case BPF_JSGT:
1154 emit(ARM_CMP_R(rn, rt), ctx);
1155 if (is_jmp64)
1156 emit(ARM_SBCS_R(ARM_IP, rm, rd), ctx);
1157 break;
1158 case BPF_JSLT:
1159 case BPF_JSGE:
1160 emit(ARM_CMP_R(rt, rn), ctx);
1161 if (is_jmp64)
1162 emit(ARM_SBCS_R(ARM_IP, rd, rm), ctx);
1163 break;
1164 }
1165}
1166
1167static int out_offset = -1;
1168static int emit_bpf_tail_call(struct jit_ctx *ctx)
1169{
1170
1171
1172 const s8 *r2 = bpf2a32[BPF_REG_2];
1173 const s8 *r3 = bpf2a32[BPF_REG_3];
1174 const s8 *tmp = bpf2a32[TMP_REG_1];
1175 const s8 *tmp2 = bpf2a32[TMP_REG_2];
1176 const s8 *tcc = bpf2a32[TCALL_CNT];
1177 const s8 *tc;
1178 const int idx0 = ctx->idx;
1179#define cur_offset (ctx->idx - idx0)
1180#define jmp_offset (out_offset - (cur_offset) - 2)
1181 u32 lo, hi;
1182 s8 r_array, r_index;
1183 int off;
1184
1185
1186
1187
1188 BUILD_BUG_ON(offsetof(struct bpf_array, map.max_entries) >
1189 ARM_INST_LDST__IMM12);
1190 off = offsetof(struct bpf_array, map.max_entries);
1191 r_array = arm_bpf_get_reg32(r2[1], tmp2[0], ctx);
1192
1193 r_index = arm_bpf_get_reg32(r3[1], tmp2[1], ctx);
1194
1195 emit(ARM_LDR_I(tmp[1], r_array, off), ctx);
1196
1197 emit(ARM_CMP_R(r_index, tmp[1]), ctx);
1198 _emit(ARM_COND_CS, ARM_B(jmp_offset), ctx);
1199
1200
1201
1202
1203
1204
1205
1206
1207 lo = (u32)MAX_TAIL_CALL_CNT;
1208 hi = (u32)((u64)MAX_TAIL_CALL_CNT >> 32);
1209 tc = arm_bpf_get_reg64(tcc, tmp, ctx);
1210 emit(ARM_CMP_I(tc[0], hi), ctx);
1211 _emit(ARM_COND_EQ, ARM_CMP_I(tc[1], lo), ctx);
1212 _emit(ARM_COND_CS, ARM_B(jmp_offset), ctx);
1213 emit(ARM_ADDS_I(tc[1], tc[1], 1), ctx);
1214 emit(ARM_ADC_I(tc[0], tc[0], 0), ctx);
1215 arm_bpf_put_reg64(tcc, tmp, ctx);
1216
1217
1218
1219
1220
1221 BUILD_BUG_ON(imm8m(offsetof(struct bpf_array, ptrs)) < 0);
1222 off = imm8m(offsetof(struct bpf_array, ptrs));
1223 emit(ARM_ADD_I(tmp[1], r_array, off), ctx);
1224 emit(ARM_LDR_R_SI(tmp[1], tmp[1], r_index, SRTYPE_ASL, 2), ctx);
1225 emit(ARM_CMP_I(tmp[1], 0), ctx);
1226 _emit(ARM_COND_EQ, ARM_B(jmp_offset), ctx);
1227
1228
1229 BUILD_BUG_ON(offsetof(struct bpf_prog, bpf_func) >
1230 ARM_INST_LDST__IMM12);
1231 off = offsetof(struct bpf_prog, bpf_func);
1232 emit(ARM_LDR_I(tmp[1], tmp[1], off), ctx);
1233 emit(ARM_ADD_I(tmp[1], tmp[1], ctx->prologue_bytes), ctx);
1234 emit_bx_r(tmp[1], ctx);
1235
1236
1237 if (out_offset == -1)
1238 out_offset = cur_offset;
1239 if (cur_offset != out_offset) {
1240 pr_err_once("tail_call out_offset = %d, expected %d!\n",
1241 cur_offset, out_offset);
1242 return -1;
1243 }
1244 return 0;
1245#undef cur_offset
1246#undef jmp_offset
1247}
1248
1249
1250static inline void emit_rev16(const u8 rd, const u8 rn, struct jit_ctx *ctx)
1251{
1252#if __LINUX_ARM_ARCH__ < 6
1253 const s8 *tmp2 = bpf2a32[TMP_REG_2];
1254
1255 emit(ARM_AND_I(tmp2[1], rn, 0xff), ctx);
1256 emit(ARM_MOV_SI(tmp2[0], rn, SRTYPE_LSR, 8), ctx);
1257 emit(ARM_AND_I(tmp2[0], tmp2[0], 0xff), ctx);
1258 emit(ARM_ORR_SI(rd, tmp2[0], tmp2[1], SRTYPE_LSL, 8), ctx);
1259#else
1260 emit(ARM_REV16(rd, rn), ctx);
1261#endif
1262}
1263
1264
1265static inline void emit_rev32(const u8 rd, const u8 rn, struct jit_ctx *ctx)
1266{
1267#if __LINUX_ARM_ARCH__ < 6
1268 const s8 *tmp2 = bpf2a32[TMP_REG_2];
1269
1270 emit(ARM_AND_I(tmp2[1], rn, 0xff), ctx);
1271 emit(ARM_MOV_SI(tmp2[0], rn, SRTYPE_LSR, 24), ctx);
1272 emit(ARM_ORR_SI(ARM_IP, tmp2[0], tmp2[1], SRTYPE_LSL, 24), ctx);
1273
1274 emit(ARM_MOV_SI(tmp2[1], rn, SRTYPE_LSR, 8), ctx);
1275 emit(ARM_AND_I(tmp2[1], tmp2[1], 0xff), ctx);
1276 emit(ARM_MOV_SI(tmp2[0], rn, SRTYPE_LSR, 16), ctx);
1277 emit(ARM_AND_I(tmp2[0], tmp2[0], 0xff), ctx);
1278 emit(ARM_MOV_SI(tmp2[0], tmp2[0], SRTYPE_LSL, 8), ctx);
1279 emit(ARM_ORR_SI(tmp2[0], tmp2[0], tmp2[1], SRTYPE_LSL, 16), ctx);
1280 emit(ARM_ORR_R(rd, ARM_IP, tmp2[0]), ctx);
1281
1282#else
1283 emit(ARM_REV(rd, rn), ctx);
1284#endif
1285}
1286
1287
1288static inline void emit_push_r64(const s8 src[], struct jit_ctx *ctx)
1289{
1290 const s8 *tmp2 = bpf2a32[TMP_REG_2];
1291 const s8 *rt;
1292 u16 reg_set = 0;
1293
1294 rt = arm_bpf_get_reg64(src, tmp2, ctx);
1295
1296 reg_set = (1 << rt[1]) | (1 << rt[0]);
1297 emit(ARM_PUSH(reg_set), ctx);
1298}
1299
1300static void build_prologue(struct jit_ctx *ctx)
1301{
1302 const s8 arm_r0 = bpf2a32[BPF_REG_0][1];
1303 const s8 *bpf_r1 = bpf2a32[BPF_REG_1];
1304 const s8 *bpf_fp = bpf2a32[BPF_REG_FP];
1305 const s8 *tcc = bpf2a32[TCALL_CNT];
1306
1307
1308#ifdef CONFIG_FRAME_POINTER
1309 u16 reg_set = CALLEE_PUSH_MASK | 1 << ARM_IP | 1 << ARM_PC;
1310 emit(ARM_MOV_R(ARM_IP, ARM_SP), ctx);
1311 emit(ARM_PUSH(reg_set), ctx);
1312 emit(ARM_SUB_I(ARM_FP, ARM_IP, 4), ctx);
1313#else
1314 emit(ARM_PUSH(CALLEE_PUSH_MASK), ctx);
1315 emit(ARM_MOV_R(ARM_FP, ARM_SP), ctx);
1316#endif
1317
1318
1319 emit(ARM_MOV_I(bpf_r1[0], 0), ctx);
1320 emit(ARM_SUB_I(bpf_r1[1], ARM_SP, SCRATCH_SIZE), ctx);
1321
1322 ctx->stack_size = imm8m(STACK_SIZE);
1323
1324
1325 emit(ARM_SUB_I(ARM_SP, ARM_SP, ctx->stack_size), ctx);
1326
1327
1328 emit_a32_mov_r64(true, bpf_fp, bpf_r1, ctx);
1329
1330
1331 emit(ARM_MOV_I(bpf_r1[1], 0), ctx);
1332 emit_a32_mov_r64(true, tcc, bpf_r1, ctx);
1333
1334
1335 emit(ARM_MOV_R(bpf_r1[1], arm_r0), ctx);
1336
1337
1338}
1339
1340
1341static void build_epilogue(struct jit_ctx *ctx)
1342{
1343#ifdef CONFIG_FRAME_POINTER
1344
1345
1346 u16 reg_set = CALLEE_POP_MASK | 1 << ARM_SP;
1347 emit(ARM_SUB_I(ARM_SP, ARM_FP, hweight16(reg_set) * 4), ctx);
1348 emit(ARM_LDM(ARM_SP, reg_set), ctx);
1349#else
1350
1351 emit(ARM_MOV_R(ARM_SP, ARM_FP), ctx);
1352 emit(ARM_POP(CALLEE_POP_MASK), ctx);
1353#endif
1354}
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364static int build_insn(const struct bpf_insn *insn, struct jit_ctx *ctx)
1365{
1366 const u8 code = insn->code;
1367 const s8 *dst = bpf2a32[insn->dst_reg];
1368 const s8 *src = bpf2a32[insn->src_reg];
1369 const s8 *tmp = bpf2a32[TMP_REG_1];
1370 const s8 *tmp2 = bpf2a32[TMP_REG_2];
1371 const s16 off = insn->off;
1372 const s32 imm = insn->imm;
1373 const int i = insn - ctx->prog->insnsi;
1374 const bool is64 = BPF_CLASS(code) == BPF_ALU64;
1375 const s8 *rd, *rs;
1376 s8 rd_lo, rt, rm, rn;
1377 s32 jmp_offset;
1378
1379#define check_imm(bits, imm) do { \
1380 if ((imm) >= (1 << ((bits) - 1)) || \
1381 (imm) < -(1 << ((bits) - 1))) { \
1382 pr_info("[%2d] imm=%d(0x%x) out of range\n", \
1383 i, imm, imm); \
1384 return -EINVAL; \
1385 } \
1386} while (0)
1387#define check_imm24(imm) check_imm(24, imm)
1388
1389 switch (code) {
1390
1391
1392
1393 case BPF_ALU | BPF_MOV | BPF_K:
1394 case BPF_ALU | BPF_MOV | BPF_X:
1395 case BPF_ALU64 | BPF_MOV | BPF_K:
1396 case BPF_ALU64 | BPF_MOV | BPF_X:
1397 switch (BPF_SRC(code)) {
1398 case BPF_X:
1399 if (imm == 1) {
1400
1401 emit_a32_mov_i(dst_hi, 0, ctx);
1402 break;
1403 }
1404 emit_a32_mov_r64(is64, dst, src, ctx);
1405 break;
1406 case BPF_K:
1407
1408 emit_a32_mov_se_i64(is64, dst, imm, ctx);
1409 break;
1410 }
1411 break;
1412
1413
1414
1415
1416
1417
1418
1419
1420 case BPF_ALU | BPF_ADD | BPF_K:
1421 case BPF_ALU | BPF_ADD | BPF_X:
1422 case BPF_ALU | BPF_SUB | BPF_K:
1423 case BPF_ALU | BPF_SUB | BPF_X:
1424 case BPF_ALU | BPF_OR | BPF_K:
1425 case BPF_ALU | BPF_OR | BPF_X:
1426 case BPF_ALU | BPF_AND | BPF_K:
1427 case BPF_ALU | BPF_AND | BPF_X:
1428 case BPF_ALU | BPF_XOR | BPF_K:
1429 case BPF_ALU | BPF_XOR | BPF_X:
1430 case BPF_ALU | BPF_MUL | BPF_K:
1431 case BPF_ALU | BPF_MUL | BPF_X:
1432 case BPF_ALU | BPF_LSH | BPF_X:
1433 case BPF_ALU | BPF_RSH | BPF_X:
1434 case BPF_ALU | BPF_ARSH | BPF_X:
1435 case BPF_ALU64 | BPF_ADD | BPF_K:
1436 case BPF_ALU64 | BPF_ADD | BPF_X:
1437 case BPF_ALU64 | BPF_SUB | BPF_K:
1438 case BPF_ALU64 | BPF_SUB | BPF_X:
1439 case BPF_ALU64 | BPF_OR | BPF_K:
1440 case BPF_ALU64 | BPF_OR | BPF_X:
1441 case BPF_ALU64 | BPF_AND | BPF_K:
1442 case BPF_ALU64 | BPF_AND | BPF_X:
1443 case BPF_ALU64 | BPF_XOR | BPF_K:
1444 case BPF_ALU64 | BPF_XOR | BPF_X:
1445 switch (BPF_SRC(code)) {
1446 case BPF_X:
1447 emit_a32_alu_r64(is64, dst, src, ctx, BPF_OP(code));
1448 break;
1449 case BPF_K:
1450
1451
1452
1453
1454
1455
1456 emit_a32_mov_se_i64(is64, tmp2, imm, ctx);
1457 emit_a32_alu_r64(is64, dst, tmp2, ctx, BPF_OP(code));
1458 break;
1459 }
1460 break;
1461
1462
1463 case BPF_ALU | BPF_DIV | BPF_K:
1464 case BPF_ALU | BPF_DIV | BPF_X:
1465 case BPF_ALU | BPF_MOD | BPF_K:
1466 case BPF_ALU | BPF_MOD | BPF_X:
1467 rd_lo = arm_bpf_get_reg32(dst_lo, tmp2[1], ctx);
1468 switch (BPF_SRC(code)) {
1469 case BPF_X:
1470 rt = arm_bpf_get_reg32(src_lo, tmp2[0], ctx);
1471 break;
1472 case BPF_K:
1473 rt = tmp2[0];
1474 emit_a32_mov_i(rt, imm, ctx);
1475 break;
1476 default:
1477 rt = src_lo;
1478 break;
1479 }
1480 emit_udivmod(rd_lo, rd_lo, rt, ctx, BPF_OP(code));
1481 arm_bpf_put_reg32(dst_lo, rd_lo, ctx);
1482 if (!ctx->prog->aux->verifier_zext)
1483 emit_a32_mov_i(dst_hi, 0, ctx);
1484 break;
1485 case BPF_ALU64 | BPF_DIV | BPF_K:
1486 case BPF_ALU64 | BPF_DIV | BPF_X:
1487 case BPF_ALU64 | BPF_MOD | BPF_K:
1488 case BPF_ALU64 | BPF_MOD | BPF_X:
1489 goto notyet;
1490
1491
1492
1493 case BPF_ALU | BPF_LSH | BPF_K:
1494 case BPF_ALU | BPF_RSH | BPF_K:
1495 case BPF_ALU | BPF_ARSH | BPF_K:
1496 if (unlikely(imm > 31))
1497 return -EINVAL;
1498 if (imm)
1499 emit_a32_alu_i(dst_lo, imm, ctx, BPF_OP(code));
1500 if (!ctx->prog->aux->verifier_zext)
1501 emit_a32_mov_i(dst_hi, 0, ctx);
1502 break;
1503
1504 case BPF_ALU64 | BPF_LSH | BPF_K:
1505 if (unlikely(imm > 63))
1506 return -EINVAL;
1507 emit_a32_lsh_i64(dst, imm, ctx);
1508 break;
1509
1510 case BPF_ALU64 | BPF_RSH | BPF_K:
1511 if (unlikely(imm > 63))
1512 return -EINVAL;
1513 emit_a32_rsh_i64(dst, imm, ctx);
1514 break;
1515
1516 case BPF_ALU64 | BPF_LSH | BPF_X:
1517 emit_a32_lsh_r64(dst, src, ctx);
1518 break;
1519
1520 case BPF_ALU64 | BPF_RSH | BPF_X:
1521 emit_a32_rsh_r64(dst, src, ctx);
1522 break;
1523
1524 case BPF_ALU64 | BPF_ARSH | BPF_X:
1525 emit_a32_arsh_r64(dst, src, ctx);
1526 break;
1527
1528 case BPF_ALU64 | BPF_ARSH | BPF_K:
1529 if (unlikely(imm > 63))
1530 return -EINVAL;
1531 emit_a32_arsh_i64(dst, imm, ctx);
1532 break;
1533
1534 case BPF_ALU | BPF_NEG:
1535 emit_a32_alu_i(dst_lo, 0, ctx, BPF_OP(code));
1536 if (!ctx->prog->aux->verifier_zext)
1537 emit_a32_mov_i(dst_hi, 0, ctx);
1538 break;
1539
1540 case BPF_ALU64 | BPF_NEG:
1541 emit_a32_neg64(dst, ctx);
1542 break;
1543
1544 case BPF_ALU64 | BPF_MUL | BPF_X:
1545 case BPF_ALU64 | BPF_MUL | BPF_K:
1546 switch (BPF_SRC(code)) {
1547 case BPF_X:
1548 emit_a32_mul_r64(dst, src, ctx);
1549 break;
1550 case BPF_K:
1551
1552
1553
1554
1555
1556
1557 emit_a32_mov_se_i64(is64, tmp2, imm, ctx);
1558 emit_a32_mul_r64(dst, tmp2, ctx);
1559 break;
1560 }
1561 break;
1562
1563
1564 case BPF_ALU | BPF_END | BPF_FROM_LE:
1565 case BPF_ALU | BPF_END | BPF_FROM_BE:
1566 rd = arm_bpf_get_reg64(dst, tmp, ctx);
1567 if (BPF_SRC(code) == BPF_FROM_LE)
1568 goto emit_bswap_uxt;
1569 switch (imm) {
1570 case 16:
1571 emit_rev16(rd[1], rd[1], ctx);
1572 goto emit_bswap_uxt;
1573 case 32:
1574 emit_rev32(rd[1], rd[1], ctx);
1575 goto emit_bswap_uxt;
1576 case 64:
1577 emit_rev32(ARM_LR, rd[1], ctx);
1578 emit_rev32(rd[1], rd[0], ctx);
1579 emit(ARM_MOV_R(rd[0], ARM_LR), ctx);
1580 break;
1581 }
1582 goto exit;
1583emit_bswap_uxt:
1584 switch (imm) {
1585 case 16:
1586
1587#if __LINUX_ARM_ARCH__ < 6
1588 emit_a32_mov_i(tmp2[1], 0xffff, ctx);
1589 emit(ARM_AND_R(rd[1], rd[1], tmp2[1]), ctx);
1590#else
1591 emit(ARM_UXTH(rd[1], rd[1]), ctx);
1592#endif
1593 if (!ctx->prog->aux->verifier_zext)
1594 emit(ARM_EOR_R(rd[0], rd[0], rd[0]), ctx);
1595 break;
1596 case 32:
1597
1598 if (!ctx->prog->aux->verifier_zext)
1599 emit(ARM_EOR_R(rd[0], rd[0], rd[0]), ctx);
1600 break;
1601 case 64:
1602
1603 break;
1604 }
1605exit:
1606 arm_bpf_put_reg64(dst, rd, ctx);
1607 break;
1608
1609 case BPF_LD | BPF_IMM | BPF_DW:
1610 {
1611 u64 val = (u32)imm | (u64)insn[1].imm << 32;
1612
1613 emit_a32_mov_i64(dst, val, ctx);
1614
1615 return 1;
1616 }
1617
1618 case BPF_LDX | BPF_MEM | BPF_W:
1619 case BPF_LDX | BPF_MEM | BPF_H:
1620 case BPF_LDX | BPF_MEM | BPF_B:
1621 case BPF_LDX | BPF_MEM | BPF_DW:
1622 rn = arm_bpf_get_reg32(src_lo, tmp2[1], ctx);
1623 emit_ldx_r(dst, rn, off, ctx, BPF_SIZE(code));
1624 break;
1625
1626 case BPF_ST | BPF_NOSPEC:
1627 break;
1628
1629 case BPF_ST | BPF_MEM | BPF_W:
1630 case BPF_ST | BPF_MEM | BPF_H:
1631 case BPF_ST | BPF_MEM | BPF_B:
1632 case BPF_ST | BPF_MEM | BPF_DW:
1633 switch (BPF_SIZE(code)) {
1634 case BPF_DW:
1635
1636 emit_a32_mov_se_i64(true, tmp2, imm, ctx);
1637 break;
1638 case BPF_W:
1639 case BPF_H:
1640 case BPF_B:
1641 emit_a32_mov_i(tmp2[1], imm, ctx);
1642 break;
1643 }
1644 emit_str_r(dst_lo, tmp2, off, ctx, BPF_SIZE(code));
1645 break;
1646
1647 case BPF_STX | BPF_ATOMIC | BPF_W:
1648 case BPF_STX | BPF_ATOMIC | BPF_DW:
1649 goto notyet;
1650
1651 case BPF_STX | BPF_MEM | BPF_W:
1652 case BPF_STX | BPF_MEM | BPF_H:
1653 case BPF_STX | BPF_MEM | BPF_B:
1654 case BPF_STX | BPF_MEM | BPF_DW:
1655 rs = arm_bpf_get_reg64(src, tmp2, ctx);
1656 emit_str_r(dst_lo, rs, off, ctx, BPF_SIZE(code));
1657 break;
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669 case BPF_JMP | BPF_JEQ | BPF_X:
1670 case BPF_JMP | BPF_JGT | BPF_X:
1671 case BPF_JMP | BPF_JGE | BPF_X:
1672 case BPF_JMP | BPF_JNE | BPF_X:
1673 case BPF_JMP | BPF_JSGT | BPF_X:
1674 case BPF_JMP | BPF_JSGE | BPF_X:
1675 case BPF_JMP | BPF_JSET | BPF_X:
1676 case BPF_JMP | BPF_JLE | BPF_X:
1677 case BPF_JMP | BPF_JLT | BPF_X:
1678 case BPF_JMP | BPF_JSLT | BPF_X:
1679 case BPF_JMP | BPF_JSLE | BPF_X:
1680 case BPF_JMP32 | BPF_JEQ | BPF_X:
1681 case BPF_JMP32 | BPF_JGT | BPF_X:
1682 case BPF_JMP32 | BPF_JGE | BPF_X:
1683 case BPF_JMP32 | BPF_JNE | BPF_X:
1684 case BPF_JMP32 | BPF_JSGT | BPF_X:
1685 case BPF_JMP32 | BPF_JSGE | BPF_X:
1686 case BPF_JMP32 | BPF_JSET | BPF_X:
1687 case BPF_JMP32 | BPF_JLE | BPF_X:
1688 case BPF_JMP32 | BPF_JLT | BPF_X:
1689 case BPF_JMP32 | BPF_JSLT | BPF_X:
1690 case BPF_JMP32 | BPF_JSLE | BPF_X:
1691
1692 rm = arm_bpf_get_reg32(src_hi, tmp2[0], ctx);
1693 rn = arm_bpf_get_reg32(src_lo, tmp2[1], ctx);
1694 goto go_jmp;
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706 case BPF_JMP | BPF_JEQ | BPF_K:
1707 case BPF_JMP | BPF_JGT | BPF_K:
1708 case BPF_JMP | BPF_JGE | BPF_K:
1709 case BPF_JMP | BPF_JNE | BPF_K:
1710 case BPF_JMP | BPF_JSGT | BPF_K:
1711 case BPF_JMP | BPF_JSGE | BPF_K:
1712 case BPF_JMP | BPF_JSET | BPF_K:
1713 case BPF_JMP | BPF_JLT | BPF_K:
1714 case BPF_JMP | BPF_JLE | BPF_K:
1715 case BPF_JMP | BPF_JSLT | BPF_K:
1716 case BPF_JMP | BPF_JSLE | BPF_K:
1717 case BPF_JMP32 | BPF_JEQ | BPF_K:
1718 case BPF_JMP32 | BPF_JGT | BPF_K:
1719 case BPF_JMP32 | BPF_JGE | BPF_K:
1720 case BPF_JMP32 | BPF_JNE | BPF_K:
1721 case BPF_JMP32 | BPF_JSGT | BPF_K:
1722 case BPF_JMP32 | BPF_JSGE | BPF_K:
1723 case BPF_JMP32 | BPF_JSET | BPF_K:
1724 case BPF_JMP32 | BPF_JLT | BPF_K:
1725 case BPF_JMP32 | BPF_JLE | BPF_K:
1726 case BPF_JMP32 | BPF_JSLT | BPF_K:
1727 case BPF_JMP32 | BPF_JSLE | BPF_K:
1728 if (off == 0)
1729 break;
1730 rm = tmp2[0];
1731 rn = tmp2[1];
1732
1733 emit_a32_mov_se_i64(true, tmp2, imm, ctx);
1734go_jmp:
1735
1736 rd = arm_bpf_get_reg64(dst, tmp, ctx);
1737
1738
1739 emit_ar_r(rd[0], rd[1], rm, rn, ctx, BPF_OP(code),
1740 BPF_CLASS(code) == BPF_JMP);
1741
1742
1743 jmp_offset = bpf2a32_offset(i+off, i, ctx);
1744 switch (BPF_OP(code)) {
1745 case BPF_JNE:
1746 case BPF_JSET:
1747 _emit(ARM_COND_NE, ARM_B(jmp_offset), ctx);
1748 break;
1749 case BPF_JEQ:
1750 _emit(ARM_COND_EQ, ARM_B(jmp_offset), ctx);
1751 break;
1752 case BPF_JGT:
1753 _emit(ARM_COND_HI, ARM_B(jmp_offset), ctx);
1754 break;
1755 case BPF_JGE:
1756 _emit(ARM_COND_CS, ARM_B(jmp_offset), ctx);
1757 break;
1758 case BPF_JSGT:
1759 _emit(ARM_COND_LT, ARM_B(jmp_offset), ctx);
1760 break;
1761 case BPF_JSGE:
1762 _emit(ARM_COND_GE, ARM_B(jmp_offset), ctx);
1763 break;
1764 case BPF_JLE:
1765 _emit(ARM_COND_LS, ARM_B(jmp_offset), ctx);
1766 break;
1767 case BPF_JLT:
1768 _emit(ARM_COND_CC, ARM_B(jmp_offset), ctx);
1769 break;
1770 case BPF_JSLT:
1771 _emit(ARM_COND_LT, ARM_B(jmp_offset), ctx);
1772 break;
1773 case BPF_JSLE:
1774 _emit(ARM_COND_GE, ARM_B(jmp_offset), ctx);
1775 break;
1776 }
1777 break;
1778
1779 case BPF_JMP | BPF_JA:
1780 {
1781 if (off == 0)
1782 break;
1783 jmp_offset = bpf2a32_offset(i+off, i, ctx);
1784 check_imm24(jmp_offset);
1785 emit(ARM_B(jmp_offset), ctx);
1786 break;
1787 }
1788
1789 case BPF_JMP | BPF_TAIL_CALL:
1790 if (emit_bpf_tail_call(ctx))
1791 return -EFAULT;
1792 break;
1793
1794 case BPF_JMP | BPF_CALL:
1795 {
1796 const s8 *r0 = bpf2a32[BPF_REG_0];
1797 const s8 *r1 = bpf2a32[BPF_REG_1];
1798 const s8 *r2 = bpf2a32[BPF_REG_2];
1799 const s8 *r3 = bpf2a32[BPF_REG_3];
1800 const s8 *r4 = bpf2a32[BPF_REG_4];
1801 const s8 *r5 = bpf2a32[BPF_REG_5];
1802 const u32 func = (u32)__bpf_call_base + (u32)imm;
1803
1804 emit_a32_mov_r64(true, r0, r1, ctx);
1805 emit_a32_mov_r64(true, r1, r2, ctx);
1806 emit_push_r64(r5, ctx);
1807 emit_push_r64(r4, ctx);
1808 emit_push_r64(r3, ctx);
1809
1810 emit_a32_mov_i(tmp[1], func, ctx);
1811 emit_blx_r(tmp[1], ctx);
1812
1813 emit(ARM_ADD_I(ARM_SP, ARM_SP, imm8m(24)), ctx);
1814 break;
1815 }
1816
1817 case BPF_JMP | BPF_EXIT:
1818
1819
1820
1821 if (i == ctx->prog->len - 1)
1822 break;
1823 jmp_offset = epilogue_offset(ctx);
1824 check_imm24(jmp_offset);
1825 emit(ARM_B(jmp_offset), ctx);
1826 break;
1827notyet:
1828 pr_info_once("*** NOT YET: opcode %02x ***\n", code);
1829 return -EFAULT;
1830 default:
1831 pr_err_once("unknown opcode %02x\n", code);
1832 return -EINVAL;
1833 }
1834
1835 if (ctx->flags & FLAG_IMM_OVERFLOW)
1836
1837
1838
1839
1840
1841 return -1;
1842 return 0;
1843}
1844
1845static int build_body(struct jit_ctx *ctx)
1846{
1847 const struct bpf_prog *prog = ctx->prog;
1848 unsigned int i;
1849
1850 for (i = 0; i < prog->len; i++) {
1851 const struct bpf_insn *insn = &(prog->insnsi[i]);
1852 int ret;
1853
1854 ret = build_insn(insn, ctx);
1855
1856
1857 if (ret > 0) {
1858 i++;
1859 if (ctx->target == NULL)
1860 ctx->offsets[i] = ctx->idx;
1861 continue;
1862 }
1863
1864 if (ctx->target == NULL)
1865 ctx->offsets[i] = ctx->idx;
1866
1867
1868 if (ret)
1869 return ret;
1870 }
1871 return 0;
1872}
1873
1874static int validate_code(struct jit_ctx *ctx)
1875{
1876 int i;
1877
1878 for (i = 0; i < ctx->idx; i++) {
1879 if (ctx->target[i] == __opcode_to_mem_arm(ARM_INST_UDF))
1880 return -1;
1881 }
1882
1883 return 0;
1884}
1885
1886bool bpf_jit_needs_zext(void)
1887{
1888 return true;
1889}
1890
1891struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *prog)
1892{
1893 struct bpf_prog *tmp, *orig_prog = prog;
1894 struct bpf_binary_header *header;
1895 bool tmp_blinded = false;
1896 struct jit_ctx ctx;
1897 unsigned int tmp_idx;
1898 unsigned int image_size;
1899 u8 *image_ptr;
1900
1901
1902
1903
1904 if (!prog->jit_requested)
1905 return orig_prog;
1906
1907
1908
1909
1910
1911 tmp = bpf_jit_blind_constants(prog);
1912
1913 if (IS_ERR(tmp))
1914 return orig_prog;
1915 if (tmp != prog) {
1916 tmp_blinded = true;
1917 prog = tmp;
1918 }
1919
1920 memset(&ctx, 0, sizeof(ctx));
1921 ctx.prog = prog;
1922 ctx.cpu_architecture = cpu_architecture();
1923
1924
1925
1926
1927 ctx.offsets = kcalloc(prog->len, sizeof(int), GFP_KERNEL);
1928 if (ctx.offsets == NULL) {
1929 prog = orig_prog;
1930 goto out;
1931 }
1932
1933
1934
1935
1936
1937
1938
1939
1940
1941
1942
1943 if (build_body(&ctx)) {
1944 prog = orig_prog;
1945 goto out_off;
1946 }
1947
1948 tmp_idx = ctx.idx;
1949 build_prologue(&ctx);
1950 ctx.prologue_bytes = (ctx.idx - tmp_idx) * 4;
1951
1952 ctx.epilogue_offset = ctx.idx;
1953
1954#if __LINUX_ARM_ARCH__ < 7
1955 tmp_idx = ctx.idx;
1956 build_epilogue(&ctx);
1957 ctx.epilogue_bytes = (ctx.idx - tmp_idx) * 4;
1958
1959 ctx.idx += ctx.imm_count;
1960 if (ctx.imm_count) {
1961 ctx.imms = kcalloc(ctx.imm_count, sizeof(u32), GFP_KERNEL);
1962 if (ctx.imms == NULL) {
1963 prog = orig_prog;
1964 goto out_off;
1965 }
1966 }
1967#else
1968
1969 build_epilogue(&ctx);
1970#endif
1971
1972
1973
1974
1975
1976
1977
1978
1979 image_size = sizeof(u32) * ctx.idx;
1980
1981
1982 header = bpf_jit_binary_alloc(image_size, &image_ptr,
1983 sizeof(u32), jit_fill_hole);
1984
1985
1986
1987 if (header == NULL) {
1988 prog = orig_prog;
1989 goto out_imms;
1990 }
1991
1992
1993 ctx.target = (u32 *) image_ptr;
1994 ctx.idx = 0;
1995
1996 build_prologue(&ctx);
1997
1998
1999
2000
2001 if (build_body(&ctx) < 0) {
2002 image_ptr = NULL;
2003 bpf_jit_binary_free(header);
2004 prog = orig_prog;
2005 goto out_imms;
2006 }
2007 build_epilogue(&ctx);
2008
2009
2010 if (validate_code(&ctx)) {
2011 image_ptr = NULL;
2012 bpf_jit_binary_free(header);
2013 prog = orig_prog;
2014 goto out_imms;
2015 }
2016 flush_icache_range((u32)header, (u32)(ctx.target + ctx.idx));
2017
2018 if (bpf_jit_enable > 1)
2019
2020 bpf_jit_dump(prog->len, image_size, 2, ctx.target);
2021
2022 bpf_jit_binary_lock_ro(header);
2023 prog->bpf_func = (void *)ctx.target;
2024 prog->jited = 1;
2025 prog->jited_len = image_size;
2026
2027out_imms:
2028#if __LINUX_ARM_ARCH__ < 7
2029 if (ctx.imm_count)
2030 kfree(ctx.imms);
2031#endif
2032out_off:
2033 kfree(ctx.offsets);
2034out:
2035 if (tmp_blinded)
2036 bpf_jit_prog_release_other(prog, prog == orig_prog ?
2037 tmp : orig_prog);
2038 return prog;
2039}
2040
2041