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10#ifdef __KERNEL__
11#ifndef __CPM2__
12#define __CPM2__
13
14#include <asm/immap_cpm2.h>
15#include <asm/cpm.h>
16#include <sysdev/fsl_soc.h>
17
18
19
20#define CPM_CR_RST ((uint)0x80000000)
21#define CPM_CR_PAGE ((uint)0x7c000000)
22#define CPM_CR_SBLOCK ((uint)0x03e00000)
23#define CPM_CR_FLG ((uint)0x00010000)
24#define CPM_CR_MCN ((uint)0x00003fc0)
25#define CPM_CR_OPCODE ((uint)0x0000000f)
26
27
28
29#define CPM_CR_SCC1_SBLOCK (0x04)
30#define CPM_CR_SCC2_SBLOCK (0x05)
31#define CPM_CR_SCC3_SBLOCK (0x06)
32#define CPM_CR_SCC4_SBLOCK (0x07)
33#define CPM_CR_SMC1_SBLOCK (0x08)
34#define CPM_CR_SMC2_SBLOCK (0x09)
35#define CPM_CR_SPI_SBLOCK (0x0a)
36#define CPM_CR_I2C_SBLOCK (0x0b)
37#define CPM_CR_TIMER_SBLOCK (0x0f)
38#define CPM_CR_RAND_SBLOCK (0x0e)
39#define CPM_CR_FCC1_SBLOCK (0x10)
40#define CPM_CR_FCC2_SBLOCK (0x11)
41#define CPM_CR_FCC3_SBLOCK (0x12)
42#define CPM_CR_IDMA1_SBLOCK (0x14)
43#define CPM_CR_IDMA2_SBLOCK (0x15)
44#define CPM_CR_IDMA3_SBLOCK (0x16)
45#define CPM_CR_IDMA4_SBLOCK (0x17)
46#define CPM_CR_MCC1_SBLOCK (0x1c)
47
48#define CPM_CR_FCC_SBLOCK(x) (x + 0x10)
49
50#define CPM_CR_SCC1_PAGE (0x00)
51#define CPM_CR_SCC2_PAGE (0x01)
52#define CPM_CR_SCC3_PAGE (0x02)
53#define CPM_CR_SCC4_PAGE (0x03)
54#define CPM_CR_SMC1_PAGE (0x07)
55#define CPM_CR_SMC2_PAGE (0x08)
56#define CPM_CR_SPI_PAGE (0x09)
57#define CPM_CR_I2C_PAGE (0x0a)
58#define CPM_CR_TIMER_PAGE (0x0a)
59#define CPM_CR_RAND_PAGE (0x0a)
60#define CPM_CR_FCC1_PAGE (0x04)
61#define CPM_CR_FCC2_PAGE (0x05)
62#define CPM_CR_FCC3_PAGE (0x06)
63#define CPM_CR_IDMA1_PAGE (0x07)
64#define CPM_CR_IDMA2_PAGE (0x08)
65#define CPM_CR_IDMA3_PAGE (0x09)
66#define CPM_CR_IDMA4_PAGE (0x0a)
67#define CPM_CR_MCC1_PAGE (0x07)
68#define CPM_CR_MCC2_PAGE (0x08)
69
70#define CPM_CR_FCC_PAGE(x) (x + 0x04)
71
72
73
74#define CPM_CR_START_IDMA ((ushort)0x0009)
75
76#define mk_cr_cmd(PG, SBC, MCN, OP) \
77 ((PG << 26) | (SBC << 21) | (MCN << 6) | OP)
78
79
80
81
82
83#define NUM_CPM_HOST_PAGES 2
84
85
86
87
88extern cpm_cpm2_t __iomem *cpmp;
89
90#define cpm_dpalloc cpm_muram_alloc
91#define cpm_dpfree cpm_muram_free
92#define cpm_dpram_addr cpm_muram_addr
93
94extern void cpm2_reset(void);
95
96
97
98#define CPM_BRG_RST ((uint)0x00020000)
99#define CPM_BRG_EN ((uint)0x00010000)
100#define CPM_BRG_EXTC_INT ((uint)0x00000000)
101#define CPM_BRG_EXTC_CLK3_9 ((uint)0x00004000)
102#define CPM_BRG_EXTC_CLK5_15 ((uint)0x00008000)
103#define CPM_BRG_ATB ((uint)0x00002000)
104#define CPM_BRG_CD_MASK ((uint)0x00001ffe)
105#define CPM_BRG_DIV16 ((uint)0x00000001)
106
107#define CPM2_BRG_INT_CLK (get_brgfreq())
108#define CPM2_BRG_UART_CLK (CPM2_BRG_INT_CLK/16)
109
110extern void __cpm2_setbrg(uint brg, uint rate, uint clk, int div16, int src);
111
112
113
114
115static inline void cpm_setbrg(uint brg, uint rate)
116{
117 __cpm2_setbrg(brg, rate, CPM2_BRG_UART_CLK, 0, CPM_BRG_EXTC_INT);
118}
119
120
121
122
123static inline void cpm2_fastbrg(uint brg, uint rate, int div16)
124{
125 __cpm2_setbrg(brg, rate, CPM2_BRG_INT_CLK, div16, CPM_BRG_EXTC_INT);
126}
127
128
129
130#define PROFF_SCC1 ((uint)0x8000)
131#define PROFF_SCC2 ((uint)0x8100)
132#define PROFF_SCC3 ((uint)0x8200)
133#define PROFF_SCC4 ((uint)0x8300)
134#define PROFF_FCC1 ((uint)0x8400)
135#define PROFF_FCC2 ((uint)0x8500)
136#define PROFF_FCC3 ((uint)0x8600)
137#define PROFF_MCC1 ((uint)0x8700)
138#define PROFF_SMC1_BASE ((uint)0x87fc)
139#define PROFF_IDMA1_BASE ((uint)0x87fe)
140#define PROFF_MCC2 ((uint)0x8800)
141#define PROFF_SMC2_BASE ((uint)0x88fc)
142#define PROFF_IDMA2_BASE ((uint)0x88fe)
143#define PROFF_SPI_BASE ((uint)0x89fc)
144#define PROFF_IDMA3_BASE ((uint)0x89fe)
145#define PROFF_TIMERS ((uint)0x8ae0)
146#define PROFF_REVNUM ((uint)0x8af0)
147#define PROFF_RAND ((uint)0x8af8)
148#define PROFF_I2C_BASE ((uint)0x8afc)
149#define PROFF_IDMA4_BASE ((uint)0x8afe)
150
151#define PROFF_SCC_SIZE ((uint)0x100)
152#define PROFF_FCC_SIZE ((uint)0x100)
153#define PROFF_SMC_SIZE ((uint)64)
154
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157
158
159
160
161#define PROFF_SMC1 (0)
162#define PROFF_SMC2 (64)
163
164
165
166
167typedef struct smc_uart {
168 ushort smc_rbase;
169 ushort smc_tbase;
170 u_char smc_rfcr;
171 u_char smc_tfcr;
172 ushort smc_mrblr;
173 uint smc_rstate;
174 uint smc_idp;
175 ushort smc_rbptr;
176 ushort smc_ibc;
177 uint smc_rxtmp;
178 uint smc_tstate;
179 uint smc_tdp;
180 ushort smc_tbptr;
181 ushort smc_tbc;
182 uint smc_txtmp;
183 ushort smc_maxidl;
184 ushort smc_tmpidl;
185 ushort smc_brklen;
186 ushort smc_brkec;
187 ushort smc_brkcr;
188 ushort smc_rmask;
189 uint smc_stmp;
190} smc_uart_t;
191
192
193
194#define SMCMR_REN ((ushort)0x0001)
195#define SMCMR_TEN ((ushort)0x0002)
196#define SMCMR_DM ((ushort)0x000c)
197#define SMCMR_SM_GCI ((ushort)0x0000)
198#define SMCMR_SM_UART ((ushort)0x0020)
199#define SMCMR_SM_TRANS ((ushort)0x0030)
200#define SMCMR_SM_MASK ((ushort)0x0030)
201#define SMCMR_PM_EVEN ((ushort)0x0100)
202#define SMCMR_REVD SMCMR_PM_EVEN
203#define SMCMR_PEN ((ushort)0x0200)
204#define SMCMR_BS SMCMR_PEN
205#define SMCMR_SL ((ushort)0x0400)
206#define SMCR_CLEN_MASK ((ushort)0x7800)
207#define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK)
208
209
210
211#define SMCM_BRKE ((unsigned char)0x40)
212#define SMCM_BRK ((unsigned char)0x10)
213#define SMCM_TXE ((unsigned char)0x10)
214#define SMCM_BSY ((unsigned char)0x04)
215#define SMCM_TX ((unsigned char)0x02)
216#define SMCM_RX ((unsigned char)0x01)
217
218
219
220#define SCC_GSMRH_IRP ((uint)0x00040000)
221#define SCC_GSMRH_GDE ((uint)0x00010000)
222#define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000)
223#define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000)
224#define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000)
225#define SCC_GSMRH_REVD ((uint)0x00002000)
226#define SCC_GSMRH_TRX ((uint)0x00001000)
227#define SCC_GSMRH_TTX ((uint)0x00000800)
228#define SCC_GSMRH_CDP ((uint)0x00000400)
229#define SCC_GSMRH_CTSP ((uint)0x00000200)
230#define SCC_GSMRH_CDS ((uint)0x00000100)
231#define SCC_GSMRH_CTSS ((uint)0x00000080)
232#define SCC_GSMRH_TFL ((uint)0x00000040)
233#define SCC_GSMRH_RFW ((uint)0x00000020)
234#define SCC_GSMRH_TXSY ((uint)0x00000010)
235#define SCC_GSMRH_SYNL16 ((uint)0x0000000c)
236#define SCC_GSMRH_SYNL8 ((uint)0x00000008)
237#define SCC_GSMRH_SYNL4 ((uint)0x00000004)
238#define SCC_GSMRH_RTSM ((uint)0x00000002)
239#define SCC_GSMRH_RSYN ((uint)0x00000001)
240
241#define SCC_GSMRL_SIR ((uint)0x80000000)
242#define SCC_GSMRL_EDGE_NONE ((uint)0x60000000)
243#define SCC_GSMRL_EDGE_NEG ((uint)0x40000000)
244#define SCC_GSMRL_EDGE_POS ((uint)0x20000000)
245#define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000)
246#define SCC_GSMRL_TCI ((uint)0x10000000)
247#define SCC_GSMRL_TSNC_3 ((uint)0x0c000000)
248#define SCC_GSMRL_TSNC_4 ((uint)0x08000000)
249#define SCC_GSMRL_TSNC_14 ((uint)0x04000000)
250#define SCC_GSMRL_TSNC_INF ((uint)0x00000000)
251#define SCC_GSMRL_RINV ((uint)0x02000000)
252#define SCC_GSMRL_TINV ((uint)0x01000000)
253#define SCC_GSMRL_TPL_128 ((uint)0x00c00000)
254#define SCC_GSMRL_TPL_64 ((uint)0x00a00000)
255#define SCC_GSMRL_TPL_48 ((uint)0x00800000)
256#define SCC_GSMRL_TPL_32 ((uint)0x00600000)
257#define SCC_GSMRL_TPL_16 ((uint)0x00400000)
258#define SCC_GSMRL_TPL_8 ((uint)0x00200000)
259#define SCC_GSMRL_TPL_NONE ((uint)0x00000000)
260#define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000)
261#define SCC_GSMRL_TPP_01 ((uint)0x00100000)
262#define SCC_GSMRL_TPP_10 ((uint)0x00080000)
263#define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000)
264#define SCC_GSMRL_TEND ((uint)0x00040000)
265#define SCC_GSMRL_TDCR_32 ((uint)0x00030000)
266#define SCC_GSMRL_TDCR_16 ((uint)0x00020000)
267#define SCC_GSMRL_TDCR_8 ((uint)0x00010000)
268#define SCC_GSMRL_TDCR_1 ((uint)0x00000000)
269#define SCC_GSMRL_RDCR_32 ((uint)0x0000c000)
270#define SCC_GSMRL_RDCR_16 ((uint)0x00008000)
271#define SCC_GSMRL_RDCR_8 ((uint)0x00004000)
272#define SCC_GSMRL_RDCR_1 ((uint)0x00000000)
273#define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000)
274#define SCC_GSMRL_RENC_MANCH ((uint)0x00002000)
275#define SCC_GSMRL_RENC_FM0 ((uint)0x00001000)
276#define SCC_GSMRL_RENC_NRZI ((uint)0x00000800)
277#define SCC_GSMRL_RENC_NRZ ((uint)0x00000000)
278#define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600)
279#define SCC_GSMRL_TENC_MANCH ((uint)0x00000400)
280#define SCC_GSMRL_TENC_FM0 ((uint)0x00000200)
281#define SCC_GSMRL_TENC_NRZI ((uint)0x00000100)
282#define SCC_GSMRL_TENC_NRZ ((uint)0x00000000)
283#define SCC_GSMRL_DIAG_LE ((uint)0x000000c0)
284#define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080)
285#define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040)
286#define SCC_GSMRL_DIAG_NORM ((uint)0x00000000)
287#define SCC_GSMRL_ENR ((uint)0x00000020)
288#define SCC_GSMRL_ENT ((uint)0x00000010)
289#define SCC_GSMRL_MODE_ENET ((uint)0x0000000c)
290#define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009)
291#define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008)
292#define SCC_GSMRL_MODE_V14 ((uint)0x00000007)
293#define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006)
294#define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005)
295#define SCC_GSMRL_MODE_UART ((uint)0x00000004)
296#define SCC_GSMRL_MODE_SS7 ((uint)0x00000003)
297#define SCC_GSMRL_MODE_ATALK ((uint)0x00000002)
298#define SCC_GSMRL_MODE_HDLC ((uint)0x00000000)
299
300#define SCC_TODR_TOD ((ushort)0x8000)
301
302
303
304#define SCCM_TXE ((unsigned char)0x10)
305#define SCCM_BSY ((unsigned char)0x04)
306#define SCCM_TX ((unsigned char)0x02)
307#define SCCM_RX ((unsigned char)0x01)
308
309typedef struct scc_param {
310 ushort scc_rbase;
311 ushort scc_tbase;
312 u_char scc_rfcr;
313 u_char scc_tfcr;
314 ushort scc_mrblr;
315 uint scc_rstate;
316 uint scc_idp;
317 ushort scc_rbptr;
318 ushort scc_ibc;
319 uint scc_rxtmp;
320 uint scc_tstate;
321 uint scc_tdp;
322 ushort scc_tbptr;
323 ushort scc_tbc;
324 uint scc_txtmp;
325 uint scc_rcrc;
326 uint scc_tcrc;
327} sccp_t;
328
329
330
331#define SCC_EB ((u_char) 0x10)
332#define SCC_GBL ((u_char) 0x20)
333
334
335
336typedef struct scc_enet {
337 sccp_t sen_genscc;
338 uint sen_cpres;
339 uint sen_cmask;
340 uint sen_crcec;
341 uint sen_alec;
342 uint sen_disfc;
343 ushort sen_pads;
344 ushort sen_retlim;
345 ushort sen_retcnt;
346 ushort sen_maxflr;
347 ushort sen_minflr;
348 ushort sen_maxd1;
349 ushort sen_maxd2;
350 ushort sen_maxd;
351 ushort sen_dmacnt;
352 ushort sen_maxb;
353 ushort sen_gaddr1;
354 ushort sen_gaddr2;
355 ushort sen_gaddr3;
356 ushort sen_gaddr4;
357 uint sen_tbuf0data0;
358 uint sen_tbuf0data1;
359 uint sen_tbuf0rba;
360 uint sen_tbuf0crc;
361 ushort sen_tbuf0bcnt;
362 ushort sen_paddrh;
363 ushort sen_paddrm;
364 ushort sen_paddrl;
365 ushort sen_pper;
366 ushort sen_rfbdptr;
367 ushort sen_tfbdptr;
368 ushort sen_tlbdptr;
369 uint sen_tbuf1data0;
370 uint sen_tbuf1data1;
371 uint sen_tbuf1rba;
372 uint sen_tbuf1crc;
373 ushort sen_tbuf1bcnt;
374 ushort sen_txlen;
375 ushort sen_iaddr1;
376 ushort sen_iaddr2;
377 ushort sen_iaddr3;
378 ushort sen_iaddr4;
379 ushort sen_boffcnt;
380
381
382
383
384 ushort sen_taddrh;
385 ushort sen_taddrm;
386 ushort sen_taddrl;
387} scc_enet_t;
388
389
390
391
392#define SCCE_ENET_GRA ((ushort)0x0080)
393#define SCCE_ENET_TXE ((ushort)0x0010)
394#define SCCE_ENET_RXF ((ushort)0x0008)
395#define SCCE_ENET_BSY ((ushort)0x0004)
396#define SCCE_ENET_TXB ((ushort)0x0002)
397#define SCCE_ENET_RXB ((ushort)0x0001)
398
399
400
401#define SCC_PSMR_HBC ((ushort)0x8000)
402#define SCC_PSMR_FC ((ushort)0x4000)
403#define SCC_PSMR_RSH ((ushort)0x2000)
404#define SCC_PSMR_IAM ((ushort)0x1000)
405#define SCC_PSMR_ENCRC ((ushort)0x0800)
406#define SCC_PSMR_PRO ((ushort)0x0200)
407#define SCC_PSMR_BRO ((ushort)0x0100)
408#define SCC_PSMR_SBT ((ushort)0x0080)
409#define SCC_PSMR_LPB ((ushort)0x0040)
410#define SCC_PSMR_SIP ((ushort)0x0020)
411#define SCC_PSMR_LCW ((ushort)0x0010)
412#define SCC_PSMR_NIB22 ((ushort)0x000a)
413#define SCC_PSMR_FDE ((ushort)0x0001)
414
415
416
417typedef struct scc_uart {
418 sccp_t scc_genscc;
419 uint scc_res1;
420 uint scc_res2;
421 ushort scc_maxidl;
422 ushort scc_idlc;
423 ushort scc_brkcr;
424 ushort scc_parec;
425 ushort scc_frmec;
426 ushort scc_nosec;
427 ushort scc_brkec;
428 ushort scc_brkln;
429 ushort scc_uaddr1;
430 ushort scc_uaddr2;
431 ushort scc_rtemp;
432 ushort scc_toseq;
433 ushort scc_char1;
434 ushort scc_char2;
435 ushort scc_char3;
436 ushort scc_char4;
437 ushort scc_char5;
438 ushort scc_char6;
439 ushort scc_char7;
440 ushort scc_char8;
441 ushort scc_rccm;
442 ushort scc_rccr;
443 ushort scc_rlbc;
444} scc_uart_t;
445
446
447
448#define UART_SCCM_GLR ((ushort)0x1000)
449#define UART_SCCM_GLT ((ushort)0x0800)
450#define UART_SCCM_AB ((ushort)0x0200)
451#define UART_SCCM_IDL ((ushort)0x0100)
452#define UART_SCCM_GRA ((ushort)0x0080)
453#define UART_SCCM_BRKE ((ushort)0x0040)
454#define UART_SCCM_BRKS ((ushort)0x0020)
455#define UART_SCCM_CCR ((ushort)0x0008)
456#define UART_SCCM_BSY ((ushort)0x0004)
457#define UART_SCCM_TX ((ushort)0x0002)
458#define UART_SCCM_RX ((ushort)0x0001)
459
460
461
462#define SCU_PSMR_FLC ((ushort)0x8000)
463#define SCU_PSMR_SL ((ushort)0x4000)
464#define SCU_PSMR_CL ((ushort)0x3000)
465#define SCU_PSMR_UM ((ushort)0x0c00)
466#define SCU_PSMR_FRZ ((ushort)0x0200)
467#define SCU_PSMR_RZS ((ushort)0x0100)
468#define SCU_PSMR_SYN ((ushort)0x0080)
469#define SCU_PSMR_DRT ((ushort)0x0040)
470#define SCU_PSMR_PEN ((ushort)0x0010)
471#define SCU_PSMR_RPM ((ushort)0x000c)
472#define SCU_PSMR_REVP ((ushort)0x0008)
473#define SCU_PSMR_TPM ((ushort)0x0003)
474#define SCU_PSMR_TEVP ((ushort)0x0002)
475
476
477
478typedef struct scc_trans {
479 sccp_t st_genscc;
480 uint st_cpres;
481 uint st_cmask;
482} scc_trans_t;
483
484
485
486#define FCC_GFMR_DIAG_NORM ((uint)0x00000000)
487#define FCC_GFMR_DIAG_LE ((uint)0x40000000)
488#define FCC_GFMR_DIAG_AE ((uint)0x80000000)
489#define FCC_GFMR_DIAG_ALE ((uint)0xc0000000)
490#define FCC_GFMR_TCI ((uint)0x20000000)
491#define FCC_GFMR_TRX ((uint)0x10000000)
492#define FCC_GFMR_TTX ((uint)0x08000000)
493#define FCC_GFMR_CDP ((uint)0x04000000)
494#define FCC_GFMR_CTSP ((uint)0x02000000)
495#define FCC_GFMR_CDS ((uint)0x01000000)
496#define FCC_GFMR_CTSS ((uint)0x00800000)
497#define FCC_GFMR_SYNL_NONE ((uint)0x00000000)
498#define FCC_GFMR_SYNL_AUTO ((uint)0x00004000)
499#define FCC_GFMR_SYNL_8 ((uint)0x00008000)
500#define FCC_GFMR_SYNL_16 ((uint)0x0000c000)
501#define FCC_GFMR_RTSM ((uint)0x00002000)
502#define FCC_GFMR_RENC_NRZ ((uint)0x00000000)
503#define FCC_GFMR_RENC_NRZI ((uint)0x00000800)
504#define FCC_GFMR_REVD ((uint)0x00000400)
505#define FCC_GFMR_TENC_NRZ ((uint)0x00000000)
506#define FCC_GFMR_TENC_NRZI ((uint)0x00000100)
507#define FCC_GFMR_TCRC_16 ((uint)0x00000000)
508#define FCC_GFMR_TCRC_32 ((uint)0x00000080)
509#define FCC_GFMR_ENR ((uint)0x00000020)
510#define FCC_GFMR_ENT ((uint)0x00000010)
511#define FCC_GFMR_MODE_ENET ((uint)0x0000000c)
512#define FCC_GFMR_MODE_ATM ((uint)0x0000000a)
513#define FCC_GFMR_MODE_HDLC ((uint)0x00000000)
514
515
516
517typedef struct fcc_param {
518 ushort fcc_riptr;
519 ushort fcc_tiptr;
520 ushort fcc_res1;
521 ushort fcc_mrblr;
522 uint fcc_rstate;
523 uint fcc_rbase;
524 ushort fcc_rbdstat;
525 ushort fcc_rbdlen;
526 uint fcc_rdptr;
527 uint fcc_tstate;
528 uint fcc_tbase;
529 ushort fcc_tbdstat;
530 ushort fcc_tbdlen;
531 uint fcc_tdptr;
532 uint fcc_rbptr;
533 uint fcc_tbptr;
534 uint fcc_rcrc;
535 uint fcc_res2;
536 uint fcc_tcrc;
537} fccp_t;
538
539
540
541
542typedef struct fcc_enet {
543 fccp_t fen_genfcc;
544 uint fen_statbuf;
545 uint fen_camptr;
546 uint fen_cmask;
547 uint fen_cpres;
548 uint fen_crcec;
549 uint fen_alec;
550 uint fen_disfc;
551 ushort fen_retlim;
552 ushort fen_retcnt;
553 ushort fen_pper;
554 ushort fen_boffcnt;
555 uint fen_gaddrh;
556 uint fen_gaddrl;
557 ushort fen_tfcstat;
558 ushort fen_tfclen;
559 uint fen_tfcptr;
560 ushort fen_mflr;
561 ushort fen_paddrh;
562 ushort fen_paddrm;
563 ushort fen_paddrl;
564 ushort fen_ibdcount;
565 ushort fen_ibdstart;
566 ushort fen_ibdend;
567 ushort fen_txlen;
568 uint fen_ibdbase[8];
569 uint fen_iaddrh;
570 uint fen_iaddrl;
571 ushort fen_minflr;
572 ushort fen_taddrh;
573 ushort fen_taddrm;
574 ushort fen_taddrl;
575 ushort fen_padptr;
576 ushort fen_cftype;
577 ushort fen_cfrange;
578 ushort fen_maxb;
579 ushort fen_maxd1;
580 ushort fen_maxd2;
581 ushort fen_maxd;
582 ushort fen_dmacnt;
583 uint fen_octc;
584 uint fen_colc;
585 uint fen_broc;
586 uint fen_mulc;
587 uint fen_uspc;
588 uint fen_frgc;
589 uint fen_ospc;
590 uint fen_jbrc;
591 uint fen_p64c;
592 uint fen_p65c;
593 uint fen_p128c;
594 uint fen_p256c;
595 uint fen_p512c;
596 uint fen_p1024c;
597 uint fen_cambuf;
598 ushort fen_rfthr;
599 ushort fen_rfcnt;
600} fcc_enet_t;
601
602
603
604#define FCC_ENET_GRA ((ushort)0x0080)
605#define FCC_ENET_RXC ((ushort)0x0040)
606#define FCC_ENET_TXC ((ushort)0x0020)
607#define FCC_ENET_TXE ((ushort)0x0010)
608#define FCC_ENET_RXF ((ushort)0x0008)
609#define FCC_ENET_BSY ((ushort)0x0004)
610#define FCC_ENET_TXB ((ushort)0x0002)
611#define FCC_ENET_RXB ((ushort)0x0001)
612
613
614
615#define FCC_PSMR_HBC ((uint)0x80000000)
616#define FCC_PSMR_FC ((uint)0x40000000)
617#define FCC_PSMR_SBT ((uint)0x20000000)
618#define FCC_PSMR_LPB ((uint)0x10000000)
619#define FCC_PSMR_LCW ((uint)0x08000000)
620#define FCC_PSMR_FDE ((uint)0x04000000)
621#define FCC_PSMR_MON ((uint)0x02000000)
622#define FCC_PSMR_PRO ((uint)0x00400000)
623#define FCC_PSMR_FCE ((uint)0x00200000)
624#define FCC_PSMR_RSH ((uint)0x00100000)
625#define FCC_PSMR_CAM ((uint)0x00000400)
626#define FCC_PSMR_BRO ((uint)0x00000200)
627#define FCC_PSMR_ENCRC ((uint)0x00000080)
628
629
630
631typedef struct iic {
632 ushort iic_rbase;
633 ushort iic_tbase;
634 u_char iic_rfcr;
635 u_char iic_tfcr;
636 ushort iic_mrblr;
637 uint iic_rstate;
638 uint iic_rdp;
639 ushort iic_rbptr;
640 ushort iic_rbc;
641 uint iic_rxtmp;
642 uint iic_tstate;
643 uint iic_tdp;
644 ushort iic_tbptr;
645 ushort iic_tbc;
646 uint iic_txtmp;
647} iic_t;
648
649
650
651typedef struct idma {
652 ushort ibase;
653 ushort dcm;
654 ushort ibdptr;
655 ushort dpr_buf;
656 ushort buf_inv;
657 ushort ss_max;
658 ushort dpr_in_ptr;
659 ushort sts;
660 ushort dpr_out_ptr;
661 ushort seob;
662 ushort deob;
663 ushort dts;
664 ushort ret_add;
665 ushort res0;
666 uint bd_cnt;
667 uint s_ptr;
668 uint d_ptr;
669 uint istate;
670 u_char res1[20];
671} idma_t;
672
673
674
675#define IDMA_DCM_FB ((ushort)0x8000)
676#define IDMA_DCM_LP ((ushort)0x4000)
677#define IDMA_DCM_TC2 ((ushort)0x0400)
678#define IDMA_DCM_DMA_WRAP_MASK ((ushort)0x01c0)
679#define IDMA_DCM_DMA_WRAP_64 ((ushort)0x0000)
680#define IDMA_DCM_DMA_WRAP_128 ((ushort)0x0040)
681#define IDMA_DCM_DMA_WRAP_256 ((ushort)0x0080)
682#define IDMA_DCM_DMA_WRAP_512 ((ushort)0x00c0)
683#define IDMA_DCM_DMA_WRAP_1024 ((ushort)0x0100)
684#define IDMA_DCM_DMA_WRAP_2048 ((ushort)0x0140)
685#define IDMA_DCM_SINC ((ushort)0x0020)
686#define IDMA_DCM_DINC ((ushort)0x0010)
687#define IDMA_DCM_ERM ((ushort)0x0008)
688#define IDMA_DCM_DT ((ushort)0x0004)
689#define IDMA_DCM_SD_MASK ((ushort)0x0003)
690#define IDMA_DCM_SD_MEM2MEM ((ushort)0x0000)
691#define IDMA_DCM_SD_PER2MEM ((ushort)0x0002)
692#define IDMA_DCM_SD_MEM2PER ((ushort)0x0001)
693
694
695
696typedef struct idma_bd {
697 uint flags;
698 uint len;
699 uint src;
700 uint dst;
701} idma_bd_t;
702
703
704
705#define IDMA_BD_V ((uint)0x80000000)
706#define IDMA_BD_W ((uint)0x20000000)
707#define IDMA_BD_I ((uint)0x10000000)
708#define IDMA_BD_L ((uint)0x08000000)
709#define IDMA_BD_CM ((uint)0x02000000)
710#define IDMA_BD_SDN ((uint)0x00400000)
711#define IDMA_BD_DDN ((uint)0x00200000)
712#define IDMA_BD_DGBL ((uint)0x00100000)
713#define IDMA_BD_DBO_LE ((uint)0x00040000)
714#define IDMA_BD_DBO_BE ((uint)0x00080000)
715#define IDMA_BD_DDTB ((uint)0x00010000)
716#define IDMA_BD_SGBL ((uint)0x00002000)
717#define IDMA_BD_SBO_LE ((uint)0x00000800)
718#define IDMA_BD_SBO_BE ((uint)0x00001000)
719#define IDMA_BD_SDTB ((uint)0x00000200)
720
721
722
723typedef struct im_idma {
724 u_char idsr;
725 u_char res0[3];
726 u_char idmr;
727 u_char res1[3];
728} im_idma_t;
729
730
731
732#define IDMA_EVENT_SC ((unsigned char)0x08)
733#define IDMA_EVENT_OB ((unsigned char)0x04)
734#define IDMA_EVENT_EDN ((unsigned char)0x02)
735#define IDMA_EVENT_BC ((unsigned char)0x01)
736
737
738
739#define RCCR_TIME ((uint)0x80000000)
740#define RCCR_TIMEP_MASK ((uint)0x3f000000)
741#define RCCR_DR0M ((uint)0x00800000)
742#define RCCR_DR1M ((uint)0x00400000)
743#define RCCR_DR2M ((uint)0x00000080)
744#define RCCR_DR3M ((uint)0x00000040)
745#define RCCR_DR0QP_MASK ((uint)0x00300000)
746#define RCCR_DR0QP_HIGH ((uint)0x00000000)
747#define RCCR_DR0QP_MED ((uint)0x00100000)
748#define RCCR_DR0QP_LOW ((uint)0x00200000)
749#define RCCR_DR1QP_MASK ((uint)0x00030000)
750#define RCCR_DR1QP_HIGH ((uint)0x00000000)
751#define RCCR_DR1QP_MED ((uint)0x00010000)
752#define RCCR_DR1QP_LOW ((uint)0x00020000)
753#define RCCR_DR2QP_MASK ((uint)0x00000030)
754#define RCCR_DR2QP_HIGH ((uint)0x00000000)
755#define RCCR_DR2QP_MED ((uint)0x00000010)
756#define RCCR_DR2QP_LOW ((uint)0x00000020)
757#define RCCR_DR3QP_MASK ((uint)0x00000003)
758#define RCCR_DR3QP_HIGH ((uint)0x00000000)
759#define RCCR_DR3QP_MED ((uint)0x00000001)
760#define RCCR_DR3QP_LOW ((uint)0x00000002)
761#define RCCR_EIE ((uint)0x00080000)
762#define RCCR_SCD ((uint)0x00040000)
763#define RCCR_ERAM_MASK ((uint)0x0000e000)
764#define RCCR_ERAM_0KB ((uint)0x00000000)
765#define RCCR_ERAM_2KB ((uint)0x00002000)
766#define RCCR_ERAM_4KB ((uint)0x00004000)
767#define RCCR_ERAM_6KB ((uint)0x00006000)
768#define RCCR_ERAM_8KB ((uint)0x00008000)
769#define RCCR_ERAM_10KB ((uint)0x0000a000)
770#define RCCR_ERAM_12KB ((uint)0x0000c000)
771#define RCCR_EDM0 ((uint)0x00000800)
772#define RCCR_EDM1 ((uint)0x00000400)
773#define RCCR_EDM2 ((uint)0x00000200)
774#define RCCR_EDM3 ((uint)0x00000100)
775#define RCCR_DEM01 ((uint)0x00000008)
776#define RCCR_DEM23 ((uint)0x00000004)
777
778
779
780
781#define CMXFCR_FC1 0x40000000
782#define CMXFCR_RF1CS_MSK 0x38000000
783#define CMXFCR_TF1CS_MSK 0x07000000
784#define CMXFCR_FC2 0x00400000
785#define CMXFCR_RF2CS_MSK 0x00380000
786#define CMXFCR_TF2CS_MSK 0x00070000
787#define CMXFCR_FC3 0x00004000
788#define CMXFCR_RF3CS_MSK 0x00003800
789#define CMXFCR_TF3CS_MSK 0x00000700
790
791#define CMXFCR_RF1CS_BRG5 0x00000000
792#define CMXFCR_RF1CS_BRG6 0x08000000
793#define CMXFCR_RF1CS_BRG7 0x10000000
794#define CMXFCR_RF1CS_BRG8 0x18000000
795#define CMXFCR_RF1CS_CLK9 0x20000000
796#define CMXFCR_RF1CS_CLK10 0x28000000
797#define CMXFCR_RF1CS_CLK11 0x30000000
798#define CMXFCR_RF1CS_CLK12 0x38000000
799
800#define CMXFCR_TF1CS_BRG5 0x00000000
801#define CMXFCR_TF1CS_BRG6 0x01000000
802#define CMXFCR_TF1CS_BRG7 0x02000000
803#define CMXFCR_TF1CS_BRG8 0x03000000
804#define CMXFCR_TF1CS_CLK9 0x04000000
805#define CMXFCR_TF1CS_CLK10 0x05000000
806#define CMXFCR_TF1CS_CLK11 0x06000000
807#define CMXFCR_TF1CS_CLK12 0x07000000
808
809#define CMXFCR_RF2CS_BRG5 0x00000000
810#define CMXFCR_RF2CS_BRG6 0x00080000
811#define CMXFCR_RF2CS_BRG7 0x00100000
812#define CMXFCR_RF2CS_BRG8 0x00180000
813#define CMXFCR_RF2CS_CLK13 0x00200000
814#define CMXFCR_RF2CS_CLK14 0x00280000
815#define CMXFCR_RF2CS_CLK15 0x00300000
816#define CMXFCR_RF2CS_CLK16 0x00380000
817
818#define CMXFCR_TF2CS_BRG5 0x00000000
819#define CMXFCR_TF2CS_BRG6 0x00010000
820#define CMXFCR_TF2CS_BRG7 0x00020000
821#define CMXFCR_TF2CS_BRG8 0x00030000
822#define CMXFCR_TF2CS_CLK13 0x00040000
823#define CMXFCR_TF2CS_CLK14 0x00050000
824#define CMXFCR_TF2CS_CLK15 0x00060000
825#define CMXFCR_TF2CS_CLK16 0x00070000
826
827#define CMXFCR_RF3CS_BRG5 0x00000000
828#define CMXFCR_RF3CS_BRG6 0x00000800
829#define CMXFCR_RF3CS_BRG7 0x00001000
830#define CMXFCR_RF3CS_BRG8 0x00001800
831#define CMXFCR_RF3CS_CLK13 0x00002000
832#define CMXFCR_RF3CS_CLK14 0x00002800
833#define CMXFCR_RF3CS_CLK15 0x00003000
834#define CMXFCR_RF3CS_CLK16 0x00003800
835
836#define CMXFCR_TF3CS_BRG5 0x00000000
837#define CMXFCR_TF3CS_BRG6 0x00000100
838#define CMXFCR_TF3CS_BRG7 0x00000200
839#define CMXFCR_TF3CS_BRG8 0x00000300
840#define CMXFCR_TF3CS_CLK13 0x00000400
841#define CMXFCR_TF3CS_CLK14 0x00000500
842#define CMXFCR_TF3CS_CLK15 0x00000600
843#define CMXFCR_TF3CS_CLK16 0x00000700
844
845
846
847
848#define CMXSCR_GR1 0x80000000
849#define CMXSCR_SC1 0x40000000
850#define CMXSCR_RS1CS_MSK 0x38000000
851#define CMXSCR_TS1CS_MSK 0x07000000
852#define CMXSCR_GR2 0x00800000
853#define CMXSCR_SC2 0x00400000
854#define CMXSCR_RS2CS_MSK 0x00380000
855#define CMXSCR_TS2CS_MSK 0x00070000
856#define CMXSCR_GR3 0x00008000
857#define CMXSCR_SC3 0x00004000
858#define CMXSCR_RS3CS_MSK 0x00003800
859#define CMXSCR_TS3CS_MSK 0x00000700
860#define CMXSCR_GR4 0x00000080
861#define CMXSCR_SC4 0x00000040
862#define CMXSCR_RS4CS_MSK 0x00000038
863#define CMXSCR_TS4CS_MSK 0x00000007
864
865#define CMXSCR_RS1CS_BRG1 0x00000000
866#define CMXSCR_RS1CS_BRG2 0x08000000
867#define CMXSCR_RS1CS_BRG3 0x10000000
868#define CMXSCR_RS1CS_BRG4 0x18000000
869#define CMXSCR_RS1CS_CLK11 0x20000000
870#define CMXSCR_RS1CS_CLK12 0x28000000
871#define CMXSCR_RS1CS_CLK3 0x30000000
872#define CMXSCR_RS1CS_CLK4 0x38000000
873
874#define CMXSCR_TS1CS_BRG1 0x00000000
875#define CMXSCR_TS1CS_BRG2 0x01000000
876#define CMXSCR_TS1CS_BRG3 0x02000000
877#define CMXSCR_TS1CS_BRG4 0x03000000
878#define CMXSCR_TS1CS_CLK11 0x04000000
879#define CMXSCR_TS1CS_CLK12 0x05000000
880#define CMXSCR_TS1CS_CLK3 0x06000000
881#define CMXSCR_TS1CS_CLK4 0x07000000
882
883#define CMXSCR_RS2CS_BRG1 0x00000000
884#define CMXSCR_RS2CS_BRG2 0x00080000
885#define CMXSCR_RS2CS_BRG3 0x00100000
886#define CMXSCR_RS2CS_BRG4 0x00180000
887#define CMXSCR_RS2CS_CLK11 0x00200000
888#define CMXSCR_RS2CS_CLK12 0x00280000
889#define CMXSCR_RS2CS_CLK3 0x00300000
890#define CMXSCR_RS2CS_CLK4 0x00380000
891
892#define CMXSCR_TS2CS_BRG1 0x00000000
893#define CMXSCR_TS2CS_BRG2 0x00010000
894#define CMXSCR_TS2CS_BRG3 0x00020000
895#define CMXSCR_TS2CS_BRG4 0x00030000
896#define CMXSCR_TS2CS_CLK11 0x00040000
897#define CMXSCR_TS2CS_CLK12 0x00050000
898#define CMXSCR_TS2CS_CLK3 0x00060000
899#define CMXSCR_TS2CS_CLK4 0x00070000
900
901#define CMXSCR_RS3CS_BRG1 0x00000000
902#define CMXSCR_RS3CS_BRG2 0x00000800
903#define CMXSCR_RS3CS_BRG3 0x00001000
904#define CMXSCR_RS3CS_BRG4 0x00001800
905#define CMXSCR_RS3CS_CLK5 0x00002000
906#define CMXSCR_RS3CS_CLK6 0x00002800
907#define CMXSCR_RS3CS_CLK7 0x00003000
908#define CMXSCR_RS3CS_CLK8 0x00003800
909
910#define CMXSCR_TS3CS_BRG1 0x00000000
911#define CMXSCR_TS3CS_BRG2 0x00000100
912#define CMXSCR_TS3CS_BRG3 0x00000200
913#define CMXSCR_TS3CS_BRG4 0x00000300
914#define CMXSCR_TS3CS_CLK5 0x00000400
915#define CMXSCR_TS3CS_CLK6 0x00000500
916#define CMXSCR_TS3CS_CLK7 0x00000600
917#define CMXSCR_TS3CS_CLK8 0x00000700
918
919#define CMXSCR_RS4CS_BRG1 0x00000000
920#define CMXSCR_RS4CS_BRG2 0x00000008
921#define CMXSCR_RS4CS_BRG3 0x00000010
922#define CMXSCR_RS4CS_BRG4 0x00000018
923#define CMXSCR_RS4CS_CLK5 0x00000020
924#define CMXSCR_RS4CS_CLK6 0x00000028
925#define CMXSCR_RS4CS_CLK7 0x00000030
926#define CMXSCR_RS4CS_CLK8 0x00000038
927
928#define CMXSCR_TS4CS_BRG1 0x00000000
929#define CMXSCR_TS4CS_BRG2 0x00000001
930#define CMXSCR_TS4CS_BRG3 0x00000002
931#define CMXSCR_TS4CS_BRG4 0x00000003
932#define CMXSCR_TS4CS_CLK5 0x00000004
933#define CMXSCR_TS4CS_CLK6 0x00000005
934#define CMXSCR_TS4CS_CLK7 0x00000006
935#define CMXSCR_TS4CS_CLK8 0x00000007
936
937
938
939
940#define SIUMCR_BBD 0x80000000
941#define SIUMCR_ESE 0x40000000
942#define SIUMCR_PBSE 0x20000000
943#define SIUMCR_CDIS 0x10000000
944#define SIUMCR_DPPC00 0x00000000
945#define SIUMCR_DPPC01 0x04000000
946#define SIUMCR_DPPC10 0x08000000
947#define SIUMCR_DPPC11 0x0c000000
948#define SIUMCR_L2CPC00 0x00000000
949#define SIUMCR_L2CPC01 0x01000000
950#define SIUMCR_L2CPC10 0x02000000
951#define SIUMCR_L2CPC11 0x03000000
952#define SIUMCR_LBPC00 0x00000000
953#define SIUMCR_LBPC01 0x00400000
954#define SIUMCR_LBPC10 0x00800000
955#define SIUMCR_LBPC11 0x00c00000
956#define SIUMCR_APPC00 0x00000000
957#define SIUMCR_APPC01 0x00100000
958#define SIUMCR_APPC10 0x00200000
959#define SIUMCR_APPC11 0x00300000
960#define SIUMCR_CS10PC00 0x00000000
961#define SIUMCR_CS10PC01 0x00040000
962#define SIUMCR_CS10PC10 0x00080000
963#define SIUMCR_CS10PC11 0x000c0000
964#define SIUMCR_BCTLC00 0x00000000
965#define SIUMCR_BCTLC01 0x00010000
966#define SIUMCR_BCTLC10 0x00020000
967#define SIUMCR_BCTLC11 0x00030000
968#define SIUMCR_MMR00 0x00000000
969#define SIUMCR_MMR01 0x00004000
970#define SIUMCR_MMR10 0x00008000
971#define SIUMCR_MMR11 0x0000c000
972#define SIUMCR_LPBSE 0x00002000
973
974
975
976
977#define SCCR_PCI_MODE 0x00000100
978#define SCCR_PCI_MODCK 0x00000080
979#define SCCR_PCIDF_MSK 0x00000078
980#define SCCR_PCIDF_SHIFT 3
981
982#ifndef CPM_IMMR_OFFSET
983#define CPM_IMMR_OFFSET 0x101a8
984#endif
985
986#define FCC_PSMR_RMII ((uint)0x00020000)
987
988
989
990
991
992
993#define PC_CLK(x) ((uint)(1<<(x-1)))
994
995#define CMXFCR_RF1CS(x) ((uint)((x-5)<<27))
996#define CMXFCR_TF1CS(x) ((uint)((x-5)<<24))
997#define CMXFCR_RF2CS(x) ((uint)((x-9)<<19))
998#define CMXFCR_TF2CS(x) ((uint)((x-9)<<16))
999#define CMXFCR_RF3CS(x) ((uint)((x-9)<<11))
1000#define CMXFCR_TF3CS(x) ((uint)((x-9)<<8))
1001
1002#define PC_F1RXCLK PC_CLK(F1_RXCLK)
1003#define PC_F1TXCLK PC_CLK(F1_TXCLK)
1004#define CMX1_CLK_ROUTE (CMXFCR_RF1CS(F1_RXCLK) | CMXFCR_TF1CS(F1_TXCLK))
1005#define CMX1_CLK_MASK ((uint)0xff000000)
1006
1007#define PC_F2RXCLK PC_CLK(F2_RXCLK)
1008#define PC_F2TXCLK PC_CLK(F2_TXCLK)
1009#define CMX2_CLK_ROUTE (CMXFCR_RF2CS(F2_RXCLK) | CMXFCR_TF2CS(F2_TXCLK))
1010#define CMX2_CLK_MASK ((uint)0x00ff0000)
1011
1012#define PC_F3RXCLK PC_CLK(F3_RXCLK)
1013#define PC_F3TXCLK PC_CLK(F3_TXCLK)
1014#define CMX3_CLK_ROUTE (CMXFCR_RF3CS(F3_RXCLK) | CMXFCR_TF3CS(F3_TXCLK))
1015#define CMX3_CLK_MASK ((uint)0x0000ff00)
1016
1017#define CPMUX_CLK_MASK (CMX3_CLK_MASK | CMX2_CLK_MASK)
1018#define CPMUX_CLK_ROUTE (CMX3_CLK_ROUTE | CMX2_CLK_ROUTE)
1019
1020#define CLK_TRX (PC_F3TXCLK | PC_F3RXCLK | PC_F2TXCLK | PC_F2RXCLK)
1021
1022
1023
1024
1025#define PA1_COL 0x00000001U
1026#define PA1_CRS 0x00000002U
1027#define PA1_TXER 0x00000004U
1028#define PA1_TXEN 0x00000008U
1029#define PA1_RXDV 0x00000010U
1030#define PA1_RXER 0x00000020U
1031#define PA1_TXDAT 0x00003c00U
1032#define PA1_RXDAT 0x0003c000U
1033#define PA1_PSORA0 (PA1_RXDAT | PA1_TXDAT)
1034#define PA1_PSORA1 (PA1_COL | PA1_CRS | PA1_TXER | PA1_TXEN | \
1035 PA1_RXDV | PA1_RXER)
1036#define PA1_DIRA0 (PA1_RXDAT | PA1_CRS | PA1_COL | PA1_RXER | PA1_RXDV)
1037#define PA1_DIRA1 (PA1_TXDAT | PA1_TXEN | PA1_TXER)
1038
1039
1040
1041
1042
1043#define PB2_TXER 0x00000001U
1044#define PB2_RXDV 0x00000002U
1045#define PB2_TXEN 0x00000004U
1046#define PB2_RXER 0x00000008U
1047#define PB2_COL 0x00000010U
1048#define PB2_CRS 0x00000020U
1049#define PB2_TXDAT 0x000003c0U
1050#define PB2_RXDAT 0x00003c00U
1051#define PB2_PSORB0 (PB2_RXDAT | PB2_TXDAT | PB2_CRS | PB2_COL | \
1052 PB2_RXER | PB2_RXDV | PB2_TXER)
1053#define PB2_PSORB1 (PB2_TXEN)
1054#define PB2_DIRB0 (PB2_RXDAT | PB2_CRS | PB2_COL | PB2_RXER | PB2_RXDV)
1055#define PB2_DIRB1 (PB2_TXDAT | PB2_TXEN | PB2_TXER)
1056
1057
1058
1059
1060
1061#define PB3_RXDV 0x00004000U
1062#define PB3_RXER 0x00008000U
1063#define PB3_TXER 0x00010000U
1064#define PB3_TXEN 0x00020000U
1065#define PB3_COL 0x00040000U
1066#define PB3_CRS 0x00080000U
1067#define PB3_TXDAT 0x0f000000U
1068#define PC3_TXDAT 0x00000010U
1069#define PB3_RXDAT 0x00f00000U
1070#define PB3_PSORB0 (PB3_RXDAT | PB3_TXDAT | PB3_CRS | PB3_COL | \
1071 PB3_RXER | PB3_RXDV | PB3_TXER | PB3_TXEN)
1072#define PB3_PSORB1 0
1073#define PB3_DIRB0 (PB3_RXDAT | PB3_CRS | PB3_COL | PB3_RXER | PB3_RXDV)
1074#define PB3_DIRB1 (PB3_TXDAT | PB3_TXEN | PB3_TXER)
1075#define PC3_DIRC1 (PC3_TXDAT)
1076
1077
1078#define FCC_MEM_OFFSET(x) (CPM_FCC_SPECIAL_BASE + (x*128))
1079#define FCC1_MEM_OFFSET FCC_MEM_OFFSET(0)
1080#define FCC2_MEM_OFFSET FCC_MEM_OFFSET(1)
1081#define FCC3_MEM_OFFSET FCC_MEM_OFFSET(2)
1082
1083
1084
1085enum cpm_clk_dir {
1086 CPM_CLK_RX,
1087 CPM_CLK_TX,
1088 CPM_CLK_RTX
1089};
1090
1091enum cpm_clk_target {
1092 CPM_CLK_SCC1,
1093 CPM_CLK_SCC2,
1094 CPM_CLK_SCC3,
1095 CPM_CLK_SCC4,
1096 CPM_CLK_FCC1,
1097 CPM_CLK_FCC2,
1098 CPM_CLK_FCC3,
1099 CPM_CLK_SMC1,
1100 CPM_CLK_SMC2,
1101};
1102
1103enum cpm_clk {
1104 CPM_CLK_NONE = 0,
1105 CPM_BRG1,
1106 CPM_BRG2,
1107 CPM_BRG3,
1108 CPM_BRG4,
1109 CPM_BRG5,
1110 CPM_BRG6,
1111 CPM_BRG7,
1112 CPM_BRG8,
1113 CPM_CLK1,
1114 CPM_CLK2,
1115 CPM_CLK3,
1116 CPM_CLK4,
1117 CPM_CLK5,
1118 CPM_CLK6,
1119 CPM_CLK7,
1120 CPM_CLK8,
1121 CPM_CLK9,
1122 CPM_CLK10,
1123 CPM_CLK11,
1124 CPM_CLK12,
1125 CPM_CLK13,
1126 CPM_CLK14,
1127 CPM_CLK15,
1128 CPM_CLK16,
1129 CPM_CLK17,
1130 CPM_CLK18,
1131 CPM_CLK19,
1132 CPM_CLK20,
1133 CPM_CLK_DUMMY
1134};
1135
1136int __init cpm2_clk_setup(enum cpm_clk_target target, int clock, int mode);
1137int __init cpm2_smc_clk_setup(enum cpm_clk_target target, int clock);
1138
1139#define CPM_PIN_INPUT 0
1140#define CPM_PIN_OUTPUT 1
1141#define CPM_PIN_PRIMARY 0
1142#define CPM_PIN_SECONDARY 2
1143#define CPM_PIN_GPIO 4
1144#define CPM_PIN_OPENDRAIN 8
1145
1146void __init cpm2_set_pin(int port, int pin, int flags);
1147
1148#endif
1149#endif
1150