1
2
3
4
5
6
7
8
9
10
11
12#include <linux/clk.h>
13#include <linux/crypto.h>
14#include <linux/delay.h>
15#include <linux/dma-mapping.h>
16#include <linux/interrupt.h>
17#include <linux/io.h>
18#include <linux/irq.h>
19#include <linux/module.h>
20#include <linux/of.h>
21#include <linux/of_device.h>
22#include <linux/platform_device.h>
23#include <linux/pm_runtime.h>
24#include <linux/reset.h>
25#include <crypto/internal/rng.h>
26#include <crypto/internal/skcipher.h>
27
28#include "sun8i-ce.h"
29
30
31
32
33
34
35
36static const struct ce_variant ce_h3_variant = {
37 .alg_cipher = { CE_ALG_AES, CE_ALG_DES, CE_ALG_3DES,
38 },
39 .alg_hash = { CE_ALG_MD5, CE_ALG_SHA1, CE_ALG_SHA224, CE_ALG_SHA256,
40 CE_ALG_SHA384, CE_ALG_SHA512
41 },
42 .op_mode = { CE_OP_ECB, CE_OP_CBC
43 },
44 .ce_clks = {
45 { "bus", 0, 200000000 },
46 { "mod", 50000000, 0 },
47 },
48 .esr = ESR_H3,
49 .prng = CE_ALG_PRNG,
50 .trng = CE_ID_NOTSUPP,
51};
52
53static const struct ce_variant ce_h5_variant = {
54 .alg_cipher = { CE_ALG_AES, CE_ALG_DES, CE_ALG_3DES,
55 },
56 .alg_hash = { CE_ALG_MD5, CE_ALG_SHA1, CE_ALG_SHA224, CE_ALG_SHA256,
57 CE_ID_NOTSUPP, CE_ID_NOTSUPP
58 },
59 .op_mode = { CE_OP_ECB, CE_OP_CBC
60 },
61 .ce_clks = {
62 { "bus", 0, 200000000 },
63 { "mod", 300000000, 0 },
64 },
65 .esr = ESR_H5,
66 .prng = CE_ALG_PRNG,
67 .trng = CE_ID_NOTSUPP,
68};
69
70static const struct ce_variant ce_h6_variant = {
71 .alg_cipher = { CE_ALG_AES, CE_ALG_DES, CE_ALG_3DES,
72 },
73 .alg_hash = { CE_ALG_MD5, CE_ALG_SHA1, CE_ALG_SHA224, CE_ALG_SHA256,
74 CE_ALG_SHA384, CE_ALG_SHA512
75 },
76 .op_mode = { CE_OP_ECB, CE_OP_CBC
77 },
78 .cipher_t_dlen_in_bytes = true,
79 .hash_t_dlen_in_bits = true,
80 .prng_t_dlen_in_bytes = true,
81 .trng_t_dlen_in_bytes = true,
82 .ce_clks = {
83 { "bus", 0, 200000000 },
84 { "mod", 300000000, 0 },
85 { "ram", 0, 400000000 },
86 },
87 .esr = ESR_H6,
88 .prng = CE_ALG_PRNG_V2,
89 .trng = CE_ALG_TRNG_V2,
90};
91
92static const struct ce_variant ce_a64_variant = {
93 .alg_cipher = { CE_ALG_AES, CE_ALG_DES, CE_ALG_3DES,
94 },
95 .alg_hash = { CE_ALG_MD5, CE_ALG_SHA1, CE_ALG_SHA224, CE_ALG_SHA256,
96 CE_ID_NOTSUPP, CE_ID_NOTSUPP
97 },
98 .op_mode = { CE_OP_ECB, CE_OP_CBC
99 },
100 .ce_clks = {
101 { "bus", 0, 200000000 },
102 { "mod", 300000000, 0 },
103 },
104 .esr = ESR_A64,
105 .prng = CE_ALG_PRNG,
106 .trng = CE_ID_NOTSUPP,
107};
108
109static const struct ce_variant ce_d1_variant = {
110 .alg_cipher = { CE_ALG_AES, CE_ALG_DES, CE_ALG_3DES,
111 },
112 .alg_hash = { CE_ALG_MD5, CE_ALG_SHA1, CE_ALG_SHA224, CE_ALG_SHA256,
113 CE_ALG_SHA384, CE_ALG_SHA512
114 },
115 .op_mode = { CE_OP_ECB, CE_OP_CBC
116 },
117 .ce_clks = {
118 { "bus", 0, 200000000 },
119 { "mod", 300000000, 0 },
120 { "ram", 0, 400000000 },
121 },
122 .esr = ESR_D1,
123 .prng = CE_ALG_PRNG,
124 .trng = CE_ALG_TRNG,
125};
126
127static const struct ce_variant ce_r40_variant = {
128 .alg_cipher = { CE_ALG_AES, CE_ALG_DES, CE_ALG_3DES,
129 },
130 .alg_hash = { CE_ALG_MD5, CE_ALG_SHA1, CE_ALG_SHA224, CE_ALG_SHA256,
131 CE_ID_NOTSUPP, CE_ID_NOTSUPP
132 },
133 .op_mode = { CE_OP_ECB, CE_OP_CBC
134 },
135 .ce_clks = {
136 { "bus", 0, 200000000 },
137 { "mod", 300000000, 0 },
138 },
139 .esr = ESR_R40,
140 .prng = CE_ALG_PRNG,
141 .trng = CE_ID_NOTSUPP,
142};
143
144
145
146
147
148
149int sun8i_ce_get_engine_number(struct sun8i_ce_dev *ce)
150{
151 return atomic_inc_return(&ce->flow) % (MAXFLOW - 1);
152}
153
154int sun8i_ce_run_task(struct sun8i_ce_dev *ce, int flow, const char *name)
155{
156 u32 v;
157 int err = 0;
158 struct ce_task *cet = ce->chanlist[flow].tl;
159
160#ifdef CONFIG_CRYPTO_DEV_SUN8I_CE_DEBUG
161 ce->chanlist[flow].stat_req++;
162#endif
163
164 mutex_lock(&ce->mlock);
165
166 v = readl(ce->base + CE_ICR);
167 v |= 1 << flow;
168 writel(v, ce->base + CE_ICR);
169
170 reinit_completion(&ce->chanlist[flow].complete);
171 writel(ce->chanlist[flow].t_phy, ce->base + CE_TDQ);
172
173 ce->chanlist[flow].status = 0;
174
175 wmb();
176
177
178
179
180 v = 1 | ((le32_to_cpu(ce->chanlist[flow].tl->t_common_ctl) & 0x7F) << 8);
181 writel(v, ce->base + CE_TLR);
182 mutex_unlock(&ce->mlock);
183
184 wait_for_completion_interruptible_timeout(&ce->chanlist[flow].complete,
185 msecs_to_jiffies(ce->chanlist[flow].timeout));
186
187 if (ce->chanlist[flow].status == 0) {
188 dev_err(ce->dev, "DMA timeout for %s (tm=%d) on flow %d\n", name,
189 ce->chanlist[flow].timeout, flow);
190 err = -EFAULT;
191 }
192
193
194
195 v = readl(ce->base + CE_ESR);
196 switch (ce->variant->esr) {
197 case ESR_H3:
198
199 if (v) {
200 dev_err(ce->dev, "CE ERROR: %x for flow %x\n", v, flow);
201 err = -EFAULT;
202 print_hex_dump(KERN_INFO, "TASK: ", DUMP_PREFIX_NONE, 16, 4,
203 cet, sizeof(struct ce_task), false);
204 }
205 if (v & CE_ERR_ALGO_NOTSUP)
206 dev_err(ce->dev, "CE ERROR: algorithm not supported\n");
207 if (v & CE_ERR_DATALEN)
208 dev_err(ce->dev, "CE ERROR: data length error\n");
209 if (v & CE_ERR_KEYSRAM)
210 dev_err(ce->dev, "CE ERROR: keysram access error for AES\n");
211 break;
212 case ESR_A64:
213 case ESR_D1:
214 case ESR_H5:
215 case ESR_R40:
216 v >>= (flow * 4);
217 v &= 0xF;
218 if (v) {
219 dev_err(ce->dev, "CE ERROR: %x for flow %x\n", v, flow);
220 err = -EFAULT;
221 print_hex_dump(KERN_INFO, "TASK: ", DUMP_PREFIX_NONE, 16, 4,
222 cet, sizeof(struct ce_task), false);
223 }
224 if (v & CE_ERR_ALGO_NOTSUP)
225 dev_err(ce->dev, "CE ERROR: algorithm not supported\n");
226 if (v & CE_ERR_DATALEN)
227 dev_err(ce->dev, "CE ERROR: data length error\n");
228 if (v & CE_ERR_KEYSRAM)
229 dev_err(ce->dev, "CE ERROR: keysram access error for AES\n");
230 break;
231 case ESR_H6:
232 v >>= (flow * 8);
233 v &= 0xFF;
234 if (v) {
235 dev_err(ce->dev, "CE ERROR: %x for flow %x\n", v, flow);
236 err = -EFAULT;
237 print_hex_dump(KERN_INFO, "TASK: ", DUMP_PREFIX_NONE, 16, 4,
238 cet, sizeof(struct ce_task), false);
239 }
240 if (v & CE_ERR_ALGO_NOTSUP)
241 dev_err(ce->dev, "CE ERROR: algorithm not supported\n");
242 if (v & CE_ERR_DATALEN)
243 dev_err(ce->dev, "CE ERROR: data length error\n");
244 if (v & CE_ERR_KEYSRAM)
245 dev_err(ce->dev, "CE ERROR: keysram access error for AES\n");
246 if (v & CE_ERR_ADDR_INVALID)
247 dev_err(ce->dev, "CE ERROR: address invalid\n");
248 if (v & CE_ERR_KEYLADDER)
249 dev_err(ce->dev, "CE ERROR: key ladder configuration error\n");
250 break;
251 }
252
253 return err;
254}
255
256static irqreturn_t ce_irq_handler(int irq, void *data)
257{
258 struct sun8i_ce_dev *ce = (struct sun8i_ce_dev *)data;
259 int flow = 0;
260 u32 p;
261
262 p = readl(ce->base + CE_ISR);
263 for (flow = 0; flow < MAXFLOW; flow++) {
264 if (p & (BIT(flow))) {
265 writel(BIT(flow), ce->base + CE_ISR);
266 ce->chanlist[flow].status = 1;
267 complete(&ce->chanlist[flow].complete);
268 }
269 }
270
271 return IRQ_HANDLED;
272}
273
274static struct sun8i_ce_alg_template ce_algs[] = {
275{
276 .type = CRYPTO_ALG_TYPE_SKCIPHER,
277 .ce_algo_id = CE_ID_CIPHER_AES,
278 .ce_blockmode = CE_ID_OP_CBC,
279 .alg.skcipher = {
280 .base = {
281 .cra_name = "cbc(aes)",
282 .cra_driver_name = "cbc-aes-sun8i-ce",
283 .cra_priority = 400,
284 .cra_blocksize = AES_BLOCK_SIZE,
285 .cra_flags = CRYPTO_ALG_TYPE_SKCIPHER |
286 CRYPTO_ALG_ASYNC | CRYPTO_ALG_ALLOCATES_MEMORY |
287 CRYPTO_ALG_NEED_FALLBACK,
288 .cra_ctxsize = sizeof(struct sun8i_cipher_tfm_ctx),
289 .cra_module = THIS_MODULE,
290 .cra_alignmask = 0xf,
291 .cra_init = sun8i_ce_cipher_init,
292 .cra_exit = sun8i_ce_cipher_exit,
293 },
294 .min_keysize = AES_MIN_KEY_SIZE,
295 .max_keysize = AES_MAX_KEY_SIZE,
296 .ivsize = AES_BLOCK_SIZE,
297 .setkey = sun8i_ce_aes_setkey,
298 .encrypt = sun8i_ce_skencrypt,
299 .decrypt = sun8i_ce_skdecrypt,
300 }
301},
302{
303 .type = CRYPTO_ALG_TYPE_SKCIPHER,
304 .ce_algo_id = CE_ID_CIPHER_AES,
305 .ce_blockmode = CE_ID_OP_ECB,
306 .alg.skcipher = {
307 .base = {
308 .cra_name = "ecb(aes)",
309 .cra_driver_name = "ecb-aes-sun8i-ce",
310 .cra_priority = 400,
311 .cra_blocksize = AES_BLOCK_SIZE,
312 .cra_flags = CRYPTO_ALG_TYPE_SKCIPHER |
313 CRYPTO_ALG_ASYNC | CRYPTO_ALG_ALLOCATES_MEMORY |
314 CRYPTO_ALG_NEED_FALLBACK,
315 .cra_ctxsize = sizeof(struct sun8i_cipher_tfm_ctx),
316 .cra_module = THIS_MODULE,
317 .cra_alignmask = 0xf,
318 .cra_init = sun8i_ce_cipher_init,
319 .cra_exit = sun8i_ce_cipher_exit,
320 },
321 .min_keysize = AES_MIN_KEY_SIZE,
322 .max_keysize = AES_MAX_KEY_SIZE,
323 .setkey = sun8i_ce_aes_setkey,
324 .encrypt = sun8i_ce_skencrypt,
325 .decrypt = sun8i_ce_skdecrypt,
326 }
327},
328{
329 .type = CRYPTO_ALG_TYPE_SKCIPHER,
330 .ce_algo_id = CE_ID_CIPHER_DES3,
331 .ce_blockmode = CE_ID_OP_CBC,
332 .alg.skcipher = {
333 .base = {
334 .cra_name = "cbc(des3_ede)",
335 .cra_driver_name = "cbc-des3-sun8i-ce",
336 .cra_priority = 400,
337 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
338 .cra_flags = CRYPTO_ALG_TYPE_SKCIPHER |
339 CRYPTO_ALG_ASYNC | CRYPTO_ALG_ALLOCATES_MEMORY |
340 CRYPTO_ALG_NEED_FALLBACK,
341 .cra_ctxsize = sizeof(struct sun8i_cipher_tfm_ctx),
342 .cra_module = THIS_MODULE,
343 .cra_alignmask = 0xf,
344 .cra_init = sun8i_ce_cipher_init,
345 .cra_exit = sun8i_ce_cipher_exit,
346 },
347 .min_keysize = DES3_EDE_KEY_SIZE,
348 .max_keysize = DES3_EDE_KEY_SIZE,
349 .ivsize = DES3_EDE_BLOCK_SIZE,
350 .setkey = sun8i_ce_des3_setkey,
351 .encrypt = sun8i_ce_skencrypt,
352 .decrypt = sun8i_ce_skdecrypt,
353 }
354},
355{
356 .type = CRYPTO_ALG_TYPE_SKCIPHER,
357 .ce_algo_id = CE_ID_CIPHER_DES3,
358 .ce_blockmode = CE_ID_OP_ECB,
359 .alg.skcipher = {
360 .base = {
361 .cra_name = "ecb(des3_ede)",
362 .cra_driver_name = "ecb-des3-sun8i-ce",
363 .cra_priority = 400,
364 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
365 .cra_flags = CRYPTO_ALG_TYPE_SKCIPHER |
366 CRYPTO_ALG_ASYNC | CRYPTO_ALG_ALLOCATES_MEMORY |
367 CRYPTO_ALG_NEED_FALLBACK,
368 .cra_ctxsize = sizeof(struct sun8i_cipher_tfm_ctx),
369 .cra_module = THIS_MODULE,
370 .cra_alignmask = 0xf,
371 .cra_init = sun8i_ce_cipher_init,
372 .cra_exit = sun8i_ce_cipher_exit,
373 },
374 .min_keysize = DES3_EDE_KEY_SIZE,
375 .max_keysize = DES3_EDE_KEY_SIZE,
376 .setkey = sun8i_ce_des3_setkey,
377 .encrypt = sun8i_ce_skencrypt,
378 .decrypt = sun8i_ce_skdecrypt,
379 }
380},
381#ifdef CONFIG_CRYPTO_DEV_SUN8I_CE_HASH
382{ .type = CRYPTO_ALG_TYPE_AHASH,
383 .ce_algo_id = CE_ID_HASH_MD5,
384 .alg.hash = {
385 .init = sun8i_ce_hash_init,
386 .update = sun8i_ce_hash_update,
387 .final = sun8i_ce_hash_final,
388 .finup = sun8i_ce_hash_finup,
389 .digest = sun8i_ce_hash_digest,
390 .export = sun8i_ce_hash_export,
391 .import = sun8i_ce_hash_import,
392 .halg = {
393 .digestsize = MD5_DIGEST_SIZE,
394 .statesize = sizeof(struct md5_state),
395 .base = {
396 .cra_name = "md5",
397 .cra_driver_name = "md5-sun8i-ce",
398 .cra_priority = 300,
399 .cra_alignmask = 3,
400 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
401 CRYPTO_ALG_ASYNC |
402 CRYPTO_ALG_NEED_FALLBACK,
403 .cra_blocksize = MD5_HMAC_BLOCK_SIZE,
404 .cra_ctxsize = sizeof(struct sun8i_ce_hash_tfm_ctx),
405 .cra_module = THIS_MODULE,
406 .cra_init = sun8i_ce_hash_crainit,
407 .cra_exit = sun8i_ce_hash_craexit,
408 }
409 }
410 }
411},
412{ .type = CRYPTO_ALG_TYPE_AHASH,
413 .ce_algo_id = CE_ID_HASH_SHA1,
414 .alg.hash = {
415 .init = sun8i_ce_hash_init,
416 .update = sun8i_ce_hash_update,
417 .final = sun8i_ce_hash_final,
418 .finup = sun8i_ce_hash_finup,
419 .digest = sun8i_ce_hash_digest,
420 .export = sun8i_ce_hash_export,
421 .import = sun8i_ce_hash_import,
422 .halg = {
423 .digestsize = SHA1_DIGEST_SIZE,
424 .statesize = sizeof(struct sha1_state),
425 .base = {
426 .cra_name = "sha1",
427 .cra_driver_name = "sha1-sun8i-ce",
428 .cra_priority = 300,
429 .cra_alignmask = 3,
430 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
431 CRYPTO_ALG_ASYNC |
432 CRYPTO_ALG_NEED_FALLBACK,
433 .cra_blocksize = SHA1_BLOCK_SIZE,
434 .cra_ctxsize = sizeof(struct sun8i_ce_hash_tfm_ctx),
435 .cra_module = THIS_MODULE,
436 .cra_init = sun8i_ce_hash_crainit,
437 .cra_exit = sun8i_ce_hash_craexit,
438 }
439 }
440 }
441},
442{ .type = CRYPTO_ALG_TYPE_AHASH,
443 .ce_algo_id = CE_ID_HASH_SHA224,
444 .alg.hash = {
445 .init = sun8i_ce_hash_init,
446 .update = sun8i_ce_hash_update,
447 .final = sun8i_ce_hash_final,
448 .finup = sun8i_ce_hash_finup,
449 .digest = sun8i_ce_hash_digest,
450 .export = sun8i_ce_hash_export,
451 .import = sun8i_ce_hash_import,
452 .halg = {
453 .digestsize = SHA224_DIGEST_SIZE,
454 .statesize = sizeof(struct sha256_state),
455 .base = {
456 .cra_name = "sha224",
457 .cra_driver_name = "sha224-sun8i-ce",
458 .cra_priority = 300,
459 .cra_alignmask = 3,
460 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
461 CRYPTO_ALG_ASYNC |
462 CRYPTO_ALG_NEED_FALLBACK,
463 .cra_blocksize = SHA224_BLOCK_SIZE,
464 .cra_ctxsize = sizeof(struct sun8i_ce_hash_tfm_ctx),
465 .cra_module = THIS_MODULE,
466 .cra_init = sun8i_ce_hash_crainit,
467 .cra_exit = sun8i_ce_hash_craexit,
468 }
469 }
470 }
471},
472{ .type = CRYPTO_ALG_TYPE_AHASH,
473 .ce_algo_id = CE_ID_HASH_SHA256,
474 .alg.hash = {
475 .init = sun8i_ce_hash_init,
476 .update = sun8i_ce_hash_update,
477 .final = sun8i_ce_hash_final,
478 .finup = sun8i_ce_hash_finup,
479 .digest = sun8i_ce_hash_digest,
480 .export = sun8i_ce_hash_export,
481 .import = sun8i_ce_hash_import,
482 .halg = {
483 .digestsize = SHA256_DIGEST_SIZE,
484 .statesize = sizeof(struct sha256_state),
485 .base = {
486 .cra_name = "sha256",
487 .cra_driver_name = "sha256-sun8i-ce",
488 .cra_priority = 300,
489 .cra_alignmask = 3,
490 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
491 CRYPTO_ALG_ASYNC |
492 CRYPTO_ALG_NEED_FALLBACK,
493 .cra_blocksize = SHA256_BLOCK_SIZE,
494 .cra_ctxsize = sizeof(struct sun8i_ce_hash_tfm_ctx),
495 .cra_module = THIS_MODULE,
496 .cra_init = sun8i_ce_hash_crainit,
497 .cra_exit = sun8i_ce_hash_craexit,
498 }
499 }
500 }
501},
502{ .type = CRYPTO_ALG_TYPE_AHASH,
503 .ce_algo_id = CE_ID_HASH_SHA384,
504 .alg.hash = {
505 .init = sun8i_ce_hash_init,
506 .update = sun8i_ce_hash_update,
507 .final = sun8i_ce_hash_final,
508 .finup = sun8i_ce_hash_finup,
509 .digest = sun8i_ce_hash_digest,
510 .export = sun8i_ce_hash_export,
511 .import = sun8i_ce_hash_import,
512 .halg = {
513 .digestsize = SHA384_DIGEST_SIZE,
514 .statesize = sizeof(struct sha512_state),
515 .base = {
516 .cra_name = "sha384",
517 .cra_driver_name = "sha384-sun8i-ce",
518 .cra_priority = 300,
519 .cra_alignmask = 3,
520 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
521 CRYPTO_ALG_ASYNC |
522 CRYPTO_ALG_NEED_FALLBACK,
523 .cra_blocksize = SHA384_BLOCK_SIZE,
524 .cra_ctxsize = sizeof(struct sun8i_ce_hash_tfm_ctx),
525 .cra_module = THIS_MODULE,
526 .cra_init = sun8i_ce_hash_crainit,
527 .cra_exit = sun8i_ce_hash_craexit,
528 }
529 }
530 }
531},
532{ .type = CRYPTO_ALG_TYPE_AHASH,
533 .ce_algo_id = CE_ID_HASH_SHA512,
534 .alg.hash = {
535 .init = sun8i_ce_hash_init,
536 .update = sun8i_ce_hash_update,
537 .final = sun8i_ce_hash_final,
538 .finup = sun8i_ce_hash_finup,
539 .digest = sun8i_ce_hash_digest,
540 .export = sun8i_ce_hash_export,
541 .import = sun8i_ce_hash_import,
542 .halg = {
543 .digestsize = SHA512_DIGEST_SIZE,
544 .statesize = sizeof(struct sha512_state),
545 .base = {
546 .cra_name = "sha512",
547 .cra_driver_name = "sha512-sun8i-ce",
548 .cra_priority = 300,
549 .cra_alignmask = 3,
550 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
551 CRYPTO_ALG_ASYNC |
552 CRYPTO_ALG_NEED_FALLBACK,
553 .cra_blocksize = SHA512_BLOCK_SIZE,
554 .cra_ctxsize = sizeof(struct sun8i_ce_hash_tfm_ctx),
555 .cra_module = THIS_MODULE,
556 .cra_init = sun8i_ce_hash_crainit,
557 .cra_exit = sun8i_ce_hash_craexit,
558 }
559 }
560 }
561},
562#endif
563#ifdef CONFIG_CRYPTO_DEV_SUN8I_CE_PRNG
564{
565 .type = CRYPTO_ALG_TYPE_RNG,
566 .alg.rng = {
567 .base = {
568 .cra_name = "stdrng",
569 .cra_driver_name = "sun8i-ce-prng",
570 .cra_priority = 300,
571 .cra_ctxsize = sizeof(struct sun8i_ce_rng_tfm_ctx),
572 .cra_module = THIS_MODULE,
573 .cra_init = sun8i_ce_prng_init,
574 .cra_exit = sun8i_ce_prng_exit,
575 },
576 .generate = sun8i_ce_prng_generate,
577 .seed = sun8i_ce_prng_seed,
578 .seedsize = PRNG_SEED_SIZE,
579 }
580},
581#endif
582};
583
584#ifdef CONFIG_CRYPTO_DEV_SUN8I_CE_DEBUG
585static int sun8i_ce_debugfs_show(struct seq_file *seq, void *v)
586{
587 struct sun8i_ce_dev *ce = seq->private;
588 unsigned int i;
589
590 for (i = 0; i < MAXFLOW; i++)
591 seq_printf(seq, "Channel %d: nreq %lu\n", i, ce->chanlist[i].stat_req);
592
593 for (i = 0; i < ARRAY_SIZE(ce_algs); i++) {
594 if (!ce_algs[i].ce)
595 continue;
596 switch (ce_algs[i].type) {
597 case CRYPTO_ALG_TYPE_SKCIPHER:
598 seq_printf(seq, "%s %s %lu %lu\n",
599 ce_algs[i].alg.skcipher.base.cra_driver_name,
600 ce_algs[i].alg.skcipher.base.cra_name,
601 ce_algs[i].stat_req, ce_algs[i].stat_fb);
602 break;
603 case CRYPTO_ALG_TYPE_AHASH:
604 seq_printf(seq, "%s %s %lu %lu\n",
605 ce_algs[i].alg.hash.halg.base.cra_driver_name,
606 ce_algs[i].alg.hash.halg.base.cra_name,
607 ce_algs[i].stat_req, ce_algs[i].stat_fb);
608 break;
609 case CRYPTO_ALG_TYPE_RNG:
610 seq_printf(seq, "%s %s %lu %lu\n",
611 ce_algs[i].alg.rng.base.cra_driver_name,
612 ce_algs[i].alg.rng.base.cra_name,
613 ce_algs[i].stat_req, ce_algs[i].stat_bytes);
614 break;
615 }
616 }
617#ifdef CONFIG_CRYPTO_DEV_SUN8I_CE_TRNG
618 seq_printf(seq, "HWRNG %lu %lu\n",
619 ce->hwrng_stat_req, ce->hwrng_stat_bytes);
620#endif
621 return 0;
622}
623
624DEFINE_SHOW_ATTRIBUTE(sun8i_ce_debugfs);
625#endif
626
627static void sun8i_ce_free_chanlist(struct sun8i_ce_dev *ce, int i)
628{
629 while (i >= 0) {
630 crypto_engine_exit(ce->chanlist[i].engine);
631 if (ce->chanlist[i].tl)
632 dma_free_coherent(ce->dev, sizeof(struct ce_task),
633 ce->chanlist[i].tl,
634 ce->chanlist[i].t_phy);
635 i--;
636 }
637}
638
639
640
641
642static int sun8i_ce_allocate_chanlist(struct sun8i_ce_dev *ce)
643{
644 int i, err;
645
646 ce->chanlist = devm_kcalloc(ce->dev, MAXFLOW,
647 sizeof(struct sun8i_ce_flow), GFP_KERNEL);
648 if (!ce->chanlist)
649 return -ENOMEM;
650
651 for (i = 0; i < MAXFLOW; i++) {
652 init_completion(&ce->chanlist[i].complete);
653
654 ce->chanlist[i].engine = crypto_engine_alloc_init(ce->dev, true);
655 if (!ce->chanlist[i].engine) {
656 dev_err(ce->dev, "Cannot allocate engine\n");
657 i--;
658 err = -ENOMEM;
659 goto error_engine;
660 }
661 err = crypto_engine_start(ce->chanlist[i].engine);
662 if (err) {
663 dev_err(ce->dev, "Cannot start engine\n");
664 goto error_engine;
665 }
666 ce->chanlist[i].tl = dma_alloc_coherent(ce->dev,
667 sizeof(struct ce_task),
668 &ce->chanlist[i].t_phy,
669 GFP_KERNEL);
670 if (!ce->chanlist[i].tl) {
671 dev_err(ce->dev, "Cannot get DMA memory for task %d\n",
672 i);
673 err = -ENOMEM;
674 goto error_engine;
675 }
676 }
677 return 0;
678error_engine:
679 sun8i_ce_free_chanlist(ce, i);
680 return err;
681}
682
683
684
685
686
687static int sun8i_ce_pm_suspend(struct device *dev)
688{
689 struct sun8i_ce_dev *ce = dev_get_drvdata(dev);
690 int i;
691
692 reset_control_assert(ce->reset);
693 for (i = 0; i < CE_MAX_CLOCKS; i++)
694 clk_disable_unprepare(ce->ceclks[i]);
695 return 0;
696}
697
698static int sun8i_ce_pm_resume(struct device *dev)
699{
700 struct sun8i_ce_dev *ce = dev_get_drvdata(dev);
701 int err, i;
702
703 for (i = 0; i < CE_MAX_CLOCKS; i++) {
704 if (!ce->variant->ce_clks[i].name)
705 continue;
706 err = clk_prepare_enable(ce->ceclks[i]);
707 if (err) {
708 dev_err(ce->dev, "Cannot prepare_enable %s\n",
709 ce->variant->ce_clks[i].name);
710 goto error;
711 }
712 }
713 err = reset_control_deassert(ce->reset);
714 if (err) {
715 dev_err(ce->dev, "Cannot deassert reset control\n");
716 goto error;
717 }
718 return 0;
719error:
720 sun8i_ce_pm_suspend(dev);
721 return err;
722}
723
724static const struct dev_pm_ops sun8i_ce_pm_ops = {
725 SET_RUNTIME_PM_OPS(sun8i_ce_pm_suspend, sun8i_ce_pm_resume, NULL)
726};
727
728static int sun8i_ce_pm_init(struct sun8i_ce_dev *ce)
729{
730 int err;
731
732 pm_runtime_use_autosuspend(ce->dev);
733 pm_runtime_set_autosuspend_delay(ce->dev, 2000);
734
735 err = pm_runtime_set_suspended(ce->dev);
736 if (err)
737 return err;
738 pm_runtime_enable(ce->dev);
739 return err;
740}
741
742static void sun8i_ce_pm_exit(struct sun8i_ce_dev *ce)
743{
744 pm_runtime_disable(ce->dev);
745}
746
747static int sun8i_ce_get_clks(struct sun8i_ce_dev *ce)
748{
749 unsigned long cr;
750 int err, i;
751
752 for (i = 0; i < CE_MAX_CLOCKS; i++) {
753 if (!ce->variant->ce_clks[i].name)
754 continue;
755 ce->ceclks[i] = devm_clk_get(ce->dev, ce->variant->ce_clks[i].name);
756 if (IS_ERR(ce->ceclks[i])) {
757 err = PTR_ERR(ce->ceclks[i]);
758 dev_err(ce->dev, "Cannot get %s CE clock err=%d\n",
759 ce->variant->ce_clks[i].name, err);
760 return err;
761 }
762 cr = clk_get_rate(ce->ceclks[i]);
763 if (!cr)
764 return -EINVAL;
765 if (ce->variant->ce_clks[i].freq > 0 &&
766 cr != ce->variant->ce_clks[i].freq) {
767 dev_info(ce->dev, "Set %s clock to %lu (%lu Mhz) from %lu (%lu Mhz)\n",
768 ce->variant->ce_clks[i].name,
769 ce->variant->ce_clks[i].freq,
770 ce->variant->ce_clks[i].freq / 1000000,
771 cr, cr / 1000000);
772 err = clk_set_rate(ce->ceclks[i], ce->variant->ce_clks[i].freq);
773 if (err)
774 dev_err(ce->dev, "Fail to set %s clk speed to %lu hz\n",
775 ce->variant->ce_clks[i].name,
776 ce->variant->ce_clks[i].freq);
777 }
778 if (ce->variant->ce_clks[i].max_freq > 0 &&
779 cr > ce->variant->ce_clks[i].max_freq)
780 dev_warn(ce->dev, "Frequency for %s (%lu hz) is higher than datasheet's recommendation (%lu hz)",
781 ce->variant->ce_clks[i].name, cr,
782 ce->variant->ce_clks[i].max_freq);
783 }
784 return 0;
785}
786
787static int sun8i_ce_register_algs(struct sun8i_ce_dev *ce)
788{
789 int ce_method, err, id;
790 unsigned int i;
791
792 for (i = 0; i < ARRAY_SIZE(ce_algs); i++) {
793 ce_algs[i].ce = ce;
794 switch (ce_algs[i].type) {
795 case CRYPTO_ALG_TYPE_SKCIPHER:
796 id = ce_algs[i].ce_algo_id;
797 ce_method = ce->variant->alg_cipher[id];
798 if (ce_method == CE_ID_NOTSUPP) {
799 dev_dbg(ce->dev,
800 "DEBUG: Algo of %s not supported\n",
801 ce_algs[i].alg.skcipher.base.cra_name);
802 ce_algs[i].ce = NULL;
803 break;
804 }
805 id = ce_algs[i].ce_blockmode;
806 ce_method = ce->variant->op_mode[id];
807 if (ce_method == CE_ID_NOTSUPP) {
808 dev_dbg(ce->dev, "DEBUG: Blockmode of %s not supported\n",
809 ce_algs[i].alg.skcipher.base.cra_name);
810 ce_algs[i].ce = NULL;
811 break;
812 }
813 dev_info(ce->dev, "Register %s\n",
814 ce_algs[i].alg.skcipher.base.cra_name);
815 err = crypto_register_skcipher(&ce_algs[i].alg.skcipher);
816 if (err) {
817 dev_err(ce->dev, "ERROR: Fail to register %s\n",
818 ce_algs[i].alg.skcipher.base.cra_name);
819 ce_algs[i].ce = NULL;
820 return err;
821 }
822 break;
823 case CRYPTO_ALG_TYPE_AHASH:
824 id = ce_algs[i].ce_algo_id;
825 ce_method = ce->variant->alg_hash[id];
826 if (ce_method == CE_ID_NOTSUPP) {
827 dev_info(ce->dev,
828 "DEBUG: Algo of %s not supported\n",
829 ce_algs[i].alg.hash.halg.base.cra_name);
830 ce_algs[i].ce = NULL;
831 break;
832 }
833 dev_info(ce->dev, "Register %s\n",
834 ce_algs[i].alg.hash.halg.base.cra_name);
835 err = crypto_register_ahash(&ce_algs[i].alg.hash);
836 if (err) {
837 dev_err(ce->dev, "ERROR: Fail to register %s\n",
838 ce_algs[i].alg.hash.halg.base.cra_name);
839 ce_algs[i].ce = NULL;
840 return err;
841 }
842 break;
843 case CRYPTO_ALG_TYPE_RNG:
844 if (ce->variant->prng == CE_ID_NOTSUPP) {
845 dev_info(ce->dev,
846 "DEBUG: Algo of %s not supported\n",
847 ce_algs[i].alg.rng.base.cra_name);
848 ce_algs[i].ce = NULL;
849 break;
850 }
851 dev_info(ce->dev, "Register %s\n",
852 ce_algs[i].alg.rng.base.cra_name);
853 err = crypto_register_rng(&ce_algs[i].alg.rng);
854 if (err) {
855 dev_err(ce->dev, "Fail to register %s\n",
856 ce_algs[i].alg.rng.base.cra_name);
857 ce_algs[i].ce = NULL;
858 }
859 break;
860 default:
861 ce_algs[i].ce = NULL;
862 dev_err(ce->dev, "ERROR: tried to register an unknown algo\n");
863 }
864 }
865 return 0;
866}
867
868static void sun8i_ce_unregister_algs(struct sun8i_ce_dev *ce)
869{
870 unsigned int i;
871
872 for (i = 0; i < ARRAY_SIZE(ce_algs); i++) {
873 if (!ce_algs[i].ce)
874 continue;
875 switch (ce_algs[i].type) {
876 case CRYPTO_ALG_TYPE_SKCIPHER:
877 dev_info(ce->dev, "Unregister %d %s\n", i,
878 ce_algs[i].alg.skcipher.base.cra_name);
879 crypto_unregister_skcipher(&ce_algs[i].alg.skcipher);
880 break;
881 case CRYPTO_ALG_TYPE_AHASH:
882 dev_info(ce->dev, "Unregister %d %s\n", i,
883 ce_algs[i].alg.hash.halg.base.cra_name);
884 crypto_unregister_ahash(&ce_algs[i].alg.hash);
885 break;
886 case CRYPTO_ALG_TYPE_RNG:
887 dev_info(ce->dev, "Unregister %d %s\n", i,
888 ce_algs[i].alg.rng.base.cra_name);
889 crypto_unregister_rng(&ce_algs[i].alg.rng);
890 break;
891 }
892 }
893}
894
895static int sun8i_ce_probe(struct platform_device *pdev)
896{
897 struct sun8i_ce_dev *ce;
898 int err, irq;
899 u32 v;
900
901 ce = devm_kzalloc(&pdev->dev, sizeof(*ce), GFP_KERNEL);
902 if (!ce)
903 return -ENOMEM;
904
905 ce->dev = &pdev->dev;
906 platform_set_drvdata(pdev, ce);
907
908 ce->variant = of_device_get_match_data(&pdev->dev);
909 if (!ce->variant) {
910 dev_err(&pdev->dev, "Missing Crypto Engine variant\n");
911 return -EINVAL;
912 }
913
914 ce->base = devm_platform_ioremap_resource(pdev, 0);
915 if (IS_ERR(ce->base))
916 return PTR_ERR(ce->base);
917
918 err = sun8i_ce_get_clks(ce);
919 if (err)
920 return err;
921
922
923 irq = platform_get_irq(pdev, 0);
924 if (irq < 0)
925 return irq;
926
927 ce->reset = devm_reset_control_get(&pdev->dev, NULL);
928 if (IS_ERR(ce->reset))
929 return dev_err_probe(&pdev->dev, PTR_ERR(ce->reset),
930 "No reset control found\n");
931
932 mutex_init(&ce->mlock);
933 mutex_init(&ce->rnglock);
934
935 err = sun8i_ce_allocate_chanlist(ce);
936 if (err)
937 return err;
938
939 err = sun8i_ce_pm_init(ce);
940 if (err)
941 goto error_pm;
942
943 err = devm_request_irq(&pdev->dev, irq, ce_irq_handler, 0,
944 "sun8i-ce-ns", ce);
945 if (err) {
946 dev_err(ce->dev, "Cannot request CryptoEngine Non-secure IRQ (err=%d)\n", err);
947 goto error_irq;
948 }
949
950 err = sun8i_ce_register_algs(ce);
951 if (err)
952 goto error_alg;
953
954 err = pm_runtime_resume_and_get(ce->dev);
955 if (err < 0)
956 goto error_alg;
957
958#ifdef CONFIG_CRYPTO_DEV_SUN8I_CE_TRNG
959 sun8i_ce_hwrng_register(ce);
960#endif
961
962 v = readl(ce->base + CE_CTR);
963 v >>= CE_DIE_ID_SHIFT;
964 v &= CE_DIE_ID_MASK;
965 dev_info(&pdev->dev, "CryptoEngine Die ID %x\n", v);
966
967 pm_runtime_put_sync(ce->dev);
968
969#ifdef CONFIG_CRYPTO_DEV_SUN8I_CE_DEBUG
970
971 ce->dbgfs_dir = debugfs_create_dir("sun8i-ce", NULL);
972 ce->dbgfs_stats = debugfs_create_file("stats", 0444,
973 ce->dbgfs_dir, ce,
974 &sun8i_ce_debugfs_fops);
975#endif
976
977 return 0;
978error_alg:
979 sun8i_ce_unregister_algs(ce);
980error_irq:
981 sun8i_ce_pm_exit(ce);
982error_pm:
983 sun8i_ce_free_chanlist(ce, MAXFLOW - 1);
984 return err;
985}
986
987static int sun8i_ce_remove(struct platform_device *pdev)
988{
989 struct sun8i_ce_dev *ce = platform_get_drvdata(pdev);
990
991#ifdef CONFIG_CRYPTO_DEV_SUN8I_CE_TRNG
992 sun8i_ce_hwrng_unregister(ce);
993#endif
994
995 sun8i_ce_unregister_algs(ce);
996
997#ifdef CONFIG_CRYPTO_DEV_SUN8I_CE_DEBUG
998 debugfs_remove_recursive(ce->dbgfs_dir);
999#endif
1000
1001 sun8i_ce_free_chanlist(ce, MAXFLOW - 1);
1002
1003 sun8i_ce_pm_exit(ce);
1004 return 0;
1005}
1006
1007static const struct of_device_id sun8i_ce_crypto_of_match_table[] = {
1008 { .compatible = "allwinner,sun8i-h3-crypto",
1009 .data = &ce_h3_variant },
1010 { .compatible = "allwinner,sun8i-r40-crypto",
1011 .data = &ce_r40_variant },
1012 { .compatible = "allwinner,sun20i-d1-crypto",
1013 .data = &ce_d1_variant },
1014 { .compatible = "allwinner,sun50i-a64-crypto",
1015 .data = &ce_a64_variant },
1016 { .compatible = "allwinner,sun50i-h5-crypto",
1017 .data = &ce_h5_variant },
1018 { .compatible = "allwinner,sun50i-h6-crypto",
1019 .data = &ce_h6_variant },
1020 {}
1021};
1022MODULE_DEVICE_TABLE(of, sun8i_ce_crypto_of_match_table);
1023
1024static struct platform_driver sun8i_ce_driver = {
1025 .probe = sun8i_ce_probe,
1026 .remove = sun8i_ce_remove,
1027 .driver = {
1028 .name = "sun8i-ce",
1029 .pm = &sun8i_ce_pm_ops,
1030 .of_match_table = sun8i_ce_crypto_of_match_table,
1031 },
1032};
1033
1034module_platform_driver(sun8i_ce_driver);
1035
1036MODULE_DESCRIPTION("Allwinner Crypto Engine cryptographic offloader");
1037MODULE_LICENSE("GPL");
1038MODULE_AUTHOR("Corentin Labbe <clabbe.montjoie@gmail.com>");
1039
