1
2
3#ifndef ADF_DRV_H
4#define ADF_DRV_H
5
6#include <linux/list.h>
7#include <linux/pci.h>
8#include "adf_accel_devices.h"
9#include "icp_qat_fw_loader_handle.h"
10#include "icp_qat_hal.h"
11
12#define ADF_MAJOR_VERSION 0
13#define ADF_MINOR_VERSION 6
14#define ADF_BUILD_VERSION 0
15#define ADF_DRV_VERSION __stringify(ADF_MAJOR_VERSION) "." \
16 __stringify(ADF_MINOR_VERSION) "." \
17 __stringify(ADF_BUILD_VERSION)
18
19#define ADF_STATUS_RESTARTING 0
20#define ADF_STATUS_STARTING 1
21#define ADF_STATUS_CONFIGURED 2
22#define ADF_STATUS_STARTED 3
23#define ADF_STATUS_AE_INITIALISED 4
24#define ADF_STATUS_AE_UCODE_LOADED 5
25#define ADF_STATUS_AE_STARTED 6
26#define ADF_STATUS_PF_RUNNING 7
27#define ADF_STATUS_IRQ_ALLOCATED 8
28
29enum adf_dev_reset_mode {
30 ADF_DEV_RESET_ASYNC = 0,
31 ADF_DEV_RESET_SYNC
32};
33
34enum adf_event {
35 ADF_EVENT_INIT = 0,
36 ADF_EVENT_START,
37 ADF_EVENT_STOP,
38 ADF_EVENT_SHUTDOWN,
39 ADF_EVENT_RESTARTING,
40 ADF_EVENT_RESTARTED,
41};
42
43struct service_hndl {
44 int (*event_hld)(struct adf_accel_dev *accel_dev,
45 enum adf_event event);
46 unsigned long init_status[ADF_DEVS_ARRAY_SIZE];
47 unsigned long start_status[ADF_DEVS_ARRAY_SIZE];
48 char *name;
49 struct list_head list;
50};
51
52static inline int get_current_node(void)
53{
54 return topology_physical_package_id(raw_smp_processor_id());
55}
56
57int adf_service_register(struct service_hndl *service);
58int adf_service_unregister(struct service_hndl *service);
59
60int adf_dev_init(struct adf_accel_dev *accel_dev);
61int adf_dev_start(struct adf_accel_dev *accel_dev);
62void adf_dev_stop(struct adf_accel_dev *accel_dev);
63void adf_dev_shutdown(struct adf_accel_dev *accel_dev);
64
65void adf_devmgr_update_class_index(struct adf_hw_device_data *hw_data);
66void adf_clean_vf_map(bool);
67
68int adf_ctl_dev_register(void);
69void adf_ctl_dev_unregister(void);
70int adf_processes_dev_register(void);
71void adf_processes_dev_unregister(void);
72
73int adf_devmgr_add_dev(struct adf_accel_dev *accel_dev,
74 struct adf_accel_dev *pf);
75void adf_devmgr_rm_dev(struct adf_accel_dev *accel_dev,
76 struct adf_accel_dev *pf);
77struct list_head *adf_devmgr_get_head(void);
78struct adf_accel_dev *adf_devmgr_get_dev_by_id(u32 id);
79struct adf_accel_dev *adf_devmgr_get_first(void);
80struct adf_accel_dev *adf_devmgr_pci_to_accel_dev(struct pci_dev *pci_dev);
81int adf_devmgr_verify_id(u32 id);
82void adf_devmgr_get_num_dev(u32 *num);
83int adf_devmgr_in_reset(struct adf_accel_dev *accel_dev);
84int adf_dev_started(struct adf_accel_dev *accel_dev);
85int adf_dev_restarting_notify(struct adf_accel_dev *accel_dev);
86int adf_dev_restarted_notify(struct adf_accel_dev *accel_dev);
87int adf_ae_init(struct adf_accel_dev *accel_dev);
88int adf_ae_shutdown(struct adf_accel_dev *accel_dev);
89int adf_ae_fw_load(struct adf_accel_dev *accel_dev);
90void adf_ae_fw_release(struct adf_accel_dev *accel_dev);
91int adf_ae_start(struct adf_accel_dev *accel_dev);
92int adf_ae_stop(struct adf_accel_dev *accel_dev);
93
94extern const struct pci_error_handlers adf_err_handler;
95void adf_enable_aer(struct adf_accel_dev *accel_dev);
96void adf_disable_aer(struct adf_accel_dev *accel_dev);
97void adf_reset_sbr(struct adf_accel_dev *accel_dev);
98void adf_reset_flr(struct adf_accel_dev *accel_dev);
99void adf_dev_restore(struct adf_accel_dev *accel_dev);
100int adf_init_aer(void);
101void adf_exit_aer(void);
102int adf_init_admin_comms(struct adf_accel_dev *accel_dev);
103void adf_exit_admin_comms(struct adf_accel_dev *accel_dev);
104int adf_send_admin_init(struct adf_accel_dev *accel_dev);
105int adf_init_arb(struct adf_accel_dev *accel_dev);
106void adf_exit_arb(struct adf_accel_dev *accel_dev);
107void adf_update_ring_arb(struct adf_etr_ring_data *ring);
108
109int adf_dev_get(struct adf_accel_dev *accel_dev);
110void adf_dev_put(struct adf_accel_dev *accel_dev);
111int adf_dev_in_use(struct adf_accel_dev *accel_dev);
112int adf_init_etr_data(struct adf_accel_dev *accel_dev);
113void adf_cleanup_etr_data(struct adf_accel_dev *accel_dev);
114int qat_crypto_register(void);
115int qat_crypto_unregister(void);
116int qat_crypto_dev_config(struct adf_accel_dev *accel_dev);
117int qat_crypto_vf_dev_config(struct adf_accel_dev *accel_dev);
118struct qat_crypto_instance *qat_crypto_get_instance_node(int node);
119void qat_crypto_put_instance(struct qat_crypto_instance *inst);
120void qat_alg_callback(void *resp);
121void qat_alg_asym_callback(void *resp);
122int qat_algs_register(void);
123void qat_algs_unregister(void);
124int qat_asym_algs_register(void);
125void qat_asym_algs_unregister(void);
126
127int adf_isr_resource_alloc(struct adf_accel_dev *accel_dev);
128void adf_isr_resource_free(struct adf_accel_dev *accel_dev);
129int adf_vf_isr_resource_alloc(struct adf_accel_dev *accel_dev);
130void adf_vf_isr_resource_free(struct adf_accel_dev *accel_dev);
131
132int adf_pfvf_comms_disabled(struct adf_accel_dev *accel_dev);
133
134int qat_hal_init(struct adf_accel_dev *accel_dev);
135void qat_hal_deinit(struct icp_qat_fw_loader_handle *handle);
136int qat_hal_start(struct icp_qat_fw_loader_handle *handle);
137void qat_hal_stop(struct icp_qat_fw_loader_handle *handle, unsigned char ae,
138 unsigned int ctx_mask);
139void qat_hal_reset(struct icp_qat_fw_loader_handle *handle);
140int qat_hal_clr_reset(struct icp_qat_fw_loader_handle *handle);
141void qat_hal_set_live_ctx(struct icp_qat_fw_loader_handle *handle,
142 unsigned char ae, unsigned int ctx_mask);
143int qat_hal_check_ae_active(struct icp_qat_fw_loader_handle *handle,
144 unsigned int ae);
145int qat_hal_set_ae_lm_mode(struct icp_qat_fw_loader_handle *handle,
146 unsigned char ae, enum icp_qat_uof_regtype lm_type,
147 unsigned char mode);
148int qat_hal_set_ae_ctx_mode(struct icp_qat_fw_loader_handle *handle,
149 unsigned char ae, unsigned char mode);
150int qat_hal_set_ae_nn_mode(struct icp_qat_fw_loader_handle *handle,
151 unsigned char ae, unsigned char mode);
152void qat_hal_set_pc(struct icp_qat_fw_loader_handle *handle,
153 unsigned char ae, unsigned int ctx_mask, unsigned int upc);
154void qat_hal_wr_uwords(struct icp_qat_fw_loader_handle *handle,
155 unsigned char ae, unsigned int uaddr,
156 unsigned int words_num, u64 *uword);
157void qat_hal_wr_umem(struct icp_qat_fw_loader_handle *handle, unsigned char ae,
158 unsigned int uword_addr, unsigned int words_num,
159 unsigned int *data);
160int qat_hal_get_ins_num(void);
161int qat_hal_batch_wr_lm(struct icp_qat_fw_loader_handle *handle,
162 unsigned char ae,
163 struct icp_qat_uof_batch_init *lm_init_header);
164int qat_hal_init_gpr(struct icp_qat_fw_loader_handle *handle,
165 unsigned char ae, unsigned long ctx_mask,
166 enum icp_qat_uof_regtype reg_type,
167 unsigned short reg_num, unsigned int regdata);
168int qat_hal_init_wr_xfer(struct icp_qat_fw_loader_handle *handle,
169 unsigned char ae, unsigned long ctx_mask,
170 enum icp_qat_uof_regtype reg_type,
171 unsigned short reg_num, unsigned int regdata);
172int qat_hal_init_rd_xfer(struct icp_qat_fw_loader_handle *handle,
173 unsigned char ae, unsigned long ctx_mask,
174 enum icp_qat_uof_regtype reg_type,
175 unsigned short reg_num, unsigned int regdata);
176int qat_hal_init_nn(struct icp_qat_fw_loader_handle *handle,
177 unsigned char ae, unsigned long ctx_mask,
178 unsigned short reg_num, unsigned int regdata);
179int qat_hal_wr_lm(struct icp_qat_fw_loader_handle *handle,
180 unsigned char ae, unsigned short lm_addr, unsigned int value);
181void qat_hal_set_ae_tindex_mode(struct icp_qat_fw_loader_handle *handle,
182 unsigned char ae, unsigned char mode);
183int qat_uclo_wr_all_uimage(struct icp_qat_fw_loader_handle *handle);
184void qat_uclo_del_obj(struct icp_qat_fw_loader_handle *handle);
185int qat_uclo_wr_mimage(struct icp_qat_fw_loader_handle *handle, void *addr_ptr,
186 int mem_size);
187int qat_uclo_map_obj(struct icp_qat_fw_loader_handle *handle,
188 void *addr_ptr, u32 mem_size, char *obj_name);
189int qat_uclo_set_cfg_ae_mask(struct icp_qat_fw_loader_handle *handle,
190 unsigned int cfg_ae_mask);
191#if defined(CONFIG_PCI_IOV)
192int adf_sriov_configure(struct pci_dev *pdev, int numvfs);
193void adf_disable_sriov(struct adf_accel_dev *accel_dev);
194void adf_disable_vf2pf_interrupts(struct adf_accel_dev *accel_dev,
195 u32 vf_mask);
196void adf_enable_vf2pf_interrupts(struct adf_accel_dev *accel_dev,
197 u32 vf_mask);
198bool adf_recv_and_handle_pf2vf_msg(struct adf_accel_dev *accel_dev);
199bool adf_recv_and_handle_vf2pf_msg(struct adf_accel_dev *accel_dev, u32 vf_nr);
200int adf_pf2vf_handle_pf_restarting(struct adf_accel_dev *accel_dev);
201void adf_enable_pf2vf_interrupts(struct adf_accel_dev *accel_dev);
202void adf_disable_pf2vf_interrupts(struct adf_accel_dev *accel_dev);
203void adf_schedule_vf2pf_handler(struct adf_accel_vf_info *vf_info);
204int adf_init_pf_wq(void);
205void adf_exit_pf_wq(void);
206int adf_init_vf_wq(void);
207void adf_exit_vf_wq(void);
208void adf_flush_vf_wq(struct adf_accel_dev *accel_dev);
209#else
210#define adf_sriov_configure NULL
211
212static inline void adf_disable_sriov(struct adf_accel_dev *accel_dev)
213{
214}
215
216static inline void adf_enable_pf2vf_interrupts(struct adf_accel_dev *accel_dev)
217{
218}
219
220static inline void adf_disable_pf2vf_interrupts(struct adf_accel_dev *accel_dev)
221{
222}
223
224static inline int adf_init_pf_wq(void)
225{
226 return 0;
227}
228
229static inline void adf_exit_pf_wq(void)
230{
231}
232
233static inline int adf_init_vf_wq(void)
234{
235 return 0;
236}
237
238static inline void adf_exit_vf_wq(void)
239{
240}
241
242static inline void adf_flush_vf_wq(struct adf_accel_dev *accel_dev)
243{
244}
245
246#endif
247
248static inline void __iomem *adf_get_pmisc_base(struct adf_accel_dev *accel_dev)
249{
250 struct adf_hw_device_data *hw_data = accel_dev->hw_device;
251 struct adf_bar *pmisc;
252
253 pmisc = &GET_BARS(accel_dev)[hw_data->get_misc_bar_id(hw_data)];
254
255 return pmisc->virt_addr;
256}
257
258#endif
259
