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22#include <linux/edac.h>
23#include <linux/module.h>
24#include <linux/platform_device.h>
25#include <linux/interrupt.h>
26#include <linux/of.h>
27#include <linux/of_device.h>
28
29#include "edac_module.h"
30
31
32#define SYNPS_EDAC_NR_CSROWS 1
33
34
35#define SYNPS_EDAC_NR_CHANS 1
36
37
38#define SYNPS_EDAC_ERR_GRAIN 1
39
40#define SYNPS_EDAC_MSG_SIZE 256
41
42#define SYNPS_EDAC_MOD_STRING "synps_edac"
43#define SYNPS_EDAC_MOD_VER "1"
44
45
46#define CTRL_OFST 0x0
47#define T_ZQ_OFST 0xA4
48
49
50#define ECC_CTRL_OFST 0xC4
51
52#define CE_LOG_OFST 0xC8
53
54#define CE_ADDR_OFST 0xCC
55
56#define CE_DATA_31_0_OFST 0xD0
57
58
59#define UE_LOG_OFST 0xDC
60#define UE_ADDR_OFST 0xE0
61#define UE_DATA_31_0_OFST 0xE4
62
63#define STAT_OFST 0xF0
64#define SCRUB_OFST 0xF4
65
66
67#define CTRL_BW_MASK 0xC
68#define CTRL_BW_SHIFT 2
69
70#define DDRCTL_WDTH_16 1
71#define DDRCTL_WDTH_32 0
72
73
74#define T_ZQ_DDRMODE_MASK 0x2
75
76
77#define ECC_CTRL_CLR_CE_ERR 0x2
78#define ECC_CTRL_CLR_UE_ERR 0x1
79
80
81#define LOG_VALID 0x1
82#define CE_LOG_BITPOS_MASK 0xFE
83#define CE_LOG_BITPOS_SHIFT 1
84
85
86#define ADDR_COL_MASK 0xFFF
87#define ADDR_ROW_MASK 0xFFFF000
88#define ADDR_ROW_SHIFT 12
89#define ADDR_BANK_MASK 0x70000000
90#define ADDR_BANK_SHIFT 28
91
92
93#define STAT_UECNT_MASK 0xFF
94#define STAT_CECNT_MASK 0xFF00
95#define STAT_CECNT_SHIFT 8
96
97
98#define SCRUB_MODE_MASK 0x7
99#define SCRUB_MODE_SECDED 0x4
100
101
102#define DDR_ECC_INTR_SUPPORT BIT(0)
103#define DDR_ECC_DATA_POISON_SUPPORT BIT(1)
104#define DDR_ECC_INTR_SELF_CLEAR BIT(2)
105
106
107
108#define ECC_CFG0_OFST 0x70
109#define ECC_CFG1_OFST 0x74
110
111
112#define ECC_STAT_OFST 0x78
113
114
115#define ECC_CLR_OFST 0x7C
116
117
118#define ECC_ERRCNT_OFST 0x80
119
120
121#define ECC_CEADDR0_OFST 0x84
122#define ECC_CEADDR1_OFST 0x88
123
124
125#define ECC_CSYND0_OFST 0x8C
126#define ECC_CSYND1_OFST 0x90
127#define ECC_CSYND2_OFST 0x94
128
129
130#define ECC_BITMASK0_OFST 0x98
131#define ECC_BITMASK1_OFST 0x9C
132#define ECC_BITMASK2_OFST 0xA0
133
134
135#define ECC_UEADDR0_OFST 0xA4
136#define ECC_UEADDR1_OFST 0xA8
137
138
139#define ECC_UESYND0_OFST 0xAC
140#define ECC_UESYND1_OFST 0xB0
141#define ECC_UESYND2_OFST 0xB4
142
143
144#define ECC_POISON0_OFST 0xB8
145#define ECC_POISON1_OFST 0xBC
146
147#define ECC_ADDRMAP0_OFFSET 0x200
148
149
150#define ECC_CTRL_BUSWIDTH_MASK 0x3000
151#define ECC_CTRL_BUSWIDTH_SHIFT 12
152#define ECC_CTRL_CLR_CE_ERRCNT BIT(2)
153#define ECC_CTRL_CLR_UE_ERRCNT BIT(3)
154
155
156#define DDRCTL_EWDTH_16 2
157#define DDRCTL_EWDTH_32 1
158#define DDRCTL_EWDTH_64 0
159
160
161#define ECC_STAT_UECNT_MASK 0xF0000
162#define ECC_STAT_UECNT_SHIFT 16
163#define ECC_STAT_CECNT_MASK 0xF00
164#define ECC_STAT_CECNT_SHIFT 8
165#define ECC_STAT_BITNUM_MASK 0x7F
166
167
168#define DDR_QOS_IRQ_STAT_OFST 0x20200
169#define DDR_QOSUE_MASK 0x4
170#define DDR_QOSCE_MASK 0x2
171#define ECC_CE_UE_INTR_MASK 0x6
172#define DDR_QOS_IRQ_EN_OFST 0x20208
173#define DDR_QOS_IRQ_DB_OFST 0x2020C
174
175
176#define DDR_UE_MASK BIT(9)
177#define DDR_CE_MASK BIT(8)
178
179
180#define ECC_CEADDR0_RW_MASK 0x3FFFF
181#define ECC_CEADDR0_RNK_MASK BIT(24)
182#define ECC_CEADDR1_BNKGRP_MASK 0x3000000
183#define ECC_CEADDR1_BNKNR_MASK 0x70000
184#define ECC_CEADDR1_BLKNR_MASK 0xFFF
185#define ECC_CEADDR1_BNKGRP_SHIFT 24
186#define ECC_CEADDR1_BNKNR_SHIFT 16
187
188
189#define ECC_POISON0_RANK_SHIFT 24
190#define ECC_POISON0_RANK_MASK BIT(24)
191#define ECC_POISON0_COLUMN_SHIFT 0
192#define ECC_POISON0_COLUMN_MASK 0xFFF
193#define ECC_POISON1_BG_SHIFT 28
194#define ECC_POISON1_BG_MASK 0x30000000
195#define ECC_POISON1_BANKNR_SHIFT 24
196#define ECC_POISON1_BANKNR_MASK 0x7000000
197#define ECC_POISON1_ROW_SHIFT 0
198#define ECC_POISON1_ROW_MASK 0x3FFFF
199
200
201#define MEM_TYPE_DDR3 0x1
202#define MEM_TYPE_LPDDR3 0x8
203#define MEM_TYPE_DDR2 0x4
204#define MEM_TYPE_DDR4 0x10
205#define MEM_TYPE_LPDDR4 0x20
206
207
208#define DDRC_SWCTL 0x320
209
210
211#define ECC_CEPOISON_MASK 0x3
212#define ECC_UEPOISON_MASK 0x1
213
214
215#define DDRC_MSTR_CFG_MASK 0xC0000000
216#define DDRC_MSTR_CFG_SHIFT 30
217#define DDRC_MSTR_CFG_X4_MASK 0x0
218#define DDRC_MSTR_CFG_X8_MASK 0x1
219#define DDRC_MSTR_CFG_X16_MASK 0x2
220#define DDRC_MSTR_CFG_X32_MASK 0x3
221
222#define DDR_MAX_ROW_SHIFT 18
223#define DDR_MAX_COL_SHIFT 14
224#define DDR_MAX_BANK_SHIFT 3
225#define DDR_MAX_BANKGRP_SHIFT 2
226
227#define ROW_MAX_VAL_MASK 0xF
228#define COL_MAX_VAL_MASK 0xF
229#define BANK_MAX_VAL_MASK 0x1F
230#define BANKGRP_MAX_VAL_MASK 0x1F
231#define RANK_MAX_VAL_MASK 0x1F
232
233#define ROW_B0_BASE 6
234#define ROW_B1_BASE 7
235#define ROW_B2_BASE 8
236#define ROW_B3_BASE 9
237#define ROW_B4_BASE 10
238#define ROW_B5_BASE 11
239#define ROW_B6_BASE 12
240#define ROW_B7_BASE 13
241#define ROW_B8_BASE 14
242#define ROW_B9_BASE 15
243#define ROW_B10_BASE 16
244#define ROW_B11_BASE 17
245#define ROW_B12_BASE 18
246#define ROW_B13_BASE 19
247#define ROW_B14_BASE 20
248#define ROW_B15_BASE 21
249#define ROW_B16_BASE 22
250#define ROW_B17_BASE 23
251
252#define COL_B2_BASE 2
253#define COL_B3_BASE 3
254#define COL_B4_BASE 4
255#define COL_B5_BASE 5
256#define COL_B6_BASE 6
257#define COL_B7_BASE 7
258#define COL_B8_BASE 8
259#define COL_B9_BASE 9
260#define COL_B10_BASE 10
261#define COL_B11_BASE 11
262#define COL_B12_BASE 12
263#define COL_B13_BASE 13
264
265#define BANK_B0_BASE 2
266#define BANK_B1_BASE 3
267#define BANK_B2_BASE 4
268
269#define BANKGRP_B0_BASE 2
270#define BANKGRP_B1_BASE 3
271
272#define RANK_B0_BASE 6
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283
284struct ecc_error_info {
285 u32 row;
286 u32 col;
287 u32 bank;
288 u32 bitpos;
289 u32 data;
290 u32 bankgrpnr;
291 u32 blknr;
292};
293
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299
300
301struct synps_ecc_status {
302 u32 ce_cnt;
303 u32 ue_cnt;
304 struct ecc_error_info ceinfo;
305 struct ecc_error_info ueinfo;
306};
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322
323struct synps_edac_priv {
324 void __iomem *baseaddr;
325 char message[SYNPS_EDAC_MSG_SIZE];
326 struct synps_ecc_status stat;
327 const struct synps_platform_data *p_data;
328 u32 ce_cnt;
329 u32 ue_cnt;
330#ifdef CONFIG_EDAC_DEBUG
331 ulong poison_addr;
332 u32 row_shift[18];
333 u32 col_shift[14];
334 u32 bank_shift[3];
335 u32 bankgrp_shift[2];
336 u32 rank_shift[1];
337#endif
338};
339
340
341
342
343
344
345
346
347
348struct synps_platform_data {
349 int (*get_error_info)(struct synps_edac_priv *priv);
350 enum mem_type (*get_mtype)(const void __iomem *base);
351 enum dev_type (*get_dtype)(const void __iomem *base);
352 bool (*get_ecc_state)(void __iomem *base);
353 int quirks;
354};
355
356
357
358
359
360
361
362static int zynq_get_error_info(struct synps_edac_priv *priv)
363{
364 struct synps_ecc_status *p;
365 u32 regval, clearval = 0;
366 void __iomem *base;
367
368 base = priv->baseaddr;
369 p = &priv->stat;
370
371 regval = readl(base + STAT_OFST);
372 if (!regval)
373 return 1;
374
375 p->ce_cnt = (regval & STAT_CECNT_MASK) >> STAT_CECNT_SHIFT;
376 p->ue_cnt = regval & STAT_UECNT_MASK;
377
378 regval = readl(base + CE_LOG_OFST);
379 if (!(p->ce_cnt && (regval & LOG_VALID)))
380 goto ue_err;
381
382 p->ceinfo.bitpos = (regval & CE_LOG_BITPOS_MASK) >> CE_LOG_BITPOS_SHIFT;
383 regval = readl(base + CE_ADDR_OFST);
384 p->ceinfo.row = (regval & ADDR_ROW_MASK) >> ADDR_ROW_SHIFT;
385 p->ceinfo.col = regval & ADDR_COL_MASK;
386 p->ceinfo.bank = (regval & ADDR_BANK_MASK) >> ADDR_BANK_SHIFT;
387 p->ceinfo.data = readl(base + CE_DATA_31_0_OFST);
388 edac_dbg(3, "CE bit position: %d data: %d\n", p->ceinfo.bitpos,
389 p->ceinfo.data);
390 clearval = ECC_CTRL_CLR_CE_ERR;
391
392ue_err:
393 regval = readl(base + UE_LOG_OFST);
394 if (!(p->ue_cnt && (regval & LOG_VALID)))
395 goto out;
396
397 regval = readl(base + UE_ADDR_OFST);
398 p->ueinfo.row = (regval & ADDR_ROW_MASK) >> ADDR_ROW_SHIFT;
399 p->ueinfo.col = regval & ADDR_COL_MASK;
400 p->ueinfo.bank = (regval & ADDR_BANK_MASK) >> ADDR_BANK_SHIFT;
401 p->ueinfo.data = readl(base + UE_DATA_31_0_OFST);
402 clearval |= ECC_CTRL_CLR_UE_ERR;
403
404out:
405 writel(clearval, base + ECC_CTRL_OFST);
406 writel(0x0, base + ECC_CTRL_OFST);
407
408 return 0;
409}
410
411
412
413
414
415
416
417static int zynqmp_get_error_info(struct synps_edac_priv *priv)
418{
419 struct synps_ecc_status *p;
420 u32 regval, clearval = 0;
421 void __iomem *base;
422
423 base = priv->baseaddr;
424 p = &priv->stat;
425
426 regval = readl(base + ECC_STAT_OFST);
427 if (!regval)
428 return 1;
429
430 p->ce_cnt = (regval & ECC_STAT_CECNT_MASK) >> ECC_STAT_CECNT_SHIFT;
431 p->ue_cnt = (regval & ECC_STAT_UECNT_MASK) >> ECC_STAT_UECNT_SHIFT;
432 if (!p->ce_cnt)
433 goto ue_err;
434
435 p->ceinfo.bitpos = (regval & ECC_STAT_BITNUM_MASK);
436
437 regval = readl(base + ECC_CEADDR0_OFST);
438 p->ceinfo.row = (regval & ECC_CEADDR0_RW_MASK);
439 regval = readl(base + ECC_CEADDR1_OFST);
440 p->ceinfo.bank = (regval & ECC_CEADDR1_BNKNR_MASK) >>
441 ECC_CEADDR1_BNKNR_SHIFT;
442 p->ceinfo.bankgrpnr = (regval & ECC_CEADDR1_BNKGRP_MASK) >>
443 ECC_CEADDR1_BNKGRP_SHIFT;
444 p->ceinfo.blknr = (regval & ECC_CEADDR1_BLKNR_MASK);
445 p->ceinfo.data = readl(base + ECC_CSYND0_OFST);
446 edac_dbg(2, "ECCCSYN0: 0x%08X ECCCSYN1: 0x%08X ECCCSYN2: 0x%08X\n",
447 readl(base + ECC_CSYND0_OFST), readl(base + ECC_CSYND1_OFST),
448 readl(base + ECC_CSYND2_OFST));
449ue_err:
450 if (!p->ue_cnt)
451 goto out;
452
453 regval = readl(base + ECC_UEADDR0_OFST);
454 p->ueinfo.row = (regval & ECC_CEADDR0_RW_MASK);
455 regval = readl(base + ECC_UEADDR1_OFST);
456 p->ueinfo.bankgrpnr = (regval & ECC_CEADDR1_BNKGRP_MASK) >>
457 ECC_CEADDR1_BNKGRP_SHIFT;
458 p->ueinfo.bank = (regval & ECC_CEADDR1_BNKNR_MASK) >>
459 ECC_CEADDR1_BNKNR_SHIFT;
460 p->ueinfo.blknr = (regval & ECC_CEADDR1_BLKNR_MASK);
461 p->ueinfo.data = readl(base + ECC_UESYND0_OFST);
462out:
463 clearval = ECC_CTRL_CLR_CE_ERR | ECC_CTRL_CLR_CE_ERRCNT;
464 clearval |= ECC_CTRL_CLR_UE_ERR | ECC_CTRL_CLR_UE_ERRCNT;
465 writel(clearval, base + ECC_CLR_OFST);
466 writel(0x0, base + ECC_CLR_OFST);
467
468 return 0;
469}
470
471
472
473
474
475
476
477
478static void handle_error(struct mem_ctl_info *mci, struct synps_ecc_status *p)
479{
480 struct synps_edac_priv *priv = mci->pvt_info;
481 struct ecc_error_info *pinf;
482
483 if (p->ce_cnt) {
484 pinf = &p->ceinfo;
485 if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT) {
486 snprintf(priv->message, SYNPS_EDAC_MSG_SIZE,
487 "DDR ECC error type:%s Row %d Bank %d BankGroup Number %d Block Number %d Bit Position: %d Data: 0x%08x",
488 "CE", pinf->row, pinf->bank,
489 pinf->bankgrpnr, pinf->blknr,
490 pinf->bitpos, pinf->data);
491 } else {
492 snprintf(priv->message, SYNPS_EDAC_MSG_SIZE,
493 "DDR ECC error type:%s Row %d Bank %d Col %d Bit Position: %d Data: 0x%08x",
494 "CE", pinf->row, pinf->bank, pinf->col,
495 pinf->bitpos, pinf->data);
496 }
497
498 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci,
499 p->ce_cnt, 0, 0, 0, 0, 0, -1,
500 priv->message, "");
501 }
502
503 if (p->ue_cnt) {
504 pinf = &p->ueinfo;
505 if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT) {
506 snprintf(priv->message, SYNPS_EDAC_MSG_SIZE,
507 "DDR ECC error type :%s Row %d Bank %d BankGroup Number %d Block Number %d",
508 "UE", pinf->row, pinf->bank,
509 pinf->bankgrpnr, pinf->blknr);
510 } else {
511 snprintf(priv->message, SYNPS_EDAC_MSG_SIZE,
512 "DDR ECC error type :%s Row %d Bank %d Col %d ",
513 "UE", pinf->row, pinf->bank, pinf->col);
514 }
515
516 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci,
517 p->ue_cnt, 0, 0, 0, 0, 0, -1,
518 priv->message, "");
519 }
520
521 memset(p, 0, sizeof(*p));
522}
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530
531static irqreturn_t intr_handler(int irq, void *dev_id)
532{
533 const struct synps_platform_data *p_data;
534 struct mem_ctl_info *mci = dev_id;
535 struct synps_edac_priv *priv;
536 int status, regval;
537
538 priv = mci->pvt_info;
539 p_data = priv->p_data;
540
541
542
543
544
545 if (!(priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR)) {
546 regval = readl(priv->baseaddr + DDR_QOS_IRQ_STAT_OFST);
547 regval &= (DDR_QOSCE_MASK | DDR_QOSUE_MASK);
548 if (!(regval & ECC_CE_UE_INTR_MASK))
549 return IRQ_NONE;
550 }
551
552 status = p_data->get_error_info(priv);
553 if (status)
554 return IRQ_NONE;
555
556 priv->ce_cnt += priv->stat.ce_cnt;
557 priv->ue_cnt += priv->stat.ue_cnt;
558 handle_error(mci, &priv->stat);
559
560 edac_dbg(3, "Total error count CE %d UE %d\n",
561 priv->ce_cnt, priv->ue_cnt);
562
563 if (!(priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR))
564 writel(regval, priv->baseaddr + DDR_QOS_IRQ_STAT_OFST);
565 return IRQ_HANDLED;
566}
567
568
569
570
571
572
573
574static void check_errors(struct mem_ctl_info *mci)
575{
576 const struct synps_platform_data *p_data;
577 struct synps_edac_priv *priv;
578 int status;
579
580 priv = mci->pvt_info;
581 p_data = priv->p_data;
582
583 status = p_data->get_error_info(priv);
584 if (status)
585 return;
586
587 priv->ce_cnt += priv->stat.ce_cnt;
588 priv->ue_cnt += priv->stat.ue_cnt;
589 handle_error(mci, &priv->stat);
590
591 edac_dbg(3, "Total error count CE %d UE %d\n",
592 priv->ce_cnt, priv->ue_cnt);
593}
594
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603
604static enum dev_type zynq_get_dtype(const void __iomem *base)
605{
606 enum dev_type dt;
607 u32 width;
608
609 width = readl(base + CTRL_OFST);
610 width = (width & CTRL_BW_MASK) >> CTRL_BW_SHIFT;
611
612 switch (width) {
613 case DDRCTL_WDTH_16:
614 dt = DEV_X2;
615 break;
616 case DDRCTL_WDTH_32:
617 dt = DEV_X4;
618 break;
619 default:
620 dt = DEV_UNKNOWN;
621 }
622
623 return dt;
624}
625
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631
632
633
634
635static enum dev_type zynqmp_get_dtype(const void __iomem *base)
636{
637 enum dev_type dt;
638 u32 width;
639
640 width = readl(base + CTRL_OFST);
641 width = (width & ECC_CTRL_BUSWIDTH_MASK) >> ECC_CTRL_BUSWIDTH_SHIFT;
642 switch (width) {
643 case DDRCTL_EWDTH_16:
644 dt = DEV_X2;
645 break;
646 case DDRCTL_EWDTH_32:
647 dt = DEV_X4;
648 break;
649 case DDRCTL_EWDTH_64:
650 dt = DEV_X8;
651 break;
652 default:
653 dt = DEV_UNKNOWN;
654 }
655
656 return dt;
657}
658
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662
663
664
665
666
667static bool zynq_get_ecc_state(void __iomem *base)
668{
669 enum dev_type dt;
670 u32 ecctype;
671
672 dt = zynq_get_dtype(base);
673 if (dt == DEV_UNKNOWN)
674 return false;
675
676 ecctype = readl(base + SCRUB_OFST) & SCRUB_MODE_MASK;
677 if ((ecctype == SCRUB_MODE_SECDED) && (dt == DEV_X2))
678 return true;
679
680 return false;
681}
682
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690
691static bool zynqmp_get_ecc_state(void __iomem *base)
692{
693 enum dev_type dt;
694 u32 ecctype;
695
696 dt = zynqmp_get_dtype(base);
697 if (dt == DEV_UNKNOWN)
698 return false;
699
700 ecctype = readl(base + ECC_CFG0_OFST) & SCRUB_MODE_MASK;
701 if ((ecctype == SCRUB_MODE_SECDED) &&
702 ((dt == DEV_X2) || (dt == DEV_X4) || (dt == DEV_X8)))
703 return true;
704
705 return false;
706}
707
708
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711
712
713static u32 get_memsize(void)
714{
715 struct sysinfo inf;
716
717 si_meminfo(&inf);
718
719 return inf.totalram * inf.mem_unit;
720}
721
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730
731static enum mem_type zynq_get_mtype(const void __iomem *base)
732{
733 enum mem_type mt;
734 u32 memtype;
735
736 memtype = readl(base + T_ZQ_OFST);
737
738 if (memtype & T_ZQ_DDRMODE_MASK)
739 mt = MEM_DDR3;
740 else
741 mt = MEM_DDR2;
742
743 return mt;
744}
745
746
747
748
749
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753
754
755static enum mem_type zynqmp_get_mtype(const void __iomem *base)
756{
757 enum mem_type mt;
758 u32 memtype;
759
760 memtype = readl(base + CTRL_OFST);
761
762 if ((memtype & MEM_TYPE_DDR3) || (memtype & MEM_TYPE_LPDDR3))
763 mt = MEM_DDR3;
764 else if (memtype & MEM_TYPE_DDR2)
765 mt = MEM_RDDR2;
766 else if ((memtype & MEM_TYPE_LPDDR4) || (memtype & MEM_TYPE_DDR4))
767 mt = MEM_DDR4;
768 else
769 mt = MEM_EMPTY;
770
771 return mt;
772}
773
774
775
776
777
778
779
780
781static void init_csrows(struct mem_ctl_info *mci)
782{
783 struct synps_edac_priv *priv = mci->pvt_info;
784 const struct synps_platform_data *p_data;
785 struct csrow_info *csi;
786 struct dimm_info *dimm;
787 u32 size, row;
788 int j;
789
790 p_data = priv->p_data;
791
792 for (row = 0; row < mci->nr_csrows; row++) {
793 csi = mci->csrows[row];
794 size = get_memsize();
795
796 for (j = 0; j < csi->nr_channels; j++) {
797 dimm = csi->channels[j]->dimm;
798 dimm->edac_mode = EDAC_SECDED;
799 dimm->mtype = p_data->get_mtype(priv->baseaddr);
800 dimm->nr_pages = (size >> PAGE_SHIFT) / csi->nr_channels;
801 dimm->grain = SYNPS_EDAC_ERR_GRAIN;
802 dimm->dtype = p_data->get_dtype(priv->baseaddr);
803 }
804 }
805}
806
807
808
809
810
811
812
813
814
815
816static void mc_init(struct mem_ctl_info *mci, struct platform_device *pdev)
817{
818 struct synps_edac_priv *priv;
819
820 mci->pdev = &pdev->dev;
821 priv = mci->pvt_info;
822 platform_set_drvdata(pdev, mci);
823
824
825 mci->mtype_cap = MEM_FLAG_DDR3 | MEM_FLAG_DDR2;
826 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
827 mci->scrub_cap = SCRUB_HW_SRC;
828 mci->scrub_mode = SCRUB_NONE;
829
830 mci->edac_cap = EDAC_FLAG_SECDED;
831 mci->ctl_name = "synps_ddr_controller";
832 mci->dev_name = SYNPS_EDAC_MOD_STRING;
833 mci->mod_name = SYNPS_EDAC_MOD_VER;
834
835 if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT) {
836 edac_op_state = EDAC_OPSTATE_INT;
837 } else {
838 edac_op_state = EDAC_OPSTATE_POLL;
839 mci->edac_check = check_errors;
840 }
841
842 mci->ctl_page_to_phys = NULL;
843
844 init_csrows(mci);
845}
846
847static void enable_intr(struct synps_edac_priv *priv)
848{
849
850 if (priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR)
851 writel(DDR_UE_MASK | DDR_CE_MASK,
852 priv->baseaddr + ECC_CLR_OFST);
853 else
854 writel(DDR_QOSUE_MASK | DDR_QOSCE_MASK,
855 priv->baseaddr + DDR_QOS_IRQ_EN_OFST);
856
857}
858
859static void disable_intr(struct synps_edac_priv *priv)
860{
861
862 writel(DDR_QOSUE_MASK | DDR_QOSCE_MASK,
863 priv->baseaddr + DDR_QOS_IRQ_DB_OFST);
864}
865
866static int setup_irq(struct mem_ctl_info *mci,
867 struct platform_device *pdev)
868{
869 struct synps_edac_priv *priv = mci->pvt_info;
870 int ret, irq;
871
872 irq = platform_get_irq(pdev, 0);
873 if (irq < 0) {
874 edac_printk(KERN_ERR, EDAC_MC,
875 "No IRQ %d in DT\n", irq);
876 return irq;
877 }
878
879 ret = devm_request_irq(&pdev->dev, irq, intr_handler,
880 0, dev_name(&pdev->dev), mci);
881 if (ret < 0) {
882 edac_printk(KERN_ERR, EDAC_MC, "Failed to request IRQ\n");
883 return ret;
884 }
885
886 enable_intr(priv);
887
888 return 0;
889}
890
891static const struct synps_platform_data zynq_edac_def = {
892 .get_error_info = zynq_get_error_info,
893 .get_mtype = zynq_get_mtype,
894 .get_dtype = zynq_get_dtype,
895 .get_ecc_state = zynq_get_ecc_state,
896 .quirks = 0,
897};
898
899static const struct synps_platform_data zynqmp_edac_def = {
900 .get_error_info = zynqmp_get_error_info,
901 .get_mtype = zynqmp_get_mtype,
902 .get_dtype = zynqmp_get_dtype,
903 .get_ecc_state = zynqmp_get_ecc_state,
904 .quirks = (DDR_ECC_INTR_SUPPORT
905#ifdef CONFIG_EDAC_DEBUG
906 | DDR_ECC_DATA_POISON_SUPPORT
907#endif
908 ),
909};
910
911static const struct synps_platform_data synopsys_edac_def = {
912 .get_error_info = zynqmp_get_error_info,
913 .get_mtype = zynqmp_get_mtype,
914 .get_dtype = zynqmp_get_dtype,
915 .get_ecc_state = zynqmp_get_ecc_state,
916 .quirks = (DDR_ECC_INTR_SUPPORT | DDR_ECC_INTR_SELF_CLEAR
917#ifdef CONFIG_EDAC_DEBUG
918 | DDR_ECC_DATA_POISON_SUPPORT
919#endif
920 ),
921};
922
923
924static const struct of_device_id synps_edac_match[] = {
925 {
926 .compatible = "xlnx,zynq-ddrc-a05",
927 .data = (void *)&zynq_edac_def
928 },
929 {
930 .compatible = "xlnx,zynqmp-ddrc-2.40a",
931 .data = (void *)&zynqmp_edac_def
932 },
933 {
934 .compatible = "snps,ddrc-3.80a",
935 .data = (void *)&synopsys_edac_def
936 },
937 {
938
939 }
940};
941
942MODULE_DEVICE_TABLE(of, synps_edac_match);
943
944#ifdef CONFIG_EDAC_DEBUG
945#define to_mci(k) container_of(k, struct mem_ctl_info, dev)
946
947
948
949
950
951
952
953
954static void ddr_poison_setup(struct synps_edac_priv *priv)
955{
956 int col = 0, row = 0, bank = 0, bankgrp = 0, rank = 0, regval;
957 int index;
958 ulong hif_addr = 0;
959
960 hif_addr = priv->poison_addr >> 3;
961
962 for (index = 0; index < DDR_MAX_ROW_SHIFT; index++) {
963 if (priv->row_shift[index])
964 row |= (((hif_addr >> priv->row_shift[index]) &
965 BIT(0)) << index);
966 else
967 break;
968 }
969
970 for (index = 0; index < DDR_MAX_COL_SHIFT; index++) {
971 if (priv->col_shift[index] || index < 3)
972 col |= (((hif_addr >> priv->col_shift[index]) &
973 BIT(0)) << index);
974 else
975 break;
976 }
977
978 for (index = 0; index < DDR_MAX_BANK_SHIFT; index++) {
979 if (priv->bank_shift[index])
980 bank |= (((hif_addr >> priv->bank_shift[index]) &
981 BIT(0)) << index);
982 else
983 break;
984 }
985
986 for (index = 0; index < DDR_MAX_BANKGRP_SHIFT; index++) {
987 if (priv->bankgrp_shift[index])
988 bankgrp |= (((hif_addr >> priv->bankgrp_shift[index])
989 & BIT(0)) << index);
990 else
991 break;
992 }
993
994 if (priv->rank_shift[0])
995 rank = (hif_addr >> priv->rank_shift[0]) & BIT(0);
996
997 regval = (rank << ECC_POISON0_RANK_SHIFT) & ECC_POISON0_RANK_MASK;
998 regval |= (col << ECC_POISON0_COLUMN_SHIFT) & ECC_POISON0_COLUMN_MASK;
999 writel(regval, priv->baseaddr + ECC_POISON0_OFST);
1000
1001 regval = (bankgrp << ECC_POISON1_BG_SHIFT) & ECC_POISON1_BG_MASK;
1002 regval |= (bank << ECC_POISON1_BANKNR_SHIFT) & ECC_POISON1_BANKNR_MASK;
1003 regval |= (row << ECC_POISON1_ROW_SHIFT) & ECC_POISON1_ROW_MASK;
1004 writel(regval, priv->baseaddr + ECC_POISON1_OFST);
1005}
1006
1007static ssize_t inject_data_error_show(struct device *dev,
1008 struct device_attribute *mattr,
1009 char *data)
1010{
1011 struct mem_ctl_info *mci = to_mci(dev);
1012 struct synps_edac_priv *priv = mci->pvt_info;
1013
1014 return sprintf(data, "Poison0 Addr: 0x%08x\n\rPoison1 Addr: 0x%08x\n\r"
1015 "Error injection Address: 0x%lx\n\r",
1016 readl(priv->baseaddr + ECC_POISON0_OFST),
1017 readl(priv->baseaddr + ECC_POISON1_OFST),
1018 priv->poison_addr);
1019}
1020
1021static ssize_t inject_data_error_store(struct device *dev,
1022 struct device_attribute *mattr,
1023 const char *data, size_t count)
1024{
1025 struct mem_ctl_info *mci = to_mci(dev);
1026 struct synps_edac_priv *priv = mci->pvt_info;
1027
1028 if (kstrtoul(data, 0, &priv->poison_addr))
1029 return -EINVAL;
1030
1031 ddr_poison_setup(priv);
1032
1033 return count;
1034}
1035
1036static ssize_t inject_data_poison_show(struct device *dev,
1037 struct device_attribute *mattr,
1038 char *data)
1039{
1040 struct mem_ctl_info *mci = to_mci(dev);
1041 struct synps_edac_priv *priv = mci->pvt_info;
1042
1043 return sprintf(data, "Data Poisoning: %s\n\r",
1044 (((readl(priv->baseaddr + ECC_CFG1_OFST)) & 0x3) == 0x3)
1045 ? ("Correctable Error") : ("UnCorrectable Error"));
1046}
1047
1048static ssize_t inject_data_poison_store(struct device *dev,
1049 struct device_attribute *mattr,
1050 const char *data, size_t count)
1051{
1052 struct mem_ctl_info *mci = to_mci(dev);
1053 struct synps_edac_priv *priv = mci->pvt_info;
1054
1055 writel(0, priv->baseaddr + DDRC_SWCTL);
1056 if (strncmp(data, "CE", 2) == 0)
1057 writel(ECC_CEPOISON_MASK, priv->baseaddr + ECC_CFG1_OFST);
1058 else
1059 writel(ECC_UEPOISON_MASK, priv->baseaddr + ECC_CFG1_OFST);
1060 writel(1, priv->baseaddr + DDRC_SWCTL);
1061
1062 return count;
1063}
1064
1065static DEVICE_ATTR_RW(inject_data_error);
1066static DEVICE_ATTR_RW(inject_data_poison);
1067
1068static int edac_create_sysfs_attributes(struct mem_ctl_info *mci)
1069{
1070 int rc;
1071
1072 rc = device_create_file(&mci->dev, &dev_attr_inject_data_error);
1073 if (rc < 0)
1074 return rc;
1075 rc = device_create_file(&mci->dev, &dev_attr_inject_data_poison);
1076 if (rc < 0)
1077 return rc;
1078 return 0;
1079}
1080
1081static void edac_remove_sysfs_attributes(struct mem_ctl_info *mci)
1082{
1083 device_remove_file(&mci->dev, &dev_attr_inject_data_error);
1084 device_remove_file(&mci->dev, &dev_attr_inject_data_poison);
1085}
1086
1087static void setup_row_address_map(struct synps_edac_priv *priv, u32 *addrmap)
1088{
1089 u32 addrmap_row_b2_10;
1090 int index;
1091
1092 priv->row_shift[0] = (addrmap[5] & ROW_MAX_VAL_MASK) + ROW_B0_BASE;
1093 priv->row_shift[1] = ((addrmap[5] >> 8) &
1094 ROW_MAX_VAL_MASK) + ROW_B1_BASE;
1095
1096 addrmap_row_b2_10 = (addrmap[5] >> 16) & ROW_MAX_VAL_MASK;
1097 if (addrmap_row_b2_10 != ROW_MAX_VAL_MASK) {
1098 for (index = 2; index < 11; index++)
1099 priv->row_shift[index] = addrmap_row_b2_10 +
1100 index + ROW_B0_BASE;
1101
1102 } else {
1103 priv->row_shift[2] = (addrmap[9] &
1104 ROW_MAX_VAL_MASK) + ROW_B2_BASE;
1105 priv->row_shift[3] = ((addrmap[9] >> 8) &
1106 ROW_MAX_VAL_MASK) + ROW_B3_BASE;
1107 priv->row_shift[4] = ((addrmap[9] >> 16) &
1108 ROW_MAX_VAL_MASK) + ROW_B4_BASE;
1109 priv->row_shift[5] = ((addrmap[9] >> 24) &
1110 ROW_MAX_VAL_MASK) + ROW_B5_BASE;
1111 priv->row_shift[6] = (addrmap[10] &
1112 ROW_MAX_VAL_MASK) + ROW_B6_BASE;
1113 priv->row_shift[7] = ((addrmap[10] >> 8) &
1114 ROW_MAX_VAL_MASK) + ROW_B7_BASE;
1115 priv->row_shift[8] = ((addrmap[10] >> 16) &
1116 ROW_MAX_VAL_MASK) + ROW_B8_BASE;
1117 priv->row_shift[9] = ((addrmap[10] >> 24) &
1118 ROW_MAX_VAL_MASK) + ROW_B9_BASE;
1119 priv->row_shift[10] = (addrmap[11] &
1120 ROW_MAX_VAL_MASK) + ROW_B10_BASE;
1121 }
1122
1123 priv->row_shift[11] = (((addrmap[5] >> 24) & ROW_MAX_VAL_MASK) ==
1124 ROW_MAX_VAL_MASK) ? 0 : (((addrmap[5] >> 24) &
1125 ROW_MAX_VAL_MASK) + ROW_B11_BASE);
1126 priv->row_shift[12] = ((addrmap[6] & ROW_MAX_VAL_MASK) ==
1127 ROW_MAX_VAL_MASK) ? 0 : ((addrmap[6] &
1128 ROW_MAX_VAL_MASK) + ROW_B12_BASE);
1129 priv->row_shift[13] = (((addrmap[6] >> 8) & ROW_MAX_VAL_MASK) ==
1130 ROW_MAX_VAL_MASK) ? 0 : (((addrmap[6] >> 8) &
1131 ROW_MAX_VAL_MASK) + ROW_B13_BASE);
1132 priv->row_shift[14] = (((addrmap[6] >> 16) & ROW_MAX_VAL_MASK) ==
1133 ROW_MAX_VAL_MASK) ? 0 : (((addrmap[6] >> 16) &
1134 ROW_MAX_VAL_MASK) + ROW_B14_BASE);
1135 priv->row_shift[15] = (((addrmap[6] >> 24) & ROW_MAX_VAL_MASK) ==
1136 ROW_MAX_VAL_MASK) ? 0 : (((addrmap[6] >> 24) &
1137 ROW_MAX_VAL_MASK) + ROW_B15_BASE);
1138 priv->row_shift[16] = ((addrmap[7] & ROW_MAX_VAL_MASK) ==
1139 ROW_MAX_VAL_MASK) ? 0 : ((addrmap[7] &
1140 ROW_MAX_VAL_MASK) + ROW_B16_BASE);
1141 priv->row_shift[17] = (((addrmap[7] >> 8) & ROW_MAX_VAL_MASK) ==
1142 ROW_MAX_VAL_MASK) ? 0 : (((addrmap[7] >> 8) &
1143 ROW_MAX_VAL_MASK) + ROW_B17_BASE);
1144}
1145
1146static void setup_column_address_map(struct synps_edac_priv *priv, u32 *addrmap)
1147{
1148 u32 width, memtype;
1149 int index;
1150
1151 memtype = readl(priv->baseaddr + CTRL_OFST);
1152 width = (memtype & ECC_CTRL_BUSWIDTH_MASK) >> ECC_CTRL_BUSWIDTH_SHIFT;
1153
1154 priv->col_shift[0] = 0;
1155 priv->col_shift[1] = 1;
1156 priv->col_shift[2] = (addrmap[2] & COL_MAX_VAL_MASK) + COL_B2_BASE;
1157 priv->col_shift[3] = ((addrmap[2] >> 8) &
1158 COL_MAX_VAL_MASK) + COL_B3_BASE;
1159 priv->col_shift[4] = (((addrmap[2] >> 16) & COL_MAX_VAL_MASK) ==
1160 COL_MAX_VAL_MASK) ? 0 : (((addrmap[2] >> 16) &
1161 COL_MAX_VAL_MASK) + COL_B4_BASE);
1162 priv->col_shift[5] = (((addrmap[2] >> 24) & COL_MAX_VAL_MASK) ==
1163 COL_MAX_VAL_MASK) ? 0 : (((addrmap[2] >> 24) &
1164 COL_MAX_VAL_MASK) + COL_B5_BASE);
1165 priv->col_shift[6] = ((addrmap[3] & COL_MAX_VAL_MASK) ==
1166 COL_MAX_VAL_MASK) ? 0 : ((addrmap[3] &
1167 COL_MAX_VAL_MASK) + COL_B6_BASE);
1168 priv->col_shift[7] = (((addrmap[3] >> 8) & COL_MAX_VAL_MASK) ==
1169 COL_MAX_VAL_MASK) ? 0 : (((addrmap[3] >> 8) &
1170 COL_MAX_VAL_MASK) + COL_B7_BASE);
1171 priv->col_shift[8] = (((addrmap[3] >> 16) & COL_MAX_VAL_MASK) ==
1172 COL_MAX_VAL_MASK) ? 0 : (((addrmap[3] >> 16) &
1173 COL_MAX_VAL_MASK) + COL_B8_BASE);
1174 priv->col_shift[9] = (((addrmap[3] >> 24) & COL_MAX_VAL_MASK) ==
1175 COL_MAX_VAL_MASK) ? 0 : (((addrmap[3] >> 24) &
1176 COL_MAX_VAL_MASK) + COL_B9_BASE);
1177 if (width == DDRCTL_EWDTH_64) {
1178 if (memtype & MEM_TYPE_LPDDR3) {
1179 priv->col_shift[10] = ((addrmap[4] &
1180 COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 :
1181 ((addrmap[4] & COL_MAX_VAL_MASK) +
1182 COL_B10_BASE);
1183 priv->col_shift[11] = (((addrmap[4] >> 8) &
1184 COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 :
1185 (((addrmap[4] >> 8) & COL_MAX_VAL_MASK) +
1186 COL_B11_BASE);
1187 } else {
1188 priv->col_shift[11] = ((addrmap[4] &
1189 COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 :
1190 ((addrmap[4] & COL_MAX_VAL_MASK) +
1191 COL_B10_BASE);
1192 priv->col_shift[13] = (((addrmap[4] >> 8) &
1193 COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 :
1194 (((addrmap[4] >> 8) & COL_MAX_VAL_MASK) +
1195 COL_B11_BASE);
1196 }
1197 } else if (width == DDRCTL_EWDTH_32) {
1198 if (memtype & MEM_TYPE_LPDDR3) {
1199 priv->col_shift[10] = (((addrmap[3] >> 24) &
1200 COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 :
1201 (((addrmap[3] >> 24) & COL_MAX_VAL_MASK) +
1202 COL_B9_BASE);
1203 priv->col_shift[11] = ((addrmap[4] &
1204 COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 :
1205 ((addrmap[4] & COL_MAX_VAL_MASK) +
1206 COL_B10_BASE);
1207 } else {
1208 priv->col_shift[11] = (((addrmap[3] >> 24) &
1209 COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 :
1210 (((addrmap[3] >> 24) & COL_MAX_VAL_MASK) +
1211 COL_B9_BASE);
1212 priv->col_shift[13] = ((addrmap[4] &
1213 COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 :
1214 ((addrmap[4] & COL_MAX_VAL_MASK) +
1215 COL_B10_BASE);
1216 }
1217 } else {
1218 if (memtype & MEM_TYPE_LPDDR3) {
1219 priv->col_shift[10] = (((addrmap[3] >> 16) &
1220 COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 :
1221 (((addrmap[3] >> 16) & COL_MAX_VAL_MASK) +
1222 COL_B8_BASE);
1223 priv->col_shift[11] = (((addrmap[3] >> 24) &
1224 COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 :
1225 (((addrmap[3] >> 24) & COL_MAX_VAL_MASK) +
1226 COL_B9_BASE);
1227 priv->col_shift[13] = ((addrmap[4] &
1228 COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 :
1229 ((addrmap[4] & COL_MAX_VAL_MASK) +
1230 COL_B10_BASE);
1231 } else {
1232 priv->col_shift[11] = (((addrmap[3] >> 16) &
1233 COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 :
1234 (((addrmap[3] >> 16) & COL_MAX_VAL_MASK) +
1235 COL_B8_BASE);
1236 priv->col_shift[13] = (((addrmap[3] >> 24) &
1237 COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 :
1238 (((addrmap[3] >> 24) & COL_MAX_VAL_MASK) +
1239 COL_B9_BASE);
1240 }
1241 }
1242
1243 if (width) {
1244 for (index = 9; index > width; index--) {
1245 priv->col_shift[index] = priv->col_shift[index - width];
1246 priv->col_shift[index - width] = 0;
1247 }
1248 }
1249
1250}
1251
1252static void setup_bank_address_map(struct synps_edac_priv *priv, u32 *addrmap)
1253{
1254 priv->bank_shift[0] = (addrmap[1] & BANK_MAX_VAL_MASK) + BANK_B0_BASE;
1255 priv->bank_shift[1] = ((addrmap[1] >> 8) &
1256 BANK_MAX_VAL_MASK) + BANK_B1_BASE;
1257 priv->bank_shift[2] = (((addrmap[1] >> 16) &
1258 BANK_MAX_VAL_MASK) == BANK_MAX_VAL_MASK) ? 0 :
1259 (((addrmap[1] >> 16) & BANK_MAX_VAL_MASK) +
1260 BANK_B2_BASE);
1261
1262}
1263
1264static void setup_bg_address_map(struct synps_edac_priv *priv, u32 *addrmap)
1265{
1266 priv->bankgrp_shift[0] = (addrmap[8] &
1267 BANKGRP_MAX_VAL_MASK) + BANKGRP_B0_BASE;
1268 priv->bankgrp_shift[1] = (((addrmap[8] >> 8) & BANKGRP_MAX_VAL_MASK) ==
1269 BANKGRP_MAX_VAL_MASK) ? 0 : (((addrmap[8] >> 8)
1270 & BANKGRP_MAX_VAL_MASK) + BANKGRP_B1_BASE);
1271
1272}
1273
1274static void setup_rank_address_map(struct synps_edac_priv *priv, u32 *addrmap)
1275{
1276 priv->rank_shift[0] = ((addrmap[0] & RANK_MAX_VAL_MASK) ==
1277 RANK_MAX_VAL_MASK) ? 0 : ((addrmap[0] &
1278 RANK_MAX_VAL_MASK) + RANK_B0_BASE);
1279}
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289static void setup_address_map(struct synps_edac_priv *priv)
1290{
1291 u32 addrmap[12];
1292 int index;
1293
1294 for (index = 0; index < 12; index++) {
1295 u32 addrmap_offset;
1296
1297 addrmap_offset = ECC_ADDRMAP0_OFFSET + (index * 4);
1298 addrmap[index] = readl(priv->baseaddr + addrmap_offset);
1299 }
1300
1301 setup_row_address_map(priv, addrmap);
1302
1303 setup_column_address_map(priv, addrmap);
1304
1305 setup_bank_address_map(priv, addrmap);
1306
1307 setup_bg_address_map(priv, addrmap);
1308
1309 setup_rank_address_map(priv, addrmap);
1310}
1311#endif
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322static int mc_probe(struct platform_device *pdev)
1323{
1324 const struct synps_platform_data *p_data;
1325 struct edac_mc_layer layers[2];
1326 struct synps_edac_priv *priv;
1327 struct mem_ctl_info *mci;
1328 void __iomem *baseaddr;
1329 struct resource *res;
1330 int rc;
1331
1332 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1333 baseaddr = devm_ioremap_resource(&pdev->dev, res);
1334 if (IS_ERR(baseaddr))
1335 return PTR_ERR(baseaddr);
1336
1337 p_data = of_device_get_match_data(&pdev->dev);
1338 if (!p_data)
1339 return -ENODEV;
1340
1341 if (!p_data->get_ecc_state(baseaddr)) {
1342 edac_printk(KERN_INFO, EDAC_MC, "ECC not enabled\n");
1343 return -ENXIO;
1344 }
1345
1346 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
1347 layers[0].size = SYNPS_EDAC_NR_CSROWS;
1348 layers[0].is_virt_csrow = true;
1349 layers[1].type = EDAC_MC_LAYER_CHANNEL;
1350 layers[1].size = SYNPS_EDAC_NR_CHANS;
1351 layers[1].is_virt_csrow = false;
1352
1353 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
1354 sizeof(struct synps_edac_priv));
1355 if (!mci) {
1356 edac_printk(KERN_ERR, EDAC_MC,
1357 "Failed memory allocation for mc instance\n");
1358 return -ENOMEM;
1359 }
1360
1361 priv = mci->pvt_info;
1362 priv->baseaddr = baseaddr;
1363 priv->p_data = p_data;
1364
1365 mc_init(mci, pdev);
1366
1367 if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT) {
1368 rc = setup_irq(mci, pdev);
1369 if (rc)
1370 goto free_edac_mc;
1371 }
1372
1373 rc = edac_mc_add_mc(mci);
1374 if (rc) {
1375 edac_printk(KERN_ERR, EDAC_MC,
1376 "Failed to register with EDAC core\n");
1377 goto free_edac_mc;
1378 }
1379
1380#ifdef CONFIG_EDAC_DEBUG
1381 if (priv->p_data->quirks & DDR_ECC_DATA_POISON_SUPPORT) {
1382 rc = edac_create_sysfs_attributes(mci);
1383 if (rc) {
1384 edac_printk(KERN_ERR, EDAC_MC,
1385 "Failed to create sysfs entries\n");
1386 goto free_edac_mc;
1387 }
1388 }
1389
1390 if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT)
1391 setup_address_map(priv);
1392#endif
1393
1394
1395
1396
1397
1398 if (!(priv->p_data->quirks & DDR_ECC_INTR_SUPPORT))
1399 writel(0x0, baseaddr + ECC_CTRL_OFST);
1400
1401 return rc;
1402
1403free_edac_mc:
1404 edac_mc_free(mci);
1405
1406 return rc;
1407}
1408
1409
1410
1411
1412
1413
1414
1415static int mc_remove(struct platform_device *pdev)
1416{
1417 struct mem_ctl_info *mci = platform_get_drvdata(pdev);
1418 struct synps_edac_priv *priv = mci->pvt_info;
1419
1420 if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT)
1421 disable_intr(priv);
1422
1423#ifdef CONFIG_EDAC_DEBUG
1424 if (priv->p_data->quirks & DDR_ECC_DATA_POISON_SUPPORT)
1425 edac_remove_sysfs_attributes(mci);
1426#endif
1427
1428 edac_mc_del_mc(&pdev->dev);
1429 edac_mc_free(mci);
1430
1431 return 0;
1432}
1433
1434static struct platform_driver synps_edac_mc_driver = {
1435 .driver = {
1436 .name = "synopsys-edac",
1437 .of_match_table = synps_edac_match,
1438 },
1439 .probe = mc_probe,
1440 .remove = mc_remove,
1441};
1442
1443module_platform_driver(synps_edac_mc_driver);
1444
1445MODULE_AUTHOR("Xilinx Inc");
1446MODULE_DESCRIPTION("Synopsys DDR ECC driver");
1447MODULE_LICENSE("GPL v2");
1448