LXR linux/drivers/gpu/drm/amd/amdgpu/amdgpu

   1/*
   2 * Copyright 2014 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 */
  23
  24#ifndef __AMDGPU_IH_H__
  25#define __AMDGPU_IH_H__
  26
  27/* Maximum number of IVs processed at once */
  28#define AMDGPU_IH_MAX_NUM_IVS   32
  29
  30struct amdgpu_device;
  31struct amdgpu_iv_entry;
  32
  33struct amdgpu_ih_regs {
  34        uint32_t ih_rb_base;
  35        uint32_t ih_rb_base_hi;
  36        uint32_t ih_rb_cntl;
  37        uint32_t ih_rb_wptr;
  38        uint32_t ih_rb_rptr;
  39        uint32_t ih_doorbell_rptr;
  40        uint32_t ih_rb_wptr_addr_lo;
  41        uint32_t ih_rb_wptr_addr_hi;
  42        uint32_t psp_reg_id;
  43};
  44
  45/*
  46 * R6xx+ IH ring
  47 */
  48struct amdgpu_ih_ring {
  49        unsigned                ring_size;
  50        uint32_t                ptr_mask;
  51        u32                     doorbell_index;
  52        bool                    use_doorbell;
  53        bool                    use_bus_addr;
  54
  55        struct amdgpu_bo        *ring_obj;
  56        volatile uint32_t       *ring;
  57        uint64_t                gpu_addr;
  58
  59        uint64_t                wptr_addr;
  60        volatile uint32_t       *wptr_cpu;
  61
  62        uint64_t                rptr_addr;
  63        volatile uint32_t       *rptr_cpu;
  64
  65        bool                    enabled;
  66        unsigned                rptr;
  67        struct amdgpu_ih_regs   ih_regs;
  68
  69        /* For waiting on IH processing at checkpoint. */
  70        wait_queue_head_t wait_process;
  71        uint64_t                processed_timestamp;
  72};
  73
  74/* return true if time stamp t2 is after t1 with 48bit wrap around */
  75#define amdgpu_ih_ts_after(t1, t2) \
  76                (((int64_t)((t2) << 16) - (int64_t)((t1) << 16)) > 0LL)
  77
  78/* provided by the ih block */
  79struct amdgpu_ih_funcs {
  80        /* ring read/write ptr handling, called from interrupt context */
  81        u32 (*get_wptr)(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih);
  82        void (*decode_iv)(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih,
  83                          struct amdgpu_iv_entry *entry);
  84        uint64_t (*decode_iv_ts)(struct amdgpu_ih_ring *ih, u32 rptr,
  85                                 signed int offset);
  86        void (*set_rptr)(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih);
  87};
  88
  89#define amdgpu_ih_get_wptr(adev, ih) (adev)->irq.ih_funcs->get_wptr((adev), (ih))
  90#define amdgpu_ih_decode_iv(adev, iv) \
  91        (adev)->irq.ih_funcs->decode_iv((adev), (ih), (iv))
  92#define amdgpu_ih_decode_iv_ts(adev, ih, rptr, offset) \
  93        (WARN_ON_ONCE(!(adev)->irq.ih_funcs->decode_iv_ts) ? 0 : \
  94        (adev)->irq.ih_funcs->decode_iv_ts((ih), (rptr), (offset)))
  95#define amdgpu_ih_set_rptr(adev, ih) (adev)->irq.ih_funcs->set_rptr((adev), (ih))
  96
  97int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih,
  98                        unsigned ring_size, bool use_bus_addr);
  99void amdgpu_ih_ring_fini(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih);
 100void amdgpu_ih_ring_write(struct amdgpu_ih_ring *ih, const uint32_t *iv,
 101                          unsigned int num_dw);
 102int amdgpu_ih_wait_on_checkpoint_process_ts(struct amdgpu_device *adev,
 103                                            struct amdgpu_ih_ring *ih);
 104int amdgpu_ih_process(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih);
 105void amdgpu_ih_decode_iv_helper(struct amdgpu_device *adev,
 106                                struct amdgpu_ih_ring *ih,
 107                                struct amdgpu_iv_entry *entry);
 108uint64_t amdgpu_ih_decode_iv_ts_helper(struct amdgpu_ih_ring *ih, u32 rptr,
 109                                       signed int offset);
 110#endif
 111