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26#include "dccg.h"
27#include "clk_mgr_internal.h"
28
29
30#include "dce100/dce_clk_mgr.h"
31
32
33#include "dcn20/dcn20_clk_mgr.h"
34
35#include "vg_clk_mgr.h"
36#include "dcn301_smu.h"
37#include "reg_helper.h"
38#include "core_types.h"
39#include "dm_helpers.h"
40
41#include "atomfirmware.h"
42#include "vangogh_ip_offset.h"
43#include "clk/clk_11_5_0_offset.h"
44#include "clk/clk_11_5_0_sh_mask.h"
45
46
47
48#define LPDDR_MEM_RETRAIN_LATENCY 4.977
49
50
51
52#define TO_CLK_MGR_VGH(clk_mgr)\
53 container_of(clk_mgr, struct clk_mgr_vgh, base)
54
55#define REG(reg_name) \
56 (CLK_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
57
58
59static int vg_get_active_display_cnt_wa(
60 struct dc *dc,
61 struct dc_state *context)
62{
63 int i, display_count;
64 bool tmds_present = false;
65
66 display_count = 0;
67 for (i = 0; i < context->stream_count; i++) {
68 const struct dc_stream_state *stream = context->streams[i];
69
70 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A ||
71 stream->signal == SIGNAL_TYPE_DVI_SINGLE_LINK ||
72 stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK)
73 tmds_present = true;
74 }
75
76 for (i = 0; i < dc->link_count; i++) {
77 const struct dc_link *link = dc->links[i];
78
79
80 if (link->link_enc->funcs->is_dig_enabled &&
81 link->link_enc->funcs->is_dig_enabled(link->link_enc))
82 display_count++;
83 }
84
85
86 if (display_count == 0 && tmds_present)
87 display_count = 1;
88
89 return display_count;
90}
91
92static void vg_update_clocks(struct clk_mgr *clk_mgr_base,
93 struct dc_state *context,
94 bool safe_to_lower)
95{
96 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
97 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
98 struct dc *dc = clk_mgr_base->ctx->dc;
99 int display_count;
100 bool update_dppclk = false;
101 bool update_dispclk = false;
102 bool dpp_clock_lowered = false;
103
104 if (dc->work_arounds.skip_clock_update)
105 return;
106
107
108
109
110
111 if (safe_to_lower) {
112
113 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) {
114
115 display_count = vg_get_active_display_cnt_wa(dc, context);
116
117 if (display_count == 0 && !IS_DIAG_DC(dc->ctx->dce_environment)) {
118 union display_idle_optimization_u idle_info = { 0 };
119
120 idle_info.idle_info.df_request_disabled = 1;
121 idle_info.idle_info.phy_ref_clk_off = 1;
122
123 dcn301_smu_set_display_idle_optimization(clk_mgr, idle_info.data);
124
125 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;
126 }
127 }
128 } else {
129
130 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) {
131 union display_idle_optimization_u idle_info = { 0 };
132
133 dcn301_smu_set_display_idle_optimization(clk_mgr, idle_info.data);
134
135 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE;
136 }
137 }
138
139 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz) && !dc->debug.disable_min_fclk) {
140 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
141 dcn301_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz);
142 }
143
144 if (should_set_clock(safe_to_lower,
145 new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz) && !dc->debug.disable_min_fclk) {
146 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
147 dcn301_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz);
148 }
149
150
151 if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
152 if (new_clocks->dppclk_khz < 100000)
153 new_clocks->dppclk_khz = 100000;
154 }
155
156 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {
157 if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)
158 dpp_clock_lowered = true;
159 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
160 update_dppclk = true;
161 }
162
163 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
164 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
165 dcn301_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz);
166
167 update_dispclk = true;
168 }
169
170 if (dpp_clock_lowered) {
171
172 dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
173 dcn301_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
174 } else {
175
176 if (update_dppclk || update_dispclk)
177 dcn301_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
178
179 if (new_clocks->dppclk_khz >= dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz)
180 dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
181 }
182}
183
184
185static int get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)
186{
187
188 struct fixed31_32 pll_req;
189 unsigned int fbmult_frac_val = 0;
190 unsigned int fbmult_int_val = 0;
191
192
193
194
195
196
197
198 REG_GET(CLK1_0_CLK1_CLK_PLL_REQ, FbMult_frac, &fbmult_frac_val);
199 REG_GET(CLK1_0_CLK1_CLK_PLL_REQ, FbMult_int, &fbmult_int_val);
200
201 pll_req = dc_fixpt_from_int(fbmult_int_val);
202
203
204
205
206
207 pll_req.value |= fbmult_frac_val << 16;
208
209
210 pll_req = dc_fixpt_mul_int(pll_req, clk_mgr->dfs_ref_freq_khz);
211
212
213 return dc_fixpt_floor(pll_req);
214}
215
216static void vg_dump_clk_registers_internal(struct dcn301_clk_internal *internal, struct clk_mgr *clk_mgr_base)
217{
218 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
219
220 internal->CLK1_CLK3_CURRENT_CNT = REG_READ(CLK1_0_CLK1_CLK3_CURRENT_CNT);
221 internal->CLK1_CLK3_BYPASS_CNTL = REG_READ(CLK1_0_CLK1_CLK3_BYPASS_CNTL);
222
223 internal->CLK1_CLK3_DS_CNTL = REG_READ(CLK1_0_CLK1_CLK3_DS_CNTL);
224 internal->CLK1_CLK3_ALLOW_DS = REG_READ(CLK1_0_CLK1_CLK3_ALLOW_DS);
225
226 internal->CLK1_CLK1_CURRENT_CNT = REG_READ(CLK1_0_CLK1_CLK1_CURRENT_CNT);
227 internal->CLK1_CLK1_BYPASS_CNTL = REG_READ(CLK1_0_CLK1_CLK1_BYPASS_CNTL);
228
229 internal->CLK1_CLK2_CURRENT_CNT = REG_READ(CLK1_0_CLK1_CLK2_CURRENT_CNT);
230 internal->CLK1_CLK2_BYPASS_CNTL = REG_READ(CLK1_0_CLK1_CLK2_BYPASS_CNTL);
231
232 internal->CLK1_CLK0_CURRENT_CNT = REG_READ(CLK1_0_CLK1_CLK0_CURRENT_CNT);
233 internal->CLK1_CLK0_BYPASS_CNTL = REG_READ(CLK1_0_CLK1_CLK0_BYPASS_CNTL);
234}
235
236
237static void vg_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,
238 struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info)
239{
240 struct dcn301_clk_internal internal = {0};
241 char *bypass_clks[5] = {"0x0 DFS", "0x1 REFCLK", "0x2 ERROR", "0x3 400 FCH", "0x4 600 FCH"};
242 unsigned int chars_printed = 0;
243 unsigned int remaining_buffer = log_info->bufSize;
244
245 vg_dump_clk_registers_internal(&internal, clk_mgr_base);
246
247 regs_and_bypass->dcfclk = internal.CLK1_CLK3_CURRENT_CNT / 10;
248 regs_and_bypass->dcf_deep_sleep_divider = internal.CLK1_CLK3_DS_CNTL / 10;
249 regs_and_bypass->dcf_deep_sleep_allow = internal.CLK1_CLK3_ALLOW_DS;
250 regs_and_bypass->dprefclk = internal.CLK1_CLK2_CURRENT_CNT / 10;
251 regs_and_bypass->dispclk = internal.CLK1_CLK0_CURRENT_CNT / 10;
252 regs_and_bypass->dppclk = internal.CLK1_CLK1_CURRENT_CNT / 10;
253
254 regs_and_bypass->dppclk_bypass = internal.CLK1_CLK1_BYPASS_CNTL & 0x0007;
255 if (regs_and_bypass->dppclk_bypass < 0 || regs_and_bypass->dppclk_bypass > 4)
256 regs_and_bypass->dppclk_bypass = 0;
257 regs_and_bypass->dcfclk_bypass = internal.CLK1_CLK3_BYPASS_CNTL & 0x0007;
258 if (regs_and_bypass->dcfclk_bypass < 0 || regs_and_bypass->dcfclk_bypass > 4)
259 regs_and_bypass->dcfclk_bypass = 0;
260 regs_and_bypass->dispclk_bypass = internal.CLK1_CLK0_BYPASS_CNTL & 0x0007;
261 if (regs_and_bypass->dispclk_bypass < 0 || regs_and_bypass->dispclk_bypass > 4)
262 regs_and_bypass->dispclk_bypass = 0;
263 regs_and_bypass->dprefclk_bypass = internal.CLK1_CLK2_BYPASS_CNTL & 0x0007;
264 if (regs_and_bypass->dprefclk_bypass < 0 || regs_and_bypass->dprefclk_bypass > 4)
265 regs_and_bypass->dprefclk_bypass = 0;
266
267 if (log_info->enabled) {
268 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "clk_type,clk_value,deepsleep_cntl,deepsleep_allow,bypass\n");
269 remaining_buffer -= chars_printed;
270 *log_info->sum_chars_printed += chars_printed;
271 log_info->pBuf += chars_printed;
272
273 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "dcfclk,%d,%d,%d,%s\n",
274 regs_and_bypass->dcfclk,
275 regs_and_bypass->dcf_deep_sleep_divider,
276 regs_and_bypass->dcf_deep_sleep_allow,
277 bypass_clks[(int) regs_and_bypass->dcfclk_bypass]);
278 remaining_buffer -= chars_printed;
279 *log_info->sum_chars_printed += chars_printed;
280 log_info->pBuf += chars_printed;
281
282 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "dprefclk,%d,N/A,N/A,%s\n",
283 regs_and_bypass->dprefclk,
284 bypass_clks[(int) regs_and_bypass->dprefclk_bypass]);
285 remaining_buffer -= chars_printed;
286 *log_info->sum_chars_printed += chars_printed;
287 log_info->pBuf += chars_printed;
288
289 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "dispclk,%d,N/A,N/A,%s\n",
290 regs_and_bypass->dispclk,
291 bypass_clks[(int) regs_and_bypass->dispclk_bypass]);
292 remaining_buffer -= chars_printed;
293 *log_info->sum_chars_printed += chars_printed;
294 log_info->pBuf += chars_printed;
295
296
297 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "SPLIT\n");
298 remaining_buffer -= chars_printed;
299 *log_info->sum_chars_printed += chars_printed;
300 log_info->pBuf += chars_printed;
301
302
303 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "reg_name,value,clk_type\n");
304 remaining_buffer -= chars_printed;
305 *log_info->sum_chars_printed += chars_printed;
306 log_info->pBuf += chars_printed;
307
308 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_CURRENT_CNT,%d,dcfclk\n",
309 internal.CLK1_CLK3_CURRENT_CNT);
310 remaining_buffer -= chars_printed;
311 *log_info->sum_chars_printed += chars_printed;
312 log_info->pBuf += chars_printed;
313
314 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_DS_CNTL,%d,dcf_deep_sleep_divider\n",
315 internal.CLK1_CLK3_DS_CNTL);
316 remaining_buffer -= chars_printed;
317 *log_info->sum_chars_printed += chars_printed;
318 log_info->pBuf += chars_printed;
319
320 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_ALLOW_DS,%d,dcf_deep_sleep_allow\n",
321 internal.CLK1_CLK3_ALLOW_DS);
322 remaining_buffer -= chars_printed;
323 *log_info->sum_chars_printed += chars_printed;
324 log_info->pBuf += chars_printed;
325
326 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK2_CURRENT_CNT,%d,dprefclk\n",
327 internal.CLK1_CLK2_CURRENT_CNT);
328 remaining_buffer -= chars_printed;
329 *log_info->sum_chars_printed += chars_printed;
330 log_info->pBuf += chars_printed;
331
332 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK0_CURRENT_CNT,%d,dispclk\n",
333 internal.CLK1_CLK0_CURRENT_CNT);
334 remaining_buffer -= chars_printed;
335 *log_info->sum_chars_printed += chars_printed;
336 log_info->pBuf += chars_printed;
337
338 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK1_CURRENT_CNT,%d,dppclk\n",
339 internal.CLK1_CLK1_CURRENT_CNT);
340 remaining_buffer -= chars_printed;
341 *log_info->sum_chars_printed += chars_printed;
342 log_info->pBuf += chars_printed;
343
344 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_BYPASS_CNTL,%d,dcfclk_bypass\n",
345 internal.CLK1_CLK3_BYPASS_CNTL);
346 remaining_buffer -= chars_printed;
347 *log_info->sum_chars_printed += chars_printed;
348 log_info->pBuf += chars_printed;
349
350 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK2_BYPASS_CNTL,%d,dprefclk_bypass\n",
351 internal.CLK1_CLK2_BYPASS_CNTL);
352 remaining_buffer -= chars_printed;
353 *log_info->sum_chars_printed += chars_printed;
354 log_info->pBuf += chars_printed;
355
356 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK0_BYPASS_CNTL,%d,dispclk_bypass\n",
357 internal.CLK1_CLK0_BYPASS_CNTL);
358 remaining_buffer -= chars_printed;
359 *log_info->sum_chars_printed += chars_printed;
360 log_info->pBuf += chars_printed;
361
362 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK1_BYPASS_CNTL,%d,dppclk_bypass\n",
363 internal.CLK1_CLK1_BYPASS_CNTL);
364 remaining_buffer -= chars_printed;
365 *log_info->sum_chars_printed += chars_printed;
366 log_info->pBuf += chars_printed;
367 }
368}
369
370static void vg_enable_pme_wa(struct clk_mgr *clk_mgr_base)
371{
372 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
373
374 dcn301_smu_enable_pme_wa(clk_mgr);
375}
376
377static void vg_init_clocks(struct clk_mgr *clk_mgr)
378{
379 memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks));
380
381 clk_mgr->clks.p_state_change_support = true;
382 clk_mgr->clks.prev_p_state_change_support = true;
383 clk_mgr->clks.pwr_state = DCN_PWR_STATE_UNKNOWN;
384}
385
386static void vg_build_watermark_ranges(struct clk_bw_params *bw_params, struct watermarks *table)
387{
388 int i, num_valid_sets;
389
390 num_valid_sets = 0;
391
392 for (i = 0; i < WM_SET_COUNT; i++) {
393
394 if (!bw_params->wm_table.entries[i].valid)
395 continue;
396
397 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;
398 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;
399
400 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
401 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
402
403 if (table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType == WM_TYPE_PSTATE_CHG) {
404 if (i == 0)
405 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0;
406 else {
407
408 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk =
409 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1;
410 }
411 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk =
412 bw_params->clk_table.entries[i].dcfclk_mhz;
413
414 } else {
415
416 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
417 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
418
419
420 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;
421 }
422 num_valid_sets++;
423 }
424
425 ASSERT(num_valid_sets != 0);
426
427
428 table->WatermarkRow[WM_DCFCLK][0].MinMclk = 0;
429 table->WatermarkRow[WM_DCFCLK][0].MinClock = 0;
430 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxMclk = 0xFFFF;
431 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;
432
433
434 table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A;
435 table->WatermarkRow[WM_SOCCLK][0].MinClock = 0;
436 table->WatermarkRow[WM_SOCCLK][0].MaxClock = 0xFFFF;
437 table->WatermarkRow[WM_SOCCLK][0].MinMclk = 0;
438 table->WatermarkRow[WM_SOCCLK][0].MaxMclk = 0xFFFF;
439}
440
441
442static void vg_notify_wm_ranges(struct clk_mgr *clk_mgr_base)
443{
444 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
445 struct clk_mgr_vgh *clk_mgr_vgh = TO_CLK_MGR_VGH(clk_mgr);
446 struct watermarks *table = clk_mgr_vgh->smu_wm_set.wm_set;
447
448 if (!clk_mgr->smu_ver)
449 return;
450
451 if (!table || clk_mgr_vgh->smu_wm_set.mc_address.quad_part == 0)
452 return;
453
454 memset(table, 0, sizeof(*table));
455
456 vg_build_watermark_ranges(clk_mgr_base->bw_params, table);
457
458 dcn301_smu_set_dram_addr_high(clk_mgr,
459 clk_mgr_vgh->smu_wm_set.mc_address.high_part);
460 dcn301_smu_set_dram_addr_low(clk_mgr,
461 clk_mgr_vgh->smu_wm_set.mc_address.low_part);
462 dcn301_smu_transfer_wm_table_dram_2_smu(clk_mgr);
463}
464
465static bool vg_are_clock_states_equal(struct dc_clocks *a,
466 struct dc_clocks *b)
467{
468 if (a->dispclk_khz != b->dispclk_khz)
469 return false;
470 else if (a->dppclk_khz != b->dppclk_khz)
471 return false;
472 else if (a->dcfclk_khz != b->dcfclk_khz)
473 return false;
474 else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz)
475 return false;
476
477 return true;
478}
479
480
481static struct clk_mgr_funcs vg_funcs = {
482 .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
483 .update_clocks = vg_update_clocks,
484 .init_clocks = vg_init_clocks,
485 .enable_pme_wa = vg_enable_pme_wa,
486 .are_clock_states_equal = vg_are_clock_states_equal,
487 .notify_wm_ranges = vg_notify_wm_ranges
488};
489
490static struct clk_bw_params vg_bw_params = {
491 .vram_type = Ddr4MemType,
492 .num_channels = 1,
493 .clk_table = {
494 .entries = {
495 {
496 .voltage = 0,
497 .dcfclk_mhz = 400,
498 .fclk_mhz = 400,
499 .memclk_mhz = 800,
500 .socclk_mhz = 0,
501 },
502 {
503 .voltage = 0,
504 .dcfclk_mhz = 483,
505 .fclk_mhz = 800,
506 .memclk_mhz = 1600,
507 .socclk_mhz = 0,
508 },
509 {
510 .voltage = 0,
511 .dcfclk_mhz = 602,
512 .fclk_mhz = 1067,
513 .memclk_mhz = 1067,
514 .socclk_mhz = 0,
515 },
516 {
517 .voltage = 0,
518 .dcfclk_mhz = 738,
519 .fclk_mhz = 1333,
520 .memclk_mhz = 1600,
521 .socclk_mhz = 0,
522 },
523 },
524
525 .num_entries = 4,
526 },
527
528};
529
530static struct wm_table ddr4_wm_table = {
531 .entries = {
532 {
533 .wm_inst = WM_A,
534 .wm_type = WM_TYPE_PSTATE_CHG,
535 .pstate_latency_us = 11.72,
536 .sr_exit_time_us = 6.09,
537 .sr_enter_plus_exit_time_us = 7.14,
538 .valid = true,
539 },
540 {
541 .wm_inst = WM_B,
542 .wm_type = WM_TYPE_PSTATE_CHG,
543 .pstate_latency_us = 11.72,
544 .sr_exit_time_us = 10.12,
545 .sr_enter_plus_exit_time_us = 11.48,
546 .valid = true,
547 },
548 {
549 .wm_inst = WM_C,
550 .wm_type = WM_TYPE_PSTATE_CHG,
551 .pstate_latency_us = 11.72,
552 .sr_exit_time_us = 10.12,
553 .sr_enter_plus_exit_time_us = 11.48,
554 .valid = true,
555 },
556 {
557 .wm_inst = WM_D,
558 .wm_type = WM_TYPE_PSTATE_CHG,
559 .pstate_latency_us = 11.72,
560 .sr_exit_time_us = 10.12,
561 .sr_enter_plus_exit_time_us = 11.48,
562 .valid = true,
563 },
564 }
565};
566
567static struct wm_table lpddr5_wm_table = {
568 .entries = {
569 {
570 .wm_inst = WM_A,
571 .wm_type = WM_TYPE_PSTATE_CHG,
572 .pstate_latency_us = 11.65333,
573 .sr_exit_time_us = 13.5,
574 .sr_enter_plus_exit_time_us = 16.5,
575 .valid = true,
576 },
577 {
578 .wm_inst = WM_B,
579 .wm_type = WM_TYPE_PSTATE_CHG,
580 .pstate_latency_us = 11.65333,
581 .sr_exit_time_us = 13.5,
582 .sr_enter_plus_exit_time_us = 16.5,
583 .valid = true,
584 },
585 {
586 .wm_inst = WM_C,
587 .wm_type = WM_TYPE_PSTATE_CHG,
588 .pstate_latency_us = 11.65333,
589 .sr_exit_time_us = 13.5,
590 .sr_enter_plus_exit_time_us = 16.5,
591 .valid = true,
592 },
593 {
594 .wm_inst = WM_D,
595 .wm_type = WM_TYPE_PSTATE_CHG,
596 .pstate_latency_us = 11.65333,
597 .sr_exit_time_us = 13.5,
598 .sr_enter_plus_exit_time_us = 16.5,
599 .valid = true,
600 },
601 }
602};
603
604
605static unsigned int find_dcfclk_for_voltage(const struct vg_dpm_clocks *clock_table,
606 unsigned int voltage)
607{
608 int i;
609
610 for (i = 0; i < VG_NUM_SOC_VOLTAGE_LEVELS; i++) {
611 if (clock_table->SocVoltage[i] == voltage)
612 return clock_table->DcfClocks[i];
613 }
614
615 ASSERT(0);
616 return 0;
617}
618
619static void vg_clk_mgr_helper_populate_bw_params(
620 struct clk_mgr_internal *clk_mgr,
621 struct integrated_info *bios_info,
622 const struct vg_dpm_clocks *clock_table)
623{
624 int i, j;
625 struct clk_bw_params *bw_params = clk_mgr->base.bw_params;
626
627 j = -1;
628
629 ASSERT(VG_NUM_FCLK_DPM_LEVELS <= MAX_NUM_DPM_LVL);
630
631
632
633 for (i = VG_NUM_FCLK_DPM_LEVELS - 1; i >= 0; i--) {
634 if (clock_table->DfPstateTable[i].fclk != 0) {
635 j = i;
636 break;
637 }
638 }
639
640 if (j == -1) {
641
642 ASSERT(0);
643 return;
644 }
645
646 bw_params->clk_table.num_entries = j + 1;
647
648 for (i = 0; i < bw_params->clk_table.num_entries; i++, j--) {
649 bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[j].fclk;
650 bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[j].memclk;
651 bw_params->clk_table.entries[i].voltage = clock_table->DfPstateTable[j].voltage;
652 bw_params->clk_table.entries[i].dcfclk_mhz = find_dcfclk_for_voltage(clock_table, clock_table->DfPstateTable[j].voltage);
653 }
654
655 bw_params->vram_type = bios_info->memory_type;
656 bw_params->num_channels = bios_info->ma_channel_number;
657
658 for (i = 0; i < WM_SET_COUNT; i++) {
659 bw_params->wm_table.entries[i].wm_inst = i;
660
661 if (i >= bw_params->clk_table.num_entries) {
662 bw_params->wm_table.entries[i].valid = false;
663 continue;
664 }
665
666 bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG;
667 bw_params->wm_table.entries[i].valid = true;
668 }
669
670 if (bw_params->vram_type == LpDdr4MemType) {
671
672
673
674 bw_params->wm_table.entries[WM_D].pstate_latency_us = LPDDR_MEM_RETRAIN_LATENCY;
675 bw_params->wm_table.entries[WM_D].wm_inst = WM_D;
676 bw_params->wm_table.entries[WM_D].wm_type = WM_TYPE_RETRAINING;
677 bw_params->wm_table.entries[WM_D].valid = true;
678 }
679
680}
681
682
683static struct vg_dpm_clocks dummy_clocks = {
684 .DcfClocks = { 201, 403, 403, 403, 403, 403, 403 },
685 .SocClocks = { 400, 600, 600, 600, 600, 600, 600 },
686 .SocVoltage = { 2800, 2860, 2860, 2860, 2860, 2860, 2860, 2860 },
687 .DfPstateTable = {
688 { .fclk = 400, .memclk = 400, .voltage = 2800 },
689 { .fclk = 400, .memclk = 400, .voltage = 2800 },
690 { .fclk = 400, .memclk = 400, .voltage = 2800 },
691 { .fclk = 400, .memclk = 400, .voltage = 2800 }
692 }
693};
694
695static struct watermarks dummy_wms = { 0 };
696
697static void vg_get_dpm_table_from_smu(struct clk_mgr_internal *clk_mgr,
698 struct smu_dpm_clks *smu_dpm_clks)
699{
700 struct vg_dpm_clocks *table = smu_dpm_clks->dpm_clks;
701
702 if (!clk_mgr->smu_ver)
703 return;
704
705 if (!table || smu_dpm_clks->mc_address.quad_part == 0)
706 return;
707
708 memset(table, 0, sizeof(*table));
709
710 dcn301_smu_set_dram_addr_high(clk_mgr,
711 smu_dpm_clks->mc_address.high_part);
712 dcn301_smu_set_dram_addr_low(clk_mgr,
713 smu_dpm_clks->mc_address.low_part);
714 dcn301_smu_transfer_dpm_table_smu_2_dram(clk_mgr);
715}
716
717void vg_clk_mgr_construct(
718 struct dc_context *ctx,
719 struct clk_mgr_vgh *clk_mgr,
720 struct pp_smu_funcs *pp_smu,
721 struct dccg *dccg)
722{
723 struct smu_dpm_clks smu_dpm_clks = { 0 };
724
725 clk_mgr->base.base.ctx = ctx;
726 clk_mgr->base.base.funcs = &vg_funcs;
727
728 clk_mgr->base.pp_smu = pp_smu;
729
730 clk_mgr->base.dccg = dccg;
731 clk_mgr->base.dfs_bypass_disp_clk = 0;
732
733 clk_mgr->base.dprefclk_ss_percentage = 0;
734 clk_mgr->base.dprefclk_ss_divider = 1000;
735 clk_mgr->base.ss_on_dprefclk = false;
736 clk_mgr->base.dfs_ref_freq_khz = 48000;
737
738 clk_mgr->smu_wm_set.wm_set = (struct watermarks *)dm_helpers_allocate_gpu_mem(
739 clk_mgr->base.base.ctx,
740 DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
741 sizeof(struct watermarks),
742 &clk_mgr->smu_wm_set.mc_address.quad_part);
743
744 if (!clk_mgr->smu_wm_set.wm_set) {
745 clk_mgr->smu_wm_set.wm_set = &dummy_wms;
746 clk_mgr->smu_wm_set.mc_address.quad_part = 0;
747 }
748 ASSERT(clk_mgr->smu_wm_set.wm_set);
749
750 smu_dpm_clks.dpm_clks = (struct vg_dpm_clocks *)dm_helpers_allocate_gpu_mem(
751 clk_mgr->base.base.ctx,
752 DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
753 sizeof(struct vg_dpm_clocks),
754 &smu_dpm_clks.mc_address.quad_part);
755
756 if (smu_dpm_clks.dpm_clks == NULL) {
757 smu_dpm_clks.dpm_clks = &dummy_clocks;
758 smu_dpm_clks.mc_address.quad_part = 0;
759 }
760
761 ASSERT(smu_dpm_clks.dpm_clks);
762
763 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
764 vg_funcs.update_clocks = dcn2_update_clocks_fpga;
765 clk_mgr->base.base.dentist_vco_freq_khz = 3600000;
766 } else {
767 struct clk_log_info log_info = {0};
768
769 clk_mgr->base.smu_ver = dcn301_smu_get_smu_version(&clk_mgr->base);
770
771 if (clk_mgr->base.smu_ver)
772 clk_mgr->base.smu_present = true;
773
774
775 clk_mgr->base.base.dentist_vco_freq_khz = get_vco_frequency_from_reg(&clk_mgr->base);
776
777
778 if (clk_mgr->base.base.dentist_vco_freq_khz == 0)
779 clk_mgr->base.base.dentist_vco_freq_khz = 3600000;
780
781 if (ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) {
782 vg_bw_params.wm_table = lpddr5_wm_table;
783 } else {
784 vg_bw_params.wm_table = ddr4_wm_table;
785 }
786
787 vg_dump_clk_registers(&clk_mgr->base.base.boot_snapshot, &clk_mgr->base.base, &log_info);
788 }
789
790 clk_mgr->base.base.dprefclk_khz = 600000;
791 dce_clock_read_ss_info(&clk_mgr->base);
792
793 clk_mgr->base.base.bw_params = &vg_bw_params;
794
795 vg_get_dpm_table_from_smu(&clk_mgr->base, &smu_dpm_clks);
796 if (ctx->dc_bios && ctx->dc_bios->integrated_info) {
797 vg_clk_mgr_helper_populate_bw_params(
798 &clk_mgr->base,
799 ctx->dc_bios->integrated_info,
800 smu_dpm_clks.dpm_clks);
801 }
802
803 if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0)
804 dm_helpers_free_gpu_mem(clk_mgr->base.base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
805 smu_dpm_clks.dpm_clks);
806
807
808
809
810
811
812}
813
814void vg_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int)
815{
816 struct clk_mgr_vgh *clk_mgr = TO_CLK_MGR_VGH(clk_mgr_int);
817
818 if (clk_mgr->smu_wm_set.wm_set && clk_mgr->smu_wm_set.mc_address.quad_part != 0)
819 dm_helpers_free_gpu_mem(clk_mgr_int->base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
820 clk_mgr->smu_wm_set.wm_set);
821}
822
