LXR linux/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link

   1/*
   2 * Copyright 2012-15 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 * Authors: AMD
  23 *
  24 */
  25
  26
  27#include "reg_helper.h"
  28
  29#include "core_types.h"
  30#include "link_encoder.h"
  31#include "dcn31_dio_link_encoder.h"
  32#include "stream_encoder.h"
  33#include "i2caux_interface.h"
  34#include "dc_bios_types.h"
  35
  36#include "gpio_service_interface.h"
  37
  38#include "link_enc_cfg.h"
  39#include "dc_dmub_srv.h"
  40#include "dal_asic_id.h"
  41
  42#define CTX \
  43        enc10->base.ctx
  44#define DC_LOGGER \
  45        enc10->base.ctx->logger
  46
  47#define REG(reg)\
  48        (enc10->link_regs->reg)
  49
  50#undef FN
  51#define FN(reg_name, field_name) \
  52        enc10->link_shift->field_name, enc10->link_mask->field_name
  53
  54#define IND_REG(index) \
  55        (enc10->link_regs->index)
  56
  57#define AUX_REG(reg)\
  58        (enc10->aux_regs->reg)
  59
  60#define AUX_REG_READ(reg_name) \
  61                dm_read_reg(CTX, AUX_REG(reg_name))
  62
  63#define AUX_REG_WRITE(reg_name, val) \
  64                        dm_write_reg(CTX, AUX_REG(reg_name), val)
  65
  66#ifndef MIN
  67#define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
  68#endif
  69
  70static uint8_t phy_id_from_transmitter(enum transmitter t)
  71{
  72        uint8_t phy_id;
  73
  74        switch (t) {
  75        case TRANSMITTER_UNIPHY_A:
  76                phy_id = 0;
  77                break;
  78        case TRANSMITTER_UNIPHY_B:
  79                phy_id = 1;
  80                break;
  81        case TRANSMITTER_UNIPHY_C:
  82                phy_id = 2;
  83                break;
  84        case TRANSMITTER_UNIPHY_D:
  85                phy_id = 3;
  86                break;
  87        case TRANSMITTER_UNIPHY_E:
  88                phy_id = 4;
  89                break;
  90        case TRANSMITTER_UNIPHY_F:
  91                phy_id = 5;
  92                break;
  93        case TRANSMITTER_UNIPHY_G:
  94                phy_id = 6;
  95                break;
  96        default:
  97                phy_id = 0;
  98                break;
  99        }
 100        return phy_id;
 101}
 102
 103static bool has_query_dp_alt(struct link_encoder *enc)
 104{
 105        struct dc_dmub_srv *dc_dmub_srv = enc->ctx->dmub_srv;
 106
 107        /* Supports development firmware and firmware >= 4.0.11 */
 108        return dc_dmub_srv &&
 109               !(dc_dmub_srv->dmub->fw_version >= DMUB_FW_VERSION(4, 0, 0) &&
 110                 dc_dmub_srv->dmub->fw_version <= DMUB_FW_VERSION(4, 0, 10));
 111}
 112
 113static bool query_dp_alt_from_dmub(struct link_encoder *enc,
 114                                   union dmub_rb_cmd *cmd)
 115{
 116        struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
 117        struct dc_dmub_srv *dc_dmub_srv = enc->ctx->dmub_srv;
 118
 119        memset(cmd, 0, sizeof(*cmd));
 120        cmd->query_dp_alt.header.type = DMUB_CMD__VBIOS;
 121        cmd->query_dp_alt.header.sub_type =
 122                DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT;
 123        cmd->query_dp_alt.header.payload_bytes = sizeof(cmd->query_dp_alt.data);
 124        cmd->query_dp_alt.data.phy_id = phy_id_from_transmitter(enc10->base.transmitter);
 125
 126        if (!dc_dmub_srv_cmd_with_reply_data(dc_dmub_srv, cmd))
 127                return false;
 128
 129        return true;
 130}
 131
 132void dcn31_link_encoder_set_dio_phy_mux(
 133        struct link_encoder *enc,
 134        enum encoder_type_select sel,
 135        uint32_t hpo_inst)
 136{
 137        struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
 138
 139        switch (enc->transmitter) {
 140        case TRANSMITTER_UNIPHY_A:
 141                if (sel == ENCODER_TYPE_HDMI_FRL)
 142                        REG_UPDATE(DIO_LINKA_CNTL,
 143                                        HPO_HDMI_ENC_SEL, hpo_inst);
 144                else if (sel == ENCODER_TYPE_DP_128B132B)
 145                        REG_UPDATE(DIO_LINKA_CNTL,
 146                                        HPO_DP_ENC_SEL, hpo_inst);
 147                REG_UPDATE(DIO_LINKA_CNTL,
 148                                ENC_TYPE_SEL, sel);
 149                break;
 150        case TRANSMITTER_UNIPHY_B:
 151                if (sel == ENCODER_TYPE_HDMI_FRL)
 152                        REG_UPDATE(DIO_LINKB_CNTL,
 153                                        HPO_HDMI_ENC_SEL, hpo_inst);
 154                else if (sel == ENCODER_TYPE_DP_128B132B)
 155                        REG_UPDATE(DIO_LINKB_CNTL,
 156                                        HPO_DP_ENC_SEL, hpo_inst);
 157                REG_UPDATE(DIO_LINKB_CNTL,
 158                                ENC_TYPE_SEL, sel);
 159                break;
 160        case TRANSMITTER_UNIPHY_C:
 161                if (sel == ENCODER_TYPE_HDMI_FRL)
 162                        REG_UPDATE(DIO_LINKC_CNTL,
 163                                        HPO_HDMI_ENC_SEL, hpo_inst);
 164                else if (sel == ENCODER_TYPE_DP_128B132B)
 165                        REG_UPDATE(DIO_LINKC_CNTL,
 166                                        HPO_DP_ENC_SEL, hpo_inst);
 167                REG_UPDATE(DIO_LINKC_CNTL,
 168                                ENC_TYPE_SEL, sel);
 169                break;
 170        case TRANSMITTER_UNIPHY_D:
 171                if (sel == ENCODER_TYPE_HDMI_FRL)
 172                        REG_UPDATE(DIO_LINKD_CNTL,
 173                                        HPO_HDMI_ENC_SEL, hpo_inst);
 174                else if (sel == ENCODER_TYPE_DP_128B132B)
 175                        REG_UPDATE(DIO_LINKD_CNTL,
 176                                        HPO_DP_ENC_SEL, hpo_inst);
 177                REG_UPDATE(DIO_LINKD_CNTL,
 178                                ENC_TYPE_SEL, sel);
 179                break;
 180        case TRANSMITTER_UNIPHY_E:
 181                if (sel == ENCODER_TYPE_HDMI_FRL)
 182                        REG_UPDATE(DIO_LINKE_CNTL,
 183                                        HPO_HDMI_ENC_SEL, hpo_inst);
 184                else if (sel == ENCODER_TYPE_DP_128B132B)
 185                        REG_UPDATE(DIO_LINKE_CNTL,
 186                                        HPO_DP_ENC_SEL, hpo_inst);
 187                REG_UPDATE(DIO_LINKE_CNTL,
 188                                ENC_TYPE_SEL, sel);
 189                break;
 190        case TRANSMITTER_UNIPHY_F:
 191                if (sel == ENCODER_TYPE_HDMI_FRL)
 192                        REG_UPDATE(DIO_LINKF_CNTL,
 193                                        HPO_HDMI_ENC_SEL, hpo_inst);
 194                else if (sel == ENCODER_TYPE_DP_128B132B)
 195                        REG_UPDATE(DIO_LINKF_CNTL,
 196                                        HPO_DP_ENC_SEL, hpo_inst);
 197                REG_UPDATE(DIO_LINKF_CNTL,
 198                                ENC_TYPE_SEL, sel);
 199                break;
 200        default:
 201                /* Do nothing */
 202                break;
 203        }
 204}
 205
 206static void enc31_hw_init(struct link_encoder *enc)
 207{
 208        struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
 209
 210/*
 211        00 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2 : 1/2
 212        01 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4 : 3/4
 213        02 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8 : 7/8
 214        03 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16 : 15/16
 215        04 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32 : 31/32
 216        05 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64 : 63/64
 217        06 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128 : 127/128
 218        07 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256 : 255/256
 219*/
 220
 221/*
 222        AUX_REG_UPDATE_5(AUX_DPHY_RX_CONTROL0,
 223        AUX_RX_START_WINDOW = 1 [6:4]
 224        AUX_RX_RECEIVE_WINDOW = 1 default is 2 [10:8]
 225        AUX_RX_HALF_SYM_DETECT_LEN  = 1 [13:12] default is 1
 226        AUX_RX_TRANSITION_FILTER_EN = 1 [16] default is 1
 227        AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT [17] is 0  default is 0
 228        AUX_RX_ALLOW_BELOW_THRESHOLD_START [18] is 1  default is 1
 229        AUX_RX_ALLOW_BELOW_THRESHOLD_STOP [19] is 1  default is 1
 230        AUX_RX_PHASE_DETECT_LEN,  [21,20] = 0x3 default is 3
 231        AUX_RX_DETECTION_THRESHOLD [30:28] = 1
 232*/
 233        AUX_REG_WRITE(AUX_DPHY_RX_CONTROL0, 0x103d1110);
 234
 235        AUX_REG_WRITE(AUX_DPHY_TX_CONTROL, 0x21c7a);
 236
 237        //AUX_DPHY_TX_REF_CONTROL'AUX_TX_REF_DIV HW default is 0x32;
 238        // Set AUX_TX_REF_DIV Divider to generate 2 MHz reference from refclk
 239        // 27MHz -> 0xd
 240        // 100MHz -> 0x32
 241        // 48MHz -> 0x18
 242
 243#ifdef CLEANUP_FIXME
 244        /*from display_init*/
 245        REG_WRITE(RDPCSTX_DEBUG_CONFIG, 0);
 246#endif
 247
 248        // Set TMDS_CTL0 to 1.  This is a legacy setting.
 249        REG_UPDATE(TMDS_CTL_BITS, TMDS_CTL0, 1);
 250
 251        /*HW default is 5*/
 252        REG_UPDATE(RDPCSTX_CNTL,
 253                        RDPCS_TX_FIFO_RD_START_DELAY, 4);
 254
 255        dcn10_aux_initialize(enc10);
 256}
 257
 258static const struct link_encoder_funcs dcn31_link_enc_funcs = {
 259        .read_state = link_enc2_read_state,
 260        .validate_output_with_stream =
 261                        dcn30_link_encoder_validate_output_with_stream,
 262        .hw_init = enc31_hw_init,
 263        .setup = dcn10_link_encoder_setup,
 264        .enable_tmds_output = dcn10_link_encoder_enable_tmds_output,
 265        .enable_dp_output = dcn31_link_encoder_enable_dp_output,
 266        .enable_dp_mst_output = dcn31_link_encoder_enable_dp_mst_output,
 267        .disable_output = dcn31_link_encoder_disable_output,
 268        .dp_set_lane_settings = dcn10_link_encoder_dp_set_lane_settings,
 269        .dp_set_phy_pattern = dcn10_link_encoder_dp_set_phy_pattern,
 270        .update_mst_stream_allocation_table =
 271                dcn10_link_encoder_update_mst_stream_allocation_table,
 272        .psr_program_dp_dphy_fast_training =
 273                        dcn10_psr_program_dp_dphy_fast_training,
 274        .psr_program_secondary_packet = dcn10_psr_program_secondary_packet,
 275        .connect_dig_be_to_fe = dcn10_link_encoder_connect_dig_be_to_fe,
 276        .enable_hpd = dcn10_link_encoder_enable_hpd,
 277        .disable_hpd = dcn10_link_encoder_disable_hpd,
 278        .is_dig_enabled = dcn10_is_dig_enabled,
 279        .destroy = dcn10_link_encoder_destroy,
 280        .fec_set_enable = enc2_fec_set_enable,
 281        .fec_set_ready = enc2_fec_set_ready,
 282        .fec_is_active = enc2_fec_is_active,
 283        .get_dig_frontend = dcn10_get_dig_frontend,
 284        .get_dig_mode = dcn10_get_dig_mode,
 285        .is_in_alt_mode = dcn31_link_encoder_is_in_alt_mode,
 286        .get_max_link_cap = dcn31_link_encoder_get_max_link_cap,
 287        .set_dio_phy_mux = dcn31_link_encoder_set_dio_phy_mux,
 288};
 289
 290void dcn31_link_encoder_construct(
 291        struct dcn20_link_encoder *enc20,
 292        const struct encoder_init_data *init_data,
 293        const struct encoder_feature_support *enc_features,
 294        const struct dcn10_link_enc_registers *link_regs,
 295        const struct dcn10_link_enc_aux_registers *aux_regs,
 296        const struct dcn10_link_enc_hpd_registers *hpd_regs,
 297        const struct dcn10_link_enc_shift *link_shift,
 298        const struct dcn10_link_enc_mask *link_mask)
 299{
 300        struct bp_encoder_cap_info bp_cap_info = {0};
 301        const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs;
 302        enum bp_result result = BP_RESULT_OK;
 303        struct dcn10_link_encoder *enc10 = &enc20->enc10;
 304
 305        enc10->base.funcs = &dcn31_link_enc_funcs;
 306        enc10->base.ctx = init_data->ctx;
 307        enc10->base.id = init_data->encoder;
 308
 309        enc10->base.hpd_source = init_data->hpd_source;
 310        enc10->base.connector = init_data->connector;
 311
 312        enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
 313
 314        enc10->base.features = *enc_features;
 315
 316        enc10->base.transmitter = init_data->transmitter;
 317
 318        /* set the flag to indicate whether driver poll the I2C data pin
 319         * while doing the DP sink detect
 320         */
 321
 322/*      if (dal_adapter_service_is_feature_supported(as,
 323                FEATURE_DP_SINK_DETECT_POLL_DATA_PIN))
 324                enc10->base.features.flags.bits.
 325                        DP_SINK_DETECT_POLL_DATA_PIN = true;*/
 326
 327        enc10->base.output_signals =
 328                SIGNAL_TYPE_DVI_SINGLE_LINK |
 329                SIGNAL_TYPE_DVI_DUAL_LINK |
 330                SIGNAL_TYPE_LVDS |
 331                SIGNAL_TYPE_DISPLAY_PORT |
 332                SIGNAL_TYPE_DISPLAY_PORT_MST |
 333                SIGNAL_TYPE_EDP |
 334                SIGNAL_TYPE_HDMI_TYPE_A;
 335
 336        /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE.
 337         * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY.
 338         * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer
 339         * DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS.
 340         * Prefer DIG assignment is decided by board design.
 341         * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design
 342         * and VBIOS will filter out 7 UNIPHY for DCE 8.0.
 343         * By this, adding DIGG should not hurt DCE 8.0.
 344         * This will let DCE 8.1 share DCE 8.0 as much as possible
 345         */
 346
 347        enc10->link_regs = link_regs;
 348        enc10->aux_regs = aux_regs;
 349        enc10->hpd_regs = hpd_regs;
 350        enc10->link_shift = link_shift;
 351        enc10->link_mask = link_mask;
 352
 353        switch (enc10->base.transmitter) {
 354        case TRANSMITTER_UNIPHY_A:
 355                enc10->base.preferred_engine = ENGINE_ID_DIGA;
 356        break;
 357        case TRANSMITTER_UNIPHY_B:
 358                enc10->base.preferred_engine = ENGINE_ID_DIGB;
 359        break;
 360        case TRANSMITTER_UNIPHY_C:
 361                enc10->base.preferred_engine = ENGINE_ID_DIGC;
 362        break;
 363        case TRANSMITTER_UNIPHY_D:
 364                enc10->base.preferred_engine = ENGINE_ID_DIGD;
 365        break;
 366        case TRANSMITTER_UNIPHY_E:
 367                enc10->base.preferred_engine = ENGINE_ID_DIGE;
 368        break;
 369        case TRANSMITTER_UNIPHY_F:
 370                enc10->base.preferred_engine = ENGINE_ID_DIGF;
 371        break;
 372        default:
 373                ASSERT_CRITICAL(false);
 374                enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
 375        }
 376
 377        /* default to one to mirror Windows behavior */
 378        enc10->base.features.flags.bits.HDMI_6GB_EN = 1;
 379
 380        result = bp_funcs->get_encoder_cap_info(enc10->base.ctx->dc_bios,
 381                                                enc10->base.id, &bp_cap_info);
 382
 383        /* Override features with DCE-specific values */
 384        if (result == BP_RESULT_OK) {
 385                enc10->base.features.flags.bits.IS_HBR2_CAPABLE =
 386                                bp_cap_info.DP_HBR2_EN;
 387                enc10->base.features.flags.bits.IS_HBR3_CAPABLE =
 388                                bp_cap_info.DP_HBR3_EN;
 389                enc10->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;
 390                enc10->base.features.flags.bits.IS_DP2_CAPABLE = bp_cap_info.IS_DP2_CAPABLE;
 391                enc10->base.features.flags.bits.IS_UHBR10_CAPABLE = bp_cap_info.DP_UHBR10_EN;
 392                enc10->base.features.flags.bits.IS_UHBR13_5_CAPABLE = bp_cap_info.DP_UHBR13_5_EN;
 393                enc10->base.features.flags.bits.IS_UHBR20_CAPABLE = bp_cap_info.DP_UHBR20_EN;
 394                enc10->base.features.flags.bits.DP_IS_USB_C =
 395                                bp_cap_info.DP_IS_USB_C;
 396        } else {
 397                DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n",
 398                                __func__,
 399                                result);
 400        }
 401        if (enc10->base.ctx->dc->debug.hdmi20_disable) {
 402                enc10->base.features.flags.bits.HDMI_6GB_EN = 0;
 403        }
 404}
 405
 406void dcn31_link_encoder_construct_minimal(
 407        struct dcn20_link_encoder *enc20,
 408        struct dc_context *ctx,
 409        const struct encoder_feature_support *enc_features,
 410        const struct dcn10_link_enc_registers *link_regs,
 411        enum engine_id eng_id)
 412{
 413        struct dcn10_link_encoder *enc10 = &enc20->enc10;
 414
 415        enc10->base.funcs = &dcn31_link_enc_funcs;
 416        enc10->base.ctx = ctx;
 417        enc10->base.id.type = OBJECT_TYPE_ENCODER;
 418        enc10->base.hpd_source = HPD_SOURCEID_UNKNOWN;
 419        enc10->base.connector.type = OBJECT_TYPE_CONNECTOR;
 420        enc10->base.preferred_engine = eng_id;
 421        enc10->base.features = *enc_features;
 422        enc10->base.transmitter = TRANSMITTER_UNKNOWN;
 423        enc10->link_regs = link_regs;
 424
 425        enc10->base.output_signals =
 426                SIGNAL_TYPE_DISPLAY_PORT |
 427                SIGNAL_TYPE_DISPLAY_PORT_MST |
 428                SIGNAL_TYPE_EDP;
 429}
 430
 431/* DPIA equivalent of link_transmitter_control. */
 432static bool link_dpia_control(struct dc_context *dc_ctx,
 433        struct dmub_cmd_dig_dpia_control_data *dpia_control)
 434{
 435        union dmub_rb_cmd cmd;
 436        struct dc_dmub_srv *dmub = dc_ctx->dmub_srv;
 437
 438        memset(&cmd, 0, sizeof(cmd));
 439
 440        cmd.dig1_dpia_control.header.type = DMUB_CMD__DPIA;
 441        cmd.dig1_dpia_control.header.sub_type =
 442                        DMUB_CMD__DPIA_DIG1_DPIA_CONTROL;
 443        cmd.dig1_dpia_control.header.payload_bytes =
 444                sizeof(cmd.dig1_dpia_control) -
 445                sizeof(cmd.dig1_dpia_control.header);
 446
 447        cmd.dig1_dpia_control.dpia_control = *dpia_control;
 448
 449        dc_dmub_srv_cmd_queue(dmub, &cmd);
 450        dc_dmub_srv_cmd_execute(dmub);
 451        dc_dmub_srv_wait_idle(dmub);
 452
 453        return true;
 454}
 455
 456static void link_encoder_disable(struct dcn10_link_encoder *enc10)
 457{
 458        /* reset training complete */
 459        REG_UPDATE(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, 0);
 460}
 461
 462void dcn31_link_encoder_enable_dp_output(
 463        struct link_encoder *enc,
 464        const struct dc_link_settings *link_settings,
 465        enum clock_source_id clock_source)
 466{
 467        struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
 468
 469        /* Enable transmitter and encoder. */
 470        if (!link_enc_cfg_is_transmitter_mappable(enc->ctx->dc, enc)) {
 471
 472                dcn20_link_encoder_enable_dp_output(enc, link_settings, clock_source);
 473
 474        } else {
 475
 476                struct dmub_cmd_dig_dpia_control_data dpia_control = { 0 };
 477                struct dc_link *link;
 478
 479                link = link_enc_cfg_get_link_using_link_enc(enc->ctx->dc, enc->preferred_engine);
 480
 481                enc1_configure_encoder(enc10, link_settings);
 482
 483                dpia_control.action = (uint8_t)TRANSMITTER_CONTROL_ENABLE;
 484                dpia_control.enc_id = enc->preferred_engine;
 485                dpia_control.mode_laneset.digmode = 0; /* 0 for SST; 5 for MST */
 486                dpia_control.lanenum = (uint8_t)link_settings->lane_count;
 487                dpia_control.symclk_10khz = link_settings->link_rate *
 488                                LINK_RATE_REF_FREQ_IN_KHZ / 10;
 489                /* DIG_BE_CNTL.DIG_HPD_SELECT set to 5 (hpdsel - 1) to indicate HPD pin
 490                 * unused by DPIA.
 491                 */
 492                dpia_control.hpdsel = 6;
 493
 494                if (link) {
 495                        dpia_control.dpia_id = link->ddc_hw_inst;
 496                        dpia_control.fec_rdy = dc_link_should_enable_fec(link);
 497                } else {
 498                        DC_LOG_ERROR("%s: Failed to execute DPIA enable DMUB command.\n", __func__);
 499                        BREAK_TO_DEBUGGER();
 500                        return;
 501                }
 502
 503                link_dpia_control(enc->ctx, &dpia_control);
 504        }
 505}
 506
 507void dcn31_link_encoder_enable_dp_mst_output(
 508        struct link_encoder *enc,
 509        const struct dc_link_settings *link_settings,
 510        enum clock_source_id clock_source)
 511{
 512        struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
 513
 514        /* Enable transmitter and encoder. */
 515        if (!link_enc_cfg_is_transmitter_mappable(enc->ctx->dc, enc)) {
 516
 517                dcn10_link_encoder_enable_dp_mst_output(enc, link_settings, clock_source);
 518
 519        } else {
 520
 521                struct dmub_cmd_dig_dpia_control_data dpia_control = { 0 };
 522                struct dc_link *link;
 523
 524                link = link_enc_cfg_get_link_using_link_enc(enc->ctx->dc, enc->preferred_engine);
 525
 526                enc1_configure_encoder(enc10, link_settings);
 527
 528                dpia_control.action = (uint8_t)TRANSMITTER_CONTROL_ENABLE;
 529                dpia_control.enc_id = enc->preferred_engine;
 530                dpia_control.mode_laneset.digmode = 5; /* 0 for SST; 5 for MST */
 531                dpia_control.lanenum = (uint8_t)link_settings->lane_count;
 532                dpia_control.symclk_10khz = link_settings->link_rate *
 533                                LINK_RATE_REF_FREQ_IN_KHZ / 10;
 534                /* DIG_BE_CNTL.DIG_HPD_SELECT set to 5 (hpdsel - 1) to indicate HPD pin
 535                 * unused by DPIA.
 536                 */
 537                dpia_control.hpdsel = 6;
 538
 539                if (link) {
 540                        dpia_control.dpia_id = link->ddc_hw_inst;
 541                        dpia_control.fec_rdy = dc_link_should_enable_fec(link);
 542                } else {
 543                        DC_LOG_ERROR("%s: Failed to execute DPIA enable DMUB command.\n", __func__);
 544                        BREAK_TO_DEBUGGER();
 545                        return;
 546                }
 547
 548                link_dpia_control(enc->ctx, &dpia_control);
 549        }
 550}
 551
 552void dcn31_link_encoder_disable_output(
 553        struct link_encoder *enc,
 554        enum signal_type signal)
 555{
 556        struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
 557
 558        /* Disable transmitter and encoder. */
 559        if (!link_enc_cfg_is_transmitter_mappable(enc->ctx->dc, enc)) {
 560
 561                dcn10_link_encoder_disable_output(enc, signal);
 562
 563        } else {
 564
 565                struct dmub_cmd_dig_dpia_control_data dpia_control = { 0 };
 566                struct dc_link *link;
 567
 568                if (!dcn10_is_dig_enabled(enc))
 569                        return;
 570
 571                link = link_enc_cfg_get_link_using_link_enc(enc->ctx->dc, enc->preferred_engine);
 572
 573                dpia_control.action = (uint8_t)TRANSMITTER_CONTROL_DISABLE;
 574                dpia_control.enc_id = enc->preferred_engine;
 575                if (signal == SIGNAL_TYPE_DISPLAY_PORT) {
 576                        dpia_control.mode_laneset.digmode = 0; /* 0 for SST; 5 for MST */
 577                } else if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
 578                        dpia_control.mode_laneset.digmode = 5; /* 0 for SST; 5 for MST */
 579                } else {
 580                        DC_LOG_ERROR("%s: USB4 DPIA only supports DisplayPort.\n", __func__);
 581                        BREAK_TO_DEBUGGER();
 582                }
 583
 584                if (link) {
 585                        dpia_control.dpia_id = link->ddc_hw_inst;
 586                } else {
 587                        DC_LOG_ERROR("%s: Failed to execute DPIA enable DMUB command.\n", __func__);
 588                        BREAK_TO_DEBUGGER();
 589                        return;
 590                }
 591
 592                link_dpia_control(enc->ctx, &dpia_control);
 593
 594                link_encoder_disable(enc10);
 595        }
 596}
 597
 598bool dcn31_link_encoder_is_in_alt_mode(struct link_encoder *enc)
 599{
 600        struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
 601        union dmub_rb_cmd cmd;
 602        uint32_t dp_alt_mode_disable;
 603
 604        /* Only applicable to USB-C PHY. */
 605        if (!enc->features.flags.bits.DP_IS_USB_C)
 606                return false;
 607
 608        /*
 609         * Use the new interface from DMCUB if available.
 610         * Avoids hanging the RDCPSPIPE if DMCUB wasn't already running.
 611         */
 612        if (has_query_dp_alt(enc)) {
 613                if (!query_dp_alt_from_dmub(enc, &cmd))
 614                        return false;
 615
 616                return (cmd.query_dp_alt.data.is_dp_alt_disable == 0);
 617        }
 618
 619        /* Legacy path, avoid if possible. */
 620        if (enc->ctx->asic_id.hw_internal_rev != YELLOW_CARP_B0) {
 621                REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE,
 622                        &dp_alt_mode_disable);
 623        } else {
 624                /*
 625                 * B0 phys use a new set of registers to check whether alt mode is disabled.
 626                 * if value == 1 alt mode is disabled, otherwise it is enabled.
 627                 */
 628                if ((enc10->base.transmitter == TRANSMITTER_UNIPHY_A) ||
 629                    (enc10->base.transmitter == TRANSMITTER_UNIPHY_B) ||
 630                    (enc10->base.transmitter == TRANSMITTER_UNIPHY_E)) {
 631                        REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE,
 632                                &dp_alt_mode_disable);
 633                } else {
 634                        REG_GET(RDPCSPIPE_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE,
 635                                &dp_alt_mode_disable);
 636                }
 637        }
 638
 639        return (dp_alt_mode_disable == 0);
 640}
 641
 642void dcn31_link_encoder_get_max_link_cap(struct link_encoder *enc, struct dc_link_settings *link_settings)
 643{
 644        struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
 645        union dmub_rb_cmd cmd;
 646        uint32_t is_in_usb_c_dp4_mode = 0;
 647
 648        dcn10_link_encoder_get_max_link_cap(enc, link_settings);
 649
 650        /* Take the link cap directly if not USB */
 651        if (!enc->features.flags.bits.DP_IS_USB_C)
 652                return;
 653
 654        /*
 655         * Use the new interface from DMCUB if available.
 656         * Avoids hanging the RDCPSPIPE if DMCUB wasn't already running.
 657         */
 658        if (has_query_dp_alt(enc)) {
 659                if (!query_dp_alt_from_dmub(enc, &cmd))
 660                        return;
 661
 662                if (cmd.query_dp_alt.data.is_usb &&
 663                    cmd.query_dp_alt.data.is_dp4 == 0)
 664                        link_settings->lane_count = MIN(LANE_COUNT_TWO, link_settings->lane_count);
 665
 666                return;
 667        }
 668
 669        /* Legacy path, avoid if possible. */
 670        if (enc->ctx->asic_id.hw_internal_rev != YELLOW_CARP_B0) {
 671                REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DP4,
 672                        &is_in_usb_c_dp4_mode);
 673        } else {
 674                if ((enc10->base.transmitter == TRANSMITTER_UNIPHY_A) ||
 675                    (enc10->base.transmitter == TRANSMITTER_UNIPHY_B) ||
 676                    (enc10->base.transmitter == TRANSMITTER_UNIPHY_E)) {
 677                        REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DP4,
 678                                &is_in_usb_c_dp4_mode);
 679                } else {
 680                        REG_GET(RDPCSPIPE_PHY_CNTL6, RDPCS_PHY_DPALT_DP4,
 681                                &is_in_usb_c_dp4_mode);
 682                }
 683        }
 684
 685        if (!is_in_usb_c_dp4_mode)
 686                link_settings->lane_count = MIN(LANE_COUNT_TWO, link_settings->lane_count);
 687}
 688