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24#ifndef __SMU11_DRIVER_IF_SIENNA_CICHLID_H__
25#define __SMU11_DRIVER_IF_SIENNA_CICHLID_H__
26
27
28
29
30#define SMU11_DRIVER_IF_VERSION 0x3B
31
32#define PPTABLE_Sienna_Cichlid_SMU_VERSION 7
33
34#define NUM_GFXCLK_DPM_LEVELS 16
35#define NUM_SMNCLK_DPM_LEVELS 2
36#define NUM_SOCCLK_DPM_LEVELS 8
37#define NUM_MP0CLK_DPM_LEVELS 2
38#define NUM_DCLK_DPM_LEVELS 8
39#define NUM_VCLK_DPM_LEVELS 8
40#define NUM_DCEFCLK_DPM_LEVELS 8
41#define NUM_PHYCLK_DPM_LEVELS 8
42#define NUM_DISPCLK_DPM_LEVELS 8
43#define NUM_PIXCLK_DPM_LEVELS 8
44#define NUM_DTBCLK_DPM_LEVELS 8
45#define NUM_UCLK_DPM_LEVELS 4
46#define NUM_MP1CLK_DPM_LEVELS 2
47#define NUM_LINK_LEVELS 2
48#define NUM_FCLK_DPM_LEVELS 8
49#define NUM_XGMI_LEVELS 2
50#define NUM_XGMI_PSTATE_LEVELS 4
51#define NUM_OD_FAN_MAX_POINTS 6
52
53#define MAX_GFXCLK_DPM_LEVEL (NUM_GFXCLK_DPM_LEVELS - 1)
54#define MAX_SMNCLK_DPM_LEVEL (NUM_SMNCLK_DPM_LEVELS - 1)
55#define MAX_SOCCLK_DPM_LEVEL (NUM_SOCCLK_DPM_LEVELS - 1)
56#define MAX_MP0CLK_DPM_LEVEL (NUM_MP0CLK_DPM_LEVELS - 1)
57#define MAX_DCLK_DPM_LEVEL (NUM_DCLK_DPM_LEVELS - 1)
58#define MAX_VCLK_DPM_LEVEL (NUM_VCLK_DPM_LEVELS - 1)
59#define MAX_DCEFCLK_DPM_LEVEL (NUM_DCEFCLK_DPM_LEVELS - 1)
60#define MAX_DISPCLK_DPM_LEVEL (NUM_DISPCLK_DPM_LEVELS - 1)
61#define MAX_PIXCLK_DPM_LEVEL (NUM_PIXCLK_DPM_LEVELS - 1)
62#define MAX_PHYCLK_DPM_LEVEL (NUM_PHYCLK_DPM_LEVELS - 1)
63#define MAX_DTBCLK_DPM_LEVEL (NUM_DTBCLK_DPM_LEVELS - 1)
64#define MAX_UCLK_DPM_LEVEL (NUM_UCLK_DPM_LEVELS - 1)
65#define MAX_MP1CLK_DPM_LEVEL (NUM_MP1CLK_DPM_LEVELS - 1)
66#define MAX_LINK_LEVEL (NUM_LINK_LEVELS - 1)
67#define MAX_FCLK_DPM_LEVEL (NUM_FCLK_DPM_LEVELS - 1)
68
69
70#define PPSMC_GeminiModeNone 0
71#define PPSMC_GeminiModeMaster 1
72#define PPSMC_GeminiModeSlave 2
73
74
75
76#define FEATURE_DPM_PREFETCHER_BIT 0
77#define FEATURE_DPM_GFXCLK_BIT 1
78#define FEATURE_DPM_GFX_GPO_BIT 2
79#define FEATURE_DPM_UCLK_BIT 3
80#define FEATURE_DPM_FCLK_BIT 4
81#define FEATURE_DPM_SOCCLK_BIT 5
82#define FEATURE_DPM_MP0CLK_BIT 6
83#define FEATURE_DPM_LINK_BIT 7
84#define FEATURE_DPM_DCEFCLK_BIT 8
85#define FEATURE_DPM_XGMI_BIT 9
86#define FEATURE_MEM_VDDCI_SCALING_BIT 10
87#define FEATURE_MEM_MVDD_SCALING_BIT 11
88
89
90#define FEATURE_DS_GFXCLK_BIT 12
91#define FEATURE_DS_SOCCLK_BIT 13
92#define FEATURE_DS_FCLK_BIT 14
93#define FEATURE_DS_LCLK_BIT 15
94#define FEATURE_DS_DCEFCLK_BIT 16
95#define FEATURE_DS_UCLK_BIT 17
96#define FEATURE_GFX_ULV_BIT 18
97#define FEATURE_FW_DSTATE_BIT 19
98#define FEATURE_GFXOFF_BIT 20
99#define FEATURE_BACO_BIT 21
100#define FEATURE_MM_DPM_PG_BIT 22
101#define FEATURE_SPARE_23_BIT 23
102
103#define FEATURE_PPT_BIT 24
104#define FEATURE_TDC_BIT 25
105#define FEATURE_APCC_PLUS_BIT 26
106#define FEATURE_GTHR_BIT 27
107#define FEATURE_ACDC_BIT 28
108#define FEATURE_VR0HOT_BIT 29
109#define FEATURE_VR1HOT_BIT 30
110#define FEATURE_FW_CTF_BIT 31
111#define FEATURE_FAN_CONTROL_BIT 32
112#define FEATURE_THERMAL_BIT 33
113#define FEATURE_GFX_DCS_BIT 34
114
115#define FEATURE_RM_BIT 35
116#define FEATURE_LED_DISPLAY_BIT 36
117
118#define FEATURE_GFX_SS_BIT 37
119#define FEATURE_OUT_OF_BAND_MONITOR_BIT 38
120#define FEATURE_TEMP_DEPENDENT_VMIN_BIT 39
121
122#define FEATURE_MMHUB_PG_BIT 40
123#define FEATURE_ATHUB_PG_BIT 41
124#define FEATURE_APCC_DFLL_BIT 42
125#define FEATURE_DF_SUPERV_BIT 43
126#define FEATURE_RSMU_SMN_CG_BIT 44
127#define FEATURE_DF_CSTATE_BIT 45
128#define FEATURE_2_STEP_PSTATE_BIT 46
129#define FEATURE_SMNCLK_DPM_BIT 47
130#define FEATURE_PERLINK_GMIDOWN_BIT 48
131#define FEATURE_GFX_EDC_BIT 49
132#define FEATURE_GFX_PER_PART_VMIN_BIT 50
133#define FEATURE_SMART_SHIFT_BIT 51
134#define FEATURE_APT_BIT 52
135#define FEATURE_SPARE_53_BIT 53
136#define FEATURE_SPARE_54_BIT 54
137#define FEATURE_SPARE_55_BIT 55
138#define FEATURE_SPARE_56_BIT 56
139#define FEATURE_SPARE_57_BIT 57
140#define FEATURE_SPARE_58_BIT 58
141#define FEATURE_SPARE_59_BIT 59
142#define FEATURE_SPARE_60_BIT 60
143#define FEATURE_SPARE_61_BIT 61
144#define FEATURE_SPARE_62_BIT 62
145#define FEATURE_SPARE_63_BIT 63
146#define NUM_FEATURES 64
147
148
149typedef enum {
150 FEATURE_PWR_ALL,
151 FEATURE_PWR_S5,
152 FEATURE_PWR_BACO,
153 FEATURE_PWR_SOC,
154 FEATURE_PWR_GFX,
155 FEATURE_PWR_DOMAIN_COUNT,
156} FEATURE_PWR_DOMAIN_e;
157
158
159
160#define DPM_OVERRIDE_DISABLE_FCLK_PID 0x00000001
161#define DPM_OVERRIDE_DISABLE_UCLK_PID 0x00000002
162#define DPM_OVERRIDE_DISABLE_VOLT_LINK_VCN_FCLK 0x00000004
163#define DPM_OVERRIDE_ENABLE_FREQ_LINK_VCLK_FCLK 0x00000008
164#define DPM_OVERRIDE_ENABLE_FREQ_LINK_DCLK_FCLK 0x00000010
165#define DPM_OVERRIDE_ENABLE_FREQ_LINK_GFXCLK_SOCCLK 0x00000020
166#define DPM_OVERRIDE_ENABLE_FREQ_LINK_GFXCLK_UCLK 0x00000040
167#define DPM_OVERRIDE_DISABLE_VOLT_LINK_DCE_FCLK 0x00000080
168#define DPM_OVERRIDE_DISABLE_VOLT_LINK_MP0_SOCCLK 0x00000100
169#define DPM_OVERRIDE_DISABLE_DFLL_PLL_SHUTDOWN 0x00000200
170#define DPM_OVERRIDE_DISABLE_MEMORY_TEMPERATURE_READ 0x00000400
171#define DPM_OVERRIDE_DISABLE_VOLT_LINK_VCN_DCEFCLK 0x00000800
172#define DPM_OVERRIDE_DISABLE_FAST_FCLK_TIMER 0x00001000
173#define DPM_OVERRIDE_DISABLE_VCN_PG 0x00002000
174#define DPM_OVERRIDE_DISABLE_FMAX_VMAX 0x00004000
175
176
177#define VR_MAPPING_VR_SELECT_MASK 0x01
178#define VR_MAPPING_VR_SELECT_SHIFT 0x00
179
180#define VR_MAPPING_PLANE_SELECT_MASK 0x02
181#define VR_MAPPING_PLANE_SELECT_SHIFT 0x01
182
183
184#define PSI_SEL_VR0_PLANE0_PSI0 0x01
185#define PSI_SEL_VR0_PLANE0_PSI1 0x02
186#define PSI_SEL_VR0_PLANE1_PSI0 0x04
187#define PSI_SEL_VR0_PLANE1_PSI1 0x08
188#define PSI_SEL_VR1_PLANE0_PSI0 0x10
189#define PSI_SEL_VR1_PLANE0_PSI1 0x20
190#define PSI_SEL_VR1_PLANE1_PSI0 0x40
191#define PSI_SEL_VR1_PLANE1_PSI1 0x80
192
193
194#define THROTTLER_PADDING_BIT 0
195#define THROTTLER_TEMP_EDGE_BIT 1
196#define THROTTLER_TEMP_HOTSPOT_BIT 2
197#define THROTTLER_TEMP_MEM_BIT 3
198#define THROTTLER_TEMP_VR_GFX_BIT 4
199#define THROTTLER_TEMP_VR_MEM0_BIT 5
200#define THROTTLER_TEMP_VR_MEM1_BIT 6
201#define THROTTLER_TEMP_VR_SOC_BIT 7
202#define THROTTLER_TEMP_LIQUID0_BIT 8
203#define THROTTLER_TEMP_LIQUID1_BIT 9
204#define THROTTLER_TEMP_PLX_BIT 10
205#define THROTTLER_TDC_GFX_BIT 11
206#define THROTTLER_TDC_SOC_BIT 12
207#define THROTTLER_PPT0_BIT 13
208#define THROTTLER_PPT1_BIT 14
209#define THROTTLER_PPT2_BIT 15
210#define THROTTLER_PPT3_BIT 16
211#define THROTTLER_FIT_BIT 17
212#define THROTTLER_PPM_BIT 18
213#define THROTTLER_APCC_BIT 19
214#define THROTTLER_COUNT 20
215
216
217
218#define FW_DSTATE_SOC_ULV_BIT 0
219#define FW_DSTATE_G6_HSR_BIT 1
220#define FW_DSTATE_G6_PHY_VDDCI_OFF_BIT 2
221#define FW_DSTATE_MP0_DS_BIT 3
222#define FW_DSTATE_SMN_DS_BIT 4
223#define FW_DSTATE_MP1_DS_BIT 5
224#define FW_DSTATE_MP1_WHISPER_MODE_BIT 6
225#define FW_DSTATE_SOC_LIV_MIN_BIT 7
226#define FW_DSTATE_SOC_PLL_PWRDN_BIT 8
227#define FW_DSTATE_MEM_PLL_PWRDN_BIT 9
228#define FW_DSTATE_OPTIMIZE_MALL_REFRESH_BIT 10
229#define FW_DSTATE_MEM_PSI_BIT 11
230#define FW_DSTATE_HSR_NON_STROBE_BIT 12
231#define FW_DSTATE_MP0_ENTER_WFI_BIT 13
232
233#define FW_DSTATE_SOC_ULV_MASK (1 << FW_DSTATE_SOC_ULV_BIT )
234#define FW_DSTATE_G6_HSR_MASK (1 << FW_DSTATE_G6_HSR_BIT )
235#define FW_DSTATE_G6_PHY_VDDCI_OFF_MASK (1 << FW_DSTATE_G6_PHY_VDDCI_OFF_BIT )
236#define FW_DSTATE_MP1_DS_MASK (1 << FW_DSTATE_MP1_DS_BIT )
237#define FW_DSTATE_MP0_DS_MASK (1 << FW_DSTATE_MP0_DS_BIT )
238#define FW_DSTATE_SMN_DS_MASK (1 << FW_DSTATE_SMN_DS_BIT )
239#define FW_DSTATE_MP1_WHISPER_MODE_MASK (1 << FW_DSTATE_MP1_WHISPER_MODE_BIT )
240#define FW_DSTATE_SOC_LIV_MIN_MASK (1 << FW_DSTATE_SOC_LIV_MIN_BIT )
241#define FW_DSTATE_SOC_PLL_PWRDN_MASK (1 << FW_DSTATE_SOC_PLL_PWRDN_BIT )
242#define FW_DSTATE_MEM_PLL_PWRDN_MASK (1 << FW_DSTATE_MEM_PLL_PWRDN_BIT )
243#define FW_DSTATE_OPTIMIZE_MALL_REFRESH_MASK (1 << FW_DSTATE_OPTIMIZE_MALL_REFRESH_BIT )
244#define FW_DSTATE_MEM_PSI_MASK (1 << FW_DSTATE_MEM_PSI_BIT )
245#define FW_DSTATE_HSR_NON_STROBE_MASK (1 << FW_DSTATE_HSR_NON_STROBE_BIT )
246#define FW_DSTATE_MP0_ENTER_WFI_MASK (1 << FW_DSTATE_MP0_ENTER_WFI_BIT )
247
248
249#define GFX_GPO_PACE_BIT 0
250#define GFX_GPO_DEM_BIT 1
251
252#define GFX_GPO_PACE_MASK (1 << GFX_GPO_PACE_BIT)
253#define GFX_GPO_DEM_MASK (1 << GFX_GPO_DEM_BIT )
254
255#define GPO_UPDATE_REQ_UCLKDPM_MASK 0x1
256#define GPO_UPDATE_REQ_FCLKDPM_MASK 0x2
257#define GPO_UPDATE_REQ_MALLHIT_MASK 0x4
258
259
260
261#define LED_DISPLAY_GFX_DPM_BIT 0
262#define LED_DISPLAY_PCIE_BIT 1
263#define LED_DISPLAY_ERROR_BIT 2
264
265
266#define RLC_PACE_TABLE_NUM_LEVELS 16
267
268typedef enum {
269 DRAM_BIT_WIDTH_DISABLED = 0,
270 DRAM_BIT_WIDTH_X_8,
271 DRAM_BIT_WIDTH_X_16,
272 DRAM_BIT_WIDTH_X_32,
273 DRAM_BIT_WIDTH_X_64,
274 DRAM_BIT_WIDTH_X_128,
275 DRAM_BIT_WIDTH_COUNT,
276} DRAM_BIT_WIDTH_TYPE_e;
277
278
279#define NUM_I2C_CONTROLLERS 16
280
281#define I2C_CONTROLLER_ENABLED 1
282#define I2C_CONTROLLER_DISABLED 0
283
284#define MAX_SW_I2C_COMMANDS 24
285
286typedef enum {
287 I2C_CONTROLLER_PORT_0 = 0,
288 I2C_CONTROLLER_PORT_1 = 1,
289 I2C_CONTROLLER_PORT_COUNT,
290} I2cControllerPort_e;
291
292typedef enum {
293 I2C_CONTROLLER_NAME_VR_GFX = 0,
294 I2C_CONTROLLER_NAME_VR_SOC,
295 I2C_CONTROLLER_NAME_VR_VDDCI,
296 I2C_CONTROLLER_NAME_VR_MVDD,
297 I2C_CONTROLLER_NAME_LIQUID0,
298 I2C_CONTROLLER_NAME_LIQUID1,
299 I2C_CONTROLLER_NAME_PLX,
300 I2C_CONTROLLER_NAME_OTHER,
301 I2C_CONTROLLER_NAME_COUNT,
302} I2cControllerName_e;
303
304typedef enum {
305 I2C_CONTROLLER_THROTTLER_TYPE_NONE = 0,
306 I2C_CONTROLLER_THROTTLER_VR_GFX,
307 I2C_CONTROLLER_THROTTLER_VR_SOC,
308 I2C_CONTROLLER_THROTTLER_VR_VDDCI,
309 I2C_CONTROLLER_THROTTLER_VR_MVDD,
310 I2C_CONTROLLER_THROTTLER_LIQUID0,
311 I2C_CONTROLLER_THROTTLER_LIQUID1,
312 I2C_CONTROLLER_THROTTLER_PLX,
313 I2C_CONTROLLER_THROTTLER_INA3221,
314 I2C_CONTROLLER_THROTTLER_COUNT,
315} I2cControllerThrottler_e;
316
317typedef enum {
318 I2C_CONTROLLER_PROTOCOL_VR_XPDE132G5,
319 I2C_CONTROLLER_PROTOCOL_VR_IR35217,
320 I2C_CONTROLLER_PROTOCOL_TMP_TMP102A,
321 I2C_CONTROLLER_PROTOCOL_INA3221,
322 I2C_CONTROLLER_PROTOCOL_COUNT,
323} I2cControllerProtocol_e;
324
325typedef struct {
326 uint8_t Enabled;
327 uint8_t Speed;
328 uint8_t SlaveAddress;
329 uint8_t ControllerPort;
330 uint8_t ControllerName;
331 uint8_t ThermalThrotter;
332 uint8_t I2cProtocol;
333 uint8_t PaddingConfig;
334} I2cControllerConfig_t;
335
336typedef enum {
337 I2C_PORT_SVD_SCL = 0,
338 I2C_PORT_GPIO,
339} I2cPort_e;
340
341typedef enum {
342 I2C_SPEED_FAST_50K = 0,
343 I2C_SPEED_FAST_100K,
344 I2C_SPEED_FAST_400K,
345 I2C_SPEED_FAST_PLUS_1M,
346 I2C_SPEED_HIGH_1M,
347 I2C_SPEED_HIGH_2M,
348 I2C_SPEED_COUNT,
349} I2cSpeed_e;
350
351typedef enum {
352 I2C_CMD_READ = 0,
353 I2C_CMD_WRITE,
354 I2C_CMD_COUNT,
355} I2cCmdType_e;
356
357typedef enum {
358 FAN_MODE_AUTO = 0,
359 FAN_MODE_MANUAL_LINEAR,
360} FanMode_e;
361
362#define CMDCONFIG_STOP_BIT 0
363#define CMDCONFIG_RESTART_BIT 1
364#define CMDCONFIG_READWRITE_BIT 2
365
366#define CMDCONFIG_STOP_MASK (1 << CMDCONFIG_STOP_BIT)
367#define CMDCONFIG_RESTART_MASK (1 << CMDCONFIG_RESTART_BIT)
368#define CMDCONFIG_READWRITE_MASK (1 << CMDCONFIG_READWRITE_BIT)
369
370typedef struct {
371 uint8_t ReadWriteData;
372 uint8_t CmdConfig;
373} SwI2cCmd_t;
374
375typedef struct {
376 uint8_t I2CcontrollerPort;
377 uint8_t I2CSpeed;
378 uint8_t SlaveAddress;
379 uint8_t NumCmds;
380
381 SwI2cCmd_t SwI2cCmds[MAX_SW_I2C_COMMANDS];
382} SwI2cRequest_t;
383
384typedef struct {
385 SwI2cRequest_t SwI2cRequest;
386
387 uint32_t Spare[8];
388 uint32_t MmHubPadding[8];
389} SwI2cRequestExternal_t;
390
391
392typedef enum {
393 BACO_SEQUENCE,
394 MSR_SEQUENCE,
395 BAMACO_SEQUENCE,
396 ULPS_SEQUENCE,
397 D3HOT_SEQUENCE_COUNT,
398} D3HOTSequence_e;
399
400
401typedef enum {
402 PG_DYNAMIC_MODE = 0,
403 PG_STATIC_MODE,
404} PowerGatingMode_e;
405
406
407typedef enum {
408 PG_POWER_DOWN = 0,
409 PG_POWER_UP,
410} PowerGatingSettings_e;
411
412typedef struct {
413 uint32_t a;
414 uint32_t b;
415 uint32_t c;
416} QuadraticInt_t;
417
418typedef struct {
419 uint32_t a;
420 uint32_t b;
421 uint32_t c;
422} QuadraticFixedPoint_t;
423
424typedef struct {
425 uint32_t m;
426 uint32_t b;
427} LinearInt_t;
428
429typedef struct {
430 uint32_t a;
431 uint32_t b;
432 uint32_t c;
433} DroopInt_t;
434
435
436#define NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS 5
437typedef enum {
438 PIECEWISE_LINEAR_FUSED_MODEL = 0,
439 PIECEWISE_LINEAR_PP_MODEL,
440 QUADRATIC_PP_MODEL,
441 PERPART_PIECEWISE_LINEAR_PP_MODEL,
442} DfllDroopModelSelect_e;
443
444typedef struct {
445 uint32_t Fset[NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS];
446 uint32_t Vdroop[NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS];
447}PiecewiseLinearDroopInt_t;
448
449typedef enum {
450 GFXCLK_SOURCE_PLL = 0,
451 GFXCLK_SOURCE_DFLL,
452 GFXCLK_SOURCE_COUNT,
453} GFXCLK_SOURCE_e;
454
455
456typedef enum {
457 PPCLK_GFXCLK = 0,
458 PPCLK_SOCCLK,
459 PPCLK_UCLK,
460 PPCLK_FCLK,
461 PPCLK_DCLK_0,
462 PPCLK_VCLK_0,
463 PPCLK_DCLK_1,
464 PPCLK_VCLK_1,
465 PPCLK_DCEFCLK,
466 PPCLK_DISPCLK,
467 PPCLK_PIXCLK,
468 PPCLK_PHYCLK,
469 PPCLK_DTBCLK,
470 PPCLK_COUNT,
471} PPCLK_e;
472
473typedef enum {
474 VOLTAGE_MODE_AVFS = 0,
475 VOLTAGE_MODE_AVFS_SS,
476 VOLTAGE_MODE_SS,
477 VOLTAGE_MODE_COUNT,
478} VOLTAGE_MODE_e;
479
480
481typedef enum {
482 AVFS_VOLTAGE_GFX = 0,
483 AVFS_VOLTAGE_SOC,
484 AVFS_VOLTAGE_COUNT,
485} AVFS_VOLTAGE_TYPE_e;
486
487typedef enum {
488 UCLK_DIV_BY_1 = 0,
489 UCLK_DIV_BY_2,
490 UCLK_DIV_BY_4,
491 UCLK_DIV_BY_8,
492} UCLK_DIV_e;
493
494typedef enum {
495 GPIO_INT_POLARITY_ACTIVE_LOW = 0,
496 GPIO_INT_POLARITY_ACTIVE_HIGH,
497} GpioIntPolarity_e;
498
499typedef enum {
500 PWR_CONFIG_TDP = 0,
501 PWR_CONFIG_TGP,
502 PWR_CONFIG_TCP_ESTIMATED,
503 PWR_CONFIG_TCP_MEASURED,
504} PwrConfig_e;
505
506typedef enum {
507 XGMI_LINK_RATE_2 = 2,
508 XGMI_LINK_RATE_4 = 4,
509 XGMI_LINK_RATE_8 = 8,
510 XGMI_LINK_RATE_12 = 12,
511 XGMI_LINK_RATE_16 = 16,
512 XGMI_LINK_RATE_17 = 17,
513 XGMI_LINK_RATE_18 = 18,
514 XGMI_LINK_RATE_19 = 19,
515 XGMI_LINK_RATE_20 = 20,
516 XGMI_LINK_RATE_21 = 21,
517 XGMI_LINK_RATE_22 = 22,
518 XGMI_LINK_RATE_23 = 23,
519 XGMI_LINK_RATE_24 = 24,
520 XGMI_LINK_RATE_25 = 25,
521 XGMI_LINK_RATE_COUNT
522} XGMI_LINK_RATE_e;
523
524typedef enum {
525 XGMI_LINK_WIDTH_1 = 0,
526 XGMI_LINK_WIDTH_2,
527 XGMI_LINK_WIDTH_4,
528 XGMI_LINK_WIDTH_8,
529 XGMI_LINK_WIDTH_9,
530 XGMI_LINK_WIDTH_16,
531 XGMI_LINK_WIDTH_COUNT
532} XGMI_LINK_WIDTH_e;
533
534typedef struct {
535 uint8_t VoltageMode;
536 uint8_t SnapToDiscrete;
537 uint8_t NumDiscreteLevels;
538 uint8_t Padding;
539 LinearInt_t ConversionToAvfsClk;
540 QuadraticInt_t SsCurve;
541 uint16_t SsFmin;
542 uint16_t Padding16;
543} DpmDescriptor_t;
544
545typedef enum {
546 PPT_THROTTLER_PPT0,
547 PPT_THROTTLER_PPT1,
548 PPT_THROTTLER_PPT2,
549 PPT_THROTTLER_PPT3,
550 PPT_THROTTLER_COUNT
551} PPT_THROTTLER_e;
552
553typedef enum {
554 TEMP_EDGE,
555 TEMP_HOTSPOT,
556 TEMP_MEM,
557 TEMP_VR_GFX,
558 TEMP_VR_MEM0,
559 TEMP_VR_MEM1,
560 TEMP_VR_SOC,
561 TEMP_LIQUID0,
562 TEMP_LIQUID1,
563 TEMP_PLX,
564 TEMP_COUNT,
565} TEMP_e;
566
567typedef enum {
568 TDC_THROTTLER_GFX,
569 TDC_THROTTLER_SOC,
570 TDC_THROTTLER_COUNT
571} TDC_THROTTLER_e;
572
573typedef enum {
574 CUSTOMER_VARIANT_ROW,
575 CUSTOMER_VARIANT_FALCON,
576 CUSTOMER_VARIANT_COUNT,
577} CUSTOMER_VARIANT_e;
578
579
580typedef struct {
581 uint16_t Fmin;
582 uint16_t Fmax;
583} UclkDpmChangeRange_t;
584
585typedef struct {
586
587
588 uint32_t Version;
589
590
591 uint32_t FeaturesToRun[NUM_FEATURES / 32];
592
593
594 uint16_t SocketPowerLimitAc[PPT_THROTTLER_COUNT];
595 uint16_t SocketPowerLimitAcTau[PPT_THROTTLER_COUNT];
596 uint16_t SocketPowerLimitDc[PPT_THROTTLER_COUNT];
597 uint16_t SocketPowerLimitDcTau[PPT_THROTTLER_COUNT];
598
599 uint16_t TdcLimit[TDC_THROTTLER_COUNT];
600 uint16_t TdcLimitTau[TDC_THROTTLER_COUNT];
601
602 uint16_t TemperatureLimit[TEMP_COUNT];
603
604 uint32_t FitLimit;
605
606
607 uint8_t TotalPowerConfig;
608 uint8_t TotalPowerPadding[3];
609
610
611 uint32_t ApccPlusResidencyLimit;
612
613
614 uint16_t SmnclkDpmFreq [NUM_SMNCLK_DPM_LEVELS];
615 uint16_t SmnclkDpmVoltage [NUM_SMNCLK_DPM_LEVELS];
616
617 uint32_t PaddingAPCC;
618 uint16_t PerPartDroopVsetGfxDfll[NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS];
619 uint16_t PaddingPerPartDroop;
620
621
622 uint32_t ThrottlerControlMask;
623
624
625 uint32_t FwDStateMask;
626
627
628 uint16_t UlvVoltageOffsetSoc;
629 uint16_t UlvVoltageOffsetGfx;
630
631 uint16_t MinVoltageUlvGfx;
632 uint16_t MinVoltageUlvSoc;
633
634 uint16_t SocLIVmin;
635 uint16_t PaddingLIVmin;
636
637 uint8_t GceaLinkMgrIdleThreshold;
638 uint8_t paddingRlcUlvParams[3];
639
640
641 uint16_t MinVoltageGfx;
642 uint16_t MinVoltageSoc;
643 uint16_t MaxVoltageGfx;
644 uint16_t MaxVoltageSoc;
645
646 uint16_t LoadLineResistanceGfx;
647 uint16_t LoadLineResistanceSoc;
648
649
650 uint16_t VDDGFX_TVmin;
651 uint16_t VDDSOC_TVmin;
652 uint16_t VDDGFX_Vmin_HiTemp;
653 uint16_t VDDGFX_Vmin_LoTemp;
654 uint16_t VDDSOC_Vmin_HiTemp;
655 uint16_t VDDSOC_Vmin_LoTemp;
656
657 uint16_t VDDGFX_TVminHystersis;
658 uint16_t VDDSOC_TVminHystersis;
659
660
661 DpmDescriptor_t DpmDescriptor[PPCLK_COUNT];
662
663 uint16_t FreqTableGfx [NUM_GFXCLK_DPM_LEVELS ];
664 uint16_t FreqTableVclk [NUM_VCLK_DPM_LEVELS ];
665 uint16_t FreqTableDclk [NUM_DCLK_DPM_LEVELS ];
666 uint16_t FreqTableSocclk [NUM_SOCCLK_DPM_LEVELS ];
667 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ];
668 uint16_t FreqTableDcefclk [NUM_DCEFCLK_DPM_LEVELS ];
669 uint16_t FreqTableDispclk [NUM_DISPCLK_DPM_LEVELS ];
670 uint16_t FreqTablePixclk [NUM_PIXCLK_DPM_LEVELS ];
671 uint16_t FreqTablePhyclk [NUM_PHYCLK_DPM_LEVELS ];
672 uint16_t FreqTableDtbclk [NUM_DTBCLK_DPM_LEVELS ];
673 uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ];
674 uint32_t Paddingclks;
675
676 DroopInt_t PerPartDroopModelGfxDfll[NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS];
677
678 uint32_t DcModeMaxFreq [PPCLK_COUNT ];
679
680 uint8_t FreqTableUclkDiv [NUM_UCLK_DPM_LEVELS ];
681
682
683 uint16_t FclkBoostFreq;
684 uint16_t FclkParamPadding;
685
686
687 uint16_t Mp0clkFreq [NUM_MP0CLK_DPM_LEVELS];
688 uint16_t Mp0DpmVoltage [NUM_MP0CLK_DPM_LEVELS];
689 uint16_t MemVddciVoltage [NUM_UCLK_DPM_LEVELS];
690 uint16_t MemMvddVoltage [NUM_UCLK_DPM_LEVELS];
691
692 uint16_t GfxclkFgfxoffEntry;
693 uint16_t GfxclkFinit;
694 uint16_t GfxclkFidle;
695 uint8_t GfxclkSource;
696 uint8_t GfxclkPadding;
697
698
699 uint8_t GfxGpoSubFeatureMask;
700 uint8_t GfxGpoEnabledWorkPolicyMask;
701 uint8_t GfxGpoDisabledWorkPolicyMask;
702 uint8_t GfxGpoPadding[1];
703 uint32_t GfxGpoVotingAllow;
704
705 uint32_t GfxGpoPadding32[4];
706
707 uint16_t GfxDcsFopt;
708 uint16_t GfxDcsFclkFopt;
709 uint16_t GfxDcsUclkFopt;
710
711 uint16_t DcsGfxOffVoltage;
712
713 uint16_t DcsMinGfxOffTime;
714 uint16_t DcsMaxGfxOffTime;
715
716 uint32_t DcsMinCreditAccum;
717
718 uint16_t DcsExitHysteresis;
719 uint16_t DcsTimeout;
720
721 uint32_t DcsParamPadding[5];
722
723 uint16_t FlopsPerByteTable[RLC_PACE_TABLE_NUM_LEVELS];
724
725
726 uint8_t LowestUclkReservedForUlv;
727 uint8_t PaddingMem[3];
728
729 uint8_t UclkDpmPstates [NUM_UCLK_DPM_LEVELS];
730
731
732 UclkDpmChangeRange_t UclkDpmSrcFreqRange;
733 UclkDpmChangeRange_t UclkDpmTargFreqRange;
734 uint16_t UclkDpmMidstepFreq;
735 uint16_t UclkMidstepPadding;
736
737
738 uint8_t PcieGenSpeed[NUM_LINK_LEVELS];
739 uint8_t PcieLaneCount[NUM_LINK_LEVELS];
740 uint16_t LclkFreq[NUM_LINK_LEVELS];
741
742
743 uint16_t FanStopTemp;
744 uint16_t FanStartTemp;
745
746 uint16_t FanGain[TEMP_COUNT];
747
748 uint16_t FanPwmMin;
749 uint16_t FanAcousticLimitRpm;
750 uint16_t FanThrottlingRpm;
751 uint16_t FanMaximumRpm;
752 uint16_t MGpuFanBoostLimitRpm;
753 uint16_t FanTargetTemperature;
754 uint16_t FanTargetGfxclk;
755 uint16_t FanPadding16;
756 uint8_t FanTempInputSelect;
757 uint8_t FanPadding;
758 uint8_t FanZeroRpmEnable;
759 uint8_t FanTachEdgePerRev;
760
761
762 int16_t FuzzyFan_ErrorSetDelta;
763 int16_t FuzzyFan_ErrorRateSetDelta;
764 int16_t FuzzyFan_PwmSetDelta;
765 uint16_t FuzzyFan_Reserved;
766
767
768
769 uint8_t OverrideAvfsGb[AVFS_VOLTAGE_COUNT];
770 uint8_t dBtcGbGfxDfllModelSelect;
771 uint8_t Padding8_Avfs;
772
773 QuadraticInt_t qAvfsGb[AVFS_VOLTAGE_COUNT];
774 DroopInt_t dBtcGbGfxPll;
775 DroopInt_t dBtcGbGfxDfll;
776 DroopInt_t dBtcGbSoc;
777 LinearInt_t qAgingGb[AVFS_VOLTAGE_COUNT];
778
779 PiecewiseLinearDroopInt_t PiecewiseLinearDroopIntGfxDfll;
780
781 QuadraticInt_t qStaticVoltageOffset[AVFS_VOLTAGE_COUNT];
782
783 uint16_t DcTol[AVFS_VOLTAGE_COUNT];
784
785 uint8_t DcBtcEnabled[AVFS_VOLTAGE_COUNT];
786 uint8_t Padding8_GfxBtc[2];
787
788 uint16_t DcBtcMin[AVFS_VOLTAGE_COUNT];
789 uint16_t DcBtcMax[AVFS_VOLTAGE_COUNT];
790
791 uint16_t DcBtcGb[AVFS_VOLTAGE_COUNT];
792
793
794 uint8_t XgmiDpmPstates[NUM_XGMI_LEVELS];
795 uint8_t XgmiDpmSpare[2];
796
797
798 uint32_t DebugOverrides;
799 QuadraticInt_t ReservedEquation0;
800 QuadraticInt_t ReservedEquation1;
801 QuadraticInt_t ReservedEquation2;
802 QuadraticInt_t ReservedEquation3;
803
804
805 uint8_t CustomerVariant;
806
807
808 uint8_t VcBtcEnabled;
809 uint16_t VcBtcVminT0;
810 uint16_t VcBtcFixedVminAgingOffset;
811 uint16_t VcBtcVmin2PsmDegrationGb;
812 uint32_t VcBtcPsmA;
813 uint32_t VcBtcPsmB;
814 uint32_t VcBtcVminA;
815 uint32_t VcBtcVminB;
816
817
818 uint16_t LedGpio;
819 uint16_t GfxPowerStagesGpio;
820
821 uint32_t SkuReserved[8];
822
823
824
825
826
827 uint32_t GamingClk[6];
828
829
830 I2cControllerConfig_t I2cControllers[NUM_I2C_CONTROLLERS];
831
832 uint8_t GpioScl;
833 uint8_t GpioSda;
834 uint8_t FchUsbPdSlaveAddr;
835 uint8_t I2cSpare[1];
836
837
838 uint8_t VddGfxVrMapping;
839 uint8_t VddSocVrMapping;
840 uint8_t VddMem0VrMapping;
841 uint8_t VddMem1VrMapping;
842
843 uint8_t GfxUlvPhaseSheddingMask;
844 uint8_t SocUlvPhaseSheddingMask;
845 uint8_t VddciUlvPhaseSheddingMask;
846 uint8_t MvddUlvPhaseSheddingMask;
847
848
849 uint16_t GfxMaxCurrent;
850 int8_t GfxOffset;
851 uint8_t Padding_TelemetryGfx;
852
853 uint16_t SocMaxCurrent;
854 int8_t SocOffset;
855 uint8_t Padding_TelemetrySoc;
856
857 uint16_t Mem0MaxCurrent;
858 int8_t Mem0Offset;
859 uint8_t Padding_TelemetryMem0;
860
861 uint16_t Mem1MaxCurrent;
862 int8_t Mem1Offset;
863 uint8_t Padding_TelemetryMem1;
864
865 uint32_t MvddRatio;
866
867
868 uint8_t AcDcGpio;
869 uint8_t AcDcPolarity;
870 uint8_t VR0HotGpio;
871 uint8_t VR0HotPolarity;
872
873 uint8_t VR1HotGpio;
874 uint8_t VR1HotPolarity;
875 uint8_t GthrGpio;
876 uint8_t GthrPolarity;
877
878
879 uint8_t LedPin0;
880 uint8_t LedPin1;
881 uint8_t LedPin2;
882 uint8_t LedEnableMask;
883
884 uint8_t LedPcie;
885 uint8_t LedError;
886 uint8_t LedSpare1[2];
887
888
889
890
891 uint8_t PllGfxclkSpreadEnabled;
892 uint8_t PllGfxclkSpreadPercent;
893 uint16_t PllGfxclkSpreadFreq;
894
895
896 uint8_t DfllGfxclkSpreadEnabled;
897 uint8_t DfllGfxclkSpreadPercent;
898 uint16_t DfllGfxclkSpreadFreq;
899
900
901 uint16_t UclkSpreadPadding;
902 uint16_t UclkSpreadFreq;
903
904
905 uint8_t FclkSpreadEnabled;
906 uint8_t FclkSpreadPercent;
907 uint16_t FclkSpreadFreq;
908
909
910 uint32_t MemoryChannelEnabled;
911
912 uint8_t DramBitWidth;
913 uint8_t PaddingMem1[3];
914
915
916 uint16_t TotalBoardPower;
917 uint16_t BoardPowerPadding;
918
919
920 uint8_t XgmiLinkSpeed [NUM_XGMI_PSTATE_LEVELS];
921 uint8_t XgmiLinkWidth [NUM_XGMI_PSTATE_LEVELS];
922
923 uint16_t XgmiFclkFreq [NUM_XGMI_PSTATE_LEVELS];
924 uint16_t XgmiSocVoltage [NUM_XGMI_PSTATE_LEVELS];
925
926
927 uint8_t HsrEnabled;
928 uint8_t VddqOffEnabled;
929 uint8_t PaddingUmcFlags[2];
930
931
932 uint8_t UclkSpreadPercent[16];
933
934
935 uint32_t BoardReserved[11];
936
937
938
939
940 uint32_t MmHubPadding[8];
941
942} PPTable_t;
943
944typedef struct {
945
946
947 uint32_t Version;
948
949
950 uint32_t FeaturesToRun[NUM_FEATURES / 32];
951
952
953 uint16_t SocketPowerLimitAc[PPT_THROTTLER_COUNT];
954 uint16_t SocketPowerLimitAcTau[PPT_THROTTLER_COUNT];
955 uint16_t SocketPowerLimitDc[PPT_THROTTLER_COUNT];
956 uint16_t SocketPowerLimitDcTau[PPT_THROTTLER_COUNT];
957
958 uint16_t TdcLimit[TDC_THROTTLER_COUNT];
959 uint16_t TdcLimitTau[TDC_THROTTLER_COUNT];
960
961 uint16_t TemperatureLimit[TEMP_COUNT];
962
963 uint32_t FitLimit;
964
965
966 uint8_t TotalPowerConfig;
967 uint8_t TotalPowerPadding[3];
968
969
970 uint32_t ApccPlusResidencyLimit;
971
972
973 uint16_t SmnclkDpmFreq [NUM_SMNCLK_DPM_LEVELS];
974 uint16_t SmnclkDpmVoltage [NUM_SMNCLK_DPM_LEVELS];
975
976 uint32_t PaddingAPCC;
977 uint16_t PerPartDroopVsetGfxDfll[NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS];
978 uint16_t PaddingPerPartDroop;
979
980
981 uint32_t ThrottlerControlMask;
982
983
984 uint32_t FwDStateMask;
985
986
987 uint16_t UlvVoltageOffsetSoc;
988 uint16_t UlvVoltageOffsetGfx;
989
990 uint16_t MinVoltageUlvGfx;
991 uint16_t MinVoltageUlvSoc;
992
993 uint16_t SocLIVmin;
994 uint16_t SocLIVminoffset;
995
996 uint8_t GceaLinkMgrIdleThreshold;
997 uint8_t paddingRlcUlvParams[3];
998
999
1000 uint16_t MinVoltageGfx;
1001 uint16_t MinVoltageSoc;
1002 uint16_t MaxVoltageGfx;
1003 uint16_t MaxVoltageSoc;
1004
1005 uint16_t LoadLineResistanceGfx;
1006 uint16_t LoadLineResistanceSoc;
1007
1008
1009 uint16_t VDDGFX_TVmin;
1010 uint16_t VDDSOC_TVmin;
1011 uint16_t VDDGFX_Vmin_HiTemp;
1012 uint16_t VDDGFX_Vmin_LoTemp;
1013 uint16_t VDDSOC_Vmin_HiTemp;
1014 uint16_t VDDSOC_Vmin_LoTemp;
1015
1016 uint16_t VDDGFX_TVminHystersis;
1017 uint16_t VDDSOC_TVminHystersis;
1018
1019
1020 DpmDescriptor_t DpmDescriptor[PPCLK_COUNT];
1021
1022 uint16_t FreqTableGfx [NUM_GFXCLK_DPM_LEVELS ];
1023 uint16_t FreqTableVclk [NUM_VCLK_DPM_LEVELS ];
1024 uint16_t FreqTableDclk [NUM_DCLK_DPM_LEVELS ];
1025 uint16_t FreqTableSocclk [NUM_SOCCLK_DPM_LEVELS ];
1026 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ];
1027 uint16_t FreqTableDcefclk [NUM_DCEFCLK_DPM_LEVELS ];
1028 uint16_t FreqTableDispclk [NUM_DISPCLK_DPM_LEVELS ];
1029 uint16_t FreqTablePixclk [NUM_PIXCLK_DPM_LEVELS ];
1030 uint16_t FreqTablePhyclk [NUM_PHYCLK_DPM_LEVELS ];
1031 uint16_t FreqTableDtbclk [NUM_DTBCLK_DPM_LEVELS ];
1032 uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ];
1033 uint32_t Paddingclks;
1034
1035 DroopInt_t PerPartDroopModelGfxDfll[NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS];
1036
1037 uint32_t DcModeMaxFreq [PPCLK_COUNT ];
1038
1039 uint8_t FreqTableUclkDiv [NUM_UCLK_DPM_LEVELS ];
1040
1041
1042 uint16_t FclkBoostFreq;
1043 uint16_t FclkParamPadding;
1044
1045
1046 uint16_t Mp0clkFreq [NUM_MP0CLK_DPM_LEVELS];
1047 uint16_t Mp0DpmVoltage [NUM_MP0CLK_DPM_LEVELS];
1048 uint16_t MemVddciVoltage [NUM_UCLK_DPM_LEVELS];
1049 uint16_t MemMvddVoltage [NUM_UCLK_DPM_LEVELS];
1050
1051 uint16_t GfxclkFgfxoffEntry;
1052 uint16_t GfxclkFinit;
1053 uint16_t GfxclkFidle;
1054 uint8_t GfxclkSource;
1055 uint8_t GfxclkPadding;
1056
1057
1058 uint8_t GfxGpoSubFeatureMask;
1059 uint8_t GfxGpoEnabledWorkPolicyMask;
1060 uint8_t GfxGpoDisabledWorkPolicyMask;
1061 uint8_t GfxGpoPadding[1];
1062 uint32_t GfxGpoVotingAllow;
1063
1064 uint32_t GfxGpoPadding32[4];
1065
1066 uint16_t GfxDcsFopt;
1067 uint16_t GfxDcsFclkFopt;
1068 uint16_t GfxDcsUclkFopt;
1069
1070 uint16_t DcsGfxOffVoltage;
1071
1072 uint16_t DcsMinGfxOffTime;
1073 uint16_t DcsMaxGfxOffTime;
1074
1075 uint32_t DcsMinCreditAccum;
1076
1077 uint16_t DcsExitHysteresis;
1078 uint16_t DcsTimeout;
1079
1080 uint32_t DcsParamPadding[5];
1081
1082 uint16_t FlopsPerByteTable[RLC_PACE_TABLE_NUM_LEVELS];
1083
1084
1085 uint8_t LowestUclkReservedForUlv;
1086 uint8_t PaddingMem[3];
1087
1088 uint8_t UclkDpmPstates [NUM_UCLK_DPM_LEVELS];
1089
1090
1091 UclkDpmChangeRange_t UclkDpmSrcFreqRange;
1092 UclkDpmChangeRange_t UclkDpmTargFreqRange;
1093 uint16_t UclkDpmMidstepFreq;
1094 uint16_t UclkMidstepPadding;
1095
1096
1097 uint8_t PcieGenSpeed[NUM_LINK_LEVELS];
1098 uint8_t PcieLaneCount[NUM_LINK_LEVELS];
1099 uint16_t LclkFreq[NUM_LINK_LEVELS];
1100
1101
1102 uint16_t FanStopTemp;
1103 uint16_t FanStartTemp;
1104
1105 uint16_t FanGain[TEMP_COUNT];
1106
1107 uint16_t FanPwmMin;
1108 uint16_t FanAcousticLimitRpm;
1109 uint16_t FanThrottlingRpm;
1110 uint16_t FanMaximumRpm;
1111 uint16_t MGpuFanBoostLimitRpm;
1112 uint16_t FanTargetTemperature;
1113 uint16_t FanTargetGfxclk;
1114 uint16_t FanPadding16;
1115 uint8_t FanTempInputSelect;
1116 uint8_t FanPadding;
1117 uint8_t FanZeroRpmEnable;
1118 uint8_t FanTachEdgePerRev;
1119
1120
1121 int16_t FuzzyFan_ErrorSetDelta;
1122 int16_t FuzzyFan_ErrorRateSetDelta;
1123 int16_t FuzzyFan_PwmSetDelta;
1124 uint16_t FuzzyFan_Reserved;
1125
1126
1127
1128 uint8_t OverrideAvfsGb[AVFS_VOLTAGE_COUNT];
1129 uint8_t dBtcGbGfxDfllModelSelect;
1130 uint8_t Padding8_Avfs;
1131
1132 QuadraticInt_t qAvfsGb[AVFS_VOLTAGE_COUNT];
1133 DroopInt_t dBtcGbGfxPll;
1134 DroopInt_t dBtcGbGfxDfll;
1135 DroopInt_t dBtcGbSoc;
1136 LinearInt_t qAgingGb[AVFS_VOLTAGE_COUNT];
1137
1138 PiecewiseLinearDroopInt_t PiecewiseLinearDroopIntGfxDfll;
1139
1140 QuadraticInt_t qStaticVoltageOffset[AVFS_VOLTAGE_COUNT];
1141
1142 uint16_t DcTol[AVFS_VOLTAGE_COUNT];
1143
1144 uint8_t DcBtcEnabled[AVFS_VOLTAGE_COUNT];
1145 uint8_t Padding8_GfxBtc[2];
1146
1147 uint16_t DcBtcMin[AVFS_VOLTAGE_COUNT];
1148 uint16_t DcBtcMax[AVFS_VOLTAGE_COUNT];
1149
1150 uint16_t DcBtcGb[AVFS_VOLTAGE_COUNT];
1151
1152
1153 uint8_t XgmiDpmPstates[NUM_XGMI_LEVELS];
1154 uint8_t XgmiDpmSpare[2];
1155
1156
1157 uint32_t DebugOverrides;
1158 QuadraticInt_t ReservedEquation0;
1159 QuadraticInt_t ReservedEquation1;
1160 QuadraticInt_t ReservedEquation2;
1161 QuadraticInt_t ReservedEquation3;
1162
1163
1164 uint8_t CustomerVariant;
1165
1166
1167 uint8_t VcBtcEnabled;
1168 uint16_t VcBtcVminT0;
1169 uint16_t VcBtcFixedVminAgingOffset;
1170 uint16_t VcBtcVmin2PsmDegrationGb;
1171 uint32_t VcBtcPsmA;
1172 uint32_t VcBtcPsmB;
1173 uint32_t VcBtcVminA;
1174 uint32_t VcBtcVminB;
1175
1176
1177 uint16_t LedGpio;
1178 uint16_t GfxPowerStagesGpio;
1179
1180 uint32_t SkuReserved[63];
1181
1182
1183
1184
1185
1186
1187 uint32_t GamingClk[6];
1188
1189
1190 I2cControllerConfig_t I2cControllers[NUM_I2C_CONTROLLERS];
1191
1192 uint8_t GpioScl;
1193 uint8_t GpioSda;
1194 uint8_t FchUsbPdSlaveAddr;
1195 uint8_t I2cSpare[1];
1196
1197
1198 uint8_t VddGfxVrMapping;
1199 uint8_t VddSocVrMapping;
1200 uint8_t VddMem0VrMapping;
1201 uint8_t VddMem1VrMapping;
1202
1203 uint8_t GfxUlvPhaseSheddingMask;
1204 uint8_t SocUlvPhaseSheddingMask;
1205 uint8_t VddciUlvPhaseSheddingMask;
1206 uint8_t MvddUlvPhaseSheddingMask;
1207
1208
1209 uint16_t GfxMaxCurrent;
1210 int8_t GfxOffset;
1211 uint8_t Padding_TelemetryGfx;
1212
1213 uint16_t SocMaxCurrent;
1214 int8_t SocOffset;
1215 uint8_t Padding_TelemetrySoc;
1216
1217 uint16_t Mem0MaxCurrent;
1218 int8_t Mem0Offset;
1219 uint8_t Padding_TelemetryMem0;
1220
1221 uint16_t Mem1MaxCurrent;
1222 int8_t Mem1Offset;
1223 uint8_t Padding_TelemetryMem1;
1224
1225 uint32_t MvddRatio;
1226
1227
1228 uint8_t AcDcGpio;
1229 uint8_t AcDcPolarity;
1230 uint8_t VR0HotGpio;
1231 uint8_t VR0HotPolarity;
1232
1233 uint8_t VR1HotGpio;
1234 uint8_t VR1HotPolarity;
1235 uint8_t GthrGpio;
1236 uint8_t GthrPolarity;
1237
1238
1239 uint8_t LedPin0;
1240 uint8_t LedPin1;
1241 uint8_t LedPin2;
1242 uint8_t LedEnableMask;
1243
1244 uint8_t LedPcie;
1245 uint8_t LedError;
1246 uint8_t LedSpare1[2];
1247
1248
1249
1250
1251 uint8_t PllGfxclkSpreadEnabled;
1252 uint8_t PllGfxclkSpreadPercent;
1253 uint16_t PllGfxclkSpreadFreq;
1254
1255
1256 uint8_t DfllGfxclkSpreadEnabled;
1257 uint8_t DfllGfxclkSpreadPercent;
1258 uint16_t DfllGfxclkSpreadFreq;
1259
1260
1261 uint16_t UclkSpreadPadding;
1262 uint16_t UclkSpreadFreq;
1263
1264
1265 uint8_t FclkSpreadEnabled;
1266 uint8_t FclkSpreadPercent;
1267 uint16_t FclkSpreadFreq;
1268
1269
1270 uint32_t MemoryChannelEnabled;
1271
1272 uint8_t DramBitWidth;
1273 uint8_t PaddingMem1[3];
1274
1275
1276 uint16_t TotalBoardPower;
1277 uint16_t BoardPowerPadding;
1278
1279
1280 uint8_t XgmiLinkSpeed [NUM_XGMI_PSTATE_LEVELS];
1281 uint8_t XgmiLinkWidth [NUM_XGMI_PSTATE_LEVELS];
1282
1283 uint16_t XgmiFclkFreq [NUM_XGMI_PSTATE_LEVELS];
1284 uint16_t XgmiSocVoltage [NUM_XGMI_PSTATE_LEVELS];
1285
1286
1287 uint8_t HsrEnabled;
1288 uint8_t VddqOffEnabled;
1289 uint8_t PaddingUmcFlags[2];
1290
1291
1292 uint8_t UclkSpreadPercent[16];
1293
1294
1295 uint32_t BoardReserved[11];
1296
1297
1298
1299
1300 uint32_t MmHubPadding[8];
1301
1302
1303} PPTable_beige_goby_t;
1304
1305typedef struct {
1306
1307 uint16_t GfxclkAverageLpfTau;
1308 uint16_t FclkAverageLpfTau;
1309 uint16_t UclkAverageLpfTau;
1310 uint16_t GfxActivityLpfTau;
1311 uint16_t UclkActivityLpfTau;
1312 uint16_t SocketPowerLpfTau;
1313 uint16_t VcnClkAverageLpfTau;
1314 uint16_t padding16;
1315} DriverSmuConfig_t;
1316
1317typedef struct {
1318 DriverSmuConfig_t DriverSmuConfig;
1319
1320 uint32_t Spare[7];
1321
1322 uint32_t MmHubPadding[8];
1323} DriverSmuConfigExternal_t;
1324
1325typedef struct {
1326 uint16_t GfxclkFmin;
1327 uint16_t GfxclkFmax;
1328 QuadraticInt_t CustomGfxVfCurve;
1329 uint16_t CustomCurveFmin;
1330 uint16_t UclkFmin;
1331 uint16_t UclkFmax;
1332 int16_t OverDrivePct;
1333 uint16_t FanMaximumRpm;
1334 uint16_t FanMinimumPwm;
1335 uint16_t FanAcousticLimitRpm;
1336 uint16_t FanTargetTemperature;
1337 uint8_t FanLinearPwmPoints[NUM_OD_FAN_MAX_POINTS];
1338 uint8_t FanLinearTempPoints[NUM_OD_FAN_MAX_POINTS];
1339 uint16_t MaxOpTemp;
1340 int16_t VddGfxOffset;
1341 uint8_t FanZeroRpmEnable;
1342 uint8_t FanZeroRpmStopTemp;
1343 uint8_t FanMode;
1344 uint8_t Padding[1];
1345} OverDriveTable_t;
1346
1347typedef struct {
1348 OverDriveTable_t OverDriveTable;
1349 uint32_t Spare[8];
1350
1351 uint32_t MmHubPadding[8];
1352} OverDriveTableExternal_t;
1353
1354typedef struct {
1355 uint32_t CurrClock[PPCLK_COUNT];
1356
1357 uint16_t AverageGfxclkFrequencyPreDs;
1358 uint16_t AverageGfxclkFrequencyPostDs;
1359 uint16_t AverageFclkFrequencyPreDs;
1360 uint16_t AverageFclkFrequencyPostDs;
1361 uint16_t AverageUclkFrequencyPreDs ;
1362 uint16_t AverageUclkFrequencyPostDs ;
1363
1364
1365 uint16_t AverageGfxActivity ;
1366 uint16_t AverageUclkActivity ;
1367 uint8_t CurrSocVoltageOffset ;
1368 uint8_t CurrGfxVoltageOffset ;
1369 uint8_t CurrMemVidOffset ;
1370 uint8_t Padding8 ;
1371 uint16_t AverageSocketPower ;
1372 uint16_t TemperatureEdge ;
1373 uint16_t TemperatureHotspot ;
1374 uint16_t TemperatureMem ;
1375 uint16_t TemperatureVrGfx ;
1376 uint16_t TemperatureVrMem0 ;
1377 uint16_t TemperatureVrMem1 ;
1378 uint16_t TemperatureVrSoc ;
1379 uint16_t TemperatureLiquid0 ;
1380 uint16_t TemperatureLiquid1 ;
1381 uint16_t TemperaturePlx ;
1382 uint16_t Padding16 ;
1383 uint32_t ThrottlerStatus ;
1384
1385 uint8_t LinkDpmLevel;
1386 uint8_t CurrFanPwm;
1387 uint16_t CurrFanSpeed;
1388
1389
1390
1391 uint8_t D3HotEntryCountPerMode[D3HOT_SEQUENCE_COUNT];
1392 uint8_t D3HotExitCountPerMode[D3HOT_SEQUENCE_COUNT];
1393 uint8_t ArmMsgReceivedCountPerMode[D3HOT_SEQUENCE_COUNT];
1394
1395
1396 uint32_t EnergyAccumulator;
1397 uint16_t AverageVclk0Frequency ;
1398 uint16_t AverageDclk0Frequency ;
1399 uint16_t AverageVclk1Frequency ;
1400 uint16_t AverageDclk1Frequency ;
1401 uint16_t VcnActivityPercentage ;
1402 uint8_t PcieRate ;
1403 uint8_t PcieWidth ;
1404 uint16_t AverageGfxclkFrequencyTarget;
1405 uint16_t Padding16_2;
1406
1407} SmuMetrics_t;
1408
1409typedef struct {
1410 uint32_t CurrClock[PPCLK_COUNT];
1411
1412 uint16_t AverageGfxclkFrequencyPreDs;
1413 uint16_t AverageGfxclkFrequencyPostDs;
1414 uint16_t AverageFclkFrequencyPreDs;
1415 uint16_t AverageFclkFrequencyPostDs;
1416 uint16_t AverageUclkFrequencyPreDs ;
1417 uint16_t AverageUclkFrequencyPostDs ;
1418
1419
1420 uint16_t AverageGfxActivity ;
1421 uint16_t AverageUclkActivity ;
1422 uint8_t CurrSocVoltageOffset ;
1423 uint8_t CurrGfxVoltageOffset ;
1424 uint8_t CurrMemVidOffset ;
1425 uint8_t Padding8 ;
1426 uint16_t AverageSocketPower ;
1427 uint16_t TemperatureEdge ;
1428 uint16_t TemperatureHotspot ;
1429 uint16_t TemperatureMem ;
1430 uint16_t TemperatureVrGfx ;
1431 uint16_t TemperatureVrMem0 ;
1432 uint16_t TemperatureVrMem1 ;
1433 uint16_t TemperatureVrSoc ;
1434 uint16_t TemperatureLiquid0 ;
1435 uint16_t TemperatureLiquid1 ;
1436 uint16_t TemperaturePlx ;
1437 uint16_t Padding16 ;
1438 uint32_t AccCnt ;
1439 uint8_t ThrottlingPercentage[THROTTLER_COUNT];
1440
1441
1442 uint8_t LinkDpmLevel;
1443 uint8_t CurrFanPwm;
1444 uint16_t CurrFanSpeed;
1445
1446
1447
1448 uint8_t D3HotEntryCountPerMode[D3HOT_SEQUENCE_COUNT];
1449 uint8_t D3HotExitCountPerMode[D3HOT_SEQUENCE_COUNT];
1450 uint8_t ArmMsgReceivedCountPerMode[D3HOT_SEQUENCE_COUNT];
1451
1452
1453 uint32_t EnergyAccumulator;
1454 uint16_t AverageVclk0Frequency ;
1455 uint16_t AverageDclk0Frequency ;
1456 uint16_t AverageVclk1Frequency ;
1457 uint16_t AverageDclk1Frequency ;
1458 uint16_t VcnActivityPercentage ;
1459 uint8_t PcieRate ;
1460 uint8_t PcieWidth ;
1461 uint16_t AverageGfxclkFrequencyTarget;
1462 uint16_t Padding16_2;
1463
1464} SmuMetrics_V2_t;
1465
1466typedef struct {
1467 union {
1468 SmuMetrics_t SmuMetrics;
1469 SmuMetrics_V2_t SmuMetrics_V2;
1470 };
1471 uint32_t Spare[1];
1472
1473
1474 uint32_t MmHubPadding[8];
1475} SmuMetricsExternal_t;
1476
1477typedef struct {
1478 uint16_t MinClock;
1479 uint16_t MaxClock;
1480 uint16_t MinUclk;
1481 uint16_t MaxUclk;
1482
1483 uint8_t WmSetting;
1484 uint8_t Flags;
1485 uint8_t Padding[2];
1486
1487} WatermarkRowGeneric_t;
1488
1489#define NUM_WM_RANGES 4
1490
1491typedef enum {
1492 WM_SOCCLK = 0,
1493 WM_DCEFCLK,
1494 WM_COUNT,
1495} WM_CLOCK_e;
1496
1497typedef enum {
1498 WATERMARKS_CLOCK_RANGE = 0,
1499 WATERMARKS_DUMMY_PSTATE,
1500 WATERMARKS_MALL,
1501 WATERMARKS_COUNT,
1502} WATERMARKS_FLAGS_e;
1503
1504typedef struct {
1505
1506 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
1507} Watermarks_t;
1508
1509typedef struct {
1510 Watermarks_t Watermarks;
1511
1512 uint32_t MmHubPadding[8];
1513} WatermarksExternal_t;
1514
1515typedef struct {
1516 uint16_t avgPsmCount[67];
1517 uint16_t minPsmCount[67];
1518 float avgPsmVoltage[67];
1519 float minPsmVoltage[67];
1520} AvfsDebugTable_t;
1521
1522typedef struct {
1523 AvfsDebugTable_t AvfsDebugTable;
1524
1525 uint32_t MmHubPadding[8];
1526} AvfsDebugTableExternal_t;
1527
1528typedef struct {
1529 uint8_t AvfsVersion;
1530 uint8_t Padding;
1531
1532 uint8_t AvfsEn[AVFS_VOLTAGE_COUNT];
1533
1534 uint8_t OverrideVFT[AVFS_VOLTAGE_COUNT];
1535 uint8_t OverrideAvfsGb[AVFS_VOLTAGE_COUNT];
1536
1537 uint8_t OverrideTemperatures[AVFS_VOLTAGE_COUNT];
1538 uint8_t OverrideVInversion[AVFS_VOLTAGE_COUNT];
1539 uint8_t OverrideP2V[AVFS_VOLTAGE_COUNT];
1540 uint8_t OverrideP2VCharzFreq[AVFS_VOLTAGE_COUNT];
1541
1542 int32_t VFT0_m1[AVFS_VOLTAGE_COUNT];
1543 int32_t VFT0_m2[AVFS_VOLTAGE_COUNT];
1544 int32_t VFT0_b[AVFS_VOLTAGE_COUNT];
1545
1546 int32_t VFT1_m1[AVFS_VOLTAGE_COUNT];
1547 int32_t VFT1_m2[AVFS_VOLTAGE_COUNT];
1548 int32_t VFT1_b[AVFS_VOLTAGE_COUNT];
1549
1550 int32_t VFT2_m1[AVFS_VOLTAGE_COUNT];
1551 int32_t VFT2_m2[AVFS_VOLTAGE_COUNT];
1552 int32_t VFT2_b[AVFS_VOLTAGE_COUNT];
1553
1554 int32_t AvfsGb0_m1[AVFS_VOLTAGE_COUNT];
1555 int32_t AvfsGb0_m2[AVFS_VOLTAGE_COUNT];
1556 int32_t AvfsGb0_b[AVFS_VOLTAGE_COUNT];
1557
1558 int32_t AcBtcGb_m1[AVFS_VOLTAGE_COUNT];
1559 int32_t AcBtcGb_m2[AVFS_VOLTAGE_COUNT];
1560 int32_t AcBtcGb_b[AVFS_VOLTAGE_COUNT];
1561
1562 uint32_t AvfsTempCold[AVFS_VOLTAGE_COUNT];
1563 uint32_t AvfsTempMid[AVFS_VOLTAGE_COUNT];
1564 uint32_t AvfsTempHot[AVFS_VOLTAGE_COUNT];
1565
1566 uint32_t VInversion[AVFS_VOLTAGE_COUNT];
1567
1568
1569 int32_t P2V_m1[AVFS_VOLTAGE_COUNT];
1570 int32_t P2V_m2[AVFS_VOLTAGE_COUNT];
1571 int32_t P2V_b[AVFS_VOLTAGE_COUNT];
1572
1573 uint32_t P2VCharzFreq[AVFS_VOLTAGE_COUNT];
1574
1575 uint32_t EnabledAvfsModules[3];
1576} AvfsFuseOverride_t;
1577
1578typedef struct {
1579 AvfsFuseOverride_t AvfsFuseOverride;
1580
1581 uint32_t MmHubPadding[8];
1582} AvfsFuseOverrideExternal_t;
1583
1584typedef struct {
1585 uint8_t Gfx_ActiveHystLimit;
1586 uint8_t Gfx_IdleHystLimit;
1587 uint8_t Gfx_FPS;
1588 uint8_t Gfx_MinActiveFreqType;
1589 uint8_t Gfx_BoosterFreqType;
1590 uint8_t Gfx_MinFreqStep;
1591 uint16_t Gfx_MinActiveFreq;
1592 uint16_t Gfx_BoosterFreq;
1593 uint16_t Gfx_PD_Data_time_constant;
1594 uint32_t Gfx_PD_Data_limit_a;
1595 uint32_t Gfx_PD_Data_limit_b;
1596 uint32_t Gfx_PD_Data_limit_c;
1597 uint32_t Gfx_PD_Data_error_coeff;
1598 uint32_t Gfx_PD_Data_error_rate_coeff;
1599
1600 uint8_t Fclk_ActiveHystLimit;
1601 uint8_t Fclk_IdleHystLimit;
1602 uint8_t Fclk_FPS;
1603 uint8_t Fclk_MinActiveFreqType;
1604 uint8_t Fclk_BoosterFreqType;
1605 uint8_t Fclk_MinFreqStep;
1606 uint16_t Fclk_MinActiveFreq;
1607 uint16_t Fclk_BoosterFreq;
1608 uint16_t Fclk_PD_Data_time_constant;
1609 uint32_t Fclk_PD_Data_limit_a;
1610 uint32_t Fclk_PD_Data_limit_b;
1611 uint32_t Fclk_PD_Data_limit_c;
1612 uint32_t Fclk_PD_Data_error_coeff;
1613 uint32_t Fclk_PD_Data_error_rate_coeff;
1614
1615 uint8_t Mem_ActiveHystLimit;
1616 uint8_t Mem_IdleHystLimit;
1617 uint8_t Mem_FPS;
1618 uint8_t Mem_MinActiveFreqType;
1619 uint8_t Mem_BoosterFreqType;
1620 uint8_t Mem_MinFreqStep;
1621 uint16_t Mem_MinActiveFreq;
1622 uint16_t Mem_BoosterFreq;
1623 uint16_t Mem_PD_Data_time_constant;
1624 uint32_t Mem_PD_Data_limit_a;
1625 uint32_t Mem_PD_Data_limit_b;
1626 uint32_t Mem_PD_Data_limit_c;
1627 uint32_t Mem_PD_Data_error_coeff;
1628 uint32_t Mem_PD_Data_error_rate_coeff;
1629
1630 uint32_t Mem_UpThreshold_Limit;
1631 uint8_t Mem_UpHystLimit;
1632 uint8_t Mem_DownHystLimit;
1633 uint16_t Mem_Fps;
1634
1635} DpmActivityMonitorCoeffInt_t;
1636
1637
1638typedef struct {
1639 DpmActivityMonitorCoeffInt_t DpmActivityMonitorCoeffInt;
1640 uint32_t MmHubPadding[8];
1641} DpmActivityMonitorCoeffIntExternal_t;
1642
1643
1644#define WORKLOAD_PPLIB_DEFAULT_BIT 0
1645#define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 1
1646#define WORKLOAD_PPLIB_POWER_SAVING_BIT 2
1647#define WORKLOAD_PPLIB_VIDEO_BIT 3
1648#define WORKLOAD_PPLIB_VR_BIT 4
1649#define WORKLOAD_PPLIB_COMPUTE_BIT 5
1650#define WORKLOAD_PPLIB_CUSTOM_BIT 6
1651#define WORKLOAD_PPLIB_W3D_BIT 7
1652#define WORKLOAD_PPLIB_COUNT 8
1653
1654
1655
1656
1657
1658
1659
1660#define TABLE_TRANSFER_OK 0x0
1661#define TABLE_TRANSFER_FAILED 0xFF
1662
1663
1664#define TABLE_PPTABLE 0
1665#define TABLE_WATERMARKS 1
1666#define TABLE_AVFS_PSM_DEBUG 2
1667#define TABLE_AVFS_FUSE_OVERRIDE 3
1668#define TABLE_PMSTATUSLOG 4
1669#define TABLE_SMU_METRICS 5
1670#define TABLE_DRIVER_SMU_CONFIG 6
1671#define TABLE_ACTIVITY_MONITOR_COEFF 7
1672#define TABLE_OVERDRIVE 8
1673#define TABLE_I2C_COMMANDS 9
1674#define TABLE_PACE 10
1675#define TABLE_COUNT 11
1676
1677typedef struct {
1678 float FlopsPerByteTable[RLC_PACE_TABLE_NUM_LEVELS];
1679} RlcPaceFlopsPerByteOverride_t;
1680
1681typedef struct {
1682 RlcPaceFlopsPerByteOverride_t RlcPaceFlopsPerByteOverride;
1683
1684 uint32_t MmHubPadding[8];
1685} RlcPaceFlopsPerByteOverrideExternal_t;
1686
1687
1688#define UCLK_SWITCH_SLOW 0
1689#define UCLK_SWITCH_FAST 1
1690#define UCLK_SWITCH_DUMMY 2
1691#endif
1692