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24#define SWSMU_CODE_LAYER_L2
25
26#include <linux/firmware.h>
27#include "amdgpu.h"
28#include "amdgpu_smu.h"
29#include "atomfirmware.h"
30#include "amdgpu_atomfirmware.h"
31#include "amdgpu_atombios.h"
32#include "smu_v13_0.h"
33#include "smu13_driver_if_aldebaran.h"
34#include "soc15_common.h"
35#include "atom.h"
36#include "power_state.h"
37#include "aldebaran_ppt.h"
38#include "smu_v13_0_pptable.h"
39#include "aldebaran_ppsmc.h"
40#include "nbio/nbio_7_4_offset.h"
41#include "nbio/nbio_7_4_sh_mask.h"
42#include "thm/thm_11_0_2_offset.h"
43#include "thm/thm_11_0_2_sh_mask.h"
44#include "amdgpu_xgmi.h"
45#include <linux/pci.h>
46#include "amdgpu_ras.h"
47#include "smu_cmn.h"
48#include "mp/mp_13_0_2_offset.h"
49
50
51
52
53
54
55#undef pr_err
56#undef pr_warn
57#undef pr_info
58#undef pr_debug
59
60#define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c))
61
62#define ALDEBARAN_FEA_MAP(smu_feature, aldebaran_feature) \
63 [smu_feature] = {1, (aldebaran_feature)}
64
65#define FEATURE_MASK(feature) (1ULL << feature)
66#define SMC_DPM_FEATURE ( \
67 FEATURE_MASK(FEATURE_DATA_CALCULATIONS) | \
68 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \
69 FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \
70 FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \
71 FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \
72 FEATURE_MASK(FEATURE_DPM_LCLK_BIT) | \
73 FEATURE_MASK(FEATURE_DPM_XGMI_BIT) | \
74 FEATURE_MASK(FEATURE_DPM_VCN_BIT))
75
76
77#define EPSILON 1
78
79#define smnPCIE_ESM_CTRL 0x111003D0
80
81
82
83
84
85#define SUPPORT_ECCTABLE_SMU_VERSION 0x00442a00
86
87static const struct smu_temperature_range smu13_thermal_policy[] =
88{
89 {-273150, 99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000},
90 { 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000},
91};
92
93static const struct cmn2asic_msg_mapping aldebaran_message_map[SMU_MSG_MAX_COUNT] = {
94 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 0),
95 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1),
96 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1),
97 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0),
98 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0),
99 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetEnabledSmuFeaturesLow, 1),
100 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetEnabledSmuFeaturesHigh, 1),
101 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1),
102 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1),
103 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0),
104 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0),
105 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1),
106 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0),
107 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0),
108 MSG_MAP(SetSystemVirtualDramAddrHigh, PPSMC_MSG_SetSystemVirtualDramAddrHigh, 0),
109 MSG_MAP(SetSystemVirtualDramAddrLow, PPSMC_MSG_SetSystemVirtualDramAddrLow, 0),
110 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 0),
111 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 0),
112 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 0),
113 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0),
114 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 0),
115 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 0),
116 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1),
117 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 1),
118 MSG_MAP(GetVoltageByDpm, PPSMC_MSG_GetVoltageByDpm, 0),
119 MSG_MAP(GetVoltageByDpmOverdrive, PPSMC_MSG_GetVoltageByDpmOverdrive, 0),
120 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0),
121 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 1),
122 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 0),
123 MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDriverReset, 0),
124 MSG_MAP(RunDcBtc, PPSMC_MSG_RunDcBtc, 0),
125 MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh, 0),
126 MSG_MAP(DramLogSetDramAddrLow, PPSMC_MSG_DramLogSetDramAddrLow, 0),
127 MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize, 0),
128 MSG_MAP(GetDebugData, PPSMC_MSG_GetDebugData, 0),
129 MSG_MAP(WaflTest, PPSMC_MSG_WaflTest, 0),
130 MSG_MAP(SetMemoryChannelEnable, PPSMC_MSG_SetMemoryChannelEnable, 0),
131 MSG_MAP(SetNumBadHbmPagesRetired, PPSMC_MSG_SetNumBadHbmPagesRetired, 0),
132 MSG_MAP(DFCstateControl, PPSMC_MSG_DFCstateControl, 0),
133 MSG_MAP(GetGmiPwrDnHyst, PPSMC_MSG_GetGmiPwrDnHyst, 0),
134 MSG_MAP(SetGmiPwrDnHyst, PPSMC_MSG_SetGmiPwrDnHyst, 0),
135 MSG_MAP(GmiPwrDnControl, PPSMC_MSG_GmiPwrDnControl, 0),
136 MSG_MAP(EnterGfxoff, PPSMC_MSG_EnterGfxoff, 0),
137 MSG_MAP(ExitGfxoff, PPSMC_MSG_ExitGfxoff, 0),
138 MSG_MAP(SetExecuteDMATest, PPSMC_MSG_SetExecuteDMATest, 0),
139 MSG_MAP(EnableDeterminism, PPSMC_MSG_EnableDeterminism, 0),
140 MSG_MAP(DisableDeterminism, PPSMC_MSG_DisableDeterminism, 0),
141 MSG_MAP(SetUclkDpmMode, PPSMC_MSG_SetUclkDpmMode, 0),
142 MSG_MAP(GfxDriverResetRecovery, PPSMC_MSG_GfxDriverResetRecovery, 0),
143 MSG_MAP(BoardPowerCalibration, PPSMC_MSG_BoardPowerCalibration, 0),
144 MSG_MAP(HeavySBR, PPSMC_MSG_HeavySBR, 0),
145};
146
147static const struct cmn2asic_mapping aldebaran_clk_map[SMU_CLK_COUNT] = {
148 CLK_MAP(GFXCLK, PPCLK_GFXCLK),
149 CLK_MAP(SCLK, PPCLK_GFXCLK),
150 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
151 CLK_MAP(FCLK, PPCLK_FCLK),
152 CLK_MAP(UCLK, PPCLK_UCLK),
153 CLK_MAP(MCLK, PPCLK_UCLK),
154 CLK_MAP(DCLK, PPCLK_DCLK),
155 CLK_MAP(VCLK, PPCLK_VCLK),
156 CLK_MAP(LCLK, PPCLK_LCLK),
157};
158
159static const struct cmn2asic_mapping aldebaran_feature_mask_map[SMU_FEATURE_COUNT] = {
160 ALDEBARAN_FEA_MAP(SMU_FEATURE_DATA_CALCULATIONS_BIT, FEATURE_DATA_CALCULATIONS),
161 ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_GFXCLK_BIT, FEATURE_DPM_GFXCLK_BIT),
162 ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_UCLK_BIT, FEATURE_DPM_UCLK_BIT),
163 ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_SOCCLK_BIT, FEATURE_DPM_SOCCLK_BIT),
164 ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_FCLK_BIT, FEATURE_DPM_FCLK_BIT),
165 ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_LCLK_BIT, FEATURE_DPM_LCLK_BIT),
166 ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_XGMI_BIT, FEATURE_DPM_XGMI_BIT),
167 ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_GFXCLK_BIT, FEATURE_DS_GFXCLK_BIT),
168 ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_SOCCLK_BIT, FEATURE_DS_SOCCLK_BIT),
169 ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_LCLK_BIT, FEATURE_DS_LCLK_BIT),
170 ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_FCLK_BIT, FEATURE_DS_FCLK_BIT),
171 ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_UCLK_BIT, FEATURE_DS_UCLK_BIT),
172 ALDEBARAN_FEA_MAP(SMU_FEATURE_GFX_SS_BIT, FEATURE_GFX_SS_BIT),
173 ALDEBARAN_FEA_MAP(SMU_FEATURE_VCN_DPM_BIT, FEATURE_DPM_VCN_BIT),
174 ALDEBARAN_FEA_MAP(SMU_FEATURE_RSMU_SMN_CG_BIT, FEATURE_RSMU_SMN_CG_BIT),
175 ALDEBARAN_FEA_MAP(SMU_FEATURE_WAFL_CG_BIT, FEATURE_WAFL_CG_BIT),
176 ALDEBARAN_FEA_MAP(SMU_FEATURE_PPT_BIT, FEATURE_PPT_BIT),
177 ALDEBARAN_FEA_MAP(SMU_FEATURE_TDC_BIT, FEATURE_TDC_BIT),
178 ALDEBARAN_FEA_MAP(SMU_FEATURE_APCC_PLUS_BIT, FEATURE_APCC_PLUS_BIT),
179 ALDEBARAN_FEA_MAP(SMU_FEATURE_APCC_DFLL_BIT, FEATURE_APCC_DFLL_BIT),
180 ALDEBARAN_FEA_MAP(SMU_FEATURE_FUSE_CG_BIT, FEATURE_FUSE_CG_BIT),
181 ALDEBARAN_FEA_MAP(SMU_FEATURE_MP1_CG_BIT, FEATURE_MP1_CG_BIT),
182 ALDEBARAN_FEA_MAP(SMU_FEATURE_SMUIO_CG_BIT, FEATURE_SMUIO_CG_BIT),
183 ALDEBARAN_FEA_MAP(SMU_FEATURE_THM_CG_BIT, FEATURE_THM_CG_BIT),
184 ALDEBARAN_FEA_MAP(SMU_FEATURE_CLK_CG_BIT, FEATURE_CLK_CG_BIT),
185 ALDEBARAN_FEA_MAP(SMU_FEATURE_FW_CTF_BIT, FEATURE_FW_CTF_BIT),
186 ALDEBARAN_FEA_MAP(SMU_FEATURE_THERMAL_BIT, FEATURE_THERMAL_BIT),
187 ALDEBARAN_FEA_MAP(SMU_FEATURE_OUT_OF_BAND_MONITOR_BIT, FEATURE_OUT_OF_BAND_MONITOR_BIT),
188 ALDEBARAN_FEA_MAP(SMU_FEATURE_XGMI_PER_LINK_PWR_DWN_BIT,FEATURE_XGMI_PER_LINK_PWR_DWN),
189 ALDEBARAN_FEA_MAP(SMU_FEATURE_DF_CSTATE_BIT, FEATURE_DF_CSTATE),
190};
191
192static const struct cmn2asic_mapping aldebaran_table_map[SMU_TABLE_COUNT] = {
193 TAB_MAP(PPTABLE),
194 TAB_MAP(AVFS_PSM_DEBUG),
195 TAB_MAP(AVFS_FUSE_OVERRIDE),
196 TAB_MAP(PMSTATUSLOG),
197 TAB_MAP(SMU_METRICS),
198 TAB_MAP(DRIVER_SMU_CONFIG),
199 TAB_MAP(I2C_COMMANDS),
200 TAB_MAP(ECCINFO),
201};
202
203static const uint8_t aldebaran_throttler_map[] = {
204 [THROTTLER_PPT0_BIT] = (SMU_THROTTLER_PPT0_BIT),
205 [THROTTLER_PPT1_BIT] = (SMU_THROTTLER_PPT1_BIT),
206 [THROTTLER_TDC_GFX_BIT] = (SMU_THROTTLER_TDC_GFX_BIT),
207 [THROTTLER_TDC_SOC_BIT] = (SMU_THROTTLER_TDC_SOC_BIT),
208 [THROTTLER_TDC_HBM_BIT] = (SMU_THROTTLER_TDC_MEM_BIT),
209 [THROTTLER_TEMP_GPU_BIT] = (SMU_THROTTLER_TEMP_GPU_BIT),
210 [THROTTLER_TEMP_MEM_BIT] = (SMU_THROTTLER_TEMP_MEM_BIT),
211 [THROTTLER_TEMP_VR_GFX_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
212 [THROTTLER_TEMP_VR_SOC_BIT] = (SMU_THROTTLER_TEMP_VR_SOC_BIT),
213 [THROTTLER_TEMP_VR_MEM_BIT] = (SMU_THROTTLER_TEMP_VR_MEM0_BIT),
214 [THROTTLER_APCC_BIT] = (SMU_THROTTLER_APCC_BIT),
215};
216
217static int aldebaran_tables_init(struct smu_context *smu)
218{
219 struct smu_table_context *smu_table = &smu->smu_table;
220 struct smu_table *tables = smu_table->tables;
221
222 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
223 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
224
225 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU13_TOOL_SIZE,
226 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
227
228 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
229 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
230
231 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
232 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
233
234 SMU_TABLE_INIT(tables, SMU_TABLE_ECCINFO, sizeof(EccInfoTable_t),
235 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
236
237 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
238 if (!smu_table->metrics_table)
239 return -ENOMEM;
240 smu_table->metrics_time = 0;
241
242 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3);
243 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
244 if (!smu_table->gpu_metrics_table) {
245 kfree(smu_table->metrics_table);
246 return -ENOMEM;
247 }
248
249 smu_table->ecc_table = kzalloc(tables[SMU_TABLE_ECCINFO].size, GFP_KERNEL);
250 if (!smu_table->ecc_table)
251 return -ENOMEM;
252
253 return 0;
254}
255
256static int aldebaran_allocate_dpm_context(struct smu_context *smu)
257{
258 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
259
260 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_13_0_dpm_context),
261 GFP_KERNEL);
262 if (!smu_dpm->dpm_context)
263 return -ENOMEM;
264 smu_dpm->dpm_context_size = sizeof(struct smu_13_0_dpm_context);
265
266 return 0;
267}
268
269static int aldebaran_init_smc_tables(struct smu_context *smu)
270{
271 int ret = 0;
272
273 ret = aldebaran_tables_init(smu);
274 if (ret)
275 return ret;
276
277 ret = aldebaran_allocate_dpm_context(smu);
278 if (ret)
279 return ret;
280
281 return smu_v13_0_init_smc_tables(smu);
282}
283
284static int aldebaran_get_allowed_feature_mask(struct smu_context *smu,
285 uint32_t *feature_mask, uint32_t num)
286{
287 if (num > 2)
288 return -EINVAL;
289
290
291 memset(feature_mask, 0xFF, sizeof(uint32_t) * num);
292
293 return 0;
294}
295
296static int aldebaran_set_default_dpm_table(struct smu_context *smu)
297{
298 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
299 struct smu_13_0_dpm_table *dpm_table = NULL;
300 PPTable_t *pptable = smu->smu_table.driver_pptable;
301 int ret = 0;
302
303
304 dpm_table = &dpm_context->dpm_tables.soc_table;
305 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
306 ret = smu_v13_0_set_single_dpm_table(smu,
307 SMU_SOCCLK,
308 dpm_table);
309 if (ret)
310 return ret;
311 } else {
312 dpm_table->count = 1;
313 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
314 dpm_table->dpm_levels[0].enabled = true;
315 dpm_table->min = dpm_table->dpm_levels[0].value;
316 dpm_table->max = dpm_table->dpm_levels[0].value;
317 }
318
319
320 dpm_table = &dpm_context->dpm_tables.gfx_table;
321 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
322
323 dpm_table->count = 2;
324 dpm_table->dpm_levels[0].value = pptable->GfxclkFmin;
325 dpm_table->dpm_levels[0].enabled = true;
326 dpm_table->dpm_levels[1].value = pptable->GfxclkFmax;
327 dpm_table->dpm_levels[1].enabled = true;
328 dpm_table->min = dpm_table->dpm_levels[0].value;
329 dpm_table->max = dpm_table->dpm_levels[1].value;
330 } else {
331 dpm_table->count = 1;
332 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
333 dpm_table->dpm_levels[0].enabled = true;
334 dpm_table->min = dpm_table->dpm_levels[0].value;
335 dpm_table->max = dpm_table->dpm_levels[0].value;
336 }
337
338
339 dpm_table = &dpm_context->dpm_tables.uclk_table;
340 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
341 ret = smu_v13_0_set_single_dpm_table(smu,
342 SMU_UCLK,
343 dpm_table);
344 if (ret)
345 return ret;
346 } else {
347 dpm_table->count = 1;
348 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
349 dpm_table->dpm_levels[0].enabled = true;
350 dpm_table->min = dpm_table->dpm_levels[0].value;
351 dpm_table->max = dpm_table->dpm_levels[0].value;
352 }
353
354
355 dpm_table = &dpm_context->dpm_tables.fclk_table;
356 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
357 ret = smu_v13_0_set_single_dpm_table(smu,
358 SMU_FCLK,
359 dpm_table);
360 if (ret)
361 return ret;
362 } else {
363 dpm_table->count = 1;
364 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
365 dpm_table->dpm_levels[0].enabled = true;
366 dpm_table->min = dpm_table->dpm_levels[0].value;
367 dpm_table->max = dpm_table->dpm_levels[0].value;
368 }
369
370 return 0;
371}
372
373static int aldebaran_check_powerplay_table(struct smu_context *smu)
374{
375 struct smu_table_context *table_context = &smu->smu_table;
376 struct smu_13_0_powerplay_table *powerplay_table =
377 table_context->power_play_table;
378
379 table_context->thermal_controller_type =
380 powerplay_table->thermal_controller_type;
381
382 return 0;
383}
384
385static int aldebaran_store_powerplay_table(struct smu_context *smu)
386{
387 struct smu_table_context *table_context = &smu->smu_table;
388 struct smu_13_0_powerplay_table *powerplay_table =
389 table_context->power_play_table;
390 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
391 sizeof(PPTable_t));
392
393 return 0;
394}
395
396static int aldebaran_append_powerplay_table(struct smu_context *smu)
397{
398 struct smu_table_context *table_context = &smu->smu_table;
399 PPTable_t *smc_pptable = table_context->driver_pptable;
400 struct atom_smc_dpm_info_v4_10 *smc_dpm_table;
401 int index, ret;
402
403 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
404 smc_dpm_info);
405
406 ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL,
407 (uint8_t **)&smc_dpm_table);
408 if (ret)
409 return ret;
410
411 dev_info(smu->adev->dev, "smc_dpm_info table revision(format.content): %d.%d\n",
412 smc_dpm_table->table_header.format_revision,
413 smc_dpm_table->table_header.content_revision);
414
415 if ((smc_dpm_table->table_header.format_revision == 4) &&
416 (smc_dpm_table->table_header.content_revision == 10))
417 smu_memcpy_trailing(smc_pptable, GfxMaxCurrent, reserved,
418 smc_dpm_table, GfxMaxCurrent);
419 return 0;
420}
421
422static int aldebaran_setup_pptable(struct smu_context *smu)
423{
424 int ret = 0;
425
426
427 smu->smu_table.boot_values.pp_table_id = 0;
428
429 ret = smu_v13_0_setup_pptable(smu);
430 if (ret)
431 return ret;
432
433 ret = aldebaran_store_powerplay_table(smu);
434 if (ret)
435 return ret;
436
437 ret = aldebaran_append_powerplay_table(smu);
438 if (ret)
439 return ret;
440
441 ret = aldebaran_check_powerplay_table(smu);
442 if (ret)
443 return ret;
444
445 return ret;
446}
447
448static bool aldebaran_is_primary(struct smu_context *smu)
449{
450 struct amdgpu_device *adev = smu->adev;
451
452 if (adev->smuio.funcs && adev->smuio.funcs->get_die_id)
453 return adev->smuio.funcs->get_die_id(adev) == 0;
454
455 return true;
456}
457
458static int aldebaran_run_board_btc(struct smu_context *smu)
459{
460 u32 smu_version;
461 int ret;
462
463 if (!aldebaran_is_primary(smu))
464 return 0;
465
466 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
467 if (ret) {
468 dev_err(smu->adev->dev, "Failed to get smu version!\n");
469 return ret;
470 }
471 if (smu_version <= 0x00441d00)
472 return 0;
473
474 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_BoardPowerCalibration, NULL);
475 if (ret)
476 dev_err(smu->adev->dev, "Board power calibration failed!\n");
477
478 return ret;
479}
480
481static int aldebaran_run_btc(struct smu_context *smu)
482{
483 int ret;
484
485 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
486 if (ret)
487 dev_err(smu->adev->dev, "RunDcBtc failed!\n");
488 else
489 ret = aldebaran_run_board_btc(smu);
490
491 return ret;
492}
493
494static int aldebaran_populate_umd_state_clk(struct smu_context *smu)
495{
496 struct smu_13_0_dpm_context *dpm_context =
497 smu->smu_dpm.dpm_context;
498 struct smu_13_0_dpm_table *gfx_table =
499 &dpm_context->dpm_tables.gfx_table;
500 struct smu_13_0_dpm_table *mem_table =
501 &dpm_context->dpm_tables.uclk_table;
502 struct smu_13_0_dpm_table *soc_table =
503 &dpm_context->dpm_tables.soc_table;
504 struct smu_umd_pstate_table *pstate_table =
505 &smu->pstate_table;
506
507 pstate_table->gfxclk_pstate.min = gfx_table->min;
508 pstate_table->gfxclk_pstate.peak = gfx_table->max;
509 pstate_table->gfxclk_pstate.curr.min = gfx_table->min;
510 pstate_table->gfxclk_pstate.curr.max = gfx_table->max;
511
512 pstate_table->uclk_pstate.min = mem_table->min;
513 pstate_table->uclk_pstate.peak = mem_table->max;
514 pstate_table->uclk_pstate.curr.min = mem_table->min;
515 pstate_table->uclk_pstate.curr.max = mem_table->max;
516
517 pstate_table->socclk_pstate.min = soc_table->min;
518 pstate_table->socclk_pstate.peak = soc_table->max;
519 pstate_table->socclk_pstate.curr.min = soc_table->min;
520 pstate_table->socclk_pstate.curr.max = soc_table->max;
521
522 if (gfx_table->count > ALDEBARAN_UMD_PSTATE_GFXCLK_LEVEL &&
523 mem_table->count > ALDEBARAN_UMD_PSTATE_MCLK_LEVEL &&
524 soc_table->count > ALDEBARAN_UMD_PSTATE_SOCCLK_LEVEL) {
525 pstate_table->gfxclk_pstate.standard =
526 gfx_table->dpm_levels[ALDEBARAN_UMD_PSTATE_GFXCLK_LEVEL].value;
527 pstate_table->uclk_pstate.standard =
528 mem_table->dpm_levels[ALDEBARAN_UMD_PSTATE_MCLK_LEVEL].value;
529 pstate_table->socclk_pstate.standard =
530 soc_table->dpm_levels[ALDEBARAN_UMD_PSTATE_SOCCLK_LEVEL].value;
531 } else {
532 pstate_table->gfxclk_pstate.standard =
533 pstate_table->gfxclk_pstate.min;
534 pstate_table->uclk_pstate.standard =
535 pstate_table->uclk_pstate.min;
536 pstate_table->socclk_pstate.standard =
537 pstate_table->socclk_pstate.min;
538 }
539
540 return 0;
541}
542
543static int aldebaran_get_clk_table(struct smu_context *smu,
544 struct pp_clock_levels_with_latency *clocks,
545 struct smu_13_0_dpm_table *dpm_table)
546{
547 int i, count;
548
549 count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
550 clocks->num_levels = count;
551
552 for (i = 0; i < count; i++) {
553 clocks->data[i].clocks_in_khz =
554 dpm_table->dpm_levels[i].value * 1000;
555 clocks->data[i].latency_in_us = 0;
556 }
557
558 return 0;
559}
560
561static int aldebaran_freqs_in_same_level(int32_t frequency1,
562 int32_t frequency2)
563{
564 return (abs(frequency1 - frequency2) <= EPSILON);
565}
566
567static int aldebaran_get_smu_metrics_data(struct smu_context *smu,
568 MetricsMember_t member,
569 uint32_t *value)
570{
571 struct smu_table_context *smu_table= &smu->smu_table;
572 SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table;
573 int ret = 0;
574
575 mutex_lock(&smu->metrics_lock);
576
577 ret = smu_cmn_get_metrics_table_locked(smu,
578 NULL,
579 false);
580 if (ret) {
581 mutex_unlock(&smu->metrics_lock);
582 return ret;
583 }
584
585 switch (member) {
586 case METRICS_CURR_GFXCLK:
587 *value = metrics->CurrClock[PPCLK_GFXCLK];
588 break;
589 case METRICS_CURR_SOCCLK:
590 *value = metrics->CurrClock[PPCLK_SOCCLK];
591 break;
592 case METRICS_CURR_UCLK:
593 *value = metrics->CurrClock[PPCLK_UCLK];
594 break;
595 case METRICS_CURR_VCLK:
596 *value = metrics->CurrClock[PPCLK_VCLK];
597 break;
598 case METRICS_CURR_DCLK:
599 *value = metrics->CurrClock[PPCLK_DCLK];
600 break;
601 case METRICS_CURR_FCLK:
602 *value = metrics->CurrClock[PPCLK_FCLK];
603 break;
604 case METRICS_AVERAGE_GFXCLK:
605 *value = metrics->AverageGfxclkFrequency;
606 break;
607 case METRICS_AVERAGE_SOCCLK:
608 *value = metrics->AverageSocclkFrequency;
609 break;
610 case METRICS_AVERAGE_UCLK:
611 *value = metrics->AverageUclkFrequency;
612 break;
613 case METRICS_AVERAGE_GFXACTIVITY:
614 *value = metrics->AverageGfxActivity;
615 break;
616 case METRICS_AVERAGE_MEMACTIVITY:
617 *value = metrics->AverageUclkActivity;
618 break;
619 case METRICS_AVERAGE_SOCKETPOWER:
620
621 *value = aldebaran_is_primary(smu) ?
622 metrics->AverageSocketPower << 8 :
623 0;
624 break;
625 case METRICS_TEMPERATURE_EDGE:
626 *value = metrics->TemperatureEdge *
627 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
628 break;
629 case METRICS_TEMPERATURE_HOTSPOT:
630 *value = metrics->TemperatureHotspot *
631 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
632 break;
633 case METRICS_TEMPERATURE_MEM:
634 *value = metrics->TemperatureHBM *
635 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
636 break;
637 case METRICS_TEMPERATURE_VRGFX:
638 *value = metrics->TemperatureVrGfx *
639 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
640 break;
641 case METRICS_TEMPERATURE_VRSOC:
642 *value = metrics->TemperatureVrSoc *
643 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
644 break;
645 case METRICS_TEMPERATURE_VRMEM:
646 *value = metrics->TemperatureVrMem *
647 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
648 break;
649 case METRICS_THROTTLER_STATUS:
650 *value = metrics->ThrottlerStatus;
651 break;
652 default:
653 *value = UINT_MAX;
654 break;
655 }
656
657 mutex_unlock(&smu->metrics_lock);
658
659 return ret;
660}
661
662static int aldebaran_get_current_clk_freq_by_table(struct smu_context *smu,
663 enum smu_clk_type clk_type,
664 uint32_t *value)
665{
666 MetricsMember_t member_type;
667 int clk_id = 0;
668
669 if (!value)
670 return -EINVAL;
671
672 clk_id = smu_cmn_to_asic_specific_index(smu,
673 CMN2ASIC_MAPPING_CLK,
674 clk_type);
675 if (clk_id < 0)
676 return -EINVAL;
677
678 switch (clk_id) {
679 case PPCLK_GFXCLK:
680
681
682
683
684
685
686 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT))
687 member_type = METRICS_CURR_GFXCLK;
688 else
689 member_type = METRICS_AVERAGE_GFXCLK;
690 break;
691 case PPCLK_UCLK:
692 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT))
693 member_type = METRICS_CURR_UCLK;
694 else
695 member_type = METRICS_AVERAGE_UCLK;
696 break;
697 case PPCLK_SOCCLK:
698 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT))
699 member_type = METRICS_CURR_SOCCLK;
700 else
701 member_type = METRICS_AVERAGE_SOCCLK;
702 break;
703 case PPCLK_VCLK:
704 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT))
705 member_type = METRICS_CURR_VCLK;
706 else
707 member_type = METRICS_AVERAGE_VCLK;
708 break;
709 case PPCLK_DCLK:
710 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT))
711 member_type = METRICS_CURR_DCLK;
712 else
713 member_type = METRICS_AVERAGE_DCLK;
714 break;
715 case PPCLK_FCLK:
716 member_type = METRICS_CURR_FCLK;
717 break;
718 default:
719 return -EINVAL;
720 }
721
722 return aldebaran_get_smu_metrics_data(smu,
723 member_type,
724 value);
725}
726
727static int aldebaran_print_clk_levels(struct smu_context *smu,
728 enum smu_clk_type type, char *buf)
729{
730 int i, now, size = 0;
731 int ret = 0;
732 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
733 struct pp_clock_levels_with_latency clocks;
734 struct smu_13_0_dpm_table *single_dpm_table;
735 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
736 struct smu_13_0_dpm_context *dpm_context = NULL;
737 uint32_t display_levels;
738 uint32_t freq_values[3] = {0};
739 uint32_t min_clk, max_clk;
740
741 smu_cmn_get_sysfs_buf(&buf, &size);
742
743 if (amdgpu_ras_intr_triggered()) {
744 size += sysfs_emit_at(buf, size, "unavailable\n");
745 return size;
746 }
747
748 dpm_context = smu_dpm->dpm_context;
749
750 switch (type) {
751
752 case SMU_OD_SCLK:
753 size += sysfs_emit_at(buf, size, "%s:\n", "GFXCLK");
754 fallthrough;
755 case SMU_SCLK:
756 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_GFXCLK, &now);
757 if (ret) {
758 dev_err(smu->adev->dev, "Attempt to get current gfx clk Failed!");
759 return ret;
760 }
761
762 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
763 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table);
764 if (ret) {
765 dev_err(smu->adev->dev, "Attempt to get gfx clk levels Failed!");
766 return ret;
767 }
768
769 display_levels = clocks.num_levels;
770
771 min_clk = pstate_table->gfxclk_pstate.curr.min;
772 max_clk = pstate_table->gfxclk_pstate.curr.max;
773
774 freq_values[0] = min_clk;
775 freq_values[1] = max_clk;
776
777
778 if (now > min_clk && now < max_clk) {
779 display_levels = clocks.num_levels + 1;
780 freq_values[2] = max_clk;
781 freq_values[1] = now;
782 }
783
784
785
786
787
788 if (display_levels == clocks.num_levels) {
789 for (i = 0; i < clocks.num_levels; i++)
790 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i,
791 freq_values[i],
792 (clocks.num_levels == 1) ?
793 "*" :
794 (aldebaran_freqs_in_same_level(
795 freq_values[i], now) ?
796 "*" :
797 ""));
798 } else {
799 for (i = 0; i < display_levels; i++)
800 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i,
801 freq_values[i], i == 1 ? "*" : "");
802 }
803
804 break;
805
806 case SMU_OD_MCLK:
807 size += sysfs_emit_at(buf, size, "%s:\n", "MCLK");
808 fallthrough;
809 case SMU_MCLK:
810 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_UCLK, &now);
811 if (ret) {
812 dev_err(smu->adev->dev, "Attempt to get current mclk Failed!");
813 return ret;
814 }
815
816 single_dpm_table = &(dpm_context->dpm_tables.uclk_table);
817 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table);
818 if (ret) {
819 dev_err(smu->adev->dev, "Attempt to get memory clk levels Failed!");
820 return ret;
821 }
822
823 for (i = 0; i < clocks.num_levels; i++)
824 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
825 i, clocks.data[i].clocks_in_khz / 1000,
826 (clocks.num_levels == 1) ? "*" :
827 (aldebaran_freqs_in_same_level(
828 clocks.data[i].clocks_in_khz / 1000,
829 now) ? "*" : ""));
830 break;
831
832 case SMU_SOCCLK:
833 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_SOCCLK, &now);
834 if (ret) {
835 dev_err(smu->adev->dev, "Attempt to get current socclk Failed!");
836 return ret;
837 }
838
839 single_dpm_table = &(dpm_context->dpm_tables.soc_table);
840 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table);
841 if (ret) {
842 dev_err(smu->adev->dev, "Attempt to get socclk levels Failed!");
843 return ret;
844 }
845
846 for (i = 0; i < clocks.num_levels; i++)
847 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
848 i, clocks.data[i].clocks_in_khz / 1000,
849 (clocks.num_levels == 1) ? "*" :
850 (aldebaran_freqs_in_same_level(
851 clocks.data[i].clocks_in_khz / 1000,
852 now) ? "*" : ""));
853 break;
854
855 case SMU_FCLK:
856 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_FCLK, &now);
857 if (ret) {
858 dev_err(smu->adev->dev, "Attempt to get current fclk Failed!");
859 return ret;
860 }
861
862 single_dpm_table = &(dpm_context->dpm_tables.fclk_table);
863 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table);
864 if (ret) {
865 dev_err(smu->adev->dev, "Attempt to get fclk levels Failed!");
866 return ret;
867 }
868
869 for (i = 0; i < single_dpm_table->count; i++)
870 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
871 i, single_dpm_table->dpm_levels[i].value,
872 (clocks.num_levels == 1) ? "*" :
873 (aldebaran_freqs_in_same_level(
874 clocks.data[i].clocks_in_khz / 1000,
875 now) ? "*" : ""));
876 break;
877
878 case SMU_VCLK:
879 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_VCLK, &now);
880 if (ret) {
881 dev_err(smu->adev->dev, "Attempt to get current vclk Failed!");
882 return ret;
883 }
884
885 single_dpm_table = &(dpm_context->dpm_tables.vclk_table);
886 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table);
887 if (ret) {
888 dev_err(smu->adev->dev, "Attempt to get vclk levels Failed!");
889 return ret;
890 }
891
892 for (i = 0; i < single_dpm_table->count; i++)
893 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
894 i, single_dpm_table->dpm_levels[i].value,
895 (clocks.num_levels == 1) ? "*" :
896 (aldebaran_freqs_in_same_level(
897 clocks.data[i].clocks_in_khz / 1000,
898 now) ? "*" : ""));
899 break;
900
901 case SMU_DCLK:
902 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_DCLK, &now);
903 if (ret) {
904 dev_err(smu->adev->dev, "Attempt to get current dclk Failed!");
905 return ret;
906 }
907
908 single_dpm_table = &(dpm_context->dpm_tables.dclk_table);
909 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table);
910 if (ret) {
911 dev_err(smu->adev->dev, "Attempt to get dclk levels Failed!");
912 return ret;
913 }
914
915 for (i = 0; i < single_dpm_table->count; i++)
916 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
917 i, single_dpm_table->dpm_levels[i].value,
918 (clocks.num_levels == 1) ? "*" :
919 (aldebaran_freqs_in_same_level(
920 clocks.data[i].clocks_in_khz / 1000,
921 now) ? "*" : ""));
922 break;
923
924 default:
925 break;
926 }
927
928 return size;
929}
930
931static int aldebaran_upload_dpm_level(struct smu_context *smu,
932 bool max,
933 uint32_t feature_mask,
934 uint32_t level)
935{
936 struct smu_13_0_dpm_context *dpm_context =
937 smu->smu_dpm.dpm_context;
938 uint32_t freq;
939 int ret = 0;
940
941 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
942 (feature_mask & FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT))) {
943 freq = dpm_context->dpm_tables.gfx_table.dpm_levels[level].value;
944 ret = smu_cmn_send_smc_msg_with_param(smu,
945 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
946 (PPCLK_GFXCLK << 16) | (freq & 0xffff),
947 NULL);
948 if (ret) {
949 dev_err(smu->adev->dev, "Failed to set soft %s gfxclk !\n",
950 max ? "max" : "min");
951 return ret;
952 }
953 }
954
955 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
956 (feature_mask & FEATURE_MASK(FEATURE_DPM_UCLK_BIT))) {
957 freq = dpm_context->dpm_tables.uclk_table.dpm_levels[level].value;
958 ret = smu_cmn_send_smc_msg_with_param(smu,
959 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
960 (PPCLK_UCLK << 16) | (freq & 0xffff),
961 NULL);
962 if (ret) {
963 dev_err(smu->adev->dev, "Failed to set soft %s memclk !\n",
964 max ? "max" : "min");
965 return ret;
966 }
967 }
968
969 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) &&
970 (feature_mask & FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT))) {
971 freq = dpm_context->dpm_tables.soc_table.dpm_levels[level].value;
972 ret = smu_cmn_send_smc_msg_with_param(smu,
973 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
974 (PPCLK_SOCCLK << 16) | (freq & 0xffff),
975 NULL);
976 if (ret) {
977 dev_err(smu->adev->dev, "Failed to set soft %s socclk !\n",
978 max ? "max" : "min");
979 return ret;
980 }
981 }
982
983 return ret;
984}
985
986static int aldebaran_force_clk_levels(struct smu_context *smu,
987 enum smu_clk_type type, uint32_t mask)
988{
989 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
990 struct smu_13_0_dpm_table *single_dpm_table = NULL;
991 uint32_t soft_min_level, soft_max_level;
992 int ret = 0;
993
994 soft_min_level = mask ? (ffs(mask) - 1) : 0;
995 soft_max_level = mask ? (fls(mask) - 1) : 0;
996
997 switch (type) {
998 case SMU_SCLK:
999 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
1000 if (soft_max_level >= single_dpm_table->count) {
1001 dev_err(smu->adev->dev, "Clock level specified %d is over max allowed %d\n",
1002 soft_max_level, single_dpm_table->count - 1);
1003 ret = -EINVAL;
1004 break;
1005 }
1006
1007 ret = aldebaran_upload_dpm_level(smu,
1008 false,
1009 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT),
1010 soft_min_level);
1011 if (ret) {
1012 dev_err(smu->adev->dev, "Failed to upload boot level to lowest!\n");
1013 break;
1014 }
1015
1016 ret = aldebaran_upload_dpm_level(smu,
1017 true,
1018 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT),
1019 soft_max_level);
1020 if (ret)
1021 dev_err(smu->adev->dev, "Failed to upload dpm max level to highest!\n");
1022
1023 break;
1024
1025 case SMU_MCLK:
1026 case SMU_SOCCLK:
1027 case SMU_FCLK:
1028
1029
1030
1031
1032 ret = -EINVAL;
1033 break;
1034
1035 default:
1036 break;
1037 }
1038
1039 return ret;
1040}
1041
1042static int aldebaran_get_thermal_temperature_range(struct smu_context *smu,
1043 struct smu_temperature_range *range)
1044{
1045 struct smu_table_context *table_context = &smu->smu_table;
1046 struct smu_13_0_powerplay_table *powerplay_table =
1047 table_context->power_play_table;
1048 PPTable_t *pptable = smu->smu_table.driver_pptable;
1049
1050 if (!range)
1051 return -EINVAL;
1052
1053 memcpy(range, &smu13_thermal_policy[0], sizeof(struct smu_temperature_range));
1054
1055 range->hotspot_crit_max = pptable->ThotspotLimit *
1056 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1057 range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
1058 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1059 range->mem_crit_max = pptable->TmemLimit *
1060 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1061 range->mem_emergency_max = (pptable->TmemLimit + CTF_OFFSET_MEM)*
1062 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1063 range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
1064
1065 return 0;
1066}
1067
1068static int aldebaran_get_current_activity_percent(struct smu_context *smu,
1069 enum amd_pp_sensors sensor,
1070 uint32_t *value)
1071{
1072 int ret = 0;
1073
1074 if (!value)
1075 return -EINVAL;
1076
1077 switch (sensor) {
1078 case AMDGPU_PP_SENSOR_GPU_LOAD:
1079 ret = aldebaran_get_smu_metrics_data(smu,
1080 METRICS_AVERAGE_GFXACTIVITY,
1081 value);
1082 break;
1083 case AMDGPU_PP_SENSOR_MEM_LOAD:
1084 ret = aldebaran_get_smu_metrics_data(smu,
1085 METRICS_AVERAGE_MEMACTIVITY,
1086 value);
1087 break;
1088 default:
1089 dev_err(smu->adev->dev, "Invalid sensor for retrieving clock activity\n");
1090 return -EINVAL;
1091 }
1092
1093 return ret;
1094}
1095
1096static int aldebaran_get_gpu_power(struct smu_context *smu, uint32_t *value)
1097{
1098 if (!value)
1099 return -EINVAL;
1100
1101 return aldebaran_get_smu_metrics_data(smu,
1102 METRICS_AVERAGE_SOCKETPOWER,
1103 value);
1104}
1105
1106static int aldebaran_thermal_get_temperature(struct smu_context *smu,
1107 enum amd_pp_sensors sensor,
1108 uint32_t *value)
1109{
1110 int ret = 0;
1111
1112 if (!value)
1113 return -EINVAL;
1114
1115 switch (sensor) {
1116 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1117 ret = aldebaran_get_smu_metrics_data(smu,
1118 METRICS_TEMPERATURE_HOTSPOT,
1119 value);
1120 break;
1121 case AMDGPU_PP_SENSOR_EDGE_TEMP:
1122 ret = aldebaran_get_smu_metrics_data(smu,
1123 METRICS_TEMPERATURE_EDGE,
1124 value);
1125 break;
1126 case AMDGPU_PP_SENSOR_MEM_TEMP:
1127 ret = aldebaran_get_smu_metrics_data(smu,
1128 METRICS_TEMPERATURE_MEM,
1129 value);
1130 break;
1131 default:
1132 dev_err(smu->adev->dev, "Invalid sensor for retrieving temp\n");
1133 return -EINVAL;
1134 }
1135
1136 return ret;
1137}
1138
1139static int aldebaran_read_sensor(struct smu_context *smu,
1140 enum amd_pp_sensors sensor,
1141 void *data, uint32_t *size)
1142{
1143 int ret = 0;
1144
1145 if (amdgpu_ras_intr_triggered())
1146 return 0;
1147
1148 if (!data || !size)
1149 return -EINVAL;
1150
1151 mutex_lock(&smu->sensor_lock);
1152 switch (sensor) {
1153 case AMDGPU_PP_SENSOR_MEM_LOAD:
1154 case AMDGPU_PP_SENSOR_GPU_LOAD:
1155 ret = aldebaran_get_current_activity_percent(smu,
1156 sensor,
1157 (uint32_t *)data);
1158 *size = 4;
1159 break;
1160 case AMDGPU_PP_SENSOR_GPU_POWER:
1161 ret = aldebaran_get_gpu_power(smu, (uint32_t *)data);
1162 *size = 4;
1163 break;
1164 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1165 case AMDGPU_PP_SENSOR_EDGE_TEMP:
1166 case AMDGPU_PP_SENSOR_MEM_TEMP:
1167 ret = aldebaran_thermal_get_temperature(smu, sensor,
1168 (uint32_t *)data);
1169 *size = 4;
1170 break;
1171 case AMDGPU_PP_SENSOR_GFX_MCLK:
1172 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data);
1173
1174 *(uint32_t *)data *= 100;
1175 *size = 4;
1176 break;
1177 case AMDGPU_PP_SENSOR_GFX_SCLK:
1178 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data);
1179 *(uint32_t *)data *= 100;
1180 *size = 4;
1181 break;
1182 case AMDGPU_PP_SENSOR_VDDGFX:
1183 ret = smu_v13_0_get_gfx_vdd(smu, (uint32_t *)data);
1184 *size = 4;
1185 break;
1186 default:
1187 ret = -EOPNOTSUPP;
1188 break;
1189 }
1190 mutex_unlock(&smu->sensor_lock);
1191
1192 return ret;
1193}
1194
1195static int aldebaran_get_power_limit(struct smu_context *smu,
1196 uint32_t *current_power_limit,
1197 uint32_t *default_power_limit,
1198 uint32_t *max_power_limit)
1199{
1200 PPTable_t *pptable = smu->smu_table.driver_pptable;
1201 uint32_t power_limit = 0;
1202 int ret;
1203
1204 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
1205 if (current_power_limit)
1206 *current_power_limit = 0;
1207 if (default_power_limit)
1208 *default_power_limit = 0;
1209 if (max_power_limit)
1210 *max_power_limit = 0;
1211
1212 dev_warn(smu->adev->dev,
1213 "PPT feature is not enabled, power values can't be fetched.");
1214
1215 return 0;
1216 }
1217
1218
1219
1220
1221 if (aldebaran_is_primary(smu)) {
1222 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetPptLimit,
1223 &power_limit);
1224
1225 if (ret) {
1226
1227 if (!pptable) {
1228 dev_err(smu->adev->dev,
1229 "Cannot get PPT limit due to pptable missing!");
1230 return -EINVAL;
1231 }
1232 power_limit = pptable->PptLimit;
1233 }
1234 }
1235
1236 if (current_power_limit)
1237 *current_power_limit = power_limit;
1238 if (default_power_limit)
1239 *default_power_limit = power_limit;
1240
1241 if (max_power_limit) {
1242 if (pptable)
1243 *max_power_limit = pptable->PptLimit;
1244 }
1245
1246 return 0;
1247}
1248
1249static int aldebaran_set_power_limit(struct smu_context *smu,
1250 enum smu_ppt_limit_type limit_type,
1251 uint32_t limit)
1252{
1253
1254 if (aldebaran_is_primary(smu))
1255 return smu_v13_0_set_power_limit(smu, limit_type, limit);
1256
1257 return -EINVAL;
1258}
1259
1260static int aldebaran_system_features_control(struct smu_context *smu, bool enable)
1261{
1262 int ret;
1263
1264 ret = smu_v13_0_system_features_control(smu, enable);
1265 if (!ret && enable)
1266 ret = aldebaran_run_btc(smu);
1267
1268 return ret;
1269}
1270
1271static int aldebaran_set_performance_level(struct smu_context *smu,
1272 enum amd_dpm_forced_level level)
1273{
1274 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
1275 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1276 struct smu_13_0_dpm_table *gfx_table =
1277 &dpm_context->dpm_tables.gfx_table;
1278 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
1279
1280
1281 if ((smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) &&
1282 (level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)) {
1283 smu_cmn_send_smc_msg(smu, SMU_MSG_DisableDeterminism, NULL);
1284 pstate_table->gfxclk_pstate.curr.max = gfx_table->max;
1285 }
1286
1287 switch (level) {
1288
1289 case AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM:
1290 return 0;
1291
1292 case AMD_DPM_FORCED_LEVEL_HIGH:
1293 case AMD_DPM_FORCED_LEVEL_LOW:
1294 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1295 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1296 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1297 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1298 default:
1299 break;
1300 }
1301
1302 return smu_v13_0_set_performance_level(smu, level);
1303}
1304
1305static int aldebaran_set_soft_freq_limited_range(struct smu_context *smu,
1306 enum smu_clk_type clk_type,
1307 uint32_t min,
1308 uint32_t max)
1309{
1310 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
1311 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1312 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
1313 struct amdgpu_device *adev = smu->adev;
1314 uint32_t min_clk;
1315 uint32_t max_clk;
1316 int ret = 0;
1317
1318 if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK)
1319 return -EINVAL;
1320
1321 if ((smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
1322 && (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM))
1323 return -EINVAL;
1324
1325 if (smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
1326 if (min >= max) {
1327 dev_err(smu->adev->dev,
1328 "Minimum GFX clk should be less than the maximum allowed clock\n");
1329 return -EINVAL;
1330 }
1331
1332 if ((min == pstate_table->gfxclk_pstate.curr.min) &&
1333 (max == pstate_table->gfxclk_pstate.curr.max))
1334 return 0;
1335
1336 ret = smu_v13_0_set_soft_freq_limited_range(smu, SMU_GFXCLK,
1337 min, max);
1338 if (!ret) {
1339 pstate_table->gfxclk_pstate.curr.min = min;
1340 pstate_table->gfxclk_pstate.curr.max = max;
1341 }
1342
1343 return ret;
1344 }
1345
1346 if (smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) {
1347 if (!max || (max < dpm_context->dpm_tables.gfx_table.min) ||
1348 (max > dpm_context->dpm_tables.gfx_table.max)) {
1349 dev_warn(adev->dev,
1350 "Invalid max frequency %d MHz specified for determinism\n", max);
1351 return -EINVAL;
1352 }
1353
1354
1355 min_clk = dpm_context->dpm_tables.gfx_table.min;
1356 max_clk = dpm_context->dpm_tables.gfx_table.max;
1357 ret = smu_v13_0_set_soft_freq_limited_range(smu, SMU_GFXCLK, min_clk, max_clk);
1358 if (!ret) {
1359 usleep_range(500, 1000);
1360 ret = smu_cmn_send_smc_msg_with_param(smu,
1361 SMU_MSG_EnableDeterminism,
1362 max, NULL);
1363 if (ret) {
1364 dev_err(adev->dev,
1365 "Failed to enable determinism at GFX clock %d MHz\n", max);
1366 } else {
1367 pstate_table->gfxclk_pstate.curr.min = min_clk;
1368 pstate_table->gfxclk_pstate.curr.max = max;
1369 }
1370 }
1371 }
1372
1373 return ret;
1374}
1375
1376static int aldebaran_usr_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type,
1377 long input[], uint32_t size)
1378{
1379 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
1380 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1381 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
1382 uint32_t min_clk;
1383 uint32_t max_clk;
1384 int ret = 0;
1385
1386
1387 if ((smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
1388 && (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM))
1389 return -EINVAL;
1390
1391 switch (type) {
1392 case PP_OD_EDIT_SCLK_VDDC_TABLE:
1393 if (size != 2) {
1394 dev_err(smu->adev->dev, "Input parameter number not correct\n");
1395 return -EINVAL;
1396 }
1397
1398 if (input[0] == 0) {
1399 if (input[1] < dpm_context->dpm_tables.gfx_table.min) {
1400 dev_warn(smu->adev->dev, "Minimum GFX clk (%ld) MHz specified is less than the minimum allowed (%d) MHz\n",
1401 input[1], dpm_context->dpm_tables.gfx_table.min);
1402 pstate_table->gfxclk_pstate.custom.min =
1403 pstate_table->gfxclk_pstate.curr.min;
1404 return -EINVAL;
1405 }
1406
1407 pstate_table->gfxclk_pstate.custom.min = input[1];
1408 } else if (input[0] == 1) {
1409 if (input[1] > dpm_context->dpm_tables.gfx_table.max) {
1410 dev_warn(smu->adev->dev, "Maximum GFX clk (%ld) MHz specified is greater than the maximum allowed (%d) MHz\n",
1411 input[1], dpm_context->dpm_tables.gfx_table.max);
1412 pstate_table->gfxclk_pstate.custom.max =
1413 pstate_table->gfxclk_pstate.curr.max;
1414 return -EINVAL;
1415 }
1416
1417 pstate_table->gfxclk_pstate.custom.max = input[1];
1418 } else {
1419 return -EINVAL;
1420 }
1421 break;
1422 case PP_OD_RESTORE_DEFAULT_TABLE:
1423 if (size != 0) {
1424 dev_err(smu->adev->dev, "Input parameter number not correct\n");
1425 return -EINVAL;
1426 } else {
1427
1428 min_clk = dpm_context->dpm_tables.gfx_table.min;
1429 max_clk = dpm_context->dpm_tables.gfx_table.max;
1430
1431 return aldebaran_set_soft_freq_limited_range(smu, SMU_GFXCLK, min_clk, max_clk);
1432 }
1433 break;
1434 case PP_OD_COMMIT_DPM_TABLE:
1435 if (size != 0) {
1436 dev_err(smu->adev->dev, "Input parameter number not correct\n");
1437 return -EINVAL;
1438 } else {
1439 if (!pstate_table->gfxclk_pstate.custom.min)
1440 pstate_table->gfxclk_pstate.custom.min =
1441 pstate_table->gfxclk_pstate.curr.min;
1442
1443 if (!pstate_table->gfxclk_pstate.custom.max)
1444 pstate_table->gfxclk_pstate.custom.max =
1445 pstate_table->gfxclk_pstate.curr.max;
1446
1447 min_clk = pstate_table->gfxclk_pstate.custom.min;
1448 max_clk = pstate_table->gfxclk_pstate.custom.max;
1449
1450 return aldebaran_set_soft_freq_limited_range(smu, SMU_GFXCLK, min_clk, max_clk);
1451 }
1452 break;
1453 default:
1454 return -ENOSYS;
1455 }
1456
1457 return ret;
1458}
1459
1460static bool aldebaran_is_dpm_running(struct smu_context *smu)
1461{
1462 int ret;
1463 uint32_t feature_mask[2];
1464 unsigned long feature_enabled;
1465
1466 ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
1467 if (ret)
1468 return false;
1469 feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
1470 ((uint64_t)feature_mask[1] << 32));
1471 return !!(feature_enabled & SMC_DPM_FEATURE);
1472}
1473
1474static int aldebaran_i2c_xfer(struct i2c_adapter *i2c_adap,
1475 struct i2c_msg *msg, int num_msgs)
1476{
1477 struct amdgpu_device *adev = to_amdgpu_device(i2c_adap);
1478 struct smu_table_context *smu_table = &adev->smu.smu_table;
1479 struct smu_table *table = &smu_table->driver_table;
1480 SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr;
1481 int i, j, r, c;
1482 u16 dir;
1483
1484 req = kzalloc(sizeof(*req), GFP_KERNEL);
1485 if (!req)
1486 return -ENOMEM;
1487
1488 req->I2CcontrollerPort = 0;
1489 req->I2CSpeed = I2C_SPEED_FAST_400K;
1490 req->SlaveAddress = msg[0].addr << 1;
1491 dir = msg[0].flags & I2C_M_RD;
1492
1493 for (c = i = 0; i < num_msgs; i++) {
1494 for (j = 0; j < msg[i].len; j++, c++) {
1495 SwI2cCmd_t *cmd = &req->SwI2cCmds[c];
1496
1497 if (!(msg[i].flags & I2C_M_RD)) {
1498
1499 cmd->CmdConfig |= CMDCONFIG_READWRITE_MASK;
1500 cmd->ReadWriteData = msg[i].buf[j];
1501 }
1502
1503 if ((dir ^ msg[i].flags) & I2C_M_RD) {
1504
1505
1506 dir = msg[i].flags & I2C_M_RD;
1507 cmd->CmdConfig |= CMDCONFIG_RESTART_MASK;
1508 }
1509
1510 req->NumCmds++;
1511
1512
1513
1514
1515
1516
1517 if ((j == msg[i].len - 1) &&
1518 ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) {
1519 cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK;
1520 cmd->CmdConfig |= CMDCONFIG_STOP_MASK;
1521 }
1522 }
1523 }
1524 mutex_lock(&adev->smu.mutex);
1525 r = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, req, true);
1526 mutex_unlock(&adev->smu.mutex);
1527 if (r)
1528 goto fail;
1529
1530 for (c = i = 0; i < num_msgs; i++) {
1531 if (!(msg[i].flags & I2C_M_RD)) {
1532 c += msg[i].len;
1533 continue;
1534 }
1535 for (j = 0; j < msg[i].len; j++, c++) {
1536 SwI2cCmd_t *cmd = &res->SwI2cCmds[c];
1537
1538 msg[i].buf[j] = cmd->ReadWriteData;
1539 }
1540 }
1541 r = num_msgs;
1542fail:
1543 kfree(req);
1544 return r;
1545}
1546
1547static u32 aldebaran_i2c_func(struct i2c_adapter *adap)
1548{
1549 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
1550}
1551
1552
1553static const struct i2c_algorithm aldebaran_i2c_algo = {
1554 .master_xfer = aldebaran_i2c_xfer,
1555 .functionality = aldebaran_i2c_func,
1556};
1557
1558static const struct i2c_adapter_quirks aldebaran_i2c_control_quirks = {
1559 .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN,
1560 .max_read_len = MAX_SW_I2C_COMMANDS,
1561 .max_write_len = MAX_SW_I2C_COMMANDS,
1562 .max_comb_1st_msg_len = 2,
1563 .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2,
1564};
1565
1566static int aldebaran_i2c_control_init(struct smu_context *smu, struct i2c_adapter *control)
1567{
1568 struct amdgpu_device *adev = to_amdgpu_device(control);
1569 int res;
1570
1571 control->owner = THIS_MODULE;
1572 control->class = I2C_CLASS_SPD;
1573 control->dev.parent = &adev->pdev->dev;
1574 control->algo = &aldebaran_i2c_algo;
1575 snprintf(control->name, sizeof(control->name), "AMDGPU SMU");
1576 control->quirks = &aldebaran_i2c_control_quirks;
1577
1578 res = i2c_add_adapter(control);
1579 if (res)
1580 DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
1581
1582 return res;
1583}
1584
1585static void aldebaran_i2c_control_fini(struct smu_context *smu, struct i2c_adapter *control)
1586{
1587 i2c_del_adapter(control);
1588}
1589
1590static void aldebaran_get_unique_id(struct smu_context *smu)
1591{
1592 struct amdgpu_device *adev = smu->adev;
1593 SmuMetrics_t *metrics = smu->smu_table.metrics_table;
1594 uint32_t upper32 = 0, lower32 = 0;
1595 int ret;
1596
1597 mutex_lock(&smu->metrics_lock);
1598 ret = smu_cmn_get_metrics_table_locked(smu, NULL, false);
1599 if (ret)
1600 goto out_unlock;
1601
1602 upper32 = metrics->PublicSerialNumUpper32;
1603 lower32 = metrics->PublicSerialNumLower32;
1604
1605out_unlock:
1606 mutex_unlock(&smu->metrics_lock);
1607
1608 adev->unique_id = ((uint64_t)upper32 << 32) | lower32;
1609 if (adev->serial[0] == '\0')
1610 sprintf(adev->serial, "%016llx", adev->unique_id);
1611}
1612
1613static bool aldebaran_is_baco_supported(struct smu_context *smu)
1614{
1615
1616
1617 return false;
1618}
1619
1620static int aldebaran_set_df_cstate(struct smu_context *smu,
1621 enum pp_df_cstate state)
1622{
1623 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DFCstateControl, state, NULL);
1624}
1625
1626static int aldebaran_allow_xgmi_power_down(struct smu_context *smu, bool en)
1627{
1628 struct amdgpu_device *adev = smu->adev;
1629
1630
1631
1632 if (!adev->smuio.funcs->get_socket_id(adev) &&
1633 !adev->smuio.funcs->get_die_id(adev))
1634 return smu_cmn_send_smc_msg_with_param(smu,
1635 SMU_MSG_GmiPwrDnControl,
1636 en ? 0 : 1,
1637 NULL);
1638 else
1639 return 0;
1640}
1641
1642static const struct throttling_logging_label {
1643 uint32_t feature_mask;
1644 const char *label;
1645} logging_label[] = {
1646 {(1U << THROTTLER_TEMP_MEM_BIT), "HBM"},
1647 {(1U << THROTTLER_TEMP_VR_GFX_BIT), "VR of GFX rail"},
1648 {(1U << THROTTLER_TEMP_VR_MEM_BIT), "VR of HBM rail"},
1649 {(1U << THROTTLER_TEMP_VR_SOC_BIT), "VR of SOC rail"},
1650};
1651static void aldebaran_log_thermal_throttling_event(struct smu_context *smu)
1652{
1653 int ret;
1654 int throttler_idx, throtting_events = 0, buf_idx = 0;
1655 struct amdgpu_device *adev = smu->adev;
1656 uint32_t throttler_status;
1657 char log_buf[256];
1658
1659 ret = aldebaran_get_smu_metrics_data(smu,
1660 METRICS_THROTTLER_STATUS,
1661 &throttler_status);
1662 if (ret)
1663 return;
1664
1665 memset(log_buf, 0, sizeof(log_buf));
1666 for (throttler_idx = 0; throttler_idx < ARRAY_SIZE(logging_label);
1667 throttler_idx++) {
1668 if (throttler_status & logging_label[throttler_idx].feature_mask) {
1669 throtting_events++;
1670 buf_idx += snprintf(log_buf + buf_idx,
1671 sizeof(log_buf) - buf_idx,
1672 "%s%s",
1673 throtting_events > 1 ? " and " : "",
1674 logging_label[throttler_idx].label);
1675 if (buf_idx >= sizeof(log_buf)) {
1676 dev_err(adev->dev, "buffer overflow!\n");
1677 log_buf[sizeof(log_buf) - 1] = '\0';
1678 break;
1679 }
1680 }
1681 }
1682
1683 dev_warn(adev->dev, "WARN: GPU thermal throttling temperature reached, expect performance decrease. %s.\n",
1684 log_buf);
1685 kgd2kfd_smi_event_throttle(smu->adev->kfd.dev,
1686 smu_cmn_get_indep_throttler_status(throttler_status,
1687 aldebaran_throttler_map));
1688}
1689
1690static int aldebaran_get_current_pcie_link_speed(struct smu_context *smu)
1691{
1692 struct amdgpu_device *adev = smu->adev;
1693 uint32_t esm_ctrl;
1694
1695
1696 esm_ctrl = RREG32_PCIE(smnPCIE_ESM_CTRL);
1697 if ((esm_ctrl >> 15) & 0x1FFFF)
1698 return (((esm_ctrl >> 8) & 0x3F) + 128);
1699
1700 return smu_v13_0_get_current_pcie_link_speed(smu);
1701}
1702
1703static ssize_t aldebaran_get_gpu_metrics(struct smu_context *smu,
1704 void **table)
1705{
1706 struct smu_table_context *smu_table = &smu->smu_table;
1707 struct gpu_metrics_v1_3 *gpu_metrics =
1708 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
1709 SmuMetrics_t metrics;
1710 int i, ret = 0;
1711
1712 ret = smu_cmn_get_metrics_table(smu,
1713 &metrics,
1714 true);
1715 if (ret)
1716 return ret;
1717
1718 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
1719
1720 gpu_metrics->temperature_edge = metrics.TemperatureEdge;
1721 gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
1722 gpu_metrics->temperature_mem = metrics.TemperatureHBM;
1723 gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx;
1724 gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc;
1725 gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem;
1726
1727 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
1728 gpu_metrics->average_umc_activity = metrics.AverageUclkActivity;
1729 gpu_metrics->average_mm_activity = 0;
1730
1731
1732 if (aldebaran_is_primary(smu)) {
1733 gpu_metrics->average_socket_power = metrics.AverageSocketPower;
1734 gpu_metrics->energy_accumulator =
1735 (uint64_t)metrics.EnergyAcc64bitHigh << 32 |
1736 metrics.EnergyAcc64bitLow;
1737 } else {
1738 gpu_metrics->average_socket_power = 0;
1739 gpu_metrics->energy_accumulator = 0;
1740 }
1741
1742 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency;
1743 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency;
1744 gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency;
1745 gpu_metrics->average_vclk0_frequency = 0;
1746 gpu_metrics->average_dclk0_frequency = 0;
1747
1748 gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK];
1749 gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK];
1750 gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];
1751 gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK];
1752 gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
1753
1754 gpu_metrics->throttle_status = metrics.ThrottlerStatus;
1755 gpu_metrics->indep_throttle_status =
1756 smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
1757 aldebaran_throttler_map);
1758
1759 gpu_metrics->current_fan_speed = 0;
1760
1761 gpu_metrics->pcie_link_width =
1762 smu_v13_0_get_current_pcie_link_width(smu);
1763 gpu_metrics->pcie_link_speed =
1764 aldebaran_get_current_pcie_link_speed(smu);
1765
1766 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
1767
1768 gpu_metrics->gfx_activity_acc = metrics.GfxBusyAcc;
1769 gpu_metrics->mem_activity_acc = metrics.DramBusyAcc;
1770
1771 for (i = 0; i < NUM_HBM_INSTANCES; i++)
1772 gpu_metrics->temperature_hbm[i] = metrics.TemperatureAllHBM[i];
1773
1774 gpu_metrics->firmware_timestamp = ((uint64_t)metrics.TimeStampHigh << 32) |
1775 metrics.TimeStampLow;
1776
1777 *table = (void *)gpu_metrics;
1778
1779 return sizeof(struct gpu_metrics_v1_3);
1780}
1781
1782static int aldebaran_check_ecc_table_support(struct smu_context *smu)
1783{
1784 uint32_t if_version = 0xff, smu_version = 0xff;
1785 int ret = 0;
1786
1787 ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version);
1788 if (ret) {
1789
1790 ret = -EOPNOTSUPP;
1791 }
1792
1793 if (smu_version < SUPPORT_ECCTABLE_SMU_VERSION)
1794 ret = -EOPNOTSUPP;
1795
1796 return ret;
1797}
1798
1799static ssize_t aldebaran_get_ecc_info(struct smu_context *smu,
1800 void *table)
1801{
1802 struct smu_table_context *smu_table = &smu->smu_table;
1803 EccInfoTable_t *ecc_table = NULL;
1804 struct ecc_info_per_ch *ecc_info_per_channel = NULL;
1805 int i, ret = 0;
1806 struct umc_ecc_info *eccinfo = (struct umc_ecc_info *)table;
1807
1808 ret = aldebaran_check_ecc_table_support(smu);
1809 if (ret)
1810 return ret;
1811
1812 ret = smu_cmn_update_table(smu,
1813 SMU_TABLE_ECCINFO,
1814 0,
1815 smu_table->ecc_table,
1816 false);
1817 if (ret) {
1818 dev_info(smu->adev->dev, "Failed to export SMU ecc table!\n");
1819 return ret;
1820 }
1821
1822 ecc_table = (EccInfoTable_t *)smu_table->ecc_table;
1823
1824 for (i = 0; i < ALDEBARAN_UMC_CHANNEL_NUM; i++) {
1825 ecc_info_per_channel = &(eccinfo->ecc[i]);
1826 ecc_info_per_channel->ce_count_lo_chip =
1827 ecc_table->EccInfo[i].ce_count_lo_chip;
1828 ecc_info_per_channel->ce_count_hi_chip =
1829 ecc_table->EccInfo[i].ce_count_hi_chip;
1830 ecc_info_per_channel->mca_umc_status =
1831 ecc_table->EccInfo[i].mca_umc_status;
1832 ecc_info_per_channel->mca_umc_addr =
1833 ecc_table->EccInfo[i].mca_umc_addr;
1834 }
1835
1836 return ret;
1837}
1838
1839static int aldebaran_mode1_reset(struct smu_context *smu)
1840{
1841 u32 smu_version, fatal_err, param;
1842 int ret = 0;
1843 struct amdgpu_device *adev = smu->adev;
1844 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1845
1846 fatal_err = 0;
1847 param = SMU_RESET_MODE_1;
1848
1849
1850
1851
1852 smu_cmn_get_smc_version(smu, NULL, &smu_version);
1853 if (smu_version < 0x00440700) {
1854 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode1Reset, NULL);
1855 }
1856 else {
1857
1858
1859 if ((smu_version >= 0x00442c00) && ras &&
1860 atomic_read(&ras->in_recovery))
1861 fatal_err = 1;
1862
1863 param |= (fatal_err << 16);
1864 ret = smu_cmn_send_smc_msg_with_param(smu,
1865 SMU_MSG_GfxDeviceDriverReset, param, NULL);
1866 }
1867
1868 if (!ret)
1869 msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS);
1870
1871 return ret;
1872}
1873
1874static int aldebaran_mode2_reset(struct smu_context *smu)
1875{
1876 u32 smu_version;
1877 int ret = 0, index;
1878 struct amdgpu_device *adev = smu->adev;
1879 int timeout = 10;
1880
1881 smu_cmn_get_smc_version(smu, NULL, &smu_version);
1882
1883 index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG,
1884 SMU_MSG_GfxDeviceDriverReset);
1885
1886 mutex_lock(&smu->message_lock);
1887 if (smu_version >= 0x00441400) {
1888 ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index, SMU_RESET_MODE_2);
1889
1890 msleep(100);
1891 dev_dbg(smu->adev->dev, "restore config space...\n");
1892
1893 amdgpu_device_load_pci_state(adev->pdev);
1894
1895 dev_dbg(smu->adev->dev, "wait for reset ack\n");
1896 while (ret == -ETIME && timeout) {
1897 ret = smu_cmn_wait_for_response(smu);
1898
1899 if (ret == -ETIME) {
1900 --timeout;
1901 usleep_range(500, 1000);
1902 continue;
1903 }
1904
1905 if (ret != 1) {
1906 dev_err(adev->dev, "failed to send mode2 message \tparam: 0x%08x response %#x\n",
1907 SMU_RESET_MODE_2, ret);
1908 goto out;
1909 }
1910 }
1911
1912 } else {
1913 dev_err(adev->dev, "smu fw 0x%x does not support MSG_GfxDeviceDriverReset MSG\n",
1914 smu_version);
1915 }
1916
1917 if (ret == 1)
1918 ret = 0;
1919out:
1920 mutex_unlock(&smu->message_lock);
1921
1922 return ret;
1923}
1924
1925static int aldebaran_smu_handle_passthrough_sbr(struct smu_context *smu, bool enable)
1926{
1927 int ret = 0;
1928 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_HeavySBR, enable ? 1 : 0, NULL);
1929
1930 return ret;
1931}
1932
1933static bool aldebaran_is_mode1_reset_supported(struct smu_context *smu)
1934{
1935#if 0
1936 struct amdgpu_device *adev = smu->adev;
1937 u32 smu_version;
1938 uint32_t val;
1939
1940
1941
1942 smu_cmn_get_smc_version(smu, NULL, &smu_version);
1943 if ((smu_version < 0x00440700))
1944 return false;
1945
1946
1947
1948
1949 val = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);
1950
1951 return val != 0x0;
1952#endif
1953 return true;
1954}
1955
1956static bool aldebaran_is_mode2_reset_supported(struct smu_context *smu)
1957{
1958 return true;
1959}
1960
1961static int aldebaran_set_mp1_state(struct smu_context *smu,
1962 enum pp_mp1_state mp1_state)
1963{
1964 switch (mp1_state) {
1965 case PP_MP1_STATE_UNLOAD:
1966 return smu_cmn_set_mp1_state(smu, mp1_state);
1967 default:
1968 return 0;
1969 }
1970}
1971
1972static int aldebaran_smu_send_hbm_bad_page_num(struct smu_context *smu,
1973 uint32_t size)
1974{
1975 int ret = 0;
1976
1977
1978 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetNumBadHbmPagesRetired, size, NULL);
1979 if (ret)
1980 dev_err(smu->adev->dev, "[%s] failed to message SMU to update HBM bad pages number\n",
1981 __func__);
1982
1983 return ret;
1984}
1985
1986static const struct pptable_funcs aldebaran_ppt_funcs = {
1987
1988 .get_allowed_feature_mask = aldebaran_get_allowed_feature_mask,
1989
1990 .set_default_dpm_table = aldebaran_set_default_dpm_table,
1991 .populate_umd_state_clk = aldebaran_populate_umd_state_clk,
1992 .get_thermal_temperature_range = aldebaran_get_thermal_temperature_range,
1993 .print_clk_levels = aldebaran_print_clk_levels,
1994 .force_clk_levels = aldebaran_force_clk_levels,
1995 .read_sensor = aldebaran_read_sensor,
1996 .set_performance_level = aldebaran_set_performance_level,
1997 .get_power_limit = aldebaran_get_power_limit,
1998 .is_dpm_running = aldebaran_is_dpm_running,
1999 .get_unique_id = aldebaran_get_unique_id,
2000 .init_microcode = smu_v13_0_init_microcode,
2001 .load_microcode = smu_v13_0_load_microcode,
2002 .fini_microcode = smu_v13_0_fini_microcode,
2003 .init_smc_tables = aldebaran_init_smc_tables,
2004 .fini_smc_tables = smu_v13_0_fini_smc_tables,
2005 .init_power = smu_v13_0_init_power,
2006 .fini_power = smu_v13_0_fini_power,
2007 .check_fw_status = smu_v13_0_check_fw_status,
2008
2009 .setup_pptable = aldebaran_setup_pptable,
2010 .get_vbios_bootup_values = smu_v13_0_get_vbios_bootup_values,
2011 .check_fw_version = smu_v13_0_check_fw_version,
2012 .write_pptable = smu_cmn_write_pptable,
2013 .set_driver_table_location = smu_v13_0_set_driver_table_location,
2014 .set_tool_table_location = smu_v13_0_set_tool_table_location,
2015 .notify_memory_pool_location = smu_v13_0_notify_memory_pool_location,
2016 .system_features_control = aldebaran_system_features_control,
2017 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
2018 .send_smc_msg = smu_cmn_send_smc_msg,
2019 .get_enabled_mask = smu_cmn_get_enabled_mask,
2020 .feature_is_enabled = smu_cmn_feature_is_enabled,
2021 .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
2022 .set_power_limit = aldebaran_set_power_limit,
2023 .init_max_sustainable_clocks = smu_v13_0_init_max_sustainable_clocks,
2024 .enable_thermal_alert = smu_v13_0_enable_thermal_alert,
2025 .disable_thermal_alert = smu_v13_0_disable_thermal_alert,
2026 .set_xgmi_pstate = smu_v13_0_set_xgmi_pstate,
2027 .register_irq_handler = smu_v13_0_register_irq_handler,
2028 .set_azalia_d3_pme = smu_v13_0_set_azalia_d3_pme,
2029 .get_max_sustainable_clocks_by_dc = smu_v13_0_get_max_sustainable_clocks_by_dc,
2030 .baco_is_support= aldebaran_is_baco_supported,
2031 .get_dpm_ultimate_freq = smu_v13_0_get_dpm_ultimate_freq,
2032 .set_soft_freq_limited_range = aldebaran_set_soft_freq_limited_range,
2033 .od_edit_dpm_table = aldebaran_usr_edit_dpm_table,
2034 .set_df_cstate = aldebaran_set_df_cstate,
2035 .allow_xgmi_power_down = aldebaran_allow_xgmi_power_down,
2036 .log_thermal_throttling_event = aldebaran_log_thermal_throttling_event,
2037 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
2038 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
2039 .get_gpu_metrics = aldebaran_get_gpu_metrics,
2040 .mode1_reset_is_support = aldebaran_is_mode1_reset_supported,
2041 .mode2_reset_is_support = aldebaran_is_mode2_reset_supported,
2042 .smu_handle_passthrough_sbr = aldebaran_smu_handle_passthrough_sbr,
2043 .mode1_reset = aldebaran_mode1_reset,
2044 .set_mp1_state = aldebaran_set_mp1_state,
2045 .mode2_reset = aldebaran_mode2_reset,
2046 .wait_for_event = smu_v13_0_wait_for_event,
2047 .i2c_init = aldebaran_i2c_control_init,
2048 .i2c_fini = aldebaran_i2c_control_fini,
2049 .send_hbm_bad_pages_num = aldebaran_smu_send_hbm_bad_page_num,
2050 .get_ecc_info = aldebaran_get_ecc_info,
2051};
2052
2053void aldebaran_set_ppt_funcs(struct smu_context *smu)
2054{
2055 smu->ppt_funcs = &aldebaran_ppt_funcs;
2056 smu->message_map = aldebaran_message_map;
2057 smu->clock_map = aldebaran_clk_map;
2058 smu->feature_map = aldebaran_feature_mask_map;
2059 smu->table_map = aldebaran_table_map;
2060}
2061
