LXR linux/drivers/gpu/drm/i915/display/g4x

   1// SPDX-License-Identifier: MIT
   2/*
   3 * Copyright © 2020 Intel Corporation
   4 *
   5 * HDMI support for G4x,ILK,SNB,IVB,VLV,CHV (HSW+ handled by the DDI code).
   6 */
   7
   8#include "g4x_hdmi.h"
   9#include "intel_audio.h"
  10#include "intel_connector.h"
  11#include "intel_crtc.h"
  12#include "intel_de.h"
  13#include "intel_display_types.h"
  14#include "intel_dpio_phy.h"
  15#include "intel_fifo_underrun.h"
  16#include "intel_hdmi.h"
  17#include "intel_hotplug.h"
  18#include "intel_sdvo.h"
  19#include "vlv_sideband.h"
  20
  21static void intel_hdmi_prepare(struct intel_encoder *encoder,
  22                               const struct intel_crtc_state *crtc_state)
  23{
  24        struct drm_device *dev = encoder->base.dev;
  25        struct drm_i915_private *dev_priv = to_i915(dev);
  26        struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
  27        struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
  28        const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
  29        u32 hdmi_val;
  30
  31        intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
  32
  33        hdmi_val = SDVO_ENCODING_HDMI;
  34        if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range)
  35                hdmi_val |= HDMI_COLOR_RANGE_16_235;
  36        if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
  37                hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
  38        if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
  39                hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
  40
  41        if (crtc_state->pipe_bpp > 24)
  42                hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
  43        else
  44                hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
  45
  46        if (crtc_state->has_hdmi_sink)
  47                hdmi_val |= HDMI_MODE_SELECT_HDMI;
  48
  49        if (HAS_PCH_CPT(dev_priv))
  50                hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
  51        else if (IS_CHERRYVIEW(dev_priv))
  52                hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
  53        else
  54                hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
  55
  56        intel_de_write(dev_priv, intel_hdmi->hdmi_reg, hdmi_val);
  57        intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
  58}
  59
  60static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
  61                                    enum pipe *pipe)
  62{
  63        struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
  64        struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
  65        intel_wakeref_t wakeref;
  66        bool ret;
  67
  68        wakeref = intel_display_power_get_if_enabled(dev_priv,
  69                                                     encoder->power_domain);
  70        if (!wakeref)
  71                return false;
  72
  73        ret = intel_sdvo_port_enabled(dev_priv, intel_hdmi->hdmi_reg, pipe);
  74
  75        intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
  76
  77        return ret;
  78}
  79
  80static void intel_hdmi_get_config(struct intel_encoder *encoder,
  81                                  struct intel_crtc_state *pipe_config)
  82{
  83        struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
  84        struct drm_device *dev = encoder->base.dev;
  85        struct drm_i915_private *dev_priv = to_i915(dev);
  86        u32 tmp, flags = 0;
  87        int dotclock;
  88
  89        pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
  90
  91        tmp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg);
  92
  93        if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
  94                flags |= DRM_MODE_FLAG_PHSYNC;
  95        else
  96                flags |= DRM_MODE_FLAG_NHSYNC;
  97
  98        if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
  99                flags |= DRM_MODE_FLAG_PVSYNC;
 100        else
 101                flags |= DRM_MODE_FLAG_NVSYNC;
 102
 103        if (tmp & HDMI_MODE_SELECT_HDMI)
 104                pipe_config->has_hdmi_sink = true;
 105
 106        pipe_config->infoframes.enable |=
 107                intel_hdmi_infoframes_enabled(encoder, pipe_config);
 108
 109        if (pipe_config->infoframes.enable)
 110                pipe_config->has_infoframe = true;
 111
 112        if (tmp & HDMI_AUDIO_ENABLE)
 113                pipe_config->has_audio = true;
 114
 115        if (!HAS_PCH_SPLIT(dev_priv) &&
 116            tmp & HDMI_COLOR_RANGE_16_235)
 117                pipe_config->limited_color_range = true;
 118
 119        pipe_config->hw.adjusted_mode.flags |= flags;
 120
 121        if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
 122                dotclock = pipe_config->port_clock * 2 / 3;
 123        else
 124                dotclock = pipe_config->port_clock;
 125
 126        if (pipe_config->pixel_multiplier)
 127                dotclock /= pipe_config->pixel_multiplier;
 128
 129        pipe_config->hw.adjusted_mode.crtc_clock = dotclock;
 130
 131        pipe_config->lane_count = 4;
 132
 133        intel_hdmi_read_gcp_infoframe(encoder, pipe_config);
 134
 135        intel_read_infoframe(encoder, pipe_config,
 136                             HDMI_INFOFRAME_TYPE_AVI,
 137                             &pipe_config->infoframes.avi);
 138        intel_read_infoframe(encoder, pipe_config,
 139                             HDMI_INFOFRAME_TYPE_SPD,
 140                             &pipe_config->infoframes.spd);
 141        intel_read_infoframe(encoder, pipe_config,
 142                             HDMI_INFOFRAME_TYPE_VENDOR,
 143                             &pipe_config->infoframes.hdmi);
 144}
 145
 146static void intel_enable_hdmi_audio(struct intel_encoder *encoder,
 147                                    const struct intel_crtc_state *pipe_config,
 148                                    const struct drm_connector_state *conn_state)
 149{
 150        struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 151        struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
 152
 153        drm_WARN_ON(&i915->drm, !pipe_config->has_hdmi_sink);
 154        drm_dbg_kms(&i915->drm, "Enabling HDMI audio on pipe %c\n",
 155                    pipe_name(crtc->pipe));
 156        intel_audio_codec_enable(encoder, pipe_config, conn_state);
 157}
 158
 159static void g4x_enable_hdmi(struct intel_atomic_state *state,
 160                            struct intel_encoder *encoder,
 161                            const struct intel_crtc_state *pipe_config,
 162                            const struct drm_connector_state *conn_state)
 163{
 164        struct drm_device *dev = encoder->base.dev;
 165        struct drm_i915_private *dev_priv = to_i915(dev);
 166        struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 167        u32 temp;
 168
 169        temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg);
 170
 171        temp |= SDVO_ENABLE;
 172        if (pipe_config->has_audio)
 173                temp |= HDMI_AUDIO_ENABLE;
 174
 175        intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
 176        intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
 177
 178        if (pipe_config->has_audio)
 179                intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
 180}
 181
 182static void ibx_enable_hdmi(struct intel_atomic_state *state,
 183                            struct intel_encoder *encoder,
 184                            const struct intel_crtc_state *pipe_config,
 185                            const struct drm_connector_state *conn_state)
 186{
 187        struct drm_device *dev = encoder->base.dev;
 188        struct drm_i915_private *dev_priv = to_i915(dev);
 189        struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 190        u32 temp;
 191
 192        temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg);
 193
 194        temp |= SDVO_ENABLE;
 195        if (pipe_config->has_audio)
 196                temp |= HDMI_AUDIO_ENABLE;
 197
 198        /*
 199         * HW workaround, need to write this twice for issue
 200         * that may result in first write getting masked.
 201         */
 202        intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
 203        intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
 204        intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
 205        intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
 206
 207        /*
 208         * HW workaround, need to toggle enable bit off and on
 209         * for 12bpc with pixel repeat.
 210         *
 211         * FIXME: BSpec says this should be done at the end of
 212         * the modeset sequence, so not sure if this isn't too soon.
 213         */
 214        if (pipe_config->pipe_bpp > 24 &&
 215            pipe_config->pixel_multiplier > 1) {
 216                intel_de_write(dev_priv, intel_hdmi->hdmi_reg,
 217                               temp & ~SDVO_ENABLE);
 218                intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
 219
 220                /*
 221                 * HW workaround, need to write this twice for issue
 222                 * that may result in first write getting masked.
 223                 */
 224                intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
 225                intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
 226                intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
 227                intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
 228        }
 229
 230        if (pipe_config->has_audio)
 231                intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
 232}
 233
 234static void cpt_enable_hdmi(struct intel_atomic_state *state,
 235                            struct intel_encoder *encoder,
 236                            const struct intel_crtc_state *pipe_config,
 237                            const struct drm_connector_state *conn_state)
 238{
 239        struct drm_device *dev = encoder->base.dev;
 240        struct drm_i915_private *dev_priv = to_i915(dev);
 241        struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
 242        struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 243        enum pipe pipe = crtc->pipe;
 244        u32 temp;
 245
 246        temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg);
 247
 248        temp |= SDVO_ENABLE;
 249        if (pipe_config->has_audio)
 250                temp |= HDMI_AUDIO_ENABLE;
 251
 252        /*
 253         * WaEnableHDMI8bpcBefore12bpc:snb,ivb
 254         *
 255         * The procedure for 12bpc is as follows:
 256         * 1. disable HDMI clock gating
 257         * 2. enable HDMI with 8bpc
 258         * 3. enable HDMI with 12bpc
 259         * 4. enable HDMI clock gating
 260         */
 261
 262        if (pipe_config->pipe_bpp > 24) {
 263                intel_de_write(dev_priv, TRANS_CHICKEN1(pipe),
 264                               intel_de_read(dev_priv, TRANS_CHICKEN1(pipe)) | TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
 265
 266                temp &= ~SDVO_COLOR_FORMAT_MASK;
 267                temp |= SDVO_COLOR_FORMAT_8bpc;
 268        }
 269
 270        intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
 271        intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
 272
 273        if (pipe_config->pipe_bpp > 24) {
 274                temp &= ~SDVO_COLOR_FORMAT_MASK;
 275                temp |= HDMI_COLOR_FORMAT_12bpc;
 276
 277                intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
 278                intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
 279
 280                intel_de_write(dev_priv, TRANS_CHICKEN1(pipe),
 281                               intel_de_read(dev_priv, TRANS_CHICKEN1(pipe)) & ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
 282        }
 283
 284        if (pipe_config->has_audio)
 285                intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
 286}
 287
 288static void vlv_enable_hdmi(struct intel_atomic_state *state,
 289                            struct intel_encoder *encoder,
 290                            const struct intel_crtc_state *pipe_config,
 291                            const struct drm_connector_state *conn_state)
 292{
 293}
 294
 295static void intel_disable_hdmi(struct intel_atomic_state *state,
 296                               struct intel_encoder *encoder,
 297                               const struct intel_crtc_state *old_crtc_state,
 298                               const struct drm_connector_state *old_conn_state)
 299{
 300        struct drm_device *dev = encoder->base.dev;
 301        struct drm_i915_private *dev_priv = to_i915(dev);
 302        struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 303        struct intel_digital_port *dig_port =
 304                hdmi_to_dig_port(intel_hdmi);
 305        struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
 306        u32 temp;
 307
 308        temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg);
 309
 310        temp &= ~(SDVO_ENABLE | HDMI_AUDIO_ENABLE);
 311        intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
 312        intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
 313
 314        /*
 315         * HW workaround for IBX, we need to move the port
 316         * to transcoder A after disabling it to allow the
 317         * matching DP port to be enabled on transcoder A.
 318         */
 319        if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) {
 320                /*
 321                 * We get CPU/PCH FIFO underruns on the other pipe when
 322                 * doing the workaround. Sweep them under the rug.
 323                 */
 324                intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
 325                intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
 326
 327                temp &= ~SDVO_PIPE_SEL_MASK;
 328                temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A);
 329                /*
 330                 * HW workaround, need to write this twice for issue
 331                 * that may result in first write getting masked.
 332                 */
 333                intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
 334                intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
 335                intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
 336                intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
 337
 338                temp &= ~SDVO_ENABLE;
 339                intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
 340                intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
 341
 342                intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
 343                intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
 344                intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
 345        }
 346
 347        dig_port->set_infoframes(encoder,
 348                                       false,
 349                                       old_crtc_state, old_conn_state);
 350
 351        intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
 352}
 353
 354static void g4x_disable_hdmi(struct intel_atomic_state *state,
 355                             struct intel_encoder *encoder,
 356                             const struct intel_crtc_state *old_crtc_state,
 357                             const struct drm_connector_state *old_conn_state)
 358{
 359        if (old_crtc_state->has_audio)
 360                intel_audio_codec_disable(encoder,
 361                                          old_crtc_state, old_conn_state);
 362
 363        intel_disable_hdmi(state, encoder, old_crtc_state, old_conn_state);
 364}
 365
 366static void pch_disable_hdmi(struct intel_atomic_state *state,
 367                             struct intel_encoder *encoder,
 368                             const struct intel_crtc_state *old_crtc_state,
 369                             const struct drm_connector_state *old_conn_state)
 370{
 371        if (old_crtc_state->has_audio)
 372                intel_audio_codec_disable(encoder,
 373                                          old_crtc_state, old_conn_state);
 374}
 375
 376static void pch_post_disable_hdmi(struct intel_atomic_state *state,
 377                                  struct intel_encoder *encoder,
 378                                  const struct intel_crtc_state *old_crtc_state,
 379                                  const struct drm_connector_state *old_conn_state)
 380{
 381        intel_disable_hdmi(state, encoder, old_crtc_state, old_conn_state);
 382}
 383
 384static void intel_hdmi_pre_enable(struct intel_atomic_state *state,
 385                                  struct intel_encoder *encoder,
 386                                  const struct intel_crtc_state *pipe_config,
 387                                  const struct drm_connector_state *conn_state)
 388{
 389        struct intel_digital_port *dig_port =
 390                enc_to_dig_port(encoder);
 391
 392        intel_hdmi_prepare(encoder, pipe_config);
 393
 394        dig_port->set_infoframes(encoder,
 395                                       pipe_config->has_infoframe,
 396                                       pipe_config, conn_state);
 397}
 398
 399static void vlv_hdmi_pre_enable(struct intel_atomic_state *state,
 400                                struct intel_encoder *encoder,
 401                                const struct intel_crtc_state *pipe_config,
 402                                const struct drm_connector_state *conn_state)
 403{
 404        struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 405        struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 406
 407        vlv_phy_pre_encoder_enable(encoder, pipe_config);
 408
 409        /* HDMI 1.0V-2dB */
 410        vlv_set_phy_signal_level(encoder, pipe_config,
 411                                 0x2b245f5f, 0x00002000,
 412                                 0x5578b83a, 0x2b247878);
 413
 414        dig_port->set_infoframes(encoder,
 415                              pipe_config->has_infoframe,
 416                              pipe_config, conn_state);
 417
 418        g4x_enable_hdmi(state, encoder, pipe_config, conn_state);
 419
 420        vlv_wait_port_ready(dev_priv, dig_port, 0x0);
 421}
 422
 423static void vlv_hdmi_pre_pll_enable(struct intel_atomic_state *state,
 424                                    struct intel_encoder *encoder,
 425                                    const struct intel_crtc_state *pipe_config,
 426                                    const struct drm_connector_state *conn_state)
 427{
 428        intel_hdmi_prepare(encoder, pipe_config);
 429
 430        vlv_phy_pre_pll_enable(encoder, pipe_config);
 431}
 432
 433static void chv_hdmi_pre_pll_enable(struct intel_atomic_state *state,
 434                                    struct intel_encoder *encoder,
 435                                    const struct intel_crtc_state *pipe_config,
 436                                    const struct drm_connector_state *conn_state)
 437{
 438        intel_hdmi_prepare(encoder, pipe_config);
 439
 440        chv_phy_pre_pll_enable(encoder, pipe_config);
 441}
 442
 443static void chv_hdmi_post_pll_disable(struct intel_atomic_state *state,
 444                                      struct intel_encoder *encoder,
 445                                      const struct intel_crtc_state *old_crtc_state,
 446                                      const struct drm_connector_state *old_conn_state)
 447{
 448        chv_phy_post_pll_disable(encoder, old_crtc_state);
 449}
 450
 451static void vlv_hdmi_post_disable(struct intel_atomic_state *state,
 452                                  struct intel_encoder *encoder,
 453                                  const struct intel_crtc_state *old_crtc_state,
 454                                  const struct drm_connector_state *old_conn_state)
 455{
 456        /* Reset lanes to avoid HDMI flicker (VLV w/a) */
 457        vlv_phy_reset_lanes(encoder, old_crtc_state);
 458}
 459
 460static void chv_hdmi_post_disable(struct intel_atomic_state *state,
 461                                  struct intel_encoder *encoder,
 462                                  const struct intel_crtc_state *old_crtc_state,
 463                                  const struct drm_connector_state *old_conn_state)
 464{
 465        struct drm_device *dev = encoder->base.dev;
 466        struct drm_i915_private *dev_priv = to_i915(dev);
 467
 468        vlv_dpio_get(dev_priv);
 469
 470        /* Assert data lane reset */
 471        chv_data_lane_soft_reset(encoder, old_crtc_state, true);
 472
 473        vlv_dpio_put(dev_priv);
 474}
 475
 476static void chv_hdmi_pre_enable(struct intel_atomic_state *state,
 477                                struct intel_encoder *encoder,
 478                                const struct intel_crtc_state *pipe_config,
 479                                const struct drm_connector_state *conn_state)
 480{
 481        struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 482        struct drm_device *dev = encoder->base.dev;
 483        struct drm_i915_private *dev_priv = to_i915(dev);
 484
 485        chv_phy_pre_encoder_enable(encoder, pipe_config);
 486
 487        /* FIXME: Program the support xxx V-dB */
 488        /* Use 800mV-0dB */
 489        chv_set_phy_signal_level(encoder, pipe_config, 128, 102, false);
 490
 491        dig_port->set_infoframes(encoder,
 492                              pipe_config->has_infoframe,
 493                              pipe_config, conn_state);
 494
 495        g4x_enable_hdmi(state, encoder, pipe_config, conn_state);
 496
 497        vlv_wait_port_ready(dev_priv, dig_port, 0x0);
 498
 499        /* Second common lane will stay alive on its own now */
 500        chv_phy_release_cl2_override(encoder);
 501}
 502
 503static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
 504        .destroy = intel_encoder_destroy,
 505};
 506
 507static enum intel_hotplug_state
 508intel_hdmi_hotplug(struct intel_encoder *encoder,
 509                   struct intel_connector *connector)
 510{
 511        enum intel_hotplug_state state;
 512
 513        state = intel_encoder_hotplug(encoder, connector);
 514
 515        /*
 516         * On many platforms the HDMI live state signal is known to be
 517         * unreliable, so we can't use it to detect if a sink is connected or
 518         * not. Instead we detect if it's connected based on whether we can
 519         * read the EDID or not. That in turn has a problem during disconnect,
 520         * since the HPD interrupt may be raised before the DDC lines get
 521         * disconnected (due to how the required length of DDC vs. HPD
 522         * connector pins are specified) and so we'll still be able to get a
 523         * valid EDID. To solve this schedule another detection cycle if this
 524         * time around we didn't detect any change in the sink's connection
 525         * status.
 526         */
 527        if (state == INTEL_HOTPLUG_UNCHANGED && !connector->hotplug_retries)
 528                state = INTEL_HOTPLUG_RETRY;
 529
 530        return state;
 531}
 532
 533void g4x_hdmi_init(struct drm_i915_private *dev_priv,
 534                   i915_reg_t hdmi_reg, enum port port)
 535{
 536        struct intel_digital_port *dig_port;
 537        struct intel_encoder *intel_encoder;
 538        struct intel_connector *intel_connector;
 539
 540        dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL);
 541        if (!dig_port)
 542                return;
 543
 544        intel_connector = intel_connector_alloc();
 545        if (!intel_connector) {
 546                kfree(dig_port);
 547                return;
 548        }
 549
 550        intel_encoder = &dig_port->base;
 551
 552        mutex_init(&dig_port->hdcp_mutex);
 553
 554        drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
 555                         &intel_hdmi_enc_funcs, DRM_MODE_ENCODER_TMDS,
 556                         "HDMI %c", port_name(port));
 557
 558        intel_encoder->hotplug = intel_hdmi_hotplug;
 559        intel_encoder->compute_config = intel_hdmi_compute_config;
 560        if (HAS_PCH_SPLIT(dev_priv)) {
 561                intel_encoder->disable = pch_disable_hdmi;
 562                intel_encoder->post_disable = pch_post_disable_hdmi;
 563        } else {
 564                intel_encoder->disable = g4x_disable_hdmi;
 565        }
 566        intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
 567        intel_encoder->get_config = intel_hdmi_get_config;
 568        if (IS_CHERRYVIEW(dev_priv)) {
 569                intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable;
 570                intel_encoder->pre_enable = chv_hdmi_pre_enable;
 571                intel_encoder->enable = vlv_enable_hdmi;
 572                intel_encoder->post_disable = chv_hdmi_post_disable;
 573                intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable;
 574        } else if (IS_VALLEYVIEW(dev_priv)) {
 575                intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
 576                intel_encoder->pre_enable = vlv_hdmi_pre_enable;
 577                intel_encoder->enable = vlv_enable_hdmi;
 578                intel_encoder->post_disable = vlv_hdmi_post_disable;
 579        } else {
 580                intel_encoder->pre_enable = intel_hdmi_pre_enable;
 581                if (HAS_PCH_CPT(dev_priv))
 582                        intel_encoder->enable = cpt_enable_hdmi;
 583                else if (HAS_PCH_IBX(dev_priv))
 584                        intel_encoder->enable = ibx_enable_hdmi;
 585                else
 586                        intel_encoder->enable = g4x_enable_hdmi;
 587        }
 588        intel_encoder->shutdown = intel_hdmi_encoder_shutdown;
 589
 590        intel_encoder->type = INTEL_OUTPUT_HDMI;
 591        intel_encoder->power_domain = intel_port_to_power_domain(port);
 592        intel_encoder->port = port;
 593        if (IS_CHERRYVIEW(dev_priv)) {
 594                if (port == PORT_D)
 595                        intel_encoder->pipe_mask = BIT(PIPE_C);
 596                else
 597                        intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B);
 598        } else {
 599                intel_encoder->pipe_mask = ~0;
 600        }
 601        intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
 602        intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
 603        /*
 604         * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
 605         * to work on real hardware. And since g4x can send infoframes to
 606         * only one port anyway, nothing is lost by allowing it.
 607         */
 608        if (IS_G4X(dev_priv))
 609                intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;
 610
 611        dig_port->hdmi.hdmi_reg = hdmi_reg;
 612        dig_port->dp.output_reg = INVALID_MMIO_REG;
 613        dig_port->max_lanes = 4;
 614
 615        intel_infoframe_init(dig_port);
 616
 617        dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
 618        intel_hdmi_init_connector(dig_port, intel_connector);
 619}
 620