/*
 * Copyright © 2006-2007 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *      Eric Anholt <eric@anholt.net>
 */

#include <acpi/video.h>
#include <linux/i2c.h>
#include <linux/input.h>
#include <linux/intel-iommu.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/dma-resv.h>
#include <linux/slab.h>
#include <linux/vga_switcheroo.h>

#include <drm/drm_atomic.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_atomic_uapi.h>
#include <drm/drm_damage_helper.h>
#include <drm/drm_dp_helper.h>
#include <drm/drm_edid.h>
#include <drm/drm_fourcc.h>
#include <drm/drm_plane_helper.h>
#include <drm/drm_privacy_screen_consumer.h>
#include <drm/drm_probe_helper.h>
#include <drm/drm_rect.h>

#include "display/intel_audio.h"
#include "display/intel_crt.h"
#include "display/intel_ddi.h"
#include "display/intel_display_debugfs.h"
#include "display/intel_dp.h"
#include "display/intel_dp_mst.h"
#include "display/intel_dpll.h"
#include "display/intel_dpll_mgr.h"
#include "display/intel_drrs.h"
#include "display/intel_dsi.h"
#include "display/intel_dvo.h"
#include "display/intel_fb.h"
#include "display/intel_gmbus.h"
#include "display/intel_hdmi.h"
#include "display/intel_lvds.h"
#include "display/intel_sdvo.h"
#include "display/intel_snps_phy.h"
#include "display/intel_tv.h"
#include "display/intel_vdsc.h"
#include "display/intel_vrr.h"

#include "gem/i915_gem_lmem.h"
#include "gem/i915_gem_object.h"

#include "gt/gen8_ppgtt.h"

#include "g4x_dp.h"
#include "g4x_hdmi.h"
#include "i915_drv.h"
#include "icl_dsi.h"
#include "intel_acpi.h"
#include "intel_atomic.h"
#include "intel_atomic_plane.h"
#include "intel_bw.h"
#include "intel_cdclk.h"
#include "intel_color.h"
#include "intel_crtc.h"
#include "intel_de.h"
#include "intel_display_types.h"
#include "intel_dmc.h"
#include "intel_dp_link_training.h"
#include "intel_dpt.h"
#include "intel_fbc.h"
#include "intel_fbdev.h"
#include "intel_fdi.h"
#include "intel_fifo_underrun.h"
#include "intel_frontbuffer.h"
#include "intel_hdcp.h"
#include "intel_hotplug.h"
#include "intel_overlay.h"
#include "intel_panel.h"
#include "intel_pch_display.h"
#include "intel_pch_refclk.h"
#include "intel_pcode.h"
#include "intel_pipe_crc.h"
#include "intel_plane_initial.h"
#include "intel_pm.h"
#include "intel_pps.h"
#include "intel_psr.h"
#include "intel_quirks.h"
#include "intel_sprite.h"
#include "intel_tc.h"
#include "intel_vga.h"
#include "i9xx_plane.h"
#include "skl_scaler.h"
#include "skl_universal_plane.h"
#include "vlv_dsi_pll.h"
#include "vlv_sideband.h"
#include "vlv_dsi.h"

static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state);
static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
                                         const struct intel_link_m_n *m_n,
                                         const struct intel_link_m_n *m2_n2);
static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state);
static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state);
static void hsw_set_transconf(const struct intel_crtc_state *crtc_state);
static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state);
static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state);
static void intel_modeset_setup_hw_state(struct drm_device *dev,
                                         struct drm_modeset_acquire_ctx *ctx);

/**
 * intel_update_watermarks - update FIFO watermark values based on current modes
 * @dev_priv: i915 device
 *
 * Calculate watermark values for the various WM regs based on current mode
 * and plane configuration.
 *
 * There are several cases to deal with here:
 *   - normal (i.e. non-self-refresh)
 *   - self-refresh (SR) mode
 *   - lines are large relative to FIFO size (buffer can hold up to 2)
 *   - lines are small relative to FIFO size (buffer can hold more than 2
 *     lines), so need to account for TLB latency
 *
 *   The normal calculation is:
 *     watermark = dotclock * bytes per pixel * latency
 *   where latency is platform & configuration dependent (we assume pessimal
 *   values here).
 *
 *   The SR calculation is:
 *     watermark = (trunc(latency/line time)+1) * surface width *
 *       bytes per pixel
 *   where
 *     line time = htotal / dotclock
 *     surface width = hdisplay for normal plane and 64 for cursor
 *   and latency is assumed to be high, as above.
 *
 * The final value programmed to the register should always be rounded up,
 * and include an extra 2 entries to account for clock crossings.
 *
 * We don't use the sprite, so we can ignore that.  And on Crestline we have
 * to set the non-SR watermarks to 8.
 */
static void intel_update_watermarks(struct drm_i915_private *dev_priv)
{
        if (dev_priv->wm_disp->update_wm)
                dev_priv->wm_disp->update_wm(dev_priv);
}

static int intel_compute_pipe_wm(struct intel_atomic_state *state,
                                 struct intel_crtc *crtc)
{
        struct drm_i915_private *dev_priv = to_i915(state->base.dev);
        if (dev_priv->wm_disp->compute_pipe_wm)
                return dev_priv->wm_disp->compute_pipe_wm(state, crtc);
        return 0;
}

static int intel_compute_intermediate_wm(struct intel_atomic_state *state,
                                         struct intel_crtc *crtc)
{
        struct drm_i915_private *dev_priv = to_i915(state->base.dev);
        if (!dev_priv->wm_disp->compute_intermediate_wm)
                return 0;
        if (drm_WARN_ON(&dev_priv->drm,
                        !dev_priv->wm_disp->compute_pipe_wm))
                return 0;
        return dev_priv->wm_disp->compute_intermediate_wm(state, crtc);
}

static bool intel_initial_watermarks(struct intel_atomic_state *state,
                                     struct intel_crtc *crtc)
{
        struct drm_i915_private *dev_priv = to_i915(state->base.dev);
        if (dev_priv->wm_disp->initial_watermarks) {
                dev_priv->wm_disp->initial_watermarks(state, crtc);
                return true;
        }
        return false;
}

static void intel_atomic_update_watermarks(struct intel_atomic_state *state,
                                           struct intel_crtc *crtc)
{
        struct drm_i915_private *dev_priv = to_i915(state->base.dev);
        if (dev_priv->wm_disp->atomic_update_watermarks)
                dev_priv->wm_disp->atomic_update_watermarks(state, crtc);
}

static void intel_optimize_watermarks(struct intel_atomic_state *state,
                                      struct intel_crtc *crtc)
{
        struct drm_i915_private *dev_priv = to_i915(state->base.dev);
        if (dev_priv->wm_disp->optimize_watermarks)
                dev_priv->wm_disp->optimize_watermarks(state, crtc);
}

static int intel_compute_global_watermarks(struct intel_atomic_state *state)
{
        struct drm_i915_private *dev_priv = to_i915(state->base.dev);
        if (dev_priv->wm_disp->compute_global_watermarks)
                return dev_priv->wm_disp->compute_global_watermarks(state);
        return 0;
}

/* returns HPLL frequency in kHz */
int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
{
        int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };

        /* Obtain SKU information */
        hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
                CCK_FUSE_HPLL_FREQ_MASK;

        return vco_freq[hpll_freq] * 1000;
}

int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
                      const char *name, u32 reg, int ref_freq)
{
        u32 val;
        int divider;

        val = vlv_cck_read(dev_priv, reg);
        divider = val & CCK_FREQUENCY_VALUES;

        drm_WARN(&dev_priv->drm, (val & CCK_FREQUENCY_STATUS) !=
                 (divider << CCK_FREQUENCY_STATUS_SHIFT),
                 "%s change in progress\n", name);

        return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
}

int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
                           const char *name, u32 reg)
{
        int hpll;

        vlv_cck_get(dev_priv);

        if (dev_priv->hpll_freq == 0)
                dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);

        hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq);

        vlv_cck_put(dev_priv);

        return hpll;
}

static void intel_update_czclk(struct drm_i915_private *dev_priv)
{
        if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
                return;

        dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
                                                      CCK_CZ_CLOCK_CONTROL);

        drm_dbg(&dev_priv->drm, "CZ clock rate: %d kHz\n",
                dev_priv->czclk_freq);
}

static bool is_hdr_mode(const struct intel_crtc_state *crtc_state)
{
        return (crtc_state->active_planes &
                ~(icl_hdr_plane_mask() | BIT(PLANE_CURSOR))) == 0;
}

/* WA Display #0827: Gen9:all */
static void
skl_wa_827(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable)
{
        if (enable)
                intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
                               intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | DUPS1_GATING_DIS | DUPS2_GATING_DIS);
        else
                intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
                               intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~(DUPS1_GATING_DIS | DUPS2_GATING_DIS));
}

/* Wa_2006604312:icl,ehl */
static void
icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe,
                       bool enable)
{
        if (enable)
                intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
                               intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | DPFR_GATING_DIS);
        else
                intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
                               intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~DPFR_GATING_DIS);
}

/* Wa_1604331009:icl,jsl,ehl */
static void
icl_wa_cursorclkgating(struct drm_i915_private *dev_priv, enum pipe pipe,
                       bool enable)
{
        intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), CURSOR_GATING_DIS,
                     enable ? CURSOR_GATING_DIS : 0);
}

static bool
is_trans_port_sync_slave(const struct intel_crtc_state *crtc_state)
{
        return crtc_state->master_transcoder != INVALID_TRANSCODER;
}

static bool
is_trans_port_sync_master(const struct intel_crtc_state *crtc_state)
{
        return crtc_state->sync_mode_slaves_mask != 0;
}

bool
is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state)
{
        return is_trans_port_sync_master(crtc_state) ||
                is_trans_port_sync_slave(crtc_state);
}

static struct intel_crtc *intel_master_crtc(const struct intel_crtc_state *crtc_state)
{
        if (crtc_state->bigjoiner_slave)
                return crtc_state->bigjoiner_linked_crtc;
        else
                return to_intel_crtc(crtc_state->uapi.crtc);
}

static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv,
                                    enum pipe pipe)
{
        i915_reg_t reg = PIPEDSL(pipe);
        u32 line1, line2;
        u32 line_mask;

        if (DISPLAY_VER(dev_priv) == 2)
                line_mask = DSL_LINEMASK_GEN2;
        else
                line_mask = DSL_LINEMASK_GEN3;

        line1 = intel_de_read(dev_priv, reg) & line_mask;
        msleep(5);
        line2 = intel_de_read(dev_priv, reg) & line_mask;

        return line1 != line2;
}

static void wait_for_pipe_scanline_moving(struct intel_crtc *crtc, bool state)
{
        struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
        enum pipe pipe = crtc->pipe;

        /* Wait for the display line to settle/start moving */
        if (wait_for(pipe_scanline_is_moving(dev_priv, pipe) == state, 100))
                drm_err(&dev_priv->drm,
                        "pipe %c scanline %s wait timed out\n",
                        pipe_name(pipe), onoff(state));
}

static void intel_wait_for_pipe_scanline_stopped(struct intel_crtc *crtc)
{
        wait_for_pipe_scanline_moving(crtc, false);
}

static void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc)
{
        wait_for_pipe_scanline_moving(crtc, true);
}

static void
intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state)
{
        struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
        struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

        if (DISPLAY_VER(dev_priv) >= 4) {
                enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
                i915_reg_t reg = PIPECONF(cpu_transcoder);

                /* Wait for the Pipe State to go off */
                if (intel_de_wait_for_clear(dev_priv, reg,
                                            I965_PIPECONF_ACTIVE, 100))
                        drm_WARN(&dev_priv->drm, 1,
                                 "pipe_off wait timed out\n");
        } else {
                intel_wait_for_pipe_scanline_stopped(crtc);
        }
}

void assert_transcoder(struct drm_i915_private *dev_priv,
                       enum transcoder cpu_transcoder, bool state)
{
        bool cur_state;
        enum intel_display_power_domain power_domain;
        intel_wakeref_t wakeref;

        /* we keep both pipes enabled on 830 */
        if (IS_I830(dev_priv))
                state = true;

        power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
        wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
        if (wakeref) {
                u32 val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder));
                cur_state = !!(val & PIPECONF_ENABLE);

                intel_display_power_put(dev_priv, power_domain, wakeref);
        } else {
                cur_state = false;
        }

        I915_STATE_WARN(cur_state != state,
                        "transcoder %s assertion failure (expected %s, current %s)\n",
                        transcoder_name(cpu_transcoder),
                        onoff(state), onoff(cur_state));
}

static void assert_plane(struct intel_plane *plane, bool state)
{
        enum pipe pipe;
        bool cur_state;

        cur_state = plane->get_hw_state(plane, &pipe);

        I915_STATE_WARN(cur_state != state,
                        "%s assertion failure (expected %s, current %s)\n",
                        plane->base.name, onoff(state), onoff(cur_state));
}

#define assert_plane_enabled(p) assert_plane(p, true)
#define assert_plane_disabled(p) assert_plane(p, false)

static void assert_planes_disabled(struct intel_crtc *crtc)
{
        struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
        struct intel_plane *plane;

        for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane)
                assert_plane_disabled(plane);
}

void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
                         struct intel_digital_port *dig_port,
                         unsigned int expected_mask)
{
        u32 port_mask;
        i915_reg_t dpll_reg;

        switch (dig_port->base.port) {
        case PORT_B:
                port_mask = DPLL_PORTB_READY_MASK;
                dpll_reg = DPLL(0);
                break;
        case PORT_C:
                port_mask = DPLL_PORTC_READY_MASK;
                dpll_reg = DPLL(0);
                expected_mask <<= 4;
                break;
        case PORT_D:
                port_mask = DPLL_PORTD_READY_MASK;
                dpll_reg = DPIO_PHY_STATUS;
                break;
        default:
                BUG();
        }

        if (intel_de_wait_for_register(dev_priv, dpll_reg,
                                       port_mask, expected_mask, 1000))
                drm_WARN(&dev_priv->drm, 1,
                         "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n",
                         dig_port->base.base.base.id, dig_port->base.base.name,
                         intel_de_read(dev_priv, dpll_reg) & port_mask,
                         expected_mask);
}

enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc)
{
        struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

        if (HAS_PCH_LPT(dev_priv))
                return PIPE_A;
        else
                return crtc->pipe;
}

void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state)
{
        struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
        struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
        enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
        enum pipe pipe = crtc->pipe;
        i915_reg_t reg;
        u32 val;

        drm_dbg_kms(&dev_priv->drm, "enabling pipe %c\n", pipe_name(pipe));

        assert_planes_disabled(crtc);

        /*
         * A pipe without a PLL won't actually be able to drive bits from
         * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
         * need the check.
         */
        if (HAS_GMCH(dev_priv)) {
                if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI))
                        assert_dsi_pll_enabled(dev_priv);
                else
                        assert_pll_enabled(dev_priv, pipe);
        } else {
                if (new_crtc_state->has_pch_encoder) {
                        /* if driving the PCH, we need FDI enabled */
                        assert_fdi_rx_pll_enabled(dev_priv,
                                                  intel_crtc_pch_transcoder(crtc));
                        assert_fdi_tx_pll_enabled(dev_priv,
                                                  (enum pipe) cpu_transcoder);
                }
                /* FIXME: assert CPU port conditions for SNB+ */
        }

        /* Wa_22012358565:adl-p */
        if (DISPLAY_VER(dev_priv) == 13)
                intel_de_rmw(dev_priv, PIPE_ARB_CTL(pipe),
                             0, PIPE_ARB_USE_PROG_SLOTS);

        reg = PIPECONF(cpu_transcoder);
        val = intel_de_read(dev_priv, reg);
        if (val & PIPECONF_ENABLE) {
                /* we keep both pipes enabled on 830 */
                drm_WARN_ON(&dev_priv->drm, !IS_I830(dev_priv));
                return;
        }

        intel_de_write(dev_priv, reg, val | PIPECONF_ENABLE);
        intel_de_posting_read(dev_priv, reg);

        /*
         * Until the pipe starts PIPEDSL reads will return a stale value,
         * which causes an apparent vblank timestamp jump when PIPEDSL
         * resets to its proper value. That also messes up the frame count
         * when it's derived from the timestamps. So let's wait for the
         * pipe to start properly before we call drm_crtc_vblank_on()
         */
        if (intel_crtc_max_vblank_count(new_crtc_state) == 0)
                intel_wait_for_pipe_scanline_moving(crtc);
}

void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state)
{
        struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
        struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
        enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
        enum pipe pipe = crtc->pipe;
        i915_reg_t reg;
        u32 val;

        drm_dbg_kms(&dev_priv->drm, "disabling pipe %c\n", pipe_name(pipe));

        /*
         * Make sure planes won't keep trying to pump pixels to us,
         * or we might hang the display.
         */
        assert_planes_disabled(crtc);

        reg = PIPECONF(cpu_transcoder);
        val = intel_de_read(dev_priv, reg);
        if ((val & PIPECONF_ENABLE) == 0)
                return;

        /*
         * Double wide has implications for planes
         * so best keep it disabled when not needed.
         */
        if (old_crtc_state->double_wide)
                val &= ~PIPECONF_DOUBLE_WIDE;

        /* Don't disable pipe or pipe PLLs if needed */
        if (!IS_I830(dev_priv))
                val &= ~PIPECONF_ENABLE;

        if (DISPLAY_VER(dev_priv) >= 12)
                intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder),
                             FECSTALL_DIS_DPTSTREAM_DPTTG, 0);

        intel_de_write(dev_priv, reg, val);
        if ((val & PIPECONF_ENABLE) == 0)
                intel_wait_for_pipe_off(old_crtc_state);
}

unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
{
        unsigned int size = 0;
        int i;

        for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
                size += rot_info->plane[i].dst_stride * rot_info->plane[i].width;

        return size;
}

unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info)
{
        unsigned int size = 0;
        int i;

        for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++) {
                unsigned int plane_size;

                if (rem_info->plane[i].linear)
                        plane_size = rem_info->plane[i].size;
                else
                        plane_size = rem_info->plane[i].dst_stride * rem_info->plane[i].height;

                if (plane_size == 0)
                        continue;

                if (rem_info->plane_alignment)
                        size = ALIGN(size, rem_info->plane_alignment);

                size += plane_size;
        }

        return size;
}

bool intel_plane_uses_fence(const struct intel_plane_state *plane_state)
{
        struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
        struct drm_i915_private *dev_priv = to_i915(plane->base.dev);

        return DISPLAY_VER(dev_priv) < 4 ||
                (plane->fbc &&
                 plane_state->view.gtt.type == I915_GGTT_VIEW_NORMAL);
}

/*
 * Convert the x/y offsets into a linear offset.
 * Only valid with 0/180 degree rotation, which is fine since linear
 * offset is only used with linear buffers on pre-hsw and tiled buffers
 * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
 */
u32 intel_fb_xy_to_linear(int x, int y,
                          const struct intel_plane_state *state,
                          int color_plane)
{
        const struct drm_framebuffer *fb = state->hw.fb;
        unsigned int cpp = fb->format->cpp[color_plane];
        unsigned int pitch = state->view.color_plane[color_plane].mapping_stride;

        return y * pitch + x * cpp;
}

/*
 * Add the x/y offsets derived from fb->offsets[] to the user
 * specified plane src x/y offsets. The resulting x/y offsets
 * specify the start of scanout from the beginning of the gtt mapping.
 */
void intel_add_fb_offsets(int *x, int *y,
                          const struct intel_plane_state *state,
                          int color_plane)

{
        *x += state->view.color_plane[color_plane].x;
        *y += state->view.color_plane[color_plane].y;
}

u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
                              u32 pixel_format, u64 modifier)
{
        struct intel_crtc *crtc;
        struct intel_plane *plane;

        if (!HAS_DISPLAY(dev_priv))
                return 0;

        /*
         * We assume the primary plane for pipe A has
         * the highest stride limits of them all,
         * if in case pipe A is disabled, use the first pipe from pipe_mask.
         */
        crtc = intel_first_crtc(dev_priv);
        if (!crtc)
                return 0;

        plane = to_intel_plane(crtc->base.primary);

        return plane->max_stride(plane, pixel_format, modifier,
                                 DRM_MODE_ROTATE_0);
}

static void
intel_set_plane_visible(struct intel_crtc_state *crtc_state,
                        struct intel_plane_state *plane_state,
                        bool visible)
{
        struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

        plane_state->uapi.visible = visible;

        if (visible)
                crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base);
        else
                crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base);
}

static void fixup_plane_bitmasks(struct intel_crtc_state *crtc_state)
{
        struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
        struct drm_plane *plane;

        /*
         * Active_planes aliases if multiple "primary" or cursor planes
         * have been used on the same (or wrong) pipe. plane_mask uses
         * unique ids, hence we can use that to reconstruct active_planes.
         */
        crtc_state->enabled_planes = 0;
        crtc_state->active_planes = 0;

        drm_for_each_plane_mask(plane, &dev_priv->drm,
                                crtc_state->uapi.plane_mask) {
                crtc_state->enabled_planes |= BIT(to_intel_plane(plane)->id);
                crtc_state->active_planes |= BIT(to_intel_plane(plane)->id);
        }
}

void intel_plane_disable_noatomic(struct intel_crtc *crtc,
                                  struct intel_plane *plane)
{
        struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
        struct intel_crtc_state *crtc_state =
                to_intel_crtc_state(crtc->base.state);
        struct intel_plane_state *plane_state =
                to_intel_plane_state(plane->base.state);

        drm_dbg_kms(&dev_priv->drm,
                    "Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n",
                    plane->base.base.id, plane->base.name,
                    crtc->base.base.id, crtc->base.name);

        intel_set_plane_visible(crtc_state, plane_state, false);
        fixup_plane_bitmasks(crtc_state);
        crtc_state->data_rate[plane->id] = 0;
        crtc_state->min_cdclk[plane->id] = 0;

        if (plane->id == PLANE_PRIMARY)
                hsw_disable_ips(crtc_state);

        /*
         * Vblank time updates from the shadow to live plane control register
         * are blocked if the memory self-refresh mode is active at that
         * moment. So to make sure the plane gets truly disabled, disable
         * first the self-refresh mode. The self-refresh enable bit in turn
         * will be checked/applied by the HW only at the next frame start
         * event which is after the vblank start event, so we need to have a
         * wait-for-vblank between disabling the plane and the pipe.
         */
        if (HAS_GMCH(dev_priv) &&
            intel_set_memory_cxsr(dev_priv, false))
                intel_crtc_wait_for_next_vblank(crtc);

        /*
         * Gen2 reports pipe underruns whenever all planes are disabled.
         * So disable underrun reporting before all the planes get disabled.
         */
        if (DISPLAY_VER(dev_priv) == 2 && !crtc_state->active_planes)
                intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);

        intel_plane_disable_arm(plane, crtc_state);
        intel_crtc_wait_for_next_vblank(crtc);
}

unsigned int
intel_plane_fence_y_offset(const struct intel_plane_state *plane_state)
{
        int x = 0, y = 0;

        intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
                                          plane_state->view.color_plane[0].offset, 0);

        return y;
}

static int
__intel_display_resume(struct drm_device *dev,
                       struct drm_atomic_state *state,
                       struct drm_modeset_acquire_ctx *ctx)
{
        struct drm_crtc_state *crtc_state;
        struct drm_crtc *crtc;
        int i, ret;

        intel_modeset_setup_hw_state(dev, ctx);
        intel_vga_redisable(to_i915(dev));

        if (!state)
                return 0;

        /*
         * We've duplicated the state, pointers to the old state are invalid.
         *
         * Don't attempt to use the old state until we commit the duplicated state.
         */
        for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
                /*
                 * Force recalculation even if we restore
                 * current state. With fast modeset this may not result
                 * in a modeset when the state is compatible.
                 */
                crtc_state->mode_changed = true;
        }

        /* ignore any reset values/BIOS leftovers in the WM registers */
        if (!HAS_GMCH(to_i915(dev)))
                to_intel_atomic_state(state)->skip_intermediate_wm = true;

        ret = drm_atomic_helper_commit_duplicated_state(state, ctx);

        drm_WARN_ON(dev, ret == -EDEADLK);
        return ret;
}

static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
{
        return (INTEL_INFO(dev_priv)->gpu_reset_clobbers_display &&
                intel_has_gpu_reset(to_gt(dev_priv)));
}

void intel_display_prepare_reset(struct drm_i915_private *dev_priv)
{
        struct drm_device *dev = &dev_priv->drm;
        struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
        struct drm_atomic_state *state;
        int ret;

        if (!HAS_DISPLAY(dev_priv))
                return;

        /* reset doesn't touch the display */
        if (!dev_priv->params.force_reset_modeset_test &&
            !gpu_reset_clobbers_display(dev_priv))
                return;

        /* We have a modeset vs reset deadlock, defensively unbreak it. */
        set_bit(I915_RESET_MODESET, &to_gt(dev_priv)->reset.flags);
        smp_mb__after_atomic();
        wake_up_bit(&to_gt(dev_priv)->reset.flags, I915_RESET_MODESET);

        if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) {
                drm_dbg_kms(&dev_priv->drm,
                            "Modeset potentially stuck, unbreaking through wedging\n");
                intel_gt_set_wedged(to_gt(dev_priv));
        }

        /*
         * Need mode_config.mutex so that we don't
         * trample ongoing ->detect() and whatnot.
         */
        mutex_lock(&dev->mode_config.mutex);
        drm_modeset_acquire_init(ctx, 0);
        while (1) {
                ret = drm_modeset_lock_all_ctx(dev, ctx);
                if (ret != -EDEADLK)
                        break;

                drm_modeset_backoff(ctx);
        }
        /*
         * Disabling the crtcs gracefully seems nicer. Also the
         * g33 docs say we should at least disable all the planes.
         */
        state = drm_atomic_helper_duplicate_state(dev, ctx);
        if (IS_ERR(state)) {
                ret = PTR_ERR(state);
                drm_err(&dev_priv->drm, "Duplicating state failed with %i\n",
                        ret);
                return;
        }

        ret = drm_atomic_helper_disable_all(dev, ctx);
        if (ret) {
                drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n",
                        ret);
                drm_atomic_state_put(state);
                return;
        }

        dev_priv->modeset_restore_state = state;
        state->acquire_ctx = ctx;
}

void intel_display_finish_reset(struct drm_i915_private *dev_priv)
{
        struct drm_device *dev = &dev_priv->drm;
        struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
        struct drm_atomic_state *state;
        int ret;

        if (!HAS_DISPLAY(dev_priv))
                return;

        /* reset doesn't touch the display */
        if (!test_bit(I915_RESET_MODESET, &to_gt(dev_priv)->reset.flags))
                return;

        state = fetch_and_zero(&dev_priv->modeset_restore_state);
        if (!state)
                goto unlock;

        /* reset doesn't touch the display */
        if (!gpu_reset_clobbers_display(dev_priv)) {
                /* for testing only restore the display */
                ret = __intel_display_resume(dev, state, ctx);
                if (ret)
                        drm_err(&dev_priv->drm,
                                "Restoring old state failed with %i\n", ret);
        } else {
                /*
                 * The display has been reset as well,
                 * so need a full re-initialization.
                 */
                intel_pps_unlock_regs_wa(dev_priv);
                intel_modeset_init_hw(dev_priv);
                intel_init_clock_gating(dev_priv);
                intel_hpd_init(dev_priv);

                ret = __intel_display_resume(dev, state, ctx);
                if (ret)
                        drm_err(&dev_priv->drm,
                                "Restoring old state failed with %i\n", ret);

                intel_hpd_poll_disable(dev_priv);
        }

        drm_atomic_state_put(state);
unlock:
        drm_modeset_drop_locks(ctx);
        drm_modeset_acquire_fini(ctx);
        mutex_unlock(&dev->mode_config.mutex);

        clear_bit_unlock(I915_RESET_MODESET, &to_gt(dev_priv)->reset.flags);
}

static void icl_set_pipe_chicken(const struct intel_crtc_state *crtc_state)
{
        struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
        struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
        enum pipe pipe = crtc->pipe;
        u32 tmp;

        tmp = intel_de_read(dev_priv, PIPE_CHICKEN(pipe));

        /*
         * Display WA #1153: icl
         * enable hardware to bypass the alpha math
         * and rounding for per-pixel values 00 and 0xff
         */
        tmp |= PER_PIXEL_ALPHA_BYPASS_EN;
        /*
         * Display WA # 1605353570: icl
         * Set the pixel rounding bit to 1 for allowing
         * passthrough of Frame buffer pixels unmodified
         * across pipe
         */
        tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU;

        /*
         * Underrun recovery must always be disabled on display 13+.
         * DG2 chicken bit meaning is inverted compared to other platforms.
         */
        if (IS_DG2(dev_priv))
                tmp &= ~UNDERRUN_RECOVERY_ENABLE_DG2;
        else if (DISPLAY_VER(dev_priv) >= 13)
                tmp |= UNDERRUN_RECOVERY_DISABLE_ADLP;

        /* Wa_14010547955:dg2 */
        if (IS_DG2_DISPLAY_STEP(dev_priv, STEP_B0, STEP_FOREVER))
                tmp |= DG2_RENDER_CCSTAG_4_3_EN;

        intel_de_write(dev_priv, PIPE_CHICKEN(pipe), tmp);

}

bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
{
        struct drm_crtc *crtc;
        bool cleanup_done;

        drm_for_each_crtc(crtc, &dev_priv->drm) {
                struct drm_crtc_commit *commit;
                spin_lock(&crtc->commit_lock);
                commit = list_first_entry_or_null(&crtc->commit_list,
                                                  struct drm_crtc_commit, commit_entry);
                cleanup_done = commit ?
                        try_wait_for_completion(&commit->cleanup_done) : true;
                spin_unlock(&crtc->commit_lock);

                if (cleanup_done)
                        continue;

                intel_crtc_wait_for_next_vblank(to_intel_crtc(crtc));

                return true;
        }

        return false;
}

/*
 * Finds the encoder associated with the given CRTC. This can only be
 * used when we know that the CRTC isn't feeding multiple encoders!
 */
struct intel_encoder *
intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
                           const struct intel_crtc_state *crtc_state)
{
        const struct drm_connector_state *connector_state;
        const struct drm_connector *connector;
        struct intel_encoder *encoder = NULL;
        struct intel_crtc *master_crtc;
        int num_encoders = 0;
        int i;

        master_crtc = intel_master_crtc(crtc_state);

        for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
                if (connector_state->crtc != &master_crtc->base)
                        continue;

                encoder = to_intel_encoder(connector_state->best_encoder);
                num_encoders++;
        }

        drm_WARN(encoder->base.dev, num_encoders != 1,
                 "%d encoders for pipe %c\n",
                 num_encoders, pipe_name(master_crtc->pipe));

        return encoder;
}

static void cpt_verify_modeset(struct drm_i915_private *dev_priv,
                               enum pipe pipe)
{
        i915_reg_t dslreg = PIPEDSL(pipe);
        u32 temp;

        temp = intel_de_read(dev_priv, dslreg);
        udelay(500);
        if (wait_for(intel_de_read(dev_priv, dslreg) != temp, 5)) {
                if (wait_for(intel_de_read(dev_priv, dslreg) != temp, 5))
                        drm_err(&dev_priv->drm,
                                "mode set failed: pipe %c stuck\n",
                                pipe_name(pipe));
        }
}

static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state)
{
        struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
        struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
        const struct drm_rect *dst = &crtc_state->pch_pfit.dst;
        enum pipe pipe = crtc->pipe;
        int width = drm_rect_width(dst);
        int height = drm_rect_height(dst);
        int x = dst->x1;
        int y = dst->y1;

        if (!crtc_state->pch_pfit.enabled)
                return;

        /* Force use of hard-coded filter coefficients
         * as some pre-programmed values are broken,
         * e.g. x201.
         */
        if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
                intel_de_write(dev_priv, PF_CTL(pipe), PF_ENABLE |
                               PF_FILTER_MED_3x3 | PF_PIPE_SEL_IVB(pipe));
        else
                intel_de_write(dev_priv, PF_CTL(pipe), PF_ENABLE |
                               PF_FILTER_MED_3x3);
        intel_de_write(dev_priv, PF_WIN_POS(pipe), x << 16 | y);
        intel_de_write(dev_priv, PF_WIN_SZ(pipe), width << 16 | height);
}

void hsw_enable_ips(const struct intel_crtc_state *crtc_state)
{
        struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
        struct drm_device *dev = crtc->base.dev;
        struct drm_i915_private *dev_priv = to_i915(dev);

        if (!crtc_state->ips_enabled)
                return;

        /*
         * We can only enable IPS after we enable a plane and wait for a vblank
         * This function is called from post_plane_update, which is run after
         * a vblank wait.
         */
        drm_WARN_ON(dev, !(crtc_state->active_planes & ~BIT(PLANE_CURSOR)));

        if (IS_BROADWELL(dev_priv)) {
                drm_WARN_ON(dev, sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL,
                                                         IPS_ENABLE | IPS_PCODE_CONTROL));
                /* Quoting Art Runyan: "its not safe to expect any particular
                 * value in IPS_CTL bit 31 after enabling IPS through the
                 * mailbox." Moreover, the mailbox may return a bogus state,
                 * so we need to just enable it and continue on.
                 */
        } else {
                intel_de_write(dev_priv, IPS_CTL, IPS_ENABLE);
                /* The bit only becomes 1 in the next vblank, so this wait here
                 * is essentially intel_wait_for_vblank. If we don't have this
                 * and don't wait for vblanks until the end of crtc_enable, then
                 * the HW state readout code will complain that the expected
                 * IPS_CTL value is not the one we read. */
                if (intel_de_wait_for_set(dev_priv, IPS_CTL, IPS_ENABLE, 50))
                        drm_err(&dev_priv->drm,
                                "Timed out waiting for IPS enable\n");
        }
}

void hsw_disable_ips(const struct intel_crtc_state *crtc_state)
{
        struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
        struct drm_device *dev = crtc->base.dev;
        struct drm_i915_private *dev_priv = to_i915(dev);

        if (!crtc_state->ips_enabled)
                return;

        if (IS_BROADWELL(dev_priv)) {
                drm_WARN_ON(dev,
                            sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
                /*
                 * Wait for PCODE to finish disabling IPS. The BSpec specified
                 * 42ms timeout value leads to occasional timeouts so use 100ms
                 * instead.
                 */
                if (intel_de_wait_for_clear(dev_priv, IPS_CTL, IPS_ENABLE, 100))
                        drm_err(&dev_priv->drm,
                                "Timed out waiting for IPS disable\n");
        } else {
                intel_de_write(dev_priv, IPS_CTL, 0);
                intel_de_posting_read(dev_priv, IPS_CTL);
        }

        /* We need to wait for a vblank before we can disable the plane. */
        intel_crtc_wait_for_next_vblank(crtc);
}

static void intel_crtc_dpms_overlay_disable(struct intel_crtc *crtc)
{
        if (crtc->overlay)
                (void) intel_overlay_switch_off(crtc->overlay);

        /* Let userspace switch the overlay on again. In most cases userspace
         * has to recompute where to put it anyway.
         */
}

static bool hsw_pre_update_disable_ips(const struct intel_crtc_state *old_crtc_state,
                                       const struct intel_crtc_state *new_crtc_state)
{
        struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
        struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

        if (!old_crtc_state->ips_enabled)
                return false;

        if (intel_crtc_needs_modeset(new_crtc_state))
                return true;

        /*
         * Workaround : Do not read or write the pipe palette/gamma data while
         * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
         *
         * Disable IPS before we program the LUT.
         */
        if (IS_HASWELL(dev_priv) &&
            (new_crtc_state->uapi.color_mgmt_changed ||
             new_crtc_state->update_pipe) &&
            new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
                return true;

        return !new_crtc_state->ips_enabled;
}

static bool hsw_post_update_enable_ips(const struct intel_crtc_state *old_crtc_state,
                                       const struct intel_crtc_state *new_crtc_state)
{
        struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
        struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

        if (!new_crtc_state->ips_enabled)
                return false;

        if (intel_crtc_needs_modeset(new_crtc_state))
                return true;

        /*
         * Workaround : Do not read or write the pipe palette/gamma data while
         * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
         *
         * Re-enable IPS after the LUT has been programmed.
         */
        if (IS_HASWELL(dev_priv) &&
            (new_crtc_state->uapi.color_mgmt_changed ||
             new_crtc_state->update_pipe) &&
            new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
                return true;

        /*
         * We can't read out IPS on broadwell, assume the worst and
         * forcibly enable IPS on the first fastset.
         */
        if (new_crtc_state->update_pipe && old_crtc_state->inherited)
                return true;

        return !old_crtc_state->ips_enabled;
}

static bool needs_nv12_wa(const struct intel_crtc_state *crtc_state)
{
        struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);

        if (!crtc_state->nv12_planes)
                return false;

        /* WA Display #0827: Gen9:all */
        if (DISPLAY_VER(dev_priv) == 9)
                return true;

        return false;
}

static bool needs_scalerclk_wa(const struct intel_crtc_state *crtc_state)
{
        struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);

        /* Wa_2006604312:icl,ehl */
        if (crtc_state->scaler_state.scaler_users > 0 && DISPLAY_VER(dev_priv) == 11)
                return true;

        return false;
}

static bool needs_cursorclk_wa(const struct intel_crtc_state *crtc_state)
{
        struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);

        /* Wa_1604331009:icl,jsl,ehl */
        if (is_hdr_mode(crtc_state) &&
            crtc_state->active_planes & BIT(PLANE_CURSOR) &&
            DISPLAY_VER(dev_priv) == 11)
                return true;

        return false;
}

static void intel_async_flip_vtd_wa(struct drm_i915_private *i915,
                                    enum pipe pipe, bool enable)
{
        if (DISPLAY_VER(i915) == 9) {
                /*
                 * "Plane N strech max must be programmed to 11b (x1)
                 *  when Async flips are enabled on that plane."
                 */
                intel_de_rmw(i915, CHICKEN_PIPESL_1(pipe),
                             SKL_PLANE1_STRETCH_MAX_MASK,
                             enable ? SKL_PLANE1_STRETCH_MAX_X1 : SKL_PLANE1_STRETCH_MAX_X8);
        } else {
                /* Also needed on HSW/BDW albeit undocumented */
                intel_de_rmw(i915, CHICKEN_PIPESL_1(pipe),
                             HSW_PRI_STRETCH_MAX_MASK,
                             enable ? HSW_PRI_STRETCH_MAX_X1 : HSW_PRI_STRETCH_MAX_X8);
        }
}

static bool needs_async_flip_vtd_wa(const struct intel_crtc_state *crtc_state)
{
        struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);

        return crtc_state->uapi.async_flip && intel_vtd_active(i915) &&
                (DISPLAY_VER(i915) == 9 || IS_BROADWELL(i915) || IS_HASWELL(i915));
}

static bool planes_enabling(const struct intel_crtc_state *old_crtc_state,
                            const struct intel_crtc_state *new_crtc_state)
{
        return (!old_crtc_state->active_planes || intel_crtc_needs_modeset(new_crtc_state)) &&
                new_crtc_state->active_planes;
}

static bool planes_disabling(const struct intel_crtc_state *old_crtc_state,
                             const struct intel_crtc_state *new_crtc_state)
{
        return old_crtc_state->active_planes &&
                (!new_crtc_state->active_planes || intel_crtc_needs_modeset(new_crtc_state));
}

static void intel_post_plane_update(struct intel_atomic_state *state,
                                    struct intel_crtc *crtc)
{
        struct drm_i915_private *dev_priv = to_i915(state->base.dev);
        const struct intel_crtc_state *old_crtc_state =
                intel_atomic_get_old_crtc_state(state, crtc);
        const struct intel_crtc_state *new_crtc_state =
                intel_atomic_get_new_crtc_state(state, crtc);
        enum pipe pipe = crtc->pipe;

        intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits);

        if (new_crtc_state->update_wm_post && new_crtc_state->hw.active)
                intel_update_watermarks(dev_priv);

        if (hsw_post_update_enable_ips(old_crtc_state, new_crtc_state))
                hsw_enable_ips(new_crtc_state);

        intel_fbc_post_update(state, crtc);
        intel_drrs_page_flip(state, crtc);

        if (needs_async_flip_vtd_wa(old_crtc_state) &&
            !needs_async_flip_vtd_wa(new_crtc_state))
                intel_async_flip_vtd_wa(dev_priv, pipe, false);

        if (needs_nv12_wa(old_crtc_state) &&
            !needs_nv12_wa(new_crtc_state))
                skl_wa_827(dev_priv, pipe, false);

        if (needs_scalerclk_wa(old_crtc_state) &&
            !needs_scalerclk_wa(new_crtc_state))
                icl_wa_scalerclkgating(dev_priv, pipe, false);

        if (needs_cursorclk_wa(old_crtc_state) &&
            !needs_cursorclk_wa(new_crtc_state))
                icl_wa_cursorclkgating(dev_priv, pipe, false);

}

static void intel_crtc_enable_flip_done(struct intel_atomic_state *state,
                                        struct intel_crtc *crtc)
{
        const struct intel_crtc_state *crtc_state =
                intel_atomic_get_new_crtc_state(state, crtc);
        u8 update_planes = crtc_state->update_planes;
        const struct intel_plane_state *plane_state;
        struct intel_plane *plane;
        int i;

        for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
                if (plane->enable_flip_done &&
                    plane->pipe == crtc->pipe &&
                    update_planes & BIT(plane->id))
                        plane->enable_flip_done(plane);
        }
}

static void intel_crtc_disable_flip_done(struct intel_atomic_state *state,
                                         struct intel_crtc *crtc)
{
        const struct intel_crtc_state *crtc_state =
                intel_atomic_get_new_crtc_state(state, crtc);
        u8 update_planes = crtc_state->update_planes;
        const struct intel_plane_state *plane_state;
        struct intel_plane *plane;
        int i;

        for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
                if (plane->disable_flip_done &&
                    plane->pipe == crtc->pipe &&
                    update_planes & BIT(plane->id))
                        plane->disable_flip_done(plane);
        }
}

static void intel_crtc_async_flip_disable_wa(struct intel_atomic_state *state,
                                             struct intel_crtc *crtc)
{
        const struct intel_crtc_state *old_crtc_state =
                intel_atomic_get_old_crtc_state(state, crtc);
        const struct intel_crtc_state *new_crtc_state =
                intel_atomic_get_new_crtc_state(state, crtc);
        u8 update_planes = new_crtc_state->update_planes;
        const struct intel_plane_state *old_plane_state;
        struct intel_plane *plane;
        bool need_vbl_wait = false;
        int i;

        for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) {
                if (plane->need_async_flip_disable_wa &&
                    plane->pipe == crtc->pipe &&
                    update_planes & BIT(plane->id)) {
                        /*
                         * Apart from the async flip bit we want to
                         * preserve the old state for the plane.
                         */
                        plane->async_flip(plane, old_crtc_state,
                                          old_plane_state, false);
                        need_vbl_wait = true;
                }
        }

        if (need_vbl_wait)
                intel_crtc_wait_for_next_vblank(crtc);
}

static void intel_pre_plane_update(struct intel_atomic_state *state,
                                   struct intel_crtc *crtc)
{
        struct drm_i915_private *dev_priv = to_i915(state->base.dev);
        const struct intel_crtc_state *old_crtc_state =
                intel_atomic_get_old_crtc_state(state, crtc);
        const struct intel_crtc_state *new_crtc_state =
                intel_atomic_get_new_crtc_state(state, crtc);
        enum pipe pipe = crtc->pipe;

        intel_psr_pre_plane_update(state, crtc);

        if (hsw_pre_update_disable_ips(old_crtc_state, new_crtc_state))
                hsw_disable_ips(old_crtc_state);

        if (intel_fbc_pre_update(state, crtc))
                intel_crtc_wait_for_next_vblank(crtc);

        if (!needs_async_flip_vtd_wa(old_crtc_state) &&
            needs_async_flip_vtd_wa(new_crtc_state))
                intel_async_flip_vtd_wa(dev_priv, pipe, true);

        /* Display WA 827 */
        if (!needs_nv12_wa(old_crtc_state) &&
            needs_nv12_wa(new_crtc_state))
                skl_wa_827(dev_priv, pipe, true);

        /* Wa_2006604312:icl,ehl */
        if (!needs_scalerclk_wa(old_crtc_state) &&
            needs_scalerclk_wa(new_crtc_state))
                icl_wa_scalerclkgating(dev_priv, pipe, true);

        /* Wa_1604331009:icl,jsl,ehl */
        if (!needs_cursorclk_wa(old_crtc_state) &&
            needs_cursorclk_wa(new_crtc_state))
                icl_wa_cursorclkgating(dev_priv, pipe, true);

        /*
         * Vblank time updates from the shadow to live plane control register
         * are blocked if the memory self-refresh mode is active at that
         * moment. So to make sure the plane gets truly disabled, disable
         * first the self-refresh mode. The self-refresh enable bit in turn
         * will be checked/applied by the HW only at the next frame start
         * event which is after the vblank start event, so we need to have a
         * wait-for-vblank between disabling the plane and the pipe.
         */
        if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active &&
            new_crtc_state->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
                intel_crtc_wait_for_next_vblank(crtc);

        /*
         * IVB workaround: must disable low power watermarks for at least
         * one frame before enabling scaling.  LP watermarks can be re-enabled
         * when scaling is disabled.
         *
         * WaCxSRDisabledForSpriteScaling:ivb
         */
        if (old_crtc_state->hw.active &&
            new_crtc_state->disable_lp_wm && ilk_disable_lp_wm(dev_priv))
                intel_crtc_wait_for_next_vblank(crtc);

        /*
         * If we're doing a modeset we don't need to do any
         * pre-vblank watermark programming here.
         */
        if (!intel_crtc_needs_modeset(new_crtc_state)) {
                /*
                 * For platforms that support atomic watermarks, program the
                 * 'intermediate' watermarks immediately.  On pre-gen9 platforms, these
                 * will be the intermediate values that are safe for both pre- and
                 * post- vblank; when vblank happens, the 'active' values will be set
                 * to the final 'target' values and we'll do this again to get the
                 * optimal watermarks.  For gen9+ platforms, the values we program here
                 * will be the final target values which will get automatically latched
                 * at vblank time; no further programming will be necessary.
                 *
                 * If a platform hasn't been transitioned to atomic watermarks yet,
                 * we'll continue to update watermarks the old way, if flags tell
                 * us to.
                 */
                if (!intel_initial_watermarks(state, crtc))
                        if (new_crtc_state->update_wm_pre)
                                intel_update_watermarks(dev_priv);
        }

        /*
         * Gen2 reports pipe underruns whenever all planes are disabled.
         * So disable underrun reporting before all the planes get disabled.
         *
         * We do this after .initial_watermarks() so that we have a
         * chance of catching underruns with the intermediate watermarks
         * vs. the old plane configuration.
         */
        if (DISPLAY_VER(dev_priv) == 2 && planes_disabling(old_crtc_state, new_crtc_state))
                intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);

        /*
         * WA for platforms where async address update enable bit
         * is double buffered and only latched at start of vblank.
         */
        if (old_crtc_state->uapi.async_flip && !new_crtc_state->uapi.async_flip)
                intel_crtc_async_flip_disable_wa(state, crtc);
}

static void intel_crtc_disable_planes(struct intel_atomic_state *state,
                                      struct intel_crtc *crtc)
{
        struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
        const struct intel_crtc_state *new_crtc_state =
                intel_atomic_get_new_crtc_state(state, crtc);
        unsigned int update_mask = new_crtc_state->update_planes;
        const struct intel_plane_state *old_plane_state;
        struct intel_plane *plane;
        unsigned fb_bits = 0;
        int i;

        intel_crtc_dpms_overlay_disable(crtc);

        for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) {
                if (crtc->pipe != plane->pipe ||
                    !(update_mask & BIT(plane->id)))
                        continue;

                intel_plane_disable_arm(plane, new_crtc_state);

                if (old_plane_state->uapi.visible)
                        fb_bits |= plane->frontbuffer_bit;
        }

        intel_frontbuffer_flip(dev_priv, fb_bits);
}

/*
 * intel_connector_primary_encoder - get the primary encoder for a connector
 * @connector: connector for which to return the encoder
 *
 * Returns the primary encoder for a connector. There is a 1:1 mapping from
 * all connectors to their encoder, except for DP-MST connectors which have
 * both a virtual and a primary encoder. These DP-MST primary encoders can be
 * pointed to by as many DP-MST connectors as there are pipes.
 */
static struct intel_encoder *
intel_connector_primary_encoder(struct intel_connector *connector)
{
        struct intel_encoder *encoder;

        if (connector->mst_port)
                return &dp_to_dig_port(connector->mst_port)->base;

        encoder = intel_attached_encoder(connector);
        drm_WARN_ON(connector->base.dev, !encoder);

        return encoder;
}

static void intel_encoders_update_prepare(struct intel_atomic_state *state)
{
        struct drm_i915_private *i915 = to_i915(state->base.dev);
        struct intel_crtc_state *new_crtc_state, *old_crtc_state;
        struct intel_crtc *crtc;
        struct drm_connector_state *new_conn_state;
        struct drm_connector *connector;
        int i;

        /*
         * Make sure the DPLL state is up-to-date for fastset TypeC ports after non-blocking commits.
         * TODO: Update the DPLL state for all cases in the encoder->update_prepare() hook.
         */
        if (i915->dpll.mgr) {
                for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
                        if (intel_crtc_needs_modeset(new_crtc_state))
                                continue;

                        new_crtc_state->shared_dpll = old_crtc_state->shared_dpll;
                        new_crtc_state->dpll_hw_state = old_crtc_state->dpll_hw_state;
                }
        }

        if (!state->modeset)
                return;

        for_each_new_connector_in_state(&state->base, connector, new_conn_state,
                                        i) {
                struct intel_connector *intel_connector;
                struct intel_encoder *encoder;
                struct intel_crtc *crtc;

                if (!intel_connector_needs_modeset(state, connector))
                        continue;

                intel_connector = to_intel_connector(connector);
                encoder = intel_connector_primary_encoder(intel_connector);
                if (!encoder->update_prepare)
                        continue;

                crtc = new_conn_state->crtc ?
                        to_intel_crtc(new_conn_state->crtc) : NULL;
                encoder->update_prepare(state, encoder, crtc);
        }
}

static void intel_encoders_update_complete(struct intel_atomic_state *state)
{
        struct drm_connector_state *new_conn_state;
        struct drm_connector *connector;
        int i;

        if (!state->modeset)
                return;

        for_each_new_connector_in_state(&state->base, connector, new_conn_state,
                                        i) {
                struct intel_connector *intel_connector;
                struct intel_encoder *encoder;
                struct intel_crtc *crtc;

                if (!intel_connector_needs_modeset(state, connector))
                        continue;

                intel_connector = to_intel_connector(connector);
                encoder = intel_connector_primary_encoder(intel_connector);
                if (!encoder->update_complete)
                        continue;

                crtc = new_conn_state->crtc ?
                        to_intel_crtc(new_conn_state->crtc) : NULL;
                encoder->update_complete(state, encoder, crtc);
        }
}

static void intel_encoders_pre_pll_enable(struct intel_atomic_state *state,
                                          struct intel_crtc *crtc)
{
        const struct intel_crtc_state *crtc_state =
                intel_atomic_get_new_crtc_state(state, crtc);
        const struct drm_connector_state *conn_state;
        struct drm_connector *conn;
        int i;

        for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
                struct intel_encoder *encoder =
                        to_intel_encoder(conn_state->best_encoder);

                if (conn_state->crtc != &crtc->base)
                        continue;

                if (encoder->pre_pll_enable)
                        encoder->pre_pll_enable(state, encoder,
                                                crtc_state, conn_state);
        }
}

static void intel_encoders_pre_enable(struct intel_atomic_state *state,
                                      struct intel_crtc *crtc)
{
        const struct intel_crtc_state *crtc_state =
                intel_atomic_get_new_crtc_state(state, crtc);
        const struct drm_connector_state *conn_state;
        struct drm_connector *conn;
        int i;

        for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
                struct intel_encoder *encoder =
                        to_intel_encoder(conn_state->best_encoder);

                if (conn_state->crtc != &crtc->base)
                        continue;

                if (encoder->pre_enable)
                        encoder->pre_enable(state, encoder,
                                            crtc_state, conn_state);
        }
}

static void intel_encoders_enable(struct intel_atomic_state *state,
                                  struct intel_crtc *crtc)
{
        const struct intel_crtc_state *crtc_state =
                intel_atomic_get_new_crtc_state(state, crtc);
        const struct drm_connector_state *conn_state;
        struct drm_connector *conn;
        int i;

        for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
                struct intel_encoder *encoder =
                        to_intel_encoder(conn_state->best_encoder);

                if (conn_state->crtc != &crtc->base)
                        continue;

                if (encoder->enable)
                        encoder->enable(state, encoder,
                                        crtc_state, conn_state);
                intel_opregion_notify_encoder(encoder, true);
        }
}

static void intel_encoders_disable(struct intel_atomic_state *state,
                                   struct intel_crtc *crtc)
{
        const struct intel_crtc_state *old_crtc_state =
                intel_atomic_get_old_crtc_state(state, crtc);
        const struct drm_connector_state *old_conn_state;
        struct drm_connector *conn;
        int i;

        for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
                struct intel_encoder *encoder =
                        to_intel_encoder(old_conn_state->best_encoder);

                if (old_conn_state->crtc != &crtc->base)
                        continue;

                intel_opregion_notify_encoder(encoder, false);
                if (encoder->disable)
                        encoder->disable(state, encoder,
                                         old_crtc_state, old_conn_state);
        }
}

static void intel_encoders_post_disable(struct intel_atomic_state *state,
                                        struct intel_crtc *crtc)
{
        const struct intel_crtc_state *old_crtc_state =
                intel_atomic_get_old_crtc_state(state, crtc);
        const struct drm_connector_state *old_conn_state;
        struct drm_connector *conn;
        int i;

        for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
                struct intel_encoder *encoder =
                        to_intel_encoder(old_conn_state->best_encoder);

                if (old_conn_state->crtc != &crtc->base)
                        continue;

                if (encoder->post_disable)
                        encoder->post_disable(state, encoder,
                                              old_crtc_state, old_conn_state);
        }
}

static void intel_encoders_post_pll_disable(struct intel_atomic_state *state,
                                            struct intel_crtc *crtc)
{
        const struct intel_crtc_state *old_crtc_state =
                intel_atomic_get_old_crtc_state(state, crtc);
        const struct drm_connector_state *old_conn_state;
        struct drm_connector *conn;
        int i;

        for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
                struct intel_encoder *encoder =
                        to_intel_encoder(old_conn_state->best_encoder);

                if (old_conn_state->crtc != &crtc->base)
                        continue;

                if (encoder->post_pll_disable)
                        encoder->post_pll_disable(state, encoder,
                                                  old_crtc_state, old_conn_state);
        }
}

static void intel_encoders_update_pipe(struct intel_atomic_state *state,
                                       struct intel_crtc *crtc)
{
        const struct intel_crtc_state *crtc_state =
                intel_atomic_get_new_crtc_state(state, crtc);
        const struct drm_connector_state *conn_state;
        struct drm_connector *conn;
        int i;

        for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
                struct intel_encoder *encoder =
                        to_intel_encoder(conn_state->best_encoder);

                if (conn_state->crtc != &crtc->base)
                        continue;

                if (encoder->update_pipe)
                        encoder->update_pipe(state, encoder,
                                             crtc_state, conn_state);
        }
}

static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_state)
{
        struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
        struct intel_plane *plane = to_intel_plane(crtc->base.primary);

        plane->disable_arm(plane, crtc_state);
}

static void ilk_crtc_enable(struct intel_atomic_state *state,
                            struct intel_crtc *crtc)
{
        const struct intel_crtc_state *new_crtc_state =
                intel_atomic_get_new_crtc_state(state, crtc);
        struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
        enum pipe pipe = crtc->pipe;

        if (drm_WARN_ON(&dev_priv->drm, crtc->active))
                return;

        /*
         * Sometimes spurious CPU pipe underruns happen during FDI
         * training, at least with VGA+HDMI cloning. Suppress them.
         *
         * On ILK we get an occasional spurious CPU pipe underruns
         * between eDP port A enable and vdd enable. Also PCH port
         * enable seems to result in the occasional CPU pipe underrun.
         *
         * Spurious PCH underruns also occur during PCH enabling.
         */
        intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
        intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);

        if (intel_crtc_has_dp_encoder(new_crtc_state))
                intel_dp_set_m_n(new_crtc_state, M1_N1);

        intel_set_transcoder_timings(new_crtc_state);
        intel_set_pipe_src_size(new_crtc_state);

        if (new_crtc_state->has_pch_encoder)
                intel_cpu_transcoder_set_m_n(new_crtc_state,
                                             &new_crtc_state->fdi_m_n, NULL);

        ilk_set_pipeconf(new_crtc_state);

        crtc->active = true;

        intel_encoders_pre_enable(state, crtc);

        if (new_crtc_state->has_pch_encoder) {
                /* Note: FDI PLL enabling _must_ be done before we enable the
                 * cpu pipes, hence this is separate from all the other fdi/pch
                 * enabling. */
                ilk_fdi_pll_enable(new_crtc_state);
        } else {
                assert_fdi_tx_disabled(dev_priv, pipe);
                assert_fdi_rx_disabled(dev_priv, pipe);
        }

        ilk_pfit_enable(new_crtc_state);

        /*
         * On ILK+ LUT must be loaded before the pipe is running but with
         * clocks enabled
         */
        intel_color_load_luts(new_crtc_state);
        intel_color_commit(new_crtc_state);
        /* update DSPCNTR to configure gamma for pipe bottom color */
        intel_disable_primary_plane(new_crtc_state);

        intel_initial_watermarks(state, crtc);
        intel_enable_transcoder(new_crtc_state);

        if (new_crtc_state->has_pch_encoder)
                ilk_pch_enable(state, crtc);

        intel_crtc_vblank_on(new_crtc_state);

        intel_encoders_enable(state, crtc);

        if (HAS_PCH_CPT(dev_priv))
                cpt_verify_modeset(dev_priv, pipe);

        /*
         * Must wait for vblank to avoid spurious PCH FIFO underruns.
         * And a second vblank wait is needed at least on ILK with
         * some interlaced HDMI modes. Let's do the double wait always
         * in case there are more corner cases we don't know about.
         */
        if (new_crtc_state->has_pch_encoder) {
                intel_crtc_wait_for_next_vblank(crtc);
                intel_crtc_wait_for_next_vblank(crtc);
        }
        intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
        intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
}

/* IPS only exists on ULT machines and is tied to pipe A. */
static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
{
        return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
}

static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv,
                                            enum pipe pipe, bool apply)
{
        u32 val = intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe));
        u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS;

        if (apply)
                val |= mask;
        else
                val &= ~mask;

        intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), val);
}

static void icl_pipe_mbus_enable(struct intel_crtc *crtc, bool joined_mbus)
{
        struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
        enum pipe pipe = crtc->pipe;
        u32 val;

        /* Wa_22010947358:adl-p */
        if (IS_ALDERLAKE_P(dev_priv))
                val = joined_mbus ? MBUS_DBOX_A_CREDIT(6) : MBUS_DBOX_A_CREDIT(4);
        else
                val = MBUS_DBOX_A_CREDIT(2);

        if (DISPLAY_VER(dev_priv) >= 12) {
                val |= MBUS_DBOX_BW_CREDIT(2);
                val |= MBUS_DBOX_B_CREDIT(12);
        } else {
                val |= MBUS_DBOX_BW_CREDIT(1);
                val |= MBUS_DBOX_B_CREDIT(8);
        }

        intel_de_write(dev_priv, PIPE_MBUS_DBOX_CTL(pipe), val);
}

static void hsw_set_linetime_wm(const struct intel_crtc_state *crtc_state)
{
        struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
        struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

        intel_de_write(dev_priv, WM_LINETIME(crtc->pipe),
                       HSW_LINETIME(crtc_state->linetime) |
                       HSW_IPS_LINETIME(crtc_state->ips_linetime));
}

static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state)
{
        struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
        struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
        i915_reg_t reg = CHICKEN_TRANS(crtc_state->cpu_transcoder);
        u32 val;

        val = intel_de_read(dev_priv, reg);
        val &= ~HSW_FRAME_START_DELAY_MASK;
        val |= HSW_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
        intel_de_write(dev_priv, reg, val);
}

static void icl_ddi_bigjoiner_pre_enable(struct intel_atomic_state *state,
                                         const struct intel_crtc_state *crtc_state)
{
        struct drm_i915_private *dev_priv = to_i915(state->base.dev);
        struct intel_crtc_state *master_crtc_state;
        struct intel_crtc *master_crtc;
        struct drm_connector_state *conn_state;
        struct drm_connector *conn;
        struct intel_encoder *encoder = NULL;
        int i;

        master_crtc = intel_master_crtc(crtc_state);
        master_crtc_state = intel_atomic_get_new_crtc_state(state, master_crtc);

        for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
                if (conn_state->crtc != &master_crtc->base)
                        continue;

                encoder = to_intel_encoder(conn_state->best_encoder);
                break;
        }

        /*
         * Enable sequence steps 1-7 on bigjoiner master
         */
        if (crtc_state->bigjoiner_slave)
                intel_encoders_pre_pll_enable(state, master_crtc);

        if (crtc_state->shared_dpll)
                intel_enable_shared_dpll(crtc_state);

        if (crtc_state->bigjoiner_slave)
                intel_encoders_pre_enable(state, master_crtc);

        /* need to enable VDSC, which we skipped in pre-enable */
        intel_dsc_enable(crtc_state);

        if (DISPLAY_VER(dev_priv) >= 13)
                intel_uncompressed_joiner_enable(crtc_state);
}

static void hsw_crtc_enable(struct intel_atomic_state *state,
                            struct intel_crtc *crtc)
{
        const struct intel_crtc_state *new_crtc_state =
                intel_atomic_get_new_crtc_state(state, crtc);
        struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
        enum pipe pipe = crtc->pipe, hsw_workaround_pipe;
        enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
        bool psl_clkgate_wa;

        if (drm_WARN_ON(&dev_priv->drm, crtc->active))
                return;

        if (!new_crtc_state->bigjoiner) {
                intel_encoders_pre_pll_enable(state, crtc);

                if (new_crtc_state->shared_dpll)
                        intel_enable_shared_dpll(new_crtc_state);

                intel_encoders_pre_enable(state, crtc);
        } else {
                icl_ddi_bigjoiner_pre_enable(state, new_crtc_state);
        }

        intel_set_pipe_src_size(new_crtc_state);
        if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
                bdw_set_pipemisc(new_crtc_state);

        if (!new_crtc_state->bigjoiner_slave && !transcoder_is_dsi(cpu_transcoder)) {
                intel_set_transcoder_timings(new_crtc_state);

                if (cpu_transcoder != TRANSCODER_EDP)
                        intel_de_write(dev_priv, PIPE_MULT(cpu_transcoder),
                                       new_crtc_state->pixel_multiplier - 1);

                if (new_crtc_state->has_pch_encoder)
                        intel_cpu_transcoder_set_m_n(new_crtc_state,
                                                     &new_crtc_state->fdi_m_n, NULL);

                hsw_set_frame_start_delay(new_crtc_state);

                hsw_set_transconf(new_crtc_state);
        }

        crtc->active = true;

        /* Display WA #1180: WaDisableScalarClockGating: glk */
        psl_clkgate_wa = DISPLAY_VER(dev_priv) == 10 &&
                new_crtc_state->pch_pfit.enabled;
        if (psl_clkgate_wa)
                glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true);

        if (DISPLAY_VER(dev_priv) >= 9)
                skl_pfit_enable(new_crtc_state);
        else
                ilk_pfit_enable(new_crtc_state);

        /*
         * On ILK+ LUT must be loaded before the pipe is running but with
         * clocks enabled
         */
        intel_color_load_luts(new_crtc_state);
        intel_color_commit(new_crtc_state);
        /* update DSPCNTR to configure gamma/csc for pipe bottom color */
        if (DISPLAY_VER(dev_priv) < 9)
                intel_disable_primary_plane(new_crtc_state);

        hsw_set_linetime_wm(new_crtc_state);

        if (DISPLAY_VER(dev_priv) >= 11)
                icl_set_pipe_chicken(new_crtc_state);

        intel_initial_watermarks(state, crtc);

        if (DISPLAY_VER(dev_priv) >= 11) {
                const struct intel_dbuf_state *dbuf_state =
                                intel_atomic_get_new_dbuf_state(state);

                icl_pipe_mbus_enable(crtc, dbuf_state->joined_mbus);
        }

        if (new_crtc_state->bigjoiner_slave)
                intel_crtc_vblank_on(new_crtc_state);

        intel_encoders_enable(state, crtc);

        if (psl_clkgate_wa) {
                intel_crtc_wait_for_next_vblank(crtc);
                glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false);
        }

        /* If we change the relative order between pipe/planes enabling, we need
         * to change the workaround. */
        hsw_workaround_pipe = new_crtc_state->hsw_workaround_pipe;
        if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
                struct intel_crtc *wa_crtc;

                wa_crtc = intel_crtc_for_pipe(dev_priv, hsw_workaround_pipe);

                intel_crtc_wait_for_next_vblank(wa_crtc);
                intel_crtc_wait_for_next_vblank(wa_crtc);
        }
}

void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state)
{
        struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
        struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
        enum pipe pipe = crtc->pipe;

        /* To avoid upsetting the power well on haswell only disable the pfit if
         * it's in use. The hw state code will make sure we get this right. */
        if (!old_crtc_state->pch_pfit.enabled)
                return;

        intel_de_write(dev_priv, PF_CTL(pipe), 0);
        intel_de_write(dev_priv, PF_WIN_POS(pipe), 0);
        intel_de_write(dev_priv, PF_WIN_SZ(pipe), 0);
}

static void ilk_crtc_disable(struct intel_atomic_state *state,
                             struct intel_crtc *crtc)
{
        const struct intel_crtc_state *old_crtc_state =
                intel_atomic_get_old_crtc_state(state, crtc);
        struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
        enum pipe pipe = crtc->pipe;

        /*
         * Sometimes spurious CPU pipe underruns happen when the
         * pipe is already disabled, but FDI RX/TX is still enabled.
         * Happens at least with VGA+HDMI cloning. Suppress them.
         */
        intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
        intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);

        intel_encoders_disable(state, crtc);

        intel_crtc_vblank_off(old_crtc_state);

        intel_disable_transcoder(old_crtc_state);

        ilk_pfit_disable(old_crtc_state);

        if (old_crtc_state->has_pch_encoder)
                ilk_pch_disable(state, crtc);

        intel_encoders_post_disable(state, crtc);

        if (old_crtc_state->has_pch_encoder)
                ilk_pch_post_disable(state, crtc);

        intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
        intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
}

static void hsw_crtc_disable(struct intel_atomic_state *state,
                             struct intel_crtc *crtc)
{
        const struct intel_crtc_state *old_crtc_state =
                intel_atomic_get_old_crtc_state(state, crtc);

        /*
         * FIXME collapse everything to one hook.
         * Need care with mst->ddi interactions.
         */
        if (!old_crtc_state->bigjoiner_slave) {
                intel_encoders_disable(state, crtc);
                intel_encoders_post_disable(state, crtc);
        }
}

static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
{
        struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
        struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

        if (!crtc_state->gmch_pfit.control)
                return;

        /*
         * The panel fitter should only be adjusted whilst the pipe is disabled,
         * according to register description and PRM.
         */
        drm_WARN_ON(&dev_priv->drm,
                    intel_de_read(dev_priv, PFIT_CONTROL) & PFIT_ENABLE);
        assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder);

        intel_de_write(dev_priv, PFIT_PGM_RATIOS,
                       crtc_state->gmch_pfit.pgm_ratios);
        intel_de_write(dev_priv, PFIT_CONTROL, crtc_state->gmch_pfit.control);

        /* Border color in case we don't scale up to the full screen. Black by
         * default, change to something else for debugging. */
        intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0);
}

bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
{
        if (phy == PHY_NONE)
                return false;
        else if (IS_DG2(dev_priv))
                /*
                 * DG2 outputs labelled as "combo PHY" in the bspec use
                 * SNPS PHYs with completely different programming,
                 * hence we always return false here.
                 */
                return false;
        else if (IS_ALDERLAKE_S(dev_priv))
                return phy <= PHY_E;
        else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
                return phy <= PHY_D;
        else if (IS_JSL_EHL(dev_priv))
                return phy <= PHY_C;
        else if (DISPLAY_VER(dev_priv) >= 11)
                return phy <= PHY_B;
        else
                return false;
}

bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
{
        if (IS_DG2(dev_priv))
                /* DG2's "TC1" output uses a SNPS PHY */
                return false;
        else if (IS_ALDERLAKE_P(dev_priv))
                return phy >= PHY_F && phy <= PHY_I;
        else if (IS_TIGERLAKE(dev_priv))
                return phy >= PHY_D && phy <= PHY_I;
        else if (IS_ICELAKE(dev_priv))
                return phy >= PHY_C && phy <= PHY_F;
        else
                return false;
}

bool intel_phy_is_snps(struct drm_i915_private *dev_priv, enum phy phy)
{
        if (phy == PHY_NONE)
                return false;
        else if (IS_DG2(dev_priv))
                /*
                 * All four "combo" ports and the TC1 port (PHY E) use
                 * Synopsis PHYs.
                 */
                return phy <= PHY_E;

        return false;
}

enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
{
        if (DISPLAY_VER(i915) >= 13 && port >= PORT_D_XELPD)
                return PHY_D + port - PORT_D_XELPD;
        else if (DISPLAY_VER(i915) >= 13 && port >= PORT_TC1)
                return PHY_F + port - PORT_TC1;
        else if (IS_ALDERLAKE_S(i915) && port >= PORT_TC1)
                return PHY_B + port - PORT_TC1;
        else if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_TC1)
                return PHY_C + port - PORT_TC1;
        else if (IS_JSL_EHL(i915) && port == PORT_D)
                return PHY_A;

        return PHY_A + port - PORT_A;
}

enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
{
        if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port)))
                return TC_PORT_NONE;

        if (DISPLAY_VER(dev_priv) >= 12)
                return TC_PORT_1 + port - PORT_TC1;
        else
                return TC_PORT_1 + port - PORT_C;
}

enum intel_display_power_domain intel_port_to_power_domain(enum port port)
{
        switch (port) {
        case PORT_A:
                return POWER_DOMAIN_PORT_DDI_A_LANES;
        case PORT_B:
                return POWER_DOMAIN_PORT_DDI_B_LANES;
        case PORT_C:
                return POWER_DOMAIN_PORT_DDI_C_LANES;
        case PORT_D:
                return POWER_DOMAIN_PORT_DDI_D_LANES;
        case PORT_E:
                return POWER_DOMAIN_PORT_DDI_E_LANES;
        case PORT_F:
                return POWER_DOMAIN_PORT_DDI_F_LANES;
        case PORT_G:
                return POWER_DOMAIN_PORT_DDI_G_LANES;
        case PORT_H:
                return POWER_DOMAIN_PORT_DDI_H_LANES;
        case PORT_I:
                return POWER_DOMAIN_PORT_DDI_I_LANES;
        default:
                MISSING_CASE(port);
                return POWER_DOMAIN_PORT_OTHER;
        }
}

enum intel_display_power_domain
intel_aux_power_domain(struct intel_digital_port *dig_port)
{
        if (intel_tc_port_in_tbt_alt_mode(dig_port)) {
                switch (dig_port->aux_ch) {
                case AUX_CH_C:
                        return POWER_DOMAIN_AUX_C_TBT;
                case AUX_CH_D:
                        return POWER_DOMAIN_AUX_D_TBT;
                case AUX_CH_E:
                        return POWER_DOMAIN_AUX_E_TBT;
                case AUX_CH_F:
                        return POWER_DOMAIN_AUX_F_TBT;
                case AUX_CH_G:
                        return POWER_DOMAIN_AUX_G_TBT;
                case AUX_CH_H:
                        return POWER_DOMAIN_AUX_H_TBT;
                case AUX_CH_I:
                        return POWER_DOMAIN_AUX_I_TBT;
                default:
                        MISSING_CASE(dig_port->aux_ch);
                        return POWER_DOMAIN_AUX_C_TBT;
                }
        }

        return intel_legacy_aux_to_power_domain(dig_port->aux_ch);
}

/*
 * Converts aux_ch to power_domain without caring about TBT ports for that use
 * intel_aux_power_domain()
 */
enum intel_display_power_domain
intel_legacy_aux_to_power_domain(enum aux_ch aux_ch)
{
        switch (aux_ch) {
        case AUX_CH_A:
                return POWER_DOMAIN_AUX_A;
        case AUX_CH_B:
                return POWER_DOMAIN_AUX_B;
        case AUX_CH_C:
                return POWER_DOMAIN_AUX_C;
        case AUX_CH_D:
                return POWER_DOMAIN_AUX_D;
        case AUX_CH_E:
                return POWER_DOMAIN_AUX_E;
        case AUX_CH_F:
                return POWER_DOMAIN_AUX_F;
        case AUX_CH_G:
                return POWER_DOMAIN_AUX_G;
        case AUX_CH_H:
                return POWER_DOMAIN_AUX_H;
        case AUX_CH_I:
                return POWER_DOMAIN_AUX_I;
        default:
                MISSING_CASE(aux_ch);
                return POWER_DOMAIN_AUX_A;
        }
}

static u64 get_crtc_power_domains(struct intel_crtc_state *crtc_state)
{
        struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
        struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
        enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
        struct drm_encoder *encoder;
        enum pipe pipe = crtc->pipe;
        u64 mask;

        if (!crtc_state->hw.active)
                return 0;

        mask = BIT_ULL(POWER_DOMAIN_PIPE(pipe));
        mask |= BIT_ULL(POWER_DOMAIN_TRANSCODER(cpu_transcoder));
        if (crtc_state->pch_pfit.enabled ||
            crtc_state->pch_pfit.force_thru)
                mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));

        drm_for_each_encoder_mask(encoder, &dev_priv->drm,
                                  crtc_state->uapi.encoder_mask) {
                struct intel_encoder *intel_encoder = to_intel_encoder(encoder);

                mask |= BIT_ULL(intel_encoder->power_domain);
        }

        if (HAS_DDI(dev_priv) && crtc_state->has_audio)
                mask |= BIT_ULL(POWER_DOMAIN_AUDIO_MMIO);

        if (crtc_state->shared_dpll)
                mask |= BIT_ULL(POWER_DOMAIN_DISPLAY_CORE);

        if (crtc_state->dsc.compression_enable)
                mask |= BIT_ULL(intel_dsc_power_domain(crtc, cpu_transcoder));

        return mask;
}

static u64
modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state)
{
        struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
        struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
        enum intel_display_power_domain domain;
        u64 domains, new_domains, old_domains;

        domains = get_crtc_power_domains(crtc_state);

        new_domains = domains & ~crtc->enabled_power_domains.mask;
        old_domains = crtc->enabled_power_domains.mask & ~domains;

        for_each_power_domain(domain, new_domains)
                intel_display_power_get_in_set(dev_priv,
                                               &crtc->enabled_power_domains,
                                               domain);

        return old_domains;
}

static void modeset_put_crtc_power_domains(struct intel_crtc *crtc,
                                           u64 domains)
{
        intel_display_power_put_mask_in_set(to_i915(crtc->base.dev),
                                            &crtc->enabled_power_domains,
                                            domains);
}

static void valleyview_crtc_enable(struct intel_atomic_state *state,
                                   struct intel_crtc *crtc)
{
        const struct intel_crtc_state *new_crtc_state =
                intel_atomic_get_new_crtc_state(state, crtc);
        struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
        enum pipe pipe = crtc->pipe;

        if (drm_WARN_ON(&dev_priv->drm, crtc->active))
                return;

        if (intel_crtc_has_dp_encoder(new_crtc_state))
                intel_dp_set_m_n(new_crtc_state, M1_N1);

        intel_set_transcoder_timings(new_crtc_state);
        intel_set_pipe_src_size(new_crtc_state);

        if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
                intel_de_write(dev_priv, CHV_BLEND(pipe), CHV_BLEND_LEGACY);
                intel_de_write(dev_priv, CHV_CANVAS(pipe), 0);
        }

        i9xx_set_pipeconf(new_crtc_state);

        crtc->active = true;

        intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);

        intel_encoders_pre_pll_enable(state, crtc);

        if (IS_CHERRYVIEW(dev_priv))
                chv_enable_pll(new_crtc_state);
        else
                vlv_enable_pll(new_crtc_state);

        intel_encoders_pre_enable(state, crtc);

        i9xx_pfit_enable(new_crtc_state);

        intel_color_load_luts(new_crtc_state);
        intel_color_commit(new_crtc_state);
        /* update DSPCNTR to configure gamma for pipe bottom color */
        intel_disable_primary_plane(new_crtc_state);

        intel_initial_watermarks(state, crtc);
        intel_enable_transcoder(new_crtc_state);

        intel_crtc_vblank_on(new_crtc_state);

        intel_encoders_enable(state, crtc);
}

static void i9xx_crtc_enable(struct intel_atomic_state *state,
                             struct intel_crtc *crtc)
{
        const struct intel_crtc_state *new_crtc_state =
                intel_atomic_get_new_crtc_state(state, crtc);
        struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
        enum pipe pipe = crtc->pipe;

        if (drm_WARN_ON(&dev_priv->drm, crtc->active))
                return;

        if (intel_crtc_has_dp_encoder(new_crtc_state))
                intel_dp_set_m_n(new_crtc_state, M1_N1);

        intel_set_transcoder_timings(new_crtc_state);
        intel_set_pipe_src_size(new_crtc_state);

        i9xx_set_pipeconf(new_crtc_state);

        crtc->active = true;

        if (DISPLAY_VER(dev_priv) != 2)
                intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);

        intel_encoders_pre_enable(state, crtc);

        i9xx_enable_pll(new_crtc_state);

        i9xx_pfit_enable(new_crtc_state);

        intel_color_load_luts(new_crtc_state);
        intel_color_commit(new_crtc_state);
        /* update DSPCNTR to configure gamma for pipe bottom color */
        intel_disable_primary_plane(new_crtc_state);

        if (!intel_initial_watermarks(state, crtc))
                intel_update_watermarks(dev_priv);
        intel_enable_transcoder(new_crtc_state);

        intel_crtc_vblank_on(new_crtc_state);

        intel_encoders_enable(state, crtc);

        /* prevents spurious underruns */
        if (DISPLAY_VER(dev_priv) == 2)
                intel_crtc_wait_for_next_vblank(crtc);
}

static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
{
        struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
        struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

        if (!old_crtc_state->gmch_pfit.control)
                return;

        assert_transcoder_disabled(dev_priv, old_crtc_state->cpu_transcoder);

        drm_dbg_kms(&dev_priv->drm, "disabling pfit, current: 0x%08x\n",
                    intel_de_read(dev_priv, PFIT_CONTROL));
        intel_de_write(dev_priv, PFIT_CONTROL, 0);
}

static void i9xx_crtc_disable(struct intel_atomic_state *state,
                              struct intel_crtc *crtc)
{
        struct intel_crtc_state *old_crtc_state =
                intel_atomic_get_old_crtc_state(state, crtc);
        struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
        enum pipe pipe = crtc->pipe;

        /*
         * On gen2 planes are double buffered but the pipe isn't, so we must
         * wait for planes to fully turn off before disabling the pipe.
         */
        if (DISPLAY_VER(dev_priv) == 2)
                intel_crtc_wait_for_next_vblank(crtc);

        intel_encoders_disable(state, crtc);

        intel_crtc_vblank_off(old_crtc_state);

        intel_disable_transcoder(old_crtc_state);

        i9xx_pfit_disable(old_crtc_state);

        intel_encoders_post_disable(state, crtc);

        if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) {
                if (IS_CHERRYVIEW(dev_priv))
                        chv_disable_pll(dev_priv, pipe);
                else if (IS_VALLEYVIEW(dev_priv))
                        vlv_disable_pll(dev_priv, pipe);
                else
                        i9xx_disable_pll(old_crtc_state);
        }

        intel_encoders_post_pll_disable(state, crtc);

        if (DISPLAY_VER(dev_priv) != 2)
                intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);

        if (!dev_priv->wm_disp->initial_watermarks)
                intel_update_watermarks(dev_priv);

        /* clock the pipe down to 640x480@60 to potentially save power */
        if (IS_I830(dev_priv))
                i830_enable_pipe(dev_priv, pipe);
}

static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
                                        struct drm_modeset_acquire_ctx *ctx)
{
        struct intel_encoder *encoder;
        struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
        struct intel_bw_state *bw_state =
                to_intel_bw_state(dev_priv->bw_obj.state);
        struct intel_cdclk_state *cdclk_state =
                to_intel_cdclk_state(dev_priv->cdclk.obj.state);
        struct intel_dbuf_state *dbuf_state =
                to_intel_dbuf_state(dev_priv->dbuf.obj.state);
        struct intel_crtc_state *crtc_state =
                to_intel_crtc_state(crtc->base.state);
        struct intel_plane *plane;
        struct drm_atomic_state *state;
        struct intel_crtc_state *temp_crtc_state;
        enum pipe pipe = crtc->pipe;
        int ret;

        if (!crtc_state->hw.active)
                return;

        for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
                const struct intel_plane_state *plane_state =
                        to_intel_plane_state(plane->base.state);

                if (plane_state->uapi.visible)
                        intel_plane_disable_noatomic(crtc, plane);
        }

        state = drm_atomic_state_alloc(&dev_priv->drm);
        if (!state) {
                drm_dbg_kms(&dev_priv->drm,
                            "failed to disable [CRTC:%d:%s], out of memory",
                            crtc->base.base.id, crtc->base.name);
                return;
        }

        state->acquire_ctx = ctx;

        /* Everything's already locked, -EDEADLK can't happen. */
        temp_crtc_state = intel_atomic_get_crtc_state(state, crtc);
        ret = drm_atomic_add_affected_connectors(state, &crtc->base);

        drm_WARN_ON(&dev_priv->drm, IS_ERR(temp_crtc_state) || ret);

        dev_priv->display->crtc_disable(to_intel_atomic_state(state), crtc);

        drm_atomic_state_put(state);

        drm_dbg_kms(&dev_priv->drm,
                    "[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
                    crtc->base.base.id, crtc->base.name);

        crtc->active = false;
        crtc->base.enabled = false;

        drm_WARN_ON(&dev_priv->drm,
                    drm_atomic_set_mode_for_crtc(&crtc_state->uapi, NULL) < 0);
        crtc_state->uapi.active = false;
        crtc_state->uapi.connector_mask = 0;
        crtc_state->uapi.encoder_mask = 0;
        intel_crtc_free_hw_state(crtc_state);
        memset(&crtc_state->hw, 0, sizeof(crtc_state->hw));

        for_each_encoder_on_crtc(&dev_priv->drm, &crtc->base, encoder)
                encoder->base.crtc = NULL;

        intel_fbc_disable(crtc);
        intel_update_watermarks(dev_priv);
        intel_disable_shared_dpll(crtc_state);

        intel_display_power_put_all_in_set(dev_priv, &crtc->enabled_power_domains);

        cdclk_state->min_cdclk[pipe] = 0;
        cdclk_state->min_voltage_level[pipe] = 0;
        cdclk_state->active_pipes &= ~BIT(pipe);

        dbuf_state->active_pipes &= ~BIT(pipe);

        bw_state->data_rate[pipe] = 0;
        bw_state->num_active_planes[pipe] = 0;
}

/*
 * turn all crtc's off, but do not adjust state
 * This has to be paired with a call to intel_modeset_setup_hw_state.
 */
int intel_display_suspend(struct drm_device *dev)
{
        struct drm_i915_private *dev_priv = to_i915(dev);
        struct drm_atomic_state *state;
        int ret;

        if (!HAS_DISPLAY(dev_priv))
                return 0;

        state = drm_atomic_helper_suspend(dev);
        ret = PTR_ERR_OR_ZERO(state);
        if (ret)
                drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n",
                        ret);
        else
                dev_priv->modeset_restore_state = state;
        return ret;
}

void intel_encoder_destroy(struct drm_encoder *encoder)
{
        struct intel_encoder *intel_encoder = to_intel_encoder(encoder);

        drm_encoder_cleanup(encoder);
        kfree(intel_encoder);
}

/* Cross check the actual hw state with our own modeset state tracking (and it's
 * internal consistency). */
static void intel_connector_verify_state(struct intel_crtc_state *crtc_state,
                                         struct drm_connector_state *conn_state)
{
        struct intel_connector *connector = to_intel_connector(conn_state->connector);
        struct drm_i915_private *i915 = to_i915(connector->base.dev);

        drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n",
                    connector->base.base.id, connector->base.name);

        if (connector->get_hw_state(connector)) {
                struct intel_encoder *encoder = intel_attached_encoder(connector);

                I915_STATE_WARN(!crtc_state,
                         "connector enabled without attached crtc\n");

                if (!crtc_state)
                        return;

                I915_STATE_WARN(!crtc_state->hw.active,
                                "connector is active, but attached crtc isn't\n");

                if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
                        return;

                I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
                        "atomic encoder doesn't match attached encoder\n");

                I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
                        "attached encoder crtc differs from connector crtc\n");
        } else {
                I915_STATE_WARN(crtc_state && crtc_state->hw.active,
                                "attached crtc is active, but connector isn't\n");
                I915_STATE_WARN(!crtc_state && conn_state->best_encoder,
                        "best encoder set without crtc!\n");
        }
}

bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
{
        struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
        struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

        /* IPS only exists on ULT machines and is tied to pipe A. */
        if (!hsw_crtc_supports_ips(crtc))
                return false;

        if (!dev_priv->params.enable_ips)
                return false;

        if (crtc_state->pipe_bpp > 24)
                return false;

        /*
         * We compare against max which means we must take
         * the increased cdclk requirement into account when
         * calculating the new cdclk.
         *
         * Should measure whether using a lower cdclk w/o IPS
         */
        if (IS_BROADWELL(dev_priv) &&
            crtc_state->pixel_rate > dev_priv->max_cdclk_freq * 95 / 100)
                return false;

        return true;
}

static int hsw_compute_ips_config(struct intel_crtc_state *crtc_state)
{
        struct drm_i915_private *dev_priv =
                to_i915(crtc_state->uapi.crtc->dev);
        struct intel_atomic_state *state =
                to_intel_atomic_state(crtc_state->uapi.state);

        crtc_state->ips_enabled = false;

        if (!hsw_crtc_state_ips_capable(crtc_state))
                return 0;

        /*
         * When IPS gets enabled, the pipe CRC changes. Since IPS gets
         * enabled and disabled dynamically based on package C states,
         * user space can't make reliable use of the CRCs, so let's just
         * completely disable it.
         */
        if (crtc_state->crc_enabled)
                return 0;

        /* IPS should be fine as long as at least one plane is enabled. */
        if (!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)))
                return 0;

        if (IS_BROADWELL(dev_priv)) {
                const struct intel_cdclk_state *cdclk_state;

                cdclk_state = intel_atomic_get_cdclk_state(state);
                if (IS_ERR(cdclk_state))
                        return PTR_ERR(cdclk_state);

                /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
                if (crtc_state->pixel_rate > cdclk_state->logical.cdclk * 95 / 100)
                        return 0;
        }

        crtc_state->ips_enabled = true;

        return 0;
}

static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
{
        const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

        /* GDG double wide on either pipe, otherwise pipe A only */
        return DISPLAY_VER(dev_priv) < 4 &&
                (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
}

static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state)
{
        u32 pixel_rate = crtc_state->hw.pipe_mode.crtc_clock;
        struct drm_rect src;

        /*
         * We only use IF-ID interlacing. If we ever use
         * PF-ID we'll need to adjust the pixel_rate here.
         */

        if (!crtc_state->pch_pfit.enabled)
                return pixel_rate;

        drm_rect_init(&src, 0, 0,
                      crtc_state->pipe_src_w << 16,
                      crtc_state->pipe_src_h << 16);

        return intel_adjusted_rate(&src, &crtc_state->pch_pfit.dst,
                                   pixel_rate);
}

static void intel_mode_from_crtc_timings(struct drm_display_mode *mode,
                                         const struct drm_display_mode *timings)
{
        mode->hdisplay = timings->crtc_hdisplay;
        mode->htotal = timings->crtc_htotal;
        mode->hsync_start = timings->crtc_hsync_start;
        mode->hsync_end = timings->crtc_hsync_end;

        mode->vdisplay = timings->crtc_vdisplay;
        mode->vtotal = timings->crtc_vtotal;
        mode->vsync_start = timings->crtc_vsync_start;
        mode->vsync_end = timings->crtc_vsync_end;

        mode->flags = timings->flags;
        mode->type = DRM_MODE_TYPE_DRIVER;

        mode->clock = timings->crtc_clock;

        drm_mode_set_name(mode);
}

static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
{
        struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);

        if (HAS_GMCH(dev_priv))
                /* FIXME calculate proper pipe pixel rate for GMCH pfit */
                crtc_state->pixel_rate =
                        crtc_state->hw.pipe_mode.crtc_clock;
        else
                crtc_state->pixel_rate =
                        ilk_pipe_pixel_rate(crtc_state);
}

static void intel_crtc_readout_derived_state(struct intel_crtc_state *crtc_state)
{
        struct drm_display_mode *mode = &crtc_state->hw.mode;
        struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
        struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;

        drm_mode_copy(pipe_mode, adjusted_mode);

        if (crtc_state->bigjoiner) {
                /*
                 * transcoder is programmed to the full mode,
                 * but pipe timings are half of the transcoder mode
                 */
                pipe_mode->crtc_hdisplay /= 2;
                pipe_mode->crtc_hblank_start /= 2;
                pipe_mode->crtc_hblank_end /= 2;
                pipe_mode->crtc_hsync_start /= 2;
                pipe_mode->crtc_hsync_end /= 2;
                pipe_mode->crtc_htotal /= 2;
                pipe_mode->crtc_clock /= 2;
        }

        if (crtc_state->splitter.enable) {
                int n = crtc_state->splitter.link_count;
                int overlap = crtc_state->splitter.pixel_overlap;

                /*
                 * eDP MSO uses segment timings from EDID for transcoder
                 * timings, but full mode for everything else.
                 *
                 * h_full = (h_segment - pixel_overlap) * link_count
                 */
                pipe_mode->crtc_hdisplay = (pipe_mode->crtc_hdisplay - overlap) * n;
                pipe_mode->crtc_hblank_start = (pipe_mode->crtc_hblank_start - overlap) * n;
                pipe_mode->crtc_hblank_end = (pipe_mode->crtc_hblank_end - overlap) * n;
                pipe_mode->crtc_hsync_start = (pipe_mode->crtc_hsync_start - overlap) * n;
                pipe_mode->crtc_hsync_end = (pipe_mode->crtc_hsync_end - overlap) * n;
                pipe_mode->crtc_htotal = (pipe_mode->crtc_htotal - overlap) * n;
                pipe_mode->crtc_clock *= n;

                intel_mode_from_crtc_timings(pipe_mode, pipe_mode);
                intel_mode_from_crtc_timings(adjusted_mode, pipe_mode);
        } else {
                intel_mode_from_crtc_timings(pipe_mode, pipe_mode);
                intel_mode_from_crtc_timings(adjusted_mode, adjusted_mode);
        }

        intel_crtc_compute_pixel_rate(crtc_state);

        drm_mode_copy(mode, adjusted_mode);
        mode->hdisplay = crtc_state->pipe_src_w << crtc_state->bigjoiner;
        mode->vdisplay = crtc_state->pipe_src_h;
}

static void intel_encoder_get_config(struct intel_encoder *encoder,
                                     struct intel_crtc_state *crtc_state)
{
        encoder->get_config(encoder, crtc_state);

        intel_crtc_readout_derived_state(crtc_state);
}

static int intel_crtc_compute_config(struct intel_crtc *crtc,
                                     struct intel_crtc_state *pipe_config)
{
        struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
        struct drm_display_mode *pipe_mode = &pipe_config->hw.pipe_mode;
        int clock_limit = dev_priv->max_dotclk_freq;

        drm_mode_copy(pipe_mode, &pipe_config->hw.adjusted_mode);

        /* Adjust pipe_mode for bigjoiner, with half the horizontal mode */
        if (pipe_config->bigjoiner) {
                pipe_mode->crtc_clock /= 2;
                pipe_mode->crtc_hdisplay /= 2;
                pipe_mode->crtc_hblank_start /= 2;
                pipe_mode->crtc_hblank_end /= 2;
                pipe_mode->crtc_hsync_start /= 2;
                pipe_mode->crtc_hsync_end /= 2;
                pipe_mode->crtc_htotal /= 2;
                pipe_config->pipe_src_w /= 2;
        }

        if (pipe_config->splitter.enable) {
                int n = pipe_config->splitter.link_count;
                int overlap = pipe_config->splitter.pixel_overlap;

                pipe_mode->crtc_hdisplay = (pipe_mode->crtc_hdisplay - overlap) * n;
                pipe_mode->crtc_hblank_start = (pipe_mode->crtc_hblank_start - overlap) * n;
                pipe_mode->crtc_hblank_end = (pipe_mode->crtc_hblank_end - overlap) * n;
                pipe_mode->crtc_hsync_start = (pipe_mode->crtc_hsync_start - overlap) * n;
                pipe_mode->crtc_hsync_end = (pipe_mode->crtc_hsync_end - overlap) * n;
                pipe_mode->crtc_htotal = (pipe_mode->crtc_htotal - overlap) * n;
                pipe_mode->crtc_clock *= n;
        }

        intel_mode_from_crtc_timings(pipe_mode, pipe_mode);

        if (DISPLAY_VER(dev_priv) < 4) {
                clock_limit = dev_priv->max_cdclk_freq * 9 / 10;

                /*
                 * Enable double wide mode when the dot clock
                 * is > 90% of the (display) core speed.
                 */
                if (intel_crtc_supports_double_wide(crtc) &&