1
2#ifndef _INTEL_RINGBUFFER_H_
3#define _INTEL_RINGBUFFER_H_
4
5#include <asm/cacheflush.h>
6#include <drm/drm_util.h>
7
8#include <linux/hashtable.h>
9#include <linux/irq_work.h>
10#include <linux/random.h>
11#include <linux/seqlock.h>
12
13#include "i915_pmu.h"
14#include "i915_reg.h"
15#include "i915_request.h"
16#include "i915_selftest.h"
17#include "intel_engine_types.h"
18#include "intel_gt_types.h"
19#include "intel_timeline.h"
20#include "intel_workarounds.h"
21
22struct drm_printer;
23struct intel_context;
24struct intel_gt;
25struct lock_class_key;
26
27
28
29
30
31
32#define CACHELINE_BYTES 64
33#define CACHELINE_DWORDS (CACHELINE_BYTES / sizeof(u32))
34
35#define ENGINE_TRACE(e, fmt, ...) do { \
36 const struct intel_engine_cs *e__ __maybe_unused = (e); \
37 GEM_TRACE("%s %s: " fmt, \
38 dev_name(e__->i915->drm.dev), e__->name, \
39 ##__VA_ARGS__); \
40} while (0)
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55#define __ENGINE_REG_OP(op__, engine__, ...) \
56 intel_uncore_##op__((engine__)->uncore, __VA_ARGS__)
57
58#define __ENGINE_READ_OP(op__, engine__, reg__) \
59 __ENGINE_REG_OP(op__, (engine__), reg__((engine__)->mmio_base))
60
61#define ENGINE_READ16(...) __ENGINE_READ_OP(read16, __VA_ARGS__)
62#define ENGINE_READ(...) __ENGINE_READ_OP(read, __VA_ARGS__)
63#define ENGINE_READ_FW(...) __ENGINE_READ_OP(read_fw, __VA_ARGS__)
64#define ENGINE_POSTING_READ(...) __ENGINE_READ_OP(posting_read_fw, __VA_ARGS__)
65#define ENGINE_POSTING_READ16(...) __ENGINE_READ_OP(posting_read16, __VA_ARGS__)
66
67#define ENGINE_READ64(engine__, lower_reg__, upper_reg__) \
68 __ENGINE_REG_OP(read64_2x32, (engine__), \
69 lower_reg__((engine__)->mmio_base), \
70 upper_reg__((engine__)->mmio_base))
71
72#define ENGINE_READ_IDX(engine__, reg__, idx__) \
73 __ENGINE_REG_OP(read, (engine__), reg__((engine__)->mmio_base, (idx__)))
74
75#define __ENGINE_WRITE_OP(op__, engine__, reg__, val__) \
76 __ENGINE_REG_OP(op__, (engine__), reg__((engine__)->mmio_base), (val__))
77
78#define ENGINE_WRITE16(...) __ENGINE_WRITE_OP(write16, __VA_ARGS__)
79#define ENGINE_WRITE(...) __ENGINE_WRITE_OP(write, __VA_ARGS__)
80#define ENGINE_WRITE_FW(...) __ENGINE_WRITE_OP(write_fw, __VA_ARGS__)
81
82#define GEN6_RING_FAULT_REG_READ(engine__) \
83 intel_uncore_read((engine__)->uncore, RING_FAULT_REG(engine__))
84
85#define GEN6_RING_FAULT_REG_POSTING_READ(engine__) \
86 intel_uncore_posting_read((engine__)->uncore, RING_FAULT_REG(engine__))
87
88#define GEN6_RING_FAULT_REG_RMW(engine__, clear__, set__) \
89({ \
90 u32 __val; \
91\
92 __val = intel_uncore_read((engine__)->uncore, \
93 RING_FAULT_REG(engine__)); \
94 __val &= ~(clear__); \
95 __val |= (set__); \
96 intel_uncore_write((engine__)->uncore, RING_FAULT_REG(engine__), \
97 __val); \
98})
99
100
101
102
103
104static inline unsigned int
105execlists_num_ports(const struct intel_engine_execlists * const execlists)
106{
107 return execlists->port_mask + 1;
108}
109
110static inline struct i915_request *
111execlists_active(const struct intel_engine_execlists *execlists)
112{
113 struct i915_request * const *cur, * const *old, *active;
114
115 cur = READ_ONCE(execlists->active);
116 smp_rmb();
117 do {
118 old = cur;
119
120 active = READ_ONCE(*cur);
121 cur = READ_ONCE(execlists->active);
122
123 smp_rmb();
124 } while (unlikely(cur != old));
125
126 return active;
127}
128
129struct i915_request *
130execlists_unwind_incomplete_requests(struct intel_engine_execlists *execlists);
131
132static inline u32
133intel_read_status_page(const struct intel_engine_cs *engine, int reg)
134{
135
136 return READ_ONCE(engine->status_page.addr[reg]);
137}
138
139static inline void
140intel_write_status_page(struct intel_engine_cs *engine, int reg, u32 value)
141{
142
143
144
145
146
147 if (static_cpu_has(X86_FEATURE_CLFLUSH)) {
148 mb();
149 clflush(&engine->status_page.addr[reg]);
150 engine->status_page.addr[reg] = value;
151 clflush(&engine->status_page.addr[reg]);
152 mb();
153 } else {
154 WRITE_ONCE(engine->status_page.addr[reg], value);
155 }
156}
157
158
159
160
161
162
163
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168
169
170
171
172
173
174#define I915_GEM_HWS_PREEMPT 0x32
175#define I915_GEM_HWS_PREEMPT_ADDR (I915_GEM_HWS_PREEMPT * sizeof(u32))
176#define I915_GEM_HWS_SEQNO 0x40
177#define I915_GEM_HWS_SEQNO_ADDR (I915_GEM_HWS_SEQNO * sizeof(u32))
178#define I915_GEM_HWS_MIGRATE (0x42 * sizeof(u32))
179#define I915_GEM_HWS_PXP 0x60
180#define I915_GEM_HWS_PXP_ADDR (I915_GEM_HWS_PXP * sizeof(u32))
181#define I915_GEM_HWS_SCRATCH 0x80
182
183#define I915_HWS_CSB_BUF0_INDEX 0x10
184#define I915_HWS_CSB_WRITE_INDEX 0x1f
185#define ICL_HWS_CSB_WRITE_INDEX 0x2f
186
187void intel_engine_stop(struct intel_engine_cs *engine);
188void intel_engine_cleanup(struct intel_engine_cs *engine);
189
190int intel_engines_init_mmio(struct intel_gt *gt);
191int intel_engines_init(struct intel_gt *gt);
192
193void intel_engine_free_request_pool(struct intel_engine_cs *engine);
194
195void intel_engines_release(struct intel_gt *gt);
196void intel_engines_free(struct intel_gt *gt);
197
198int intel_engine_init_common(struct intel_engine_cs *engine);
199void intel_engine_cleanup_common(struct intel_engine_cs *engine);
200
201int intel_engine_resume(struct intel_engine_cs *engine);
202
203int intel_ring_submission_setup(struct intel_engine_cs *engine);
204
205int intel_engine_stop_cs(struct intel_engine_cs *engine);
206void intel_engine_cancel_stop_cs(struct intel_engine_cs *engine);
207
208void intel_engine_set_hwsp_writemask(struct intel_engine_cs *engine, u32 mask);
209
210u64 intel_engine_get_active_head(const struct intel_engine_cs *engine);
211u64 intel_engine_get_last_batch_head(const struct intel_engine_cs *engine);
212
213void intel_engine_get_instdone(const struct intel_engine_cs *engine,
214 struct intel_instdone *instdone);
215
216void intel_engine_init_execlists(struct intel_engine_cs *engine);
217
218bool intel_engine_irq_enable(struct intel_engine_cs *engine);
219void intel_engine_irq_disable(struct intel_engine_cs *engine);
220
221static inline void __intel_engine_reset(struct intel_engine_cs *engine,
222 bool stalled)
223{
224 if (engine->reset.rewind)
225 engine->reset.rewind(engine, stalled);
226 engine->serial++;
227}
228
229bool intel_engines_are_idle(struct intel_gt *gt);
230bool intel_engine_is_idle(struct intel_engine_cs *engine);
231
232void __intel_engine_flush_submission(struct intel_engine_cs *engine, bool sync);
233static inline void intel_engine_flush_submission(struct intel_engine_cs *engine)
234{
235 __intel_engine_flush_submission(engine, true);
236}
237
238void intel_engines_reset_default_submission(struct intel_gt *gt);
239
240bool intel_engine_can_store_dword(struct intel_engine_cs *engine);
241
242__printf(3, 4)
243void intel_engine_dump(struct intel_engine_cs *engine,
244 struct drm_printer *m,
245 const char *header, ...);
246void intel_engine_dump_active_requests(struct list_head *requests,
247 struct i915_request *hung_rq,
248 struct drm_printer *m);
249
250ktime_t intel_engine_get_busy_time(struct intel_engine_cs *engine,
251 ktime_t *now);
252
253struct i915_request *
254intel_engine_execlist_find_hung_request(struct intel_engine_cs *engine);
255
256u32 intel_engine_context_size(struct intel_gt *gt, u8 class);
257struct intel_context *
258intel_engine_create_pinned_context(struct intel_engine_cs *engine,
259 struct i915_address_space *vm,
260 unsigned int ring_size,
261 unsigned int hwsp,
262 struct lock_class_key *key,
263 const char *name);
264
265void intel_engine_destroy_pinned_context(struct intel_context *ce);
266
267#define ENGINE_PHYSICAL 0
268#define ENGINE_MOCK 1
269#define ENGINE_VIRTUAL 2
270
271static inline bool intel_engine_uses_guc(const struct intel_engine_cs *engine)
272{
273 return engine->gt->submission_method >= INTEL_SUBMISSION_GUC;
274}
275
276static inline bool
277intel_engine_has_preempt_reset(const struct intel_engine_cs *engine)
278{
279 if (!CONFIG_DRM_I915_PREEMPT_TIMEOUT)
280 return false;
281
282 return intel_engine_has_preemption(engine);
283}
284
285#define FORCE_VIRTUAL BIT(0)
286struct intel_context *
287intel_engine_create_virtual(struct intel_engine_cs **siblings,
288 unsigned int count, unsigned long flags);
289
290static inline struct intel_context *
291intel_engine_create_parallel(struct intel_engine_cs **engines,
292 unsigned int num_engines,
293 unsigned int width)
294{
295 GEM_BUG_ON(!engines[0]->cops->create_parallel);
296 return engines[0]->cops->create_parallel(engines, num_engines, width);
297}
298
299static inline bool
300intel_virtual_engine_has_heartbeat(const struct intel_engine_cs *engine)
301{
302
303
304
305
306
307
308 GEM_BUG_ON(!intel_engine_uses_guc(engine));
309
310 return intel_guc_virtual_engine_has_heartbeat(engine);
311}
312
313static inline bool
314intel_engine_has_heartbeat(const struct intel_engine_cs *engine)
315{
316 if (!CONFIG_DRM_I915_HEARTBEAT_INTERVAL)
317 return false;
318
319 if (intel_engine_is_virtual(engine))
320 return intel_virtual_engine_has_heartbeat(engine);
321 else
322 return READ_ONCE(engine->props.heartbeat_interval_ms);
323}
324
325static inline struct intel_engine_cs *
326intel_engine_get_sibling(struct intel_engine_cs *engine, unsigned int sibling)
327{
328 GEM_BUG_ON(!intel_engine_is_virtual(engine));
329 return engine->cops->get_sibling(engine, sibling);
330}
331
332static inline void
333intel_engine_set_hung_context(struct intel_engine_cs *engine,
334 struct intel_context *ce)
335{
336 engine->hung_ce = ce;
337}
338
339static inline void
340intel_engine_clear_hung_context(struct intel_engine_cs *engine)
341{
342 intel_engine_set_hung_context(engine, NULL);
343}
344
345static inline struct intel_context *
346intel_engine_get_hung_context(struct intel_engine_cs *engine)
347{
348 return engine->hung_ce;
349}
350
351#endif
352