LXR linux/drivers/gpu/drm/i915/gt/uc/intel_guc

   1// SPDX-License-Identifier: MIT
   2/*
   3 * Copyright © 2014-2019 Intel Corporation
   4 *
   5 * Authors:
   6 *    Vinit Azad <vinit.azad@intel.com>
   7 *    Ben Widawsky <ben@bwidawsk.net>
   8 *    Dave Gordon <david.s.gordon@intel.com>
   9 *    Alex Dai <yu.dai@intel.com>
  10 */
  11
  12#include "gt/intel_gt.h"
  13#include "intel_guc_fw.h"
  14#include "i915_drv.h"
  15
  16static void guc_prepare_xfer(struct intel_uncore *uncore)
  17{
  18        u32 shim_flags = GUC_DISABLE_SRAM_INIT_TO_ZEROES |
  19                         GUC_ENABLE_READ_CACHE_LOGIC |
  20                         GUC_ENABLE_MIA_CACHING |
  21                         GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA |
  22                         GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA |
  23                         GUC_ENABLE_MIA_CLOCK_GATING;
  24
  25        /* Must program this register before loading the ucode with DMA */
  26        intel_uncore_write(uncore, GUC_SHIM_CONTROL, shim_flags);
  27
  28        if (IS_GEN9_LP(uncore->i915))
  29                intel_uncore_write(uncore, GEN9LP_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
  30        else
  31                intel_uncore_write(uncore, GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
  32
  33        if (GRAPHICS_VER(uncore->i915) == 9) {
  34                /* DOP Clock Gating Enable for GuC clocks */
  35                intel_uncore_rmw(uncore, GEN7_MISCCPCTL,
  36                                 0, GEN8_DOP_CLOCK_GATE_GUC_ENABLE);
  37
  38                /* allows for 5us (in 10ns units) before GT can go to RC6 */
  39                intel_uncore_write(uncore, GUC_ARAT_C6DIS, 0x1FF);
  40        }
  41}
  42
  43static int guc_xfer_rsa_mmio(struct intel_uc_fw *guc_fw,
  44                             struct intel_uncore *uncore)
  45{
  46        u32 rsa[UOS_RSA_SCRATCH_COUNT];
  47        size_t copied;
  48        int i;
  49
  50        copied = intel_uc_fw_copy_rsa(guc_fw, rsa, sizeof(rsa));
  51        if (copied < sizeof(rsa))
  52                return -ENOMEM;
  53
  54        for (i = 0; i < UOS_RSA_SCRATCH_COUNT; i++)
  55                intel_uncore_write(uncore, UOS_RSA_SCRATCH(i), rsa[i]);
  56
  57        return 0;
  58}
  59
  60static int guc_xfer_rsa_vma(struct intel_uc_fw *guc_fw,
  61                            struct intel_uncore *uncore)
  62{
  63        struct intel_guc *guc = container_of(guc_fw, struct intel_guc, fw);
  64
  65        intel_uncore_write(uncore, UOS_RSA_SCRATCH(0),
  66                           intel_guc_ggtt_offset(guc, guc_fw->rsa_data));
  67
  68        return 0;
  69}
  70
  71/* Copy RSA signature from the fw image to HW for verification */
  72static int guc_xfer_rsa(struct intel_uc_fw *guc_fw,
  73                        struct intel_uncore *uncore)
  74{
  75        if (guc_fw->rsa_data)
  76                return guc_xfer_rsa_vma(guc_fw, uncore);
  77        else
  78                return guc_xfer_rsa_mmio(guc_fw, uncore);
  79}
  80
  81/*
  82 * Read the GuC status register (GUC_STATUS) and store it in the
  83 * specified location; then return a boolean indicating whether
  84 * the value matches either of two values representing completion
  85 * of the GuC boot process.
  86 *
  87 * This is used for polling the GuC status in a wait_for()
  88 * loop below.
  89 */
  90static inline bool guc_ready(struct intel_uncore *uncore, u32 *status)
  91{
  92        u32 val = intel_uncore_read(uncore, GUC_STATUS);
  93        u32 uk_val = val & GS_UKERNEL_MASK;
  94
  95        *status = val;
  96        return (uk_val == GS_UKERNEL_READY) ||
  97                ((val & GS_MIA_CORE_STATE) && (uk_val == GS_UKERNEL_LAPIC_DONE));
  98}
  99
 100static int guc_wait_ucode(struct intel_uncore *uncore)
 101{
 102        u32 status;
 103        int ret;
 104
 105        /*
 106         * Wait for the GuC to start up.
 107         * NB: Docs recommend not using the interrupt for completion.
 108         * Measurements indicate this should take no more than 20ms, so a
 109         * timeout here indicates that the GuC has failed and is unusable.
 110         * (Higher levels of the driver may decide to reset the GuC and
 111         * attempt the ucode load again if this happens.)
 112         */
 113        ret = wait_for(guc_ready(uncore, &status), 100);
 114        if (ret) {
 115                struct drm_device *drm = &uncore->i915->drm;
 116
 117                drm_dbg(drm, "GuC load failed: status = 0x%08X\n", status);
 118                drm_dbg(drm, "GuC load failed: status: Reset = %d, "
 119                        "BootROM = 0x%02X, UKernel = 0x%02X, "
 120                        "MIA = 0x%02X, Auth = 0x%02X\n",
 121                        REG_FIELD_GET(GS_MIA_IN_RESET, status),
 122                        REG_FIELD_GET(GS_BOOTROM_MASK, status),
 123                        REG_FIELD_GET(GS_UKERNEL_MASK, status),
 124                        REG_FIELD_GET(GS_MIA_MASK, status),
 125                        REG_FIELD_GET(GS_AUTH_STATUS_MASK, status));
 126
 127                if ((status & GS_BOOTROM_MASK) == GS_BOOTROM_RSA_FAILED) {
 128                        drm_dbg(drm, "GuC firmware signature verification failed\n");
 129                        ret = -ENOEXEC;
 130                }
 131
 132                if ((status & GS_UKERNEL_MASK) == GS_UKERNEL_EXCEPTION) {
 133                        drm_dbg(drm, "GuC firmware exception. EIP: %#x\n",
 134                                intel_uncore_read(uncore, SOFT_SCRATCH(13)));
 135                        ret = -ENXIO;
 136                }
 137        }
 138
 139        return ret;
 140}
 141
 142/**
 143 * intel_guc_fw_upload() - load GuC uCode to device
 144 * @guc: intel_guc structure
 145 *
 146 * Called from intel_uc_init_hw() during driver load, resume from sleep and
 147 * after a GPU reset.
 148 *
 149 * The firmware image should have already been fetched into memory, so only
 150 * check that fetch succeeded, and then transfer the image to the h/w.
 151 *
 152 * Return:      non-zero code on error
 153 */
 154int intel_guc_fw_upload(struct intel_guc *guc)
 155{
 156        struct intel_gt *gt = guc_to_gt(guc);
 157        struct intel_uncore *uncore = gt->uncore;
 158        int ret;
 159
 160        guc_prepare_xfer(uncore);
 161
 162        /*
 163         * Note that GuC needs the CSS header plus uKernel code to be copied
 164         * by the DMA engine in one operation, whereas the RSA signature is
 165         * loaded separately, either by copying it to the UOS_RSA_SCRATCH
 166         * register (if key size <= 256) or through a ggtt-pinned vma (if key
 167         * size > 256). The RSA size and therefore the way we provide it to the
 168         * HW is fixed for each platform and hard-coded in the bootrom.
 169         */
 170        ret = guc_xfer_rsa(&guc->fw, uncore);
 171        if (ret)
 172                goto out;
 173
 174        /*
 175         * Current uCode expects the code to be loaded at 8k; locations below
 176         * this are used for the stack.
 177         */
 178        ret = intel_uc_fw_upload(&guc->fw, 0x2000, UOS_MOVE);
 179        if (ret)
 180                goto out;
 181
 182        ret = guc_wait_ucode(uncore);
 183        if (ret)
 184                goto out;
 185
 186        intel_uc_fw_change_status(&guc->fw, INTEL_UC_FIRMWARE_RUNNING);
 187        return 0;
 188
 189out:
 190        intel_uc_fw_change_status(&guc->fw, INTEL_UC_FIRMWARE_LOAD_FAIL);
 191        return ret;
 192}
 193