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25#ifndef _I915_REG_H_
26#define _I915_REG_H_
27
28#include <linux/bitfield.h>
29#include <linux/bits.h>
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127#define REG_BIT(__n) \
128 ((u32)(BIT(__n) + \
129 BUILD_BUG_ON_ZERO(__is_constexpr(__n) && \
130 ((__n) < 0 || (__n) > 31))))
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140
141#define REG_GENMASK(__high, __low) \
142 ((u32)(GENMASK(__high, __low) + \
143 BUILD_BUG_ON_ZERO(__is_constexpr(__high) && \
144 __is_constexpr(__low) && \
145 ((__low) < 0 || (__high) > 31 || (__low) > (__high)))))
146
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149
150#define IS_POWER_OF_2(__x) ((__x) && (((__x) & ((__x) - 1)) == 0))
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161
162#define REG_FIELD_PREP(__mask, __val) \
163 ((u32)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \
164 BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \
165 BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U32_MAX) + \
166 BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \
167 BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
168
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178
179#define REG_FIELD_GET(__mask, __val) ((u32)FIELD_GET(__mask, __val))
180
181typedef struct {
182 u32 reg;
183} i915_reg_t;
184
185#define _MMIO(r) ((const i915_reg_t){ .reg = (r) })
186
187#define INVALID_MMIO_REG _MMIO(0)
188
189static __always_inline u32 i915_mmio_reg_offset(i915_reg_t reg)
190{
191 return reg.reg;
192}
193
194static inline bool i915_mmio_reg_equal(i915_reg_t a, i915_reg_t b)
195{
196 return i915_mmio_reg_offset(a) == i915_mmio_reg_offset(b);
197}
198
199static inline bool i915_mmio_reg_valid(i915_reg_t reg)
200{
201 return !i915_mmio_reg_equal(reg, INVALID_MMIO_REG);
202}
203
204#define VLV_DISPLAY_BASE 0x180000
205#define VLV_MIPI_BASE VLV_DISPLAY_BASE
206#define BXT_MIPI_BASE 0x60000
207
208#define DISPLAY_MMIO_BASE(dev_priv) (INTEL_INFO(dev_priv)->display_mmio_offset)
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215
216#define _PICK_EVEN(__index, __a, __b) ((__a) + (__index) * ((__b) - (__a)))
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222
223#define _PICK(__index, ...) (((const u32 []){ __VA_ARGS__ })[__index])
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227
228#define _PIPE(pipe, a, b) _PICK_EVEN(pipe, a, b)
229#define _PLANE(plane, a, b) _PICK_EVEN(plane, a, b)
230#define _TRANS(tran, a, b) _PICK_EVEN(tran, a, b)
231#define _PORT(port, a, b) _PICK_EVEN(port, a, b)
232#define _PLL(pll, a, b) _PICK_EVEN(pll, a, b)
233#define _PHY(phy, a, b) _PICK_EVEN(phy, a, b)
234
235#define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b))
236#define _MMIO_PLANE(plane, a, b) _MMIO(_PLANE(plane, a, b))
237#define _MMIO_TRANS(tran, a, b) _MMIO(_TRANS(tran, a, b))
238#define _MMIO_PORT(port, a, b) _MMIO(_PORT(port, a, b))
239#define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b))
240#define _MMIO_PHY(phy, a, b) _MMIO(_PHY(phy, a, b))
241
242#define _PHY3(phy, ...) _PICK(phy, __VA_ARGS__)
243
244#define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
245#define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
246#define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c))
247#define _MMIO_PLL3(pll, ...) _MMIO(_PICK(pll, __VA_ARGS__))
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253
254#define _MMIO_PIPE2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->pipe_offsets[pipe] - \
255 INTEL_INFO(dev_priv)->pipe_offsets[PIPE_A] + (reg) + \
256 DISPLAY_MMIO_BASE(dev_priv))
257#define _TRANS2(tran, reg) (INTEL_INFO(dev_priv)->trans_offsets[(tran)] - \
258 INTEL_INFO(dev_priv)->trans_offsets[TRANSCODER_A] + (reg) + \
259 DISPLAY_MMIO_BASE(dev_priv))
260#define _MMIO_TRANS2(tran, reg) _MMIO(_TRANS2(tran, reg))
261#define _CURSOR2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->cursor_offsets[(pipe)] - \
262 INTEL_INFO(dev_priv)->cursor_offsets[PIPE_A] + (reg) + \
263 DISPLAY_MMIO_BASE(dev_priv))
264
265#define __MASKED_FIELD(mask, value) ((mask) << 16 | (value))
266#define _MASKED_FIELD(mask, value) ({ \
267 if (__builtin_constant_p(mask)) \
268 BUILD_BUG_ON_MSG(((mask) & 0xffff0000), "Incorrect mask"); \
269 if (__builtin_constant_p(value)) \
270 BUILD_BUG_ON_MSG((value) & 0xffff0000, "Incorrect value"); \
271 if (__builtin_constant_p(mask) && __builtin_constant_p(value)) \
272 BUILD_BUG_ON_MSG((value) & ~(mask), \
273 "Incorrect value for mask"); \
274 __MASKED_FIELD(mask, value); })
275#define _MASKED_BIT_ENABLE(a) ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); })
276#define _MASKED_BIT_DISABLE(a) (_MASKED_FIELD((a), 0))
277
278
279
280#define MCHBAR_I915 0x44
281#define MCHBAR_I965 0x48
282#define MCHBAR_SIZE (4 * 4096)
283
284#define DEVEN 0x54
285#define DEVEN_MCHBAR_EN (1 << 28)
286
287
288
289#define HPLLCC 0xc0
290#define GC_CLOCK_CONTROL_MASK (0x7 << 0)
291#define GC_CLOCK_133_200 (0 << 0)
292#define GC_CLOCK_100_200 (1 << 0)
293#define GC_CLOCK_100_133 (2 << 0)
294#define GC_CLOCK_133_266 (3 << 0)
295#define GC_CLOCK_133_200_2 (4 << 0)
296#define GC_CLOCK_133_266_2 (5 << 0)
297#define GC_CLOCK_166_266 (6 << 0)
298#define GC_CLOCK_166_250 (7 << 0)
299
300#define I915_GDRST 0xc0
301#define GRDOM_FULL (0 << 2)
302#define GRDOM_RENDER (1 << 2)
303#define GRDOM_MEDIA (3 << 2)
304#define GRDOM_MASK (3 << 2)
305#define GRDOM_RESET_STATUS (1 << 1)
306#define GRDOM_RESET_ENABLE (1 << 0)
307
308
309#define I830_CLOCK_GATE 0xc8
310#define I830_L2_CACHE_CLOCK_GATE_DISABLE (1 << 2)
311
312#define GCDGMBUS 0xcc
313
314#define GCFGC2 0xda
315#define GCFGC 0xf0
316#define GC_LOW_FREQUENCY_ENABLE (1 << 7)
317#define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
318#define GC_DISPLAY_CLOCK_333_320_MHZ (4 << 4)
319#define GC_DISPLAY_CLOCK_267_MHZ_PNV (0 << 4)
320#define GC_DISPLAY_CLOCK_333_MHZ_PNV (1 << 4)
321#define GC_DISPLAY_CLOCK_444_MHZ_PNV (2 << 4)
322#define GC_DISPLAY_CLOCK_200_MHZ_PNV (5 << 4)
323#define GC_DISPLAY_CLOCK_133_MHZ_PNV (6 << 4)
324#define GC_DISPLAY_CLOCK_167_MHZ_PNV (7 << 4)
325#define GC_DISPLAY_CLOCK_MASK (7 << 4)
326#define GM45_GC_RENDER_CLOCK_MASK (0xf << 0)
327#define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0)
328#define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0)
329#define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0)
330#define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0)
331#define I965_GC_RENDER_CLOCK_MASK (0xf << 0)
332#define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0)
333#define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0)
334#define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0)
335#define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0)
336#define I945_GC_RENDER_CLOCK_MASK (7 << 0)
337#define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0)
338#define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0)
339#define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0)
340#define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0)
341#define I915_GC_RENDER_CLOCK_MASK (7 << 0)
342#define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0)
343#define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0)
344#define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0)
345
346#define ASLE 0xe4
347#define ASLS 0xfc
348
349#define SWSCI 0xe8
350#define SWSCI_SCISEL (1 << 15)
351#define SWSCI_GSSCIE (1 << 0)
352
353#define LBPC 0xf4
354
355
356#define ILK_GDSR _MMIO(MCHBAR_MIRROR_BASE + 0x2ca4)
357#define ILK_GRDOM_FULL (0 << 1)
358#define ILK_GRDOM_RENDER (1 << 1)
359#define ILK_GRDOM_MEDIA (3 << 1)
360#define ILK_GRDOM_MASK (3 << 1)
361#define ILK_GRDOM_RESET_ENABLE (1 << 0)
362
363#define GEN6_MBCUNIT_SNPCR _MMIO(0x900c)
364#define GEN6_MBC_SNPCR_SHIFT 21
365#define GEN6_MBC_SNPCR_MASK (3 << 21)
366#define GEN6_MBC_SNPCR_MAX (0 << 21)
367#define GEN6_MBC_SNPCR_MED (1 << 21)
368#define GEN6_MBC_SNPCR_LOW (2 << 21)
369#define GEN6_MBC_SNPCR_MIN (3 << 21)
370
371#define VLV_G3DCTL _MMIO(0x9024)
372#define VLV_GSCKGCTL _MMIO(0x9028)
373
374#define FBC_LLC_READ_CTRL _MMIO(0x9044)
375#define FBC_LLC_FULLY_OPEN REG_BIT(30)
376
377#define GEN6_MBCTL _MMIO(0x0907c)
378#define GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4)
379#define GEN6_MBCTL_CTX_FETCH_NEEDED (1 << 3)
380#define GEN6_MBCTL_BME_UPDATE_ENABLE (1 << 2)
381#define GEN6_MBCTL_MAE_UPDATE_ENABLE (1 << 1)
382#define GEN6_MBCTL_BOOT_FETCH_MECH (1 << 0)
383
384#define GEN6_GDRST _MMIO(0x941c)
385#define GEN6_GRDOM_FULL (1 << 0)
386#define GEN6_GRDOM_RENDER (1 << 1)
387#define GEN6_GRDOM_MEDIA (1 << 2)
388#define GEN6_GRDOM_BLT (1 << 3)
389#define GEN6_GRDOM_VECS (1 << 4)
390#define GEN9_GRDOM_GUC (1 << 5)
391#define GEN8_GRDOM_MEDIA2 (1 << 7)
392
393#define GEN11_GRDOM_FULL GEN6_GRDOM_FULL
394#define GEN11_GRDOM_RENDER GEN6_GRDOM_RENDER
395#define GEN11_GRDOM_BLT (1 << 2)
396#define GEN11_GRDOM_GUC (1 << 3)
397#define GEN11_GRDOM_MEDIA (1 << 5)
398#define GEN11_GRDOM_MEDIA2 (1 << 6)
399#define GEN11_GRDOM_MEDIA3 (1 << 7)
400#define GEN11_GRDOM_MEDIA4 (1 << 8)
401#define GEN11_GRDOM_MEDIA5 (1 << 9)
402#define GEN11_GRDOM_MEDIA6 (1 << 10)
403#define GEN11_GRDOM_MEDIA7 (1 << 11)
404#define GEN11_GRDOM_MEDIA8 (1 << 12)
405#define GEN11_GRDOM_VECS (1 << 13)
406#define GEN11_GRDOM_VECS2 (1 << 14)
407#define GEN11_GRDOM_VECS3 (1 << 15)
408#define GEN11_GRDOM_VECS4 (1 << 16)
409#define GEN11_GRDOM_SFC0 (1 << 17)
410#define GEN11_GRDOM_SFC1 (1 << 18)
411#define GEN11_GRDOM_SFC2 (1 << 19)
412#define GEN11_GRDOM_SFC3 (1 << 20)
413
414#define GEN11_VCS_SFC_RESET_BIT(instance) (GEN11_GRDOM_SFC0 << ((instance) >> 1))
415#define GEN11_VECS_SFC_RESET_BIT(instance) (GEN11_GRDOM_SFC0 << (instance))
416
417#define GEN11_VCS_SFC_FORCED_LOCK(engine) _MMIO((engine)->mmio_base + 0x88C)
418#define GEN11_VCS_SFC_FORCED_LOCK_BIT (1 << 0)
419#define GEN11_VCS_SFC_LOCK_STATUS(engine) _MMIO((engine)->mmio_base + 0x890)
420#define GEN11_VCS_SFC_USAGE_BIT (1 << 0)
421#define GEN11_VCS_SFC_LOCK_ACK_BIT (1 << 1)
422
423#define GEN11_VECS_SFC_FORCED_LOCK(engine) _MMIO((engine)->mmio_base + 0x201C)
424#define GEN11_VECS_SFC_FORCED_LOCK_BIT (1 << 0)
425#define GEN11_VECS_SFC_LOCK_ACK(engine) _MMIO((engine)->mmio_base + 0x2018)
426#define GEN11_VECS_SFC_LOCK_ACK_BIT (1 << 0)
427#define GEN11_VECS_SFC_USAGE(engine) _MMIO((engine)->mmio_base + 0x2014)
428#define GEN11_VECS_SFC_USAGE_BIT (1 << 0)
429
430#define GEN12_HCP_SFC_FORCED_LOCK(engine) _MMIO((engine)->mmio_base + 0x2910)
431#define GEN12_HCP_SFC_FORCED_LOCK_BIT REG_BIT(0)
432#define GEN12_HCP_SFC_LOCK_STATUS(engine) _MMIO((engine)->mmio_base + 0x2914)
433#define GEN12_HCP_SFC_LOCK_ACK_BIT REG_BIT(1)
434#define GEN12_HCP_SFC_USAGE_BIT REG_BIT(0)
435
436#define GEN12_SFC_DONE(n) _MMIO(0x1cc000 + (n) * 0x1000)
437#define GEN12_SFC_DONE_MAX 4
438
439#define RING_PP_DIR_BASE(base) _MMIO((base) + 0x228)
440#define RING_PP_DIR_BASE_READ(base) _MMIO((base) + 0x518)
441#define RING_PP_DIR_DCLV(base) _MMIO((base) + 0x220)
442#define PP_DIR_DCLV_2G 0xffffffff
443
444#define GEN8_RING_PDP_UDW(base, n) _MMIO((base) + 0x270 + (n) * 8 + 4)
445#define GEN8_RING_PDP_LDW(base, n) _MMIO((base) + 0x270 + (n) * 8)
446
447#define GEN8_R_PWR_CLK_STATE _MMIO(0x20C8)
448#define GEN8_RPCS_ENABLE (1 << 31)
449#define GEN8_RPCS_S_CNT_ENABLE (1 << 18)
450#define GEN8_RPCS_S_CNT_SHIFT 15
451#define GEN8_RPCS_S_CNT_MASK (0x7 << GEN8_RPCS_S_CNT_SHIFT)
452#define GEN11_RPCS_S_CNT_SHIFT 12
453#define GEN11_RPCS_S_CNT_MASK (0x3f << GEN11_RPCS_S_CNT_SHIFT)
454#define GEN8_RPCS_SS_CNT_ENABLE (1 << 11)
455#define GEN8_RPCS_SS_CNT_SHIFT 8
456#define GEN8_RPCS_SS_CNT_MASK (0x7 << GEN8_RPCS_SS_CNT_SHIFT)
457#define GEN8_RPCS_EU_MAX_SHIFT 4
458#define GEN8_RPCS_EU_MAX_MASK (0xf << GEN8_RPCS_EU_MAX_SHIFT)
459#define GEN8_RPCS_EU_MIN_SHIFT 0
460#define GEN8_RPCS_EU_MIN_MASK (0xf << GEN8_RPCS_EU_MIN_SHIFT)
461
462#define WAIT_FOR_RC6_EXIT _MMIO(0x20CC)
463
464#define HSW_SELECTIVE_READ_ADDRESSING_SHIFT 2
465#define HSW_SELECTIVE_READ_ADDRESSING_MASK (0x3 << HSW_SLECTIVE_READ_ADDRESSING_SHIFT)
466#define HSW_SELECTIVE_WRITE_ADDRESS_SHIFT 4
467#define HSW_SELECTIVE_WRITE_ADDRESS_MASK (0x7 << HSW_SELECTIVE_WRITE_ADDRESS_SHIFT)
468
469#define HSW_WAIT_FOR_RC6_EXIT_ENABLE (1 << 0)
470#define HSW_RCS_CONTEXT_ENABLE (1 << 7)
471#define HSW_RCS_INHIBIT (1 << 8)
472
473#define GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT 4
474#define GEN8_SELECTIVE_WRITE_ADDRESS_MASK (0x3 << GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT)
475#define GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT 4
476#define GEN8_SELECTIVE_WRITE_ADDRESS_MASK (0x3 << GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT)
477#define GEN8_SELECTIVE_WRITE_ADDRESSING_ENABLE (1 << 6)
478#define GEN8_SELECTIVE_READ_SUBSLICE_SELECT_SHIFT 9
479#define GEN8_SELECTIVE_READ_SUBSLICE_SELECT_MASK (0x3 << GEN8_SELECTIVE_READ_SUBSLICE_SELECT_SHIFT)
480#define GEN8_SELECTIVE_READ_SLICE_SELECT_SHIFT 11
481#define GEN8_SELECTIVE_READ_SLICE_SELECT_MASK (0x3 << GEN8_SELECTIVE_READ_SLICE_SELECT_SHIFT)
482#define GEN8_SELECTIVE_READ_ADDRESSING_ENABLE (1 << 13)
483
484#define GAM_ECOCHK _MMIO(0x4090)
485#define BDW_DISABLE_HDC_INVALIDATION (1 << 25)
486#define ECOCHK_SNB_BIT (1 << 10)
487#define ECOCHK_DIS_TLB (1 << 8)
488#define HSW_ECOCHK_ARB_PRIO_SOL (1 << 6)
489#define ECOCHK_PPGTT_CACHE64B (0x3 << 3)
490#define ECOCHK_PPGTT_CACHE4B (0x0 << 3)
491#define ECOCHK_PPGTT_GFDT_IVB (0x1 << 4)
492#define ECOCHK_PPGTT_LLC_IVB (0x1 << 3)
493#define ECOCHK_PPGTT_UC_HSW (0x1 << 3)
494#define ECOCHK_PPGTT_WT_HSW (0x2 << 3)
495#define ECOCHK_PPGTT_WB_HSW (0x3 << 3)
496
497#define GEN8_RC6_CTX_INFO _MMIO(0x8504)
498
499#define GAC_ECO_BITS _MMIO(0x14090)
500#define ECOBITS_SNB_BIT (1 << 13)
501#define ECOBITS_PPGTT_CACHE64B (3 << 8)
502#define ECOBITS_PPGTT_CACHE4B (0 << 8)
503
504#define GEN12_GAMCNTRL_CTRL _MMIO(0xcf54)
505#define INVALIDATION_BROADCAST_MODE_DIS REG_BIT(12)
506#define GLOBAL_INVALIDATION_MODE REG_BIT(2)
507
508#define GEN12_GAMSTLB_CTRL _MMIO(0xcf4c)
509#define CONTROL_BLOCK_CLKGATE_DIS REG_BIT(12)
510#define EGRESS_BLOCK_CLKGATE_DIS REG_BIT(11)
511#define TAG_BLOCK_CLKGATE_DIS REG_BIT(7)
512
513#define GEN12_MERT_MOD_CTRL _MMIO(0xcf28)
514#define FORCE_MISS_FTLB REG_BIT(3)
515
516#define GAB_CTL _MMIO(0x24000)
517#define GAB_CTL_CONT_AFTER_PAGEFAULT (1 << 8)
518
519#define GU_CNTL _MMIO(0x101010)
520#define LMEM_INIT REG_BIT(7)
521
522#define GEN6_STOLEN_RESERVED _MMIO(0x1082C0)
523#define GEN6_STOLEN_RESERVED_ADDR_MASK (0xFFF << 20)
524#define GEN7_STOLEN_RESERVED_ADDR_MASK (0x3FFF << 18)
525#define GEN6_STOLEN_RESERVED_SIZE_MASK (3 << 4)
526#define GEN6_STOLEN_RESERVED_1M (0 << 4)
527#define GEN6_STOLEN_RESERVED_512K (1 << 4)
528#define GEN6_STOLEN_RESERVED_256K (2 << 4)
529#define GEN6_STOLEN_RESERVED_128K (3 << 4)
530#define GEN7_STOLEN_RESERVED_SIZE_MASK (1 << 5)
531#define GEN7_STOLEN_RESERVED_1M (0 << 5)
532#define GEN7_STOLEN_RESERVED_256K (1 << 5)
533#define GEN8_STOLEN_RESERVED_SIZE_MASK (3 << 7)
534#define GEN8_STOLEN_RESERVED_1M (0 << 7)
535#define GEN8_STOLEN_RESERVED_2M (1 << 7)
536#define GEN8_STOLEN_RESERVED_4M (2 << 7)
537#define GEN8_STOLEN_RESERVED_8M (3 << 7)
538#define GEN6_STOLEN_RESERVED_ENABLE (1 << 0)
539#define GEN11_STOLEN_RESERVED_ADDR_MASK (0xFFFFFFFFFFFULL << 20)
540
541
542
543#define VGA_ST01_MDA 0x3ba
544#define VGA_ST01_CGA 0x3da
545
546#define _VGA_MSR_WRITE _MMIO(0x3c2)
547#define VGA_MSR_WRITE 0x3c2
548#define VGA_MSR_READ 0x3cc
549#define VGA_MSR_MEM_EN (1 << 1)
550#define VGA_MSR_CGA_MODE (1 << 0)
551
552#define VGA_SR_INDEX 0x3c4
553#define SR01 1
554#define VGA_SR_DATA 0x3c5
555
556#define VGA_AR_INDEX 0x3c0
557#define VGA_AR_VID_EN (1 << 5)
558#define VGA_AR_DATA_WRITE 0x3c0
559#define VGA_AR_DATA_READ 0x3c1
560
561#define VGA_GR_INDEX 0x3ce
562#define VGA_GR_DATA 0x3cf
563
564#define VGA_GR_MEM_READ_MODE_SHIFT 3
565#define VGA_GR_MEM_READ_MODE_PLANE 1
566
567#define VGA_GR_MEM_MODE_MASK 0xc
568#define VGA_GR_MEM_MODE_SHIFT 2
569#define VGA_GR_MEM_A0000_AFFFF 0
570#define VGA_GR_MEM_A0000_BFFFF 1
571#define VGA_GR_MEM_B0000_B7FFF 2
572#define VGA_GR_MEM_B0000_BFFFF 3
573
574#define VGA_DACMASK 0x3c6
575#define VGA_DACRX 0x3c7
576#define VGA_DACWX 0x3c8
577#define VGA_DACDATA 0x3c9
578
579#define VGA_CR_INDEX_MDA 0x3b4
580#define VGA_CR_DATA_MDA 0x3b5
581#define VGA_CR_INDEX_CGA 0x3d4
582#define VGA_CR_DATA_CGA 0x3d5
583
584#define MI_PREDICATE_SRC0 _MMIO(0x2400)
585#define MI_PREDICATE_SRC0_UDW _MMIO(0x2400 + 4)
586#define MI_PREDICATE_SRC1 _MMIO(0x2408)
587#define MI_PREDICATE_SRC1_UDW _MMIO(0x2408 + 4)
588#define MI_PREDICATE_DATA _MMIO(0x2410)
589#define MI_PREDICATE_RESULT _MMIO(0x2418)
590#define MI_PREDICATE_RESULT_1 _MMIO(0x241c)
591#define MI_PREDICATE_RESULT_2 _MMIO(0x2214)
592#define LOWER_SLICE_ENABLED (1 << 0)
593#define LOWER_SLICE_DISABLED (0 << 0)
594
595
596
597
598#define BCS_SWCTRL _MMIO(0x22200)
599#define BCS_SRC_Y REG_BIT(0)
600#define BCS_DST_Y REG_BIT(1)
601
602
603#define BCS_GPR(n) _MMIO(0x22600 + (n) * 8)
604#define BCS_GPR_UDW(n) _MMIO(0x22600 + (n) * 8 + 4)
605
606#define GPGPU_THREADS_DISPATCHED _MMIO(0x2290)
607#define GPGPU_THREADS_DISPATCHED_UDW _MMIO(0x2290 + 4)
608#define HS_INVOCATION_COUNT _MMIO(0x2300)
609#define HS_INVOCATION_COUNT_UDW _MMIO(0x2300 + 4)
610#define DS_INVOCATION_COUNT _MMIO(0x2308)
611#define DS_INVOCATION_COUNT_UDW _MMIO(0x2308 + 4)
612#define IA_VERTICES_COUNT _MMIO(0x2310)
613#define IA_VERTICES_COUNT_UDW _MMIO(0x2310 + 4)
614#define IA_PRIMITIVES_COUNT _MMIO(0x2318)
615#define IA_PRIMITIVES_COUNT_UDW _MMIO(0x2318 + 4)
616#define VS_INVOCATION_COUNT _MMIO(0x2320)
617#define VS_INVOCATION_COUNT_UDW _MMIO(0x2320 + 4)
618#define GS_INVOCATION_COUNT _MMIO(0x2328)
619#define GS_INVOCATION_COUNT_UDW _MMIO(0x2328 + 4)
620#define GS_PRIMITIVES_COUNT _MMIO(0x2330)
621#define GS_PRIMITIVES_COUNT_UDW _MMIO(0x2330 + 4)
622#define CL_INVOCATION_COUNT _MMIO(0x2338)
623#define CL_INVOCATION_COUNT_UDW _MMIO(0x2338 + 4)
624#define CL_PRIMITIVES_COUNT _MMIO(0x2340)
625#define CL_PRIMITIVES_COUNT_UDW _MMIO(0x2340 + 4)
626#define PS_INVOCATION_COUNT _MMIO(0x2348)
627#define PS_INVOCATION_COUNT_UDW _MMIO(0x2348 + 4)
628#define PS_DEPTH_COUNT _MMIO(0x2350)
629#define PS_DEPTH_COUNT_UDW _MMIO(0x2350 + 4)
630
631
632#define GEN7_SO_NUM_PRIMS_WRITTEN(n) _MMIO(0x5200 + (n) * 8)
633#define GEN7_SO_NUM_PRIMS_WRITTEN_UDW(n) _MMIO(0x5200 + (n) * 8 + 4)
634
635#define GEN7_SO_PRIM_STORAGE_NEEDED(n) _MMIO(0x5240 + (n) * 8)
636#define GEN7_SO_PRIM_STORAGE_NEEDED_UDW(n) _MMIO(0x5240 + (n) * 8 + 4)
637
638#define GEN7_3DPRIM_END_OFFSET _MMIO(0x2420)
639#define GEN7_3DPRIM_START_VERTEX _MMIO(0x2430)
640#define GEN7_3DPRIM_VERTEX_COUNT _MMIO(0x2434)
641#define GEN7_3DPRIM_INSTANCE_COUNT _MMIO(0x2438)
642#define GEN7_3DPRIM_START_INSTANCE _MMIO(0x243C)
643#define GEN7_3DPRIM_BASE_VERTEX _MMIO(0x2440)
644
645#define GEN7_GPGPU_DISPATCHDIMX _MMIO(0x2500)
646#define GEN7_GPGPU_DISPATCHDIMY _MMIO(0x2504)
647#define GEN7_GPGPU_DISPATCHDIMZ _MMIO(0x2508)
648
649
650#define HSW_CS_GPR(n) _MMIO(0x2600 + (n) * 8)
651#define HSW_CS_GPR_UDW(n) _MMIO(0x2600 + (n) * 8 + 4)
652
653#define GEN7_OACONTROL _MMIO(0x2360)
654#define GEN7_OACONTROL_CTX_MASK 0xFFFFF000
655#define GEN7_OACONTROL_TIMER_PERIOD_MASK 0x3F
656#define GEN7_OACONTROL_TIMER_PERIOD_SHIFT 6
657#define GEN7_OACONTROL_TIMER_ENABLE (1 << 5)
658#define GEN7_OACONTROL_FORMAT_A13 (0 << 2)
659#define GEN7_OACONTROL_FORMAT_A29 (1 << 2)
660#define GEN7_OACONTROL_FORMAT_A13_B8_C8 (2 << 2)
661#define GEN7_OACONTROL_FORMAT_A29_B8_C8 (3 << 2)
662#define GEN7_OACONTROL_FORMAT_B4_C8 (4 << 2)
663#define GEN7_OACONTROL_FORMAT_A45_B8_C8 (5 << 2)
664#define GEN7_OACONTROL_FORMAT_B4_C8_A16 (6 << 2)
665#define GEN7_OACONTROL_FORMAT_C4_B8 (7 << 2)
666#define GEN7_OACONTROL_FORMAT_SHIFT 2
667#define GEN7_OACONTROL_PER_CTX_ENABLE (1 << 1)
668#define GEN7_OACONTROL_ENABLE (1 << 0)
669
670#define GEN8_OACTXID _MMIO(0x2364)
671
672#define GEN8_OA_DEBUG _MMIO(0x2B04)
673#define GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS (1 << 5)
674#define GEN9_OA_DEBUG_INCLUDE_CLK_RATIO (1 << 6)
675#define GEN9_OA_DEBUG_DISABLE_GO_1_0_REPORTS (1 << 2)
676#define GEN9_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS (1 << 1)
677
678#define GEN8_OACONTROL _MMIO(0x2B00)
679#define GEN8_OA_REPORT_FORMAT_A12 (0 << 2)
680#define GEN8_OA_REPORT_FORMAT_A12_B8_C8 (2 << 2)
681#define GEN8_OA_REPORT_FORMAT_A36_B8_C8 (5 << 2)
682#define GEN8_OA_REPORT_FORMAT_C4_B8 (7 << 2)
683#define GEN8_OA_REPORT_FORMAT_SHIFT 2
684#define GEN8_OA_SPECIFIC_CONTEXT_ENABLE (1 << 1)
685#define GEN8_OA_COUNTER_ENABLE (1 << 0)
686
687#define GEN8_OACTXCONTROL _MMIO(0x2360)
688#define GEN8_OA_TIMER_PERIOD_MASK 0x3F
689#define GEN8_OA_TIMER_PERIOD_SHIFT 2
690#define GEN8_OA_TIMER_ENABLE (1 << 1)
691#define GEN8_OA_COUNTER_RESUME (1 << 0)
692
693#define GEN7_OABUFFER _MMIO(0x23B0)
694#define GEN7_OABUFFER_OVERRUN_DISABLE (1 << 3)
695#define GEN7_OABUFFER_EDGE_TRIGGER (1 << 2)
696#define GEN7_OABUFFER_STOP_RESUME_ENABLE (1 << 1)
697#define GEN7_OABUFFER_RESUME (1 << 0)
698
699#define GEN8_OABUFFER_UDW _MMIO(0x23b4)
700#define GEN8_OABUFFER _MMIO(0x2b14)
701#define GEN8_OABUFFER_MEM_SELECT_GGTT (1 << 0)
702
703#define GEN7_OASTATUS1 _MMIO(0x2364)
704#define GEN7_OASTATUS1_TAIL_MASK 0xffffffc0
705#define GEN7_OASTATUS1_COUNTER_OVERFLOW (1 << 2)
706#define GEN7_OASTATUS1_OABUFFER_OVERFLOW (1 << 1)
707#define GEN7_OASTATUS1_REPORT_LOST (1 << 0)
708
709#define GEN7_OASTATUS2 _MMIO(0x2368)
710#define GEN7_OASTATUS2_HEAD_MASK 0xffffffc0
711#define GEN7_OASTATUS2_MEM_SELECT_GGTT (1 << 0)
712
713#define GEN8_OASTATUS _MMIO(0x2b08)
714#define GEN8_OASTATUS_TAIL_POINTER_WRAP (1 << 17)
715#define GEN8_OASTATUS_HEAD_POINTER_WRAP (1 << 16)
716#define GEN8_OASTATUS_OVERRUN_STATUS (1 << 3)
717#define GEN8_OASTATUS_COUNTER_OVERFLOW (1 << 2)
718#define GEN8_OASTATUS_OABUFFER_OVERFLOW (1 << 1)
719#define GEN8_OASTATUS_REPORT_LOST (1 << 0)
720
721#define GEN8_OAHEADPTR _MMIO(0x2B0C)
722#define GEN8_OAHEADPTR_MASK 0xffffffc0
723#define GEN8_OATAILPTR _MMIO(0x2B10)
724#define GEN8_OATAILPTR_MASK 0xffffffc0
725
726#define OABUFFER_SIZE_128K (0 << 3)
727#define OABUFFER_SIZE_256K (1 << 3)
728#define OABUFFER_SIZE_512K (2 << 3)
729#define OABUFFER_SIZE_1M (3 << 3)
730#define OABUFFER_SIZE_2M (4 << 3)
731#define OABUFFER_SIZE_4M (5 << 3)
732#define OABUFFER_SIZE_8M (6 << 3)
733#define OABUFFER_SIZE_16M (7 << 3)
734
735#define GEN12_OA_TLB_INV_CR _MMIO(0xceec)
736
737#define GEN12_SQCM _MMIO(0x8724)
738#define EN_32B_ACCESS REG_BIT(30)
739
740
741#define GEN12_OAR_OACONTROL _MMIO(0x2960)
742#define GEN12_OAR_OACONTROL_COUNTER_FORMAT_SHIFT 1
743#define GEN12_OAR_OACONTROL_COUNTER_ENABLE (1 << 0)
744
745#define GEN12_OACTXCONTROL _MMIO(0x2360)
746#define GEN12_OAR_OASTATUS _MMIO(0x2968)
747
748
749#define GEN12_OAG_OAHEADPTR _MMIO(0xdb00)
750#define GEN12_OAG_OAHEADPTR_MASK 0xffffffc0
751#define GEN12_OAG_OATAILPTR _MMIO(0xdb04)
752#define GEN12_OAG_OATAILPTR_MASK 0xffffffc0
753
754#define GEN12_OAG_OABUFFER _MMIO(0xdb08)
755#define GEN12_OAG_OABUFFER_BUFFER_SIZE_MASK (0x7)
756#define GEN12_OAG_OABUFFER_BUFFER_SIZE_SHIFT (3)
757#define GEN12_OAG_OABUFFER_MEMORY_SELECT (1 << 0)
758
759#define GEN12_OAG_OAGLBCTXCTRL _MMIO(0x2b28)
760#define GEN12_OAG_OAGLBCTXCTRL_TIMER_PERIOD_SHIFT 2
761#define GEN12_OAG_OAGLBCTXCTRL_TIMER_ENABLE (1 << 1)
762#define GEN12_OAG_OAGLBCTXCTRL_COUNTER_RESUME (1 << 0)
763
764#define GEN12_OAG_OACONTROL _MMIO(0xdaf4)
765#define GEN12_OAG_OACONTROL_OA_COUNTER_FORMAT_SHIFT 2
766#define GEN12_OAG_OACONTROL_OA_COUNTER_ENABLE (1 << 0)
767
768#define GEN12_OAG_OA_DEBUG _MMIO(0xdaf8)
769#define GEN12_OAG_OA_DEBUG_INCLUDE_CLK_RATIO (1 << 6)
770#define GEN12_OAG_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS (1 << 5)
771#define GEN12_OAG_OA_DEBUG_DISABLE_GO_1_0_REPORTS (1 << 2)
772#define GEN12_OAG_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS (1 << 1)
773
774#define GEN12_OAG_OASTATUS _MMIO(0xdafc)
775#define GEN12_OAG_OASTATUS_COUNTER_OVERFLOW (1 << 2)
776#define GEN12_OAG_OASTATUS_BUFFER_OVERFLOW (1 << 1)
777#define GEN12_OAG_OASTATUS_REPORT_LOST (1 << 0)
778
779
780
781
782
783#define EU_PERF_CNTL0 _MMIO(0xe458)
784#define EU_PERF_CNTL1 _MMIO(0xe558)
785#define EU_PERF_CNTL2 _MMIO(0xe658)
786#define EU_PERF_CNTL3 _MMIO(0xe758)
787#define EU_PERF_CNTL4 _MMIO(0xe45c)
788#define EU_PERF_CNTL5 _MMIO(0xe55c)
789#define EU_PERF_CNTL6 _MMIO(0xe65c)
790
791#define RT_CTRL _MMIO(0xe530)
792#define DIS_NULL_QUERY REG_BIT(10)
793
794
795
796
797
798#define OASTARTTRIG1 _MMIO(0x2710)
799#define OASTARTTRIG1_THRESHOLD_COUNT_MASK_MBZ 0xffff0000
800#define OASTARTTRIG1_THRESHOLD_MASK 0xffff
801
802#define OASTARTTRIG2 _MMIO(0x2714)
803#define OASTARTTRIG2_INVERT_A_0 (1 << 0)
804#define OASTARTTRIG2_INVERT_A_1 (1 << 1)
805#define OASTARTTRIG2_INVERT_A_2 (1 << 2)
806#define OASTARTTRIG2_INVERT_A_3 (1 << 3)
807#define OASTARTTRIG2_INVERT_A_4 (1 << 4)
808#define OASTARTTRIG2_INVERT_A_5 (1 << 5)
809#define OASTARTTRIG2_INVERT_A_6 (1 << 6)
810#define OASTARTTRIG2_INVERT_A_7 (1 << 7)
811#define OASTARTTRIG2_INVERT_A_8 (1 << 8)
812#define OASTARTTRIG2_INVERT_A_9 (1 << 9)
813#define OASTARTTRIG2_INVERT_A_10 (1 << 10)
814#define OASTARTTRIG2_INVERT_A_11 (1 << 11)
815#define OASTARTTRIG2_INVERT_A_12 (1 << 12)
816#define OASTARTTRIG2_INVERT_A_13 (1 << 13)
817#define OASTARTTRIG2_INVERT_A_14 (1 << 14)
818#define OASTARTTRIG2_INVERT_A_15 (1 << 15)
819#define OASTARTTRIG2_INVERT_B_0 (1 << 16)
820#define OASTARTTRIG2_INVERT_B_1 (1 << 17)
821#define OASTARTTRIG2_INVERT_B_2 (1 << 18)
822#define OASTARTTRIG2_INVERT_B_3 (1 << 19)
823#define OASTARTTRIG2_INVERT_C_0 (1 << 20)
824#define OASTARTTRIG2_INVERT_C_1 (1 << 21)
825#define OASTARTTRIG2_INVERT_D_0 (1 << 22)
826#define OASTARTTRIG2_THRESHOLD_ENABLE (1 << 23)
827#define OASTARTTRIG2_START_TRIG_FLAG_MBZ (1 << 24)
828#define OASTARTTRIG2_EVENT_SELECT_0 (1 << 28)
829#define OASTARTTRIG2_EVENT_SELECT_1 (1 << 29)
830#define OASTARTTRIG2_EVENT_SELECT_2 (1 << 30)
831#define OASTARTTRIG2_EVENT_SELECT_3 (1 << 31)
832
833#define OASTARTTRIG3 _MMIO(0x2718)
834#define OASTARTTRIG3_NOA_SELECT_MASK 0xf
835#define OASTARTTRIG3_NOA_SELECT_8_SHIFT 0
836#define OASTARTTRIG3_NOA_SELECT_9_SHIFT 4
837#define OASTARTTRIG3_NOA_SELECT_10_SHIFT 8
838#define OASTARTTRIG3_NOA_SELECT_11_SHIFT 12
839#define OASTARTTRIG3_NOA_SELECT_12_SHIFT 16
840#define OASTARTTRIG3_NOA_SELECT_13_SHIFT 20
841#define OASTARTTRIG3_NOA_SELECT_14_SHIFT 24
842#define OASTARTTRIG3_NOA_SELECT_15_SHIFT 28
843
844#define OASTARTTRIG4 _MMIO(0x271c)
845#define OASTARTTRIG4_NOA_SELECT_MASK 0xf
846#define OASTARTTRIG4_NOA_SELECT_0_SHIFT 0
847#define OASTARTTRIG4_NOA_SELECT_1_SHIFT 4
848#define OASTARTTRIG4_NOA_SELECT_2_SHIFT 8
849#define OASTARTTRIG4_NOA_SELECT_3_SHIFT 12
850#define OASTARTTRIG4_NOA_SELECT_4_SHIFT 16
851#define OASTARTTRIG4_NOA_SELECT_5_SHIFT 20
852#define OASTARTTRIG4_NOA_SELECT_6_SHIFT 24
853#define OASTARTTRIG4_NOA_SELECT_7_SHIFT 28
854
855#define OASTARTTRIG5 _MMIO(0x2720)
856#define OASTARTTRIG5_THRESHOLD_COUNT_MASK_MBZ 0xffff0000
857#define OASTARTTRIG5_THRESHOLD_MASK 0xffff
858
859#define OASTARTTRIG6 _MMIO(0x2724)
860#define OASTARTTRIG6_INVERT_A_0 (1 << 0)
861#define OASTARTTRIG6_INVERT_A_1 (1 << 1)
862#define OASTARTTRIG6_INVERT_A_2 (1 << 2)
863#define OASTARTTRIG6_INVERT_A_3 (1 << 3)
864#define OASTARTTRIG6_INVERT_A_4 (1 << 4)
865#define OASTARTTRIG6_INVERT_A_5 (1 << 5)
866#define OASTARTTRIG6_INVERT_A_6 (1 << 6)
867#define OASTARTTRIG6_INVERT_A_7 (1 << 7)
868#define OASTARTTRIG6_INVERT_A_8 (1 << 8)
869#define OASTARTTRIG6_INVERT_A_9 (1 << 9)
870#define OASTARTTRIG6_INVERT_A_10 (1 << 10)
871#define OASTARTTRIG6_INVERT_A_11 (1 << 11)
872#define OASTARTTRIG6_INVERT_A_12 (1 << 12)
873#define OASTARTTRIG6_INVERT_A_13 (1 << 13)
874#define OASTARTTRIG6_INVERT_A_14 (1 << 14)
875#define OASTARTTRIG6_INVERT_A_15 (1 << 15)
876#define OASTARTTRIG6_INVERT_B_0 (1 << 16)
877#define OASTARTTRIG6_INVERT_B_1 (1 << 17)
878#define OASTARTTRIG6_INVERT_B_2 (1 << 18)
879#define OASTARTTRIG6_INVERT_B_3 (1 << 19)
880#define OASTARTTRIG6_INVERT_C_0 (1 << 20)
881#define OASTARTTRIG6_INVERT_C_1 (1 << 21)
882#define OASTARTTRIG6_INVERT_D_0 (1 << 22)
883#define OASTARTTRIG6_THRESHOLD_ENABLE (1 << 23)
884#define OASTARTTRIG6_START_TRIG_FLAG_MBZ (1 << 24)
885#define OASTARTTRIG6_EVENT_SELECT_4 (1 << 28)
886#define OASTARTTRIG6_EVENT_SELECT_5 (1 << 29)
887#define OASTARTTRIG6_EVENT_SELECT_6 (1 << 30)
888#define OASTARTTRIG6_EVENT_SELECT_7 (1 << 31)
889
890#define OASTARTTRIG7 _MMIO(0x2728)
891#define OASTARTTRIG7_NOA_SELECT_MASK 0xf
892#define OASTARTTRIG7_NOA_SELECT_8_SHIFT 0
893#define OASTARTTRIG7_NOA_SELECT_9_SHIFT 4
894#define OASTARTTRIG7_NOA_SELECT_10_SHIFT 8
895#define OASTARTTRIG7_NOA_SELECT_11_SHIFT 12
896#define OASTARTTRIG7_NOA_SELECT_12_SHIFT 16
897#define OASTARTTRIG7_NOA_SELECT_13_SHIFT 20
898#define OASTARTTRIG7_NOA_SELECT_14_SHIFT 24
899#define OASTARTTRIG7_NOA_SELECT_15_SHIFT 28
900
901#define OASTARTTRIG8 _MMIO(0x272c)
902#define OASTARTTRIG8_NOA_SELECT_MASK 0xf
903#define OASTARTTRIG8_NOA_SELECT_0_SHIFT 0
904#define OASTARTTRIG8_NOA_SELECT_1_SHIFT 4
905#define OASTARTTRIG8_NOA_SELECT_2_SHIFT 8
906#define OASTARTTRIG8_NOA_SELECT_3_SHIFT 12
907#define OASTARTTRIG8_NOA_SELECT_4_SHIFT 16
908#define OASTARTTRIG8_NOA_SELECT_5_SHIFT 20
909#define OASTARTTRIG8_NOA_SELECT_6_SHIFT 24
910#define OASTARTTRIG8_NOA_SELECT_7_SHIFT 28
911
912#define OAREPORTTRIG1 _MMIO(0x2740)
913#define OAREPORTTRIG1_THRESHOLD_MASK 0xffff
914#define OAREPORTTRIG1_EDGE_LEVEL_TRIGGER_SELECT_MASK 0xffff0000
915
916#define OAREPORTTRIG2 _MMIO(0x2744)
917#define OAREPORTTRIG2_INVERT_A_0 (1 << 0)
918#define OAREPORTTRIG2_INVERT_A_1 (1 << 1)
919#define OAREPORTTRIG2_INVERT_A_2 (1 << 2)
920#define OAREPORTTRIG2_INVERT_A_3 (1 << 3)
921#define OAREPORTTRIG2_INVERT_A_4 (1 << 4)
922#define OAREPORTTRIG2_INVERT_A_5 (1 << 5)
923#define OAREPORTTRIG2_INVERT_A_6 (1 << 6)
924#define OAREPORTTRIG2_INVERT_A_7 (1 << 7)
925#define OAREPORTTRIG2_INVERT_A_8 (1 << 8)
926#define OAREPORTTRIG2_INVERT_A_9 (1 << 9)
927#define OAREPORTTRIG2_INVERT_A_10 (1 << 10)
928#define OAREPORTTRIG2_INVERT_A_11 (1 << 11)
929#define OAREPORTTRIG2_INVERT_A_12 (1 << 12)
930#define OAREPORTTRIG2_INVERT_A_13 (1 << 13)
931#define OAREPORTTRIG2_INVERT_A_14 (1 << 14)
932#define OAREPORTTRIG2_INVERT_A_15 (1 << 15)
933#define OAREPORTTRIG2_INVERT_B_0 (1 << 16)
934#define OAREPORTTRIG2_INVERT_B_1 (1 << 17)
935#define OAREPORTTRIG2_INVERT_B_2 (1 << 18)
936#define OAREPORTTRIG2_INVERT_B_3 (1 << 19)
937#define OAREPORTTRIG2_INVERT_C_0 (1 << 20)
938#define OAREPORTTRIG2_INVERT_C_1 (1 << 21)
939#define OAREPORTTRIG2_INVERT_D_0 (1 << 22)
940#define OAREPORTTRIG2_THRESHOLD_ENABLE (1 << 23)
941#define OAREPORTTRIG2_REPORT_TRIGGER_ENABLE (1 << 31)
942
943#define OAREPORTTRIG3 _MMIO(0x2748)
944#define OAREPORTTRIG3_NOA_SELECT_MASK 0xf
945#define OAREPORTTRIG3_NOA_SELECT_8_SHIFT 0
946#define OAREPORTTRIG3_NOA_SELECT_9_SHIFT 4
947#define OAREPORTTRIG3_NOA_SELECT_10_SHIFT 8
948#define OAREPORTTRIG3_NOA_SELECT_11_SHIFT 12
949#define OAREPORTTRIG3_NOA_SELECT_12_SHIFT 16
950#define OAREPORTTRIG3_NOA_SELECT_13_SHIFT 20
951#define OAREPORTTRIG3_NOA_SELECT_14_SHIFT 24
952#define OAREPORTTRIG3_NOA_SELECT_15_SHIFT 28
953
954#define OAREPORTTRIG4 _MMIO(0x274c)
955#define OAREPORTTRIG4_NOA_SELECT_MASK 0xf
956#define OAREPORTTRIG4_NOA_SELECT_0_SHIFT 0
957#define OAREPORTTRIG4_NOA_SELECT_1_SHIFT 4
958#define OAREPORTTRIG4_NOA_SELECT_2_SHIFT 8
959#define OAREPORTTRIG4_NOA_SELECT_3_SHIFT 12
960#define OAREPORTTRIG4_NOA_SELECT_4_SHIFT 16
961#define OAREPORTTRIG4_NOA_SELECT_5_SHIFT 20
962#define OAREPORTTRIG4_NOA_SELECT_6_SHIFT 24
963#define OAREPORTTRIG4_NOA_SELECT_7_SHIFT 28
964
965#define OAREPORTTRIG5 _MMIO(0x2750)
966#define OAREPORTTRIG5_THRESHOLD_MASK 0xffff
967#define OAREPORTTRIG5_EDGE_LEVEL_TRIGGER_SELECT_MASK 0xffff0000
968
969#define OAREPORTTRIG6 _MMIO(0x2754)
970#define OAREPORTTRIG6_INVERT_A_0 (1 << 0)
971#define OAREPORTTRIG6_INVERT_A_1 (1 << 1)
972#define OAREPORTTRIG6_INVERT_A_2 (1 << 2)
973#define OAREPORTTRIG6_INVERT_A_3 (1 << 3)
974#define OAREPORTTRIG6_INVERT_A_4 (1 << 4)
975#define OAREPORTTRIG6_INVERT_A_5 (1 << 5)
976#define OAREPORTTRIG6_INVERT_A_6 (1 << 6)
977#define OAREPORTTRIG6_INVERT_A_7 (1 << 7)
978#define OAREPORTTRIG6_INVERT_A_8 (1 << 8)
979#define OAREPORTTRIG6_INVERT_A_9 (1 << 9)
980#define OAREPORTTRIG6_INVERT_A_10 (1 << 10)
981#define OAREPORTTRIG6_INVERT_A_11 (1 << 11)
982#define OAREPORTTRIG6_INVERT_A_12 (1 << 12)
983#define OAREPORTTRIG6_INVERT_A_13 (1 << 13)
984#define OAREPORTTRIG6_INVERT_A_14 (1 << 14)
985#define OAREPORTTRIG6_INVERT_A_15 (1 << 15)
986#define OAREPORTTRIG6_INVERT_B_0 (1 << 16)
987#define OAREPORTTRIG6_INVERT_B_1 (1 << 17)
988#define OAREPORTTRIG6_INVERT_B_2 (1 << 18)
989#define OAREPORTTRIG6_INVERT_B_3 (1 << 19)
990#define OAREPORTTRIG6_INVERT_C_0 (1 << 20)
991#define OAREPORTTRIG6_INVERT_C_1 (1 << 21)
992#define OAREPORTTRIG6_INVERT_D_0 (1 << 22)
993#define OAREPORTTRIG6_THRESHOLD_ENABLE (1 << 23)
994#define OAREPORTTRIG6_REPORT_TRIGGER_ENABLE (1 << 31)
995
996#define OAREPORTTRIG7 _MMIO(0x2758)
997#define OAREPORTTRIG7_NOA_SELECT_MASK 0xf
998#define OAREPORTTRIG7_NOA_SELECT_8_SHIFT 0
999#define OAREPORTTRIG7_NOA_SELECT_9_SHIFT 4
1000#define OAREPORTTRIG7_NOA_SELECT_10_SHIFT 8
1001#define OAREPORTTRIG7_NOA_SELECT_11_SHIFT 12
1002#define OAREPORTTRIG7_NOA_SELECT_12_SHIFT 16
1003#define OAREPORTTRIG7_NOA_SELECT_13_SHIFT 20
1004#define OAREPORTTRIG7_NOA_SELECT_14_SHIFT 24
1005#define OAREPORTTRIG7_NOA_SELECT_15_SHIFT 28
1006
1007#define OAREPORTTRIG8 _MMIO(0x275c)
1008#define OAREPORTTRIG8_NOA_SELECT_MASK 0xf
1009#define OAREPORTTRIG8_NOA_SELECT_0_SHIFT 0
1010#define OAREPORTTRIG8_NOA_SELECT_1_SHIFT 4
1011#define OAREPORTTRIG8_NOA_SELECT_2_SHIFT 8
1012#define OAREPORTTRIG8_NOA_SELECT_3_SHIFT 12
1013#define OAREPORTTRIG8_NOA_SELECT_4_SHIFT 16
1014#define OAREPORTTRIG8_NOA_SELECT_5_SHIFT 20
1015#define OAREPORTTRIG8_NOA_SELECT_6_SHIFT 24
1016#define OAREPORTTRIG8_NOA_SELECT_7_SHIFT 28
1017
1018
1019#define GEN12_OAG_OASTARTTRIG1 _MMIO(0xd900)
1020#define GEN12_OAG_OASTARTTRIG2 _MMIO(0xd904)
1021#define GEN12_OAG_OASTARTTRIG3 _MMIO(0xd908)
1022#define GEN12_OAG_OASTARTTRIG4 _MMIO(0xd90c)
1023#define GEN12_OAG_OASTARTTRIG5 _MMIO(0xd910)
1024#define GEN12_OAG_OASTARTTRIG6 _MMIO(0xd914)
1025#define GEN12_OAG_OASTARTTRIG7 _MMIO(0xd918)
1026#define GEN12_OAG_OASTARTTRIG8 _MMIO(0xd91c)
1027
1028
1029#define GEN12_OAG_OAREPORTTRIG1 _MMIO(0xd920)
1030#define GEN12_OAG_OAREPORTTRIG2 _MMIO(0xd924)
1031#define GEN12_OAG_OAREPORTTRIG3 _MMIO(0xd928)
1032#define GEN12_OAG_OAREPORTTRIG4 _MMIO(0xd92c)
1033#define GEN12_OAG_OAREPORTTRIG5 _MMIO(0xd930)
1034#define GEN12_OAG_OAREPORTTRIG6 _MMIO(0xd934)
1035#define GEN12_OAG_OAREPORTTRIG7 _MMIO(0xd938)
1036#define GEN12_OAG_OAREPORTTRIG8 _MMIO(0xd93c)
1037
1038
1039#define OACEC_COMPARE_LESS_OR_EQUAL 6
1040#define OACEC_COMPARE_NOT_EQUAL 5
1041#define OACEC_COMPARE_LESS_THAN 4
1042#define OACEC_COMPARE_GREATER_OR_EQUAL 3
1043#define OACEC_COMPARE_EQUAL 2
1044#define OACEC_COMPARE_GREATER_THAN 1
1045#define OACEC_COMPARE_ANY_EQUAL 0
1046
1047#define OACEC_COMPARE_VALUE_MASK 0xffff
1048#define OACEC_COMPARE_VALUE_SHIFT 3
1049
1050#define OACEC_SELECT_NOA (0 << 19)
1051#define OACEC_SELECT_PREV (1 << 19)
1052#define OACEC_SELECT_BOOLEAN (2 << 19)
1053
1054
1055#define GEN12_OASCEC_NEGATE_MASK 0x7ff
1056#define GEN12_OASCEC_NEGATE_SHIFT 21
1057
1058
1059#define OACEC_MASK_MASK 0xffff
1060#define OACEC_CONSIDERATIONS_MASK 0xffff
1061#define OACEC_CONSIDERATIONS_SHIFT 16
1062
1063#define OACEC0_0 _MMIO(0x2770)
1064#define OACEC0_1 _MMIO(0x2774)
1065#define OACEC1_0 _MMIO(0x2778)
1066#define OACEC1_1 _MMIO(0x277c)
1067#define OACEC2_0 _MMIO(0x2780)
1068#define OACEC2_1 _MMIO(0x2784)
1069#define OACEC3_0 _MMIO(0x2788)
1070#define OACEC3_1 _MMIO(0x278c)
1071#define OACEC4_0 _MMIO(0x2790)
1072#define OACEC4_1 _MMIO(0x2794)
1073#define OACEC5_0 _MMIO(0x2798)
1074#define OACEC5_1 _MMIO(0x279c)
1075#define OACEC6_0 _MMIO(0x27a0)
1076#define OACEC6_1 _MMIO(0x27a4)
1077#define OACEC7_0 _MMIO(0x27a8)
1078#define OACEC7_1 _MMIO(0x27ac)
1079
1080
1081#define GEN12_OAG_CEC0_0 _MMIO(0xd940)
1082#define GEN12_OAG_CEC0_1 _MMIO(0xd944)
1083#define GEN12_OAG_CEC1_0 _MMIO(0xd948)
1084#define GEN12_OAG_CEC1_1 _MMIO(0xd94c)
1085#define GEN12_OAG_CEC2_0 _MMIO(0xd950)
1086#define GEN12_OAG_CEC2_1 _MMIO(0xd954)
1087#define GEN12_OAG_CEC3_0 _MMIO(0xd958)
1088#define GEN12_OAG_CEC3_1 _MMIO(0xd95c)
1089#define GEN12_OAG_CEC4_0 _MMIO(0xd960)
1090#define GEN12_OAG_CEC4_1 _MMIO(0xd964)
1091#define GEN12_OAG_CEC5_0 _MMIO(0xd968)
1092#define GEN12_OAG_CEC5_1 _MMIO(0xd96c)
1093#define GEN12_OAG_CEC6_0 _MMIO(0xd970)
1094#define GEN12_OAG_CEC6_1 _MMIO(0xd974)
1095#define GEN12_OAG_CEC7_0 _MMIO(0xd978)
1096#define GEN12_OAG_CEC7_1 _MMIO(0xd97c)
1097
1098
1099#define GEN12_OAG_SCEC0_0 _MMIO(0xdc00)
1100#define GEN12_OAG_SCEC0_1 _MMIO(0xdc04)
1101#define GEN12_OAG_SCEC1_0 _MMIO(0xdc08)
1102#define GEN12_OAG_SCEC1_1 _MMIO(0xdc0c)
1103#define GEN12_OAG_SCEC2_0 _MMIO(0xdc10)
1104#define GEN12_OAG_SCEC2_1 _MMIO(0xdc14)
1105#define GEN12_OAG_SCEC3_0 _MMIO(0xdc18)
1106#define GEN12_OAG_SCEC3_1 _MMIO(0xdc1c)
1107#define GEN12_OAG_SCEC4_0 _MMIO(0xdc20)
1108#define GEN12_OAG_SCEC4_1 _MMIO(0xdc24)
1109#define GEN12_OAG_SCEC5_0 _MMIO(0xdc28)
1110#define GEN12_OAG_SCEC5_1 _MMIO(0xdc2c)
1111#define GEN12_OAG_SCEC6_0 _MMIO(0xdc30)
1112#define GEN12_OAG_SCEC6_1 _MMIO(0xdc34)
1113#define GEN12_OAG_SCEC7_0 _MMIO(0xdc38)
1114#define GEN12_OAG_SCEC7_1 _MMIO(0xdc3c)
1115
1116
1117#define OA_PERFCNT1_LO _MMIO(0x91B8)
1118#define OA_PERFCNT1_HI _MMIO(0x91BC)
1119#define OA_PERFCNT2_LO _MMIO(0x91C0)
1120#define OA_PERFCNT2_HI _MMIO(0x91C4)
1121#define OA_PERFCNT3_LO _MMIO(0x91C8)
1122#define OA_PERFCNT3_HI _MMIO(0x91CC)
1123#define OA_PERFCNT4_LO _MMIO(0x91D8)
1124#define OA_PERFCNT4_HI _MMIO(0x91DC)
1125
1126#define OA_PERFMATRIX_LO _MMIO(0x91C8)
1127#define OA_PERFMATRIX_HI _MMIO(0x91CC)
1128
1129
1130#define RPM_CONFIG0 _MMIO(0x0D00)
1131#define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT 3
1132#define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK (1 << GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT)
1133#define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ 0
1134#define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ 1
1135#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT 3
1136#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK (0x7 << GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT)
1137#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ 0
1138#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ 1
1139#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ 2
1140#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ 3
1141#define GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT 1
1142#define GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK (0x3 << GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT)
1143
1144#define RPM_CONFIG1 _MMIO(0x0D04)
1145#define GEN10_GT_NOA_ENABLE (1 << 9)
1146
1147
1148#define CTC_MODE _MMIO(0xA26C)
1149#define CTC_SOURCE_PARAMETER_MASK 1
1150#define CTC_SOURCE_CRYSTAL_CLOCK 0
1151#define CTC_SOURCE_DIVIDE_LOGIC 1
1152#define CTC_SHIFT_PARAMETER_SHIFT 1
1153#define CTC_SHIFT_PARAMETER_MASK (0x3 << CTC_SHIFT_PARAMETER_SHIFT)
1154
1155
1156#define RCP_CONFIG _MMIO(0x0D08)
1157
1158
1159#define HSW_MBVID2_NOA0 _MMIO(0x9E80)
1160#define HSW_MBVID2_NOA1 _MMIO(0x9E84)
1161#define HSW_MBVID2_NOA2 _MMIO(0x9E88)
1162#define HSW_MBVID2_NOA3 _MMIO(0x9E8C)
1163#define HSW_MBVID2_NOA4 _MMIO(0x9E90)
1164#define HSW_MBVID2_NOA5 _MMIO(0x9E94)
1165#define HSW_MBVID2_NOA6 _MMIO(0x9E98)
1166#define HSW_MBVID2_NOA7 _MMIO(0x9E9C)
1167#define HSW_MBVID2_NOA8 _MMIO(0x9EA0)
1168#define HSW_MBVID2_NOA9 _MMIO(0x9EA4)
1169
1170#define HSW_MBVID2_MISR0 _MMIO(0x9EC0)
1171
1172
1173#define NOA_CONFIG(i) _MMIO(0x0D0C + (i) * 4)
1174
1175#define MICRO_BP0_0 _MMIO(0x9800)
1176#define MICRO_BP0_2 _MMIO(0x9804)
1177#define MICRO_BP0_1 _MMIO(0x9808)
1178
1179#define MICRO_BP1_0 _MMIO(0x980C)
1180#define MICRO_BP1_2 _MMIO(0x9810)
1181#define MICRO_BP1_1 _MMIO(0x9814)
1182
1183#define MICRO_BP2_0 _MMIO(0x9818)
1184#define MICRO_BP2_2 _MMIO(0x981C)
1185#define MICRO_BP2_1 _MMIO(0x9820)
1186
1187#define MICRO_BP3_0 _MMIO(0x9824)
1188#define MICRO_BP3_2 _MMIO(0x9828)
1189#define MICRO_BP3_1 _MMIO(0x982C)
1190
1191#define MICRO_BP_TRIGGER _MMIO(0x9830)
1192#define MICRO_BP3_COUNT_STATUS01 _MMIO(0x9834)
1193#define MICRO_BP3_COUNT_STATUS23 _MMIO(0x9838)
1194#define MICRO_BP_FIRED_ARMED _MMIO(0x983C)
1195
1196#define GEN12_OAA_DBG_REG _MMIO(0xdc44)
1197#define GEN12_OAG_OA_PESS _MMIO(0x2b2c)
1198#define GEN12_OAG_SPCTR_CNF _MMIO(0xdc40)
1199
1200#define GDT_CHICKEN_BITS _MMIO(0x9840)
1201#define GT_NOA_ENABLE 0x00000080
1202
1203#define NOA_DATA _MMIO(0x986C)
1204#define NOA_WRITE _MMIO(0x9888)
1205#define GEN10_NOA_WRITE_HIGH _MMIO(0x9884)
1206
1207#define _GEN7_PIPEA_DE_LOAD_SL 0x70068
1208#define _GEN7_PIPEB_DE_LOAD_SL 0x71068
1209#define GEN7_PIPE_DE_LOAD_SL(pipe) _MMIO_PIPE(pipe, _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL)
1210
1211
1212
1213
1214#define DEBUG_RESET_I830 _MMIO(0x6070)
1215#define DEBUG_RESET_FULL (1 << 7)
1216#define DEBUG_RESET_RENDER (1 << 8)
1217#define DEBUG_RESET_DISPLAY (1 << 9)
1218
1219
1220
1221
1222#define VLV_IOSF_DOORBELL_REQ _MMIO(VLV_DISPLAY_BASE + 0x2100)
1223#define IOSF_DEVFN_SHIFT 24
1224#define IOSF_OPCODE_SHIFT 16
1225#define IOSF_PORT_SHIFT 8
1226#define IOSF_BYTE_ENABLES_SHIFT 4
1227#define IOSF_BAR_SHIFT 1
1228#define IOSF_SB_BUSY (1 << 0)
1229#define IOSF_PORT_BUNIT 0x03
1230#define IOSF_PORT_PUNIT 0x04
1231#define IOSF_PORT_NC 0x11
1232#define IOSF_PORT_DPIO 0x12
1233#define IOSF_PORT_GPIO_NC 0x13
1234#define IOSF_PORT_CCK 0x14
1235#define IOSF_PORT_DPIO_2 0x1a
1236#define IOSF_PORT_FLISDSI 0x1b
1237#define IOSF_PORT_GPIO_SC 0x48
1238#define IOSF_PORT_GPIO_SUS 0xa8
1239#define IOSF_PORT_CCU 0xa9
1240#define CHV_IOSF_PORT_GPIO_N 0x13
1241#define CHV_IOSF_PORT_GPIO_SE 0x48
1242#define CHV_IOSF_PORT_GPIO_E 0xa8
1243#define CHV_IOSF_PORT_GPIO_SW 0xb2
1244#define VLV_IOSF_DATA _MMIO(VLV_DISPLAY_BASE + 0x2104)
1245#define VLV_IOSF_ADDR _MMIO(VLV_DISPLAY_BASE + 0x2108)
1246
1247
1248#define BUNIT_REG_BISOC 0x11
1249
1250
1251#define _SSPM0_SSC(val) ((val) << 0)
1252#define SSPM0_SSC_MASK _SSPM0_SSC(0x3)
1253#define SSPM0_SSC_PWR_ON _SSPM0_SSC(0x0)
1254#define SSPM0_SSC_CLK_GATE _SSPM0_SSC(0x1)
1255#define SSPM0_SSC_RESET _SSPM0_SSC(0x2)
1256#define SSPM0_SSC_PWR_GATE _SSPM0_SSC(0x3)
1257#define _SSPM0_SSS(val) ((val) << 24)
1258#define SSPM0_SSS_MASK _SSPM0_SSS(0x3)
1259#define SSPM0_SSS_PWR_ON _SSPM0_SSS(0x0)
1260#define SSPM0_SSS_CLK_GATE _SSPM0_SSS(0x1)
1261#define SSPM0_SSS_RESET _SSPM0_SSS(0x2)
1262#define SSPM0_SSS_PWR_GATE _SSPM0_SSS(0x3)
1263
1264
1265#define SSPM1_FREQSTAT_SHIFT 24
1266#define SSPM1_FREQSTAT_MASK (0x1f << SSPM1_FREQSTAT_SHIFT)
1267#define SSPM1_FREQGUAR_SHIFT 8
1268#define SSPM1_FREQGUAR_MASK (0x1f << SSPM1_FREQGUAR_SHIFT)
1269#define SSPM1_FREQ_SHIFT 0
1270#define SSPM1_FREQ_MASK (0x1f << SSPM1_FREQ_SHIFT)
1271
1272#define PUNIT_REG_VEDSSPM0 0x32
1273#define PUNIT_REG_VEDSSPM1 0x33
1274
1275#define PUNIT_REG_DSPSSPM 0x36
1276#define DSPFREQSTAT_SHIFT_CHV 24
1277#define DSPFREQSTAT_MASK_CHV (0x1f << DSPFREQSTAT_SHIFT_CHV)
1278#define DSPFREQGUAR_SHIFT_CHV 8
1279#define DSPFREQGUAR_MASK_CHV (0x1f << DSPFREQGUAR_SHIFT_CHV)
1280#define DSPFREQSTAT_SHIFT 30
1281#define DSPFREQSTAT_MASK (0x3 << DSPFREQSTAT_SHIFT)
1282#define DSPFREQGUAR_SHIFT 14
1283#define DSPFREQGUAR_MASK (0x3 << DSPFREQGUAR_SHIFT)
1284#define DSP_MAXFIFO_PM5_STATUS (1 << 22)
1285#define DSP_AUTO_CDCLK_GATE_DISABLE (1 << 7)
1286#define DSP_MAXFIFO_PM5_ENABLE (1 << 6)
1287#define _DP_SSC(val, pipe) ((val) << (2 * (pipe)))
1288#define DP_SSC_MASK(pipe) _DP_SSC(0x3, (pipe))
1289#define DP_SSC_PWR_ON(pipe) _DP_SSC(0x0, (pipe))
1290#define DP_SSC_CLK_GATE(pipe) _DP_SSC(0x1, (pipe))
1291#define DP_SSC_RESET(pipe) _DP_SSC(0x2, (pipe))
1292#define DP_SSC_PWR_GATE(pipe) _DP_SSC(0x3, (pipe))
1293#define _DP_SSS(val, pipe) ((val) << (2 * (pipe) + 16))
1294#define DP_SSS_MASK(pipe) _DP_SSS(0x3, (pipe))
1295#define DP_SSS_PWR_ON(pipe) _DP_SSS(0x0, (pipe))
1296#define DP_SSS_CLK_GATE(pipe) _DP_SSS(0x1, (pipe))
1297#define DP_SSS_RESET(pipe) _DP_SSS(0x2, (pipe))
1298#define DP_SSS_PWR_GATE(pipe) _DP_SSS(0x3, (pipe))
1299
1300#define PUNIT_REG_ISPSSPM0 0x39
1301#define PUNIT_REG_ISPSSPM1 0x3a
1302
1303#define PUNIT_REG_PWRGT_CTRL 0x60
1304#define PUNIT_REG_PWRGT_STATUS 0x61
1305#define PUNIT_PWRGT_MASK(pw_idx) (3 << ((pw_idx) * 2))
1306#define PUNIT_PWRGT_PWR_ON(pw_idx) (0 << ((pw_idx) * 2))
1307#define PUNIT_PWRGT_CLK_GATE(pw_idx) (1 << ((pw_idx) * 2))
1308#define PUNIT_PWRGT_RESET(pw_idx) (2 << ((pw_idx) * 2))
1309#define PUNIT_PWRGT_PWR_GATE(pw_idx) (3 << ((pw_idx) * 2))
1310
1311#define PUNIT_PWGT_IDX_RENDER 0
1312#define PUNIT_PWGT_IDX_MEDIA 1
1313#define PUNIT_PWGT_IDX_DISP2D 3
1314#define PUNIT_PWGT_IDX_DPIO_CMN_BC 5
1315#define PUNIT_PWGT_IDX_DPIO_TX_B_LANES_01 6
1316#define PUNIT_PWGT_IDX_DPIO_TX_B_LANES_23 7
1317#define PUNIT_PWGT_IDX_DPIO_TX_C_LANES_01 8
1318#define PUNIT_PWGT_IDX_DPIO_TX_C_LANES_23 9
1319#define PUNIT_PWGT_IDX_DPIO_RX0 10
1320#define PUNIT_PWGT_IDX_DPIO_RX1 11
1321#define PUNIT_PWGT_IDX_DPIO_CMN_D 12
1322
1323#define PUNIT_REG_GPU_LFM 0xd3
1324#define PUNIT_REG_GPU_FREQ_REQ 0xd4
1325#define PUNIT_REG_GPU_FREQ_STS 0xd8
1326#define GPLLENABLE (1 << 4)
1327#define GENFREQSTATUS (1 << 0)
1328#define PUNIT_REG_MEDIA_TURBO_FREQ_REQ 0xdc
1329#define PUNIT_REG_CZ_TIMESTAMP 0xce
1330
1331#define PUNIT_FUSE_BUS2 0xf6
1332#define PUNIT_FUSE_BUS1 0xf5
1333
1334#define FB_GFX_FMAX_AT_VMAX_FUSE 0x136
1335#define FB_GFX_FREQ_FUSE_MASK 0xff
1336#define FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT 24
1337#define FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT 16
1338#define FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT 8
1339
1340#define FB_GFX_FMIN_AT_VMIN_FUSE 0x137
1341#define FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT 8
1342
1343#define PUNIT_REG_DDR_SETUP2 0x139
1344#define FORCE_DDR_FREQ_REQ_ACK (1 << 8)
1345#define FORCE_DDR_LOW_FREQ (1 << 1)
1346#define FORCE_DDR_HIGH_FREQ (1 << 0)
1347
1348#define PUNIT_GPU_STATUS_REG 0xdb
1349#define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16
1350#define PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xff
1351#define PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT 8
1352#define PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK 0xff
1353
1354#define PUNIT_GPU_DUTYCYCLE_REG 0xdf
1355#define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT 8
1356#define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK 0xff
1357
1358#define IOSF_NC_FB_GFX_FREQ_FUSE 0x1c
1359#define FB_GFX_MAX_FREQ_FUSE_SHIFT 3
1360#define FB_GFX_MAX_FREQ_FUSE_MASK 0x000007f8
1361#define FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT 11
1362#define FB_GFX_FGUARANTEED_FREQ_FUSE_MASK 0x0007f800
1363#define IOSF_NC_FB_GFX_FMAX_FUSE_HI 0x34
1364#define FB_FMAX_VMIN_FREQ_HI_MASK 0x00000007
1365#define IOSF_NC_FB_GFX_FMAX_FUSE_LO 0x30
1366#define FB_FMAX_VMIN_FREQ_LO_SHIFT 27
1367#define FB_FMAX_VMIN_FREQ_LO_MASK 0xf8000000
1368
1369#define VLV_TURBO_SOC_OVERRIDE 0x04
1370#define VLV_OVERRIDE_EN 1
1371#define VLV_SOC_TDP_EN (1 << 1)
1372#define VLV_BIAS_CPU_125_SOC_875 (6 << 2)
1373#define CHV_BIAS_CPU_50_SOC_50 (3 << 2)
1374
1375
1376#define CCK_FUSE_REG 0x8
1377#define CCK_FUSE_HPLL_FREQ_MASK 0x3
1378#define CCK_REG_DSI_PLL_FUSE 0x44
1379#define CCK_REG_DSI_PLL_CONTROL 0x48
1380#define DSI_PLL_VCO_EN (1 << 31)
1381#define DSI_PLL_LDO_GATE (1 << 30)
1382#define DSI_PLL_P1_POST_DIV_SHIFT 17
1383#define DSI_PLL_P1_POST_DIV_MASK (0x1ff << 17)
1384#define DSI_PLL_P2_MUX_DSI0_DIV2 (1 << 13)
1385#define DSI_PLL_P3_MUX_DSI1_DIV2 (1 << 12)
1386#define DSI_PLL_MUX_MASK (3 << 9)
1387#define DSI_PLL_MUX_DSI0_DSIPLL (0 << 10)
1388#define DSI_PLL_MUX_DSI0_CCK (1 << 10)
1389#define DSI_PLL_MUX_DSI1_DSIPLL (0 << 9)
1390#define DSI_PLL_MUX_DSI1_CCK (1 << 9)
1391#define DSI_PLL_CLK_GATE_MASK (0xf << 5)
1392#define DSI_PLL_CLK_GATE_DSI0_DSIPLL (1 << 8)
1393#define DSI_PLL_CLK_GATE_DSI1_DSIPLL (1 << 7)
1394#define DSI_PLL_CLK_GATE_DSI0_CCK (1 << 6)
1395#define DSI_PLL_CLK_GATE_DSI1_CCK (1 << 5)
1396#define DSI_PLL_LOCK (1 << 0)
1397#define CCK_REG_DSI_PLL_DIVIDER 0x4c
1398#define DSI_PLL_LFSR (1 << 31)
1399#define DSI_PLL_FRACTION_EN (1 << 30)
1400#define DSI_PLL_FRAC_COUNTER_SHIFT 27
1401#define DSI_PLL_FRAC_COUNTER_MASK (7 << 27)
1402#define DSI_PLL_USYNC_CNT_SHIFT 18
1403#define DSI_PLL_USYNC_CNT_MASK (0x1ff << 18)
1404#define DSI_PLL_N1_DIV_SHIFT 16
1405#define DSI_PLL_N1_DIV_MASK (3 << 16)
1406#define DSI_PLL_M1_DIV_SHIFT 0
1407#define DSI_PLL_M1_DIV_MASK (0x1ff << 0)
1408#define CCK_CZ_CLOCK_CONTROL 0x62
1409#define CCK_GPLL_CLOCK_CONTROL 0x67
1410#define CCK_DISPLAY_CLOCK_CONTROL 0x6b
1411#define CCK_DISPLAY_REF_CLOCK_CONTROL 0x6c
1412#define CCK_TRUNK_FORCE_ON (1 << 17)
1413#define CCK_TRUNK_FORCE_OFF (1 << 16)
1414#define CCK_FREQUENCY_STATUS (0x1f << 8)
1415#define CCK_FREQUENCY_STATUS_SHIFT 8
1416#define CCK_FREQUENCY_VALUES (0x1f << 0)
1417
1418
1419#define DPIO_DEVFN 0
1420
1421#define DPIO_CTL _MMIO(VLV_DISPLAY_BASE + 0x2110)
1422#define DPIO_MODSEL1 (1 << 3)
1423#define DPIO_MODSEL0 (1 << 2)
1424#define DPIO_SFR_BYPASS (1 << 1)
1425#define DPIO_CMNRST (1 << 0)
1426
1427#define DPIO_PHY(pipe) ((pipe) >> 1)
1428
1429
1430
1431
1432#define _VLV_PLL_DW3_CH0 0x800c
1433#define DPIO_POST_DIV_SHIFT (28)
1434#define DPIO_POST_DIV_DAC 0
1435#define DPIO_POST_DIV_HDMIDP 1
1436#define DPIO_POST_DIV_LVDS1 2
1437#define DPIO_POST_DIV_LVDS2 3
1438#define DPIO_K_SHIFT (24)
1439#define DPIO_P1_SHIFT (21)
1440#define DPIO_P2_SHIFT (16)
1441#define DPIO_N_SHIFT (12)
1442#define DPIO_ENABLE_CALIBRATION (1 << 11)
1443#define DPIO_M1DIV_SHIFT (8)
1444#define DPIO_M2DIV_MASK 0xff
1445#define _VLV_PLL_DW3_CH1 0x802c
1446#define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1)
1447
1448#define _VLV_PLL_DW5_CH0 0x8014
1449#define DPIO_REFSEL_OVERRIDE 27
1450#define DPIO_PLL_MODESEL_SHIFT 24
1451#define DPIO_BIAS_CURRENT_CTL_SHIFT 21
1452#define DPIO_PLL_REFCLK_SEL_SHIFT 16
1453#define DPIO_PLL_REFCLK_SEL_MASK 3
1454#define DPIO_DRIVER_CTL_SHIFT 12
1455#define DPIO_CLK_BIAS_CTL_SHIFT 8
1456#define _VLV_PLL_DW5_CH1 0x8034
1457#define VLV_PLL_DW5(ch) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1)
1458
1459#define _VLV_PLL_DW7_CH0 0x801c
1460#define _VLV_PLL_DW7_CH1 0x803c
1461#define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1)
1462
1463#define _VLV_PLL_DW8_CH0 0x8040
1464#define _VLV_PLL_DW8_CH1 0x8060
1465#define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1)
1466
1467#define VLV_PLL_DW9_BCAST 0xc044
1468#define _VLV_PLL_DW9_CH0 0x8044
1469#define _VLV_PLL_DW9_CH1 0x8064
1470#define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1)
1471
1472#define _VLV_PLL_DW10_CH0 0x8048
1473#define _VLV_PLL_DW10_CH1 0x8068
1474#define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1)
1475
1476#define _VLV_PLL_DW11_CH0 0x804c
1477#define _VLV_PLL_DW11_CH1 0x806c
1478#define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1)
1479
1480
1481#define VLV_REF_DW13 0x80ac
1482
1483#define VLV_CMN_DW0 0x8100
1484
1485
1486
1487
1488
1489#define _VLV_PCS_DW0_CH0 0x8200
1490#define _VLV_PCS_DW0_CH1 0x8400
1491#define DPIO_PCS_TX_LANE2_RESET (1 << 16)
1492#define DPIO_PCS_TX_LANE1_RESET (1 << 7)
1493#define DPIO_LEFT_TXFIFO_RST_MASTER2 (1 << 4)
1494#define DPIO_RIGHT_TXFIFO_RST_MASTER2 (1 << 3)
1495#define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1)
1496
1497#define _VLV_PCS01_DW0_CH0 0x200
1498#define _VLV_PCS23_DW0_CH0 0x400
1499#define _VLV_PCS01_DW0_CH1 0x2600
1500#define _VLV_PCS23_DW0_CH1 0x2800
1501#define VLV_PCS01_DW0(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1)
1502#define VLV_PCS23_DW0(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1)
1503
1504#define _VLV_PCS_DW1_CH0 0x8204
1505#define _VLV_PCS_DW1_CH1 0x8404
1506#define CHV_PCS_REQ_SOFTRESET_EN (1 << 23)
1507#define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN (1 << 22)
1508#define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1 << 21)
1509#define DPIO_PCS_CLK_DATAWIDTH_SHIFT (6)
1510#define DPIO_PCS_CLK_SOFT_RESET (1 << 5)
1511#define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1)
1512
1513#define _VLV_PCS01_DW1_CH0 0x204
1514#define _VLV_PCS23_DW1_CH0 0x404
1515#define _VLV_PCS01_DW1_CH1 0x2604
1516#define _VLV_PCS23_DW1_CH1 0x2804
1517#define VLV_PCS01_DW1(ch) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1)
1518#define VLV_PCS23_DW1(ch) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1)
1519
1520#define _VLV_PCS_DW8_CH0 0x8220
1521#define _VLV_PCS_DW8_CH1 0x8420
1522#define CHV_PCS_USEDCLKCHANNEL_OVRRIDE (1 << 20)
1523#define CHV_PCS_USEDCLKCHANNEL (1 << 21)
1524#define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1)
1525
1526#define _VLV_PCS01_DW8_CH0 0x0220
1527#define _VLV_PCS23_DW8_CH0 0x0420
1528#define _VLV_PCS01_DW8_CH1 0x2620
1529#define _VLV_PCS23_DW8_CH1 0x2820
1530#define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1)
1531#define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1)
1532
1533#define _VLV_PCS_DW9_CH0 0x8224
1534#define _VLV_PCS_DW9_CH1 0x8424
1535#define DPIO_PCS_TX2MARGIN_MASK (0x7 << 13)
1536#define DPIO_PCS_TX2MARGIN_000 (0 << 13)
1537#define DPIO_PCS_TX2MARGIN_101 (1 << 13)
1538#define DPIO_PCS_TX1MARGIN_MASK (0x7 << 10)
1539#define DPIO_PCS_TX1MARGIN_000 (0 << 10)
1540#define DPIO_PCS_TX1MARGIN_101 (1 << 10)
1541#define VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1)
1542
1543#define _VLV_PCS01_DW9_CH0 0x224
1544#define _VLV_PCS23_DW9_CH0 0x424
1545#define _VLV_PCS01_DW9_CH1 0x2624
1546#define _VLV_PCS23_DW9_CH1 0x2824
1547#define VLV_PCS01_DW9(ch) _PORT(ch, _VLV_PCS01_DW9_CH0, _VLV_PCS01_DW9_CH1)
1548#define VLV_PCS23_DW9(ch) _PORT(ch, _VLV_PCS23_DW9_CH0, _VLV_PCS23_DW9_CH1)
1549
1550#define _CHV_PCS_DW10_CH0 0x8228
1551#define _CHV_PCS_DW10_CH1 0x8428
1552#define DPIO_PCS_SWING_CALC_TX0_TX2 (1 << 30)
1553#define DPIO_PCS_SWING_CALC_TX1_TX3 (1 << 31)
1554#define DPIO_PCS_TX2DEEMP_MASK (0xf << 24)
1555#define DPIO_PCS_TX2DEEMP_9P5 (0 << 24)
1556#define DPIO_PCS_TX2DEEMP_6P0 (2 << 24)
1557#define DPIO_PCS_TX1DEEMP_MASK (0xf << 16)
1558#define DPIO_PCS_TX1DEEMP_9P5 (0 << 16)
1559#define DPIO_PCS_TX1DEEMP_6P0 (2 << 16)
1560#define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1)
1561
1562#define _VLV_PCS01_DW10_CH0 0x0228
1563#define _VLV_PCS23_DW10_CH0 0x0428
1564#define _VLV_PCS01_DW10_CH1 0x2628
1565#define _VLV_PCS23_DW10_CH1 0x2828
1566#define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1)
1567#define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1)
1568
1569#define _VLV_PCS_DW11_CH0 0x822c
1570#define _VLV_PCS_DW11_CH1 0x842c
1571#define DPIO_TX2_STAGGER_MASK(x) ((x) << 24)
1572#define DPIO_LANEDESKEW_STRAP_OVRD (1 << 3)
1573#define DPIO_LEFT_TXFIFO_RST_MASTER (1 << 1)
1574#define DPIO_RIGHT_TXFIFO_RST_MASTER (1 << 0)
1575#define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1)
1576
1577#define _VLV_PCS01_DW11_CH0 0x022c
1578#define _VLV_PCS23_DW11_CH0 0x042c
1579#define _VLV_PCS01_DW11_CH1 0x262c
1580#define _VLV_PCS23_DW11_CH1 0x282c
1581#define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW11_CH0, _VLV_PCS01_DW11_CH1)
1582#define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW11_CH0, _VLV_PCS23_DW11_CH1)
1583
1584#define _VLV_PCS01_DW12_CH0 0x0230
1585#define _VLV_PCS23_DW12_CH0 0x0430
1586#define _VLV_PCS01_DW12_CH1 0x2630
1587#define _VLV_PCS23_DW12_CH1 0x2830
1588#define VLV_PCS01_DW12(ch) _PORT(ch, _VLV_PCS01_DW12_CH0, _VLV_PCS01_DW12_CH1)
1589#define VLV_PCS23_DW12(ch) _PORT(ch, _VLV_PCS23_DW12_CH0, _VLV_PCS23_DW12_CH1)
1590
1591#define _VLV_PCS_DW12_CH0 0x8230
1592#define _VLV_PCS_DW12_CH1 0x8430
1593#define DPIO_TX2_STAGGER_MULT(x) ((x) << 20)
1594#define DPIO_TX1_STAGGER_MULT(x) ((x) << 16)
1595#define DPIO_TX1_STAGGER_MASK(x) ((x) << 8)
1596#define DPIO_LANESTAGGER_STRAP_OVRD (1 << 6)
1597#define DPIO_LANESTAGGER_STRAP(x) ((x) << 0)
1598#define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1)
1599
1600#define _VLV_PCS_DW14_CH0 0x8238
1601#define _VLV_PCS_DW14_CH1 0x8438
1602#define VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1)
1603
1604#define _VLV_PCS_DW23_CH0 0x825c
1605#define _VLV_PCS_DW23_CH1 0x845c
1606#define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1)
1607
1608#define _VLV_TX_DW2_CH0 0x8288
1609#define _VLV_TX_DW2_CH1 0x8488
1610#define DPIO_SWING_MARGIN000_SHIFT 16
1611#define DPIO_SWING_MARGIN000_MASK (0xff << DPIO_SWING_MARGIN000_SHIFT)
1612#define DPIO_UNIQ_TRANS_SCALE_SHIFT 8
1613#define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1)
1614
1615#define _VLV_TX_DW3_CH0 0x828c
1616#define _VLV_TX_DW3_CH1 0x848c
1617
1618#define DPIO_TX_UNIQ_TRANS_SCALE_EN (1 << 27)
1619#define DPIO_SWING_MARGIN101_SHIFT 16
1620#define DPIO_SWING_MARGIN101_MASK (0xff << DPIO_SWING_MARGIN101_SHIFT)
1621#define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1)
1622
1623#define _VLV_TX_DW4_CH0 0x8290
1624#define _VLV_TX_DW4_CH1 0x8490
1625#define DPIO_SWING_DEEMPH9P5_SHIFT 24
1626#define DPIO_SWING_DEEMPH9P5_MASK (0xff << DPIO_SWING_DEEMPH9P5_SHIFT)
1627#define DPIO_SWING_DEEMPH6P0_SHIFT 16
1628#define DPIO_SWING_DEEMPH6P0_MASK (0xff << DPIO_SWING_DEEMPH6P0_SHIFT)
1629#define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1)
1630
1631#define _VLV_TX3_DW4_CH0 0x690
1632#define _VLV_TX3_DW4_CH1 0x2a90
1633#define VLV_TX3_DW4(ch) _PORT(ch, _VLV_TX3_DW4_CH0, _VLV_TX3_DW4_CH1)
1634
1635#define _VLV_TX_DW5_CH0 0x8294
1636#define _VLV_TX_DW5_CH1 0x8494
1637#define DPIO_TX_OCALINIT_EN (1 << 31)
1638#define VLV_TX_DW5(ch) _PORT(ch, _VLV_TX_DW5_CH0, _VLV_TX_DW5_CH1)
1639
1640#define _VLV_TX_DW11_CH0 0x82ac
1641#define _VLV_TX_DW11_CH1 0x84ac
1642#define VLV_TX_DW11(ch) _PORT(ch, _VLV_TX_DW11_CH0, _VLV_TX_DW11_CH1)
1643
1644#define _VLV_TX_DW14_CH0 0x82b8
1645#define _VLV_TX_DW14_CH1 0x84b8
1646#define VLV_TX_DW14(ch) _PORT(ch, _VLV_TX_DW14_CH0, _VLV_TX_DW14_CH1)
1647
1648
1649#define _CHV_PLL_DW0_CH0 0x8000
1650#define _CHV_PLL_DW0_CH1 0x8180
1651#define CHV_PLL_DW0(ch) _PIPE(ch, _CHV_PLL_DW0_CH0, _CHV_PLL_DW0_CH1)
1652
1653#define _CHV_PLL_DW1_CH0 0x8004
1654#define _CHV_PLL_DW1_CH1 0x8184
1655#define DPIO_CHV_N_DIV_SHIFT 8
1656#define DPIO_CHV_M1_DIV_BY_2 (0 << 0)
1657#define CHV_PLL_DW1(ch) _PIPE(ch, _CHV_PLL_DW1_CH0, _CHV_PLL_DW1_CH1)
1658
1659#define _CHV_PLL_DW2_CH0 0x8008
1660#define _CHV_PLL_DW2_CH1 0x8188
1661#define CHV_PLL_DW2(ch) _PIPE(ch, _CHV_PLL_DW2_CH0, _CHV_PLL_DW2_CH1)
1662
1663#define _CHV_PLL_DW3_CH0 0x800c
1664#define _CHV_PLL_DW3_CH1 0x818c
1665#define DPIO_CHV_FRAC_DIV_EN (1 << 16)
1666#define DPIO_CHV_FIRST_MOD (0 << 8)
1667#define DPIO_CHV_SECOND_MOD (1 << 8)
1668#define DPIO_CHV_FEEDFWD_GAIN_SHIFT 0
1669#define DPIO_CHV_FEEDFWD_GAIN_MASK (0xF << 0)
1670#define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1)
1671
1672#define _CHV_PLL_DW6_CH0 0x8018
1673#define _CHV_PLL_DW6_CH1 0x8198
1674#define DPIO_CHV_GAIN_CTRL_SHIFT 16
1675#define DPIO_CHV_INT_COEFF_SHIFT 8
1676#define DPIO_CHV_PROP_COEFF_SHIFT 0
1677#define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1)
1678
1679#define _CHV_PLL_DW8_CH0 0x8020
1680#define _CHV_PLL_DW8_CH1 0x81A0
1681#define DPIO_CHV_TDC_TARGET_CNT_SHIFT 0
1682#define DPIO_CHV_TDC_TARGET_CNT_MASK (0x3FF << 0)
1683#define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1)
1684
1685#define _CHV_PLL_DW9_CH0 0x8024
1686#define _CHV_PLL_DW9_CH1 0x81A4
1687#define DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT 1
1688#define DPIO_CHV_INT_LOCK_THRESHOLD_MASK (7 << 1)
1689#define DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE 1
1690#define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1)
1691
1692#define _CHV_CMN_DW0_CH0 0x8100
1693#define DPIO_ALLDL_POWERDOWN_SHIFT_CH0 19
1694#define DPIO_ANYDL_POWERDOWN_SHIFT_CH0 18
1695#define DPIO_ALLDL_POWERDOWN (1 << 1)
1696#define DPIO_ANYDL_POWERDOWN (1 << 0)
1697
1698#define _CHV_CMN_DW5_CH0 0x8114
1699#define CHV_BUFRIGHTENA1_DISABLE (0 << 20)
1700#define CHV_BUFRIGHTENA1_NORMAL (1 << 20)
1701#define CHV_BUFRIGHTENA1_FORCE (3 << 20)
1702#define CHV_BUFRIGHTENA1_MASK (3 << 20)
1703#define CHV_BUFLEFTENA1_DISABLE (0 << 22)
1704#define CHV_BUFLEFTENA1_NORMAL (1 << 22)
1705#define CHV_BUFLEFTENA1_FORCE (3 << 22)
1706#define CHV_BUFLEFTENA1_MASK (3 << 22)
1707
1708#define _CHV_CMN_DW13_CH0 0x8134
1709#define _CHV_CMN_DW0_CH1 0x8080
1710#define DPIO_CHV_S1_DIV_SHIFT 21
1711#define DPIO_CHV_P1_DIV_SHIFT 13
1712#define DPIO_CHV_P2_DIV_SHIFT 8
1713#define DPIO_CHV_K_DIV_SHIFT 4
1714#define DPIO_PLL_FREQLOCK (1 << 1)
1715#define DPIO_PLL_LOCK (1 << 0)
1716#define CHV_CMN_DW13(ch) _PIPE(ch, _CHV_CMN_DW13_CH0, _CHV_CMN_DW0_CH1)
1717
1718#define _CHV_CMN_DW14_CH0 0x8138
1719#define _CHV_CMN_DW1_CH1 0x8084
1720#define DPIO_AFC_RECAL (1 << 14)
1721#define DPIO_DCLKP_EN (1 << 13)
1722#define CHV_BUFLEFTENA2_DISABLE (0 << 17)
1723#define CHV_BUFLEFTENA2_NORMAL (1 << 17)
1724#define CHV_BUFLEFTENA2_FORCE (3 << 17)
1725#define CHV_BUFLEFTENA2_MASK (3 << 17)
1726#define CHV_BUFRIGHTENA2_DISABLE (0 << 19)
1727#define CHV_BUFRIGHTENA2_NORMAL (1 << 19)
1728#define CHV_BUFRIGHTENA2_FORCE (3 << 19)
1729#define CHV_BUFRIGHTENA2_MASK (3 << 19)
1730#define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1)
1731
1732#define _CHV_CMN_DW19_CH0 0x814c
1733#define _CHV_CMN_DW6_CH1 0x8098
1734#define DPIO_ALLDL_POWERDOWN_SHIFT_CH1 30
1735#define DPIO_ANYDL_POWERDOWN_SHIFT_CH1 29
1736#define DPIO_DYNPWRDOWNEN_CH1 (1 << 28)
1737#define CHV_CMN_USEDCLKCHANNEL (1 << 13)
1738
1739#define CHV_CMN_DW19(ch) _PIPE(ch, _CHV_CMN_DW19_CH0, _CHV_CMN_DW6_CH1)
1740
1741#define CHV_CMN_DW28 0x8170
1742#define DPIO_CL1POWERDOWNEN (1 << 23)
1743#define DPIO_DYNPWRDOWNEN_CH0 (1 << 22)
1744#define DPIO_SUS_CLK_CONFIG_ON (0 << 0)
1745#define DPIO_SUS_CLK_CONFIG_CLKREQ (1 << 0)
1746#define DPIO_SUS_CLK_CONFIG_GATE (2 << 0)
1747#define DPIO_SUS_CLK_CONFIG_GATE_CLKREQ (3 << 0)
1748
1749#define CHV_CMN_DW30 0x8178
1750#define DPIO_CL2_LDOFUSE_PWRENB (1 << 6)
1751#define DPIO_LRC_BYPASS (1 << 3)
1752
1753#define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \
1754 (lane) * 0x200 + (offset))
1755
1756#define CHV_TX_DW0(ch, lane) _TXLANE(ch, lane, 0x80)
1757#define CHV_TX_DW1(ch, lane) _TXLANE(ch, lane, 0x84)
1758#define CHV_TX_DW2(ch, lane) _TXLANE(ch, lane, 0x88)
1759#define CHV_TX_DW3(ch, lane) _TXLANE(ch, lane, 0x8c)
1760#define CHV_TX_DW4(ch, lane) _TXLANE(ch, lane, 0x90)
1761#define CHV_TX_DW5(ch, lane) _TXLANE(ch, lane, 0x94)
1762#define CHV_TX_DW6(ch, lane) _TXLANE(ch, lane, 0x98)
1763#define CHV_TX_DW7(ch, lane) _TXLANE(ch, lane, 0x9c)
1764#define CHV_TX_DW8(ch, lane) _TXLANE(ch, lane, 0xa0)
1765#define CHV_TX_DW9(ch, lane) _TXLANE(ch, lane, 0xa4)
1766#define CHV_TX_DW10(ch, lane) _TXLANE(ch, lane, 0xa8)
1767#define CHV_TX_DW11(ch, lane) _TXLANE(ch, lane, 0xac)
1768#define DPIO_FRC_LATENCY_SHFIT 8
1769#define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8)
1770#define DPIO_UPAR_SHIFT 30
1771
1772
1773#define _BXT_PHY0_BASE 0x6C000
1774#define _BXT_PHY1_BASE 0x162000
1775#define _BXT_PHY2_BASE 0x163000
1776#define BXT_PHY_BASE(phy) _PHY3((phy), _BXT_PHY0_BASE, \
1777 _BXT_PHY1_BASE, \
1778 _BXT_PHY2_BASE)
1779
1780#define _BXT_PHY(phy, reg) \
1781 _MMIO(BXT_PHY_BASE(phy) - _BXT_PHY0_BASE + (reg))
1782
1783#define _BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) \
1784 (BXT_PHY_BASE(phy) + _PIPE((ch), (reg_ch0) - _BXT_PHY0_BASE, \
1785 (reg_ch1) - _BXT_PHY0_BASE))
1786#define _MMIO_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) \
1787 _MMIO(_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1))
1788
1789#define BXT_P_CR_GT_DISP_PWRON _MMIO(0x138090)
1790#define MIPIO_RST_CTRL (1 << 2)
1791
1792#define _BXT_PHY_CTL_DDI_A 0x64C00
1793#define _BXT_PHY_CTL_DDI_B 0x64C10
1794#define _BXT_PHY_CTL_DDI_C 0x64C20
1795#define BXT_PHY_CMNLANE_POWERDOWN_ACK (1 << 10)
1796#define BXT_PHY_LANE_POWERDOWN_ACK (1 << 9)
1797#define BXT_PHY_LANE_ENABLED (1 << 8)
1798#define BXT_PHY_CTL(port) _MMIO_PORT(port, _BXT_PHY_CTL_DDI_A, \
1799 _BXT_PHY_CTL_DDI_B)
1800
1801#define _PHY_CTL_FAMILY_EDP 0x64C80
1802#define _PHY_CTL_FAMILY_DDI 0x64C90
1803#define _PHY_CTL_FAMILY_DDI_C 0x64CA0
1804#define COMMON_RESET_DIS (1 << 31)
1805#define BXT_PHY_CTL_FAMILY(phy) _MMIO_PHY3((phy), _PHY_CTL_FAMILY_DDI, \
1806 _PHY_CTL_FAMILY_EDP, \
1807 _PHY_CTL_FAMILY_DDI_C)
1808
1809
1810#define _PORT_PLL_A 0x46074
1811#define _PORT_PLL_B 0x46078
1812#define _PORT_PLL_C 0x4607c
1813#define PORT_PLL_ENABLE (1 << 31)
1814#define PORT_PLL_LOCK (1 << 30)
1815#define PORT_PLL_REF_SEL (1 << 27)
1816#define PORT_PLL_POWER_ENABLE (1 << 26)
1817#define PORT_PLL_POWER_STATE (1 << 25)
1818#define BXT_PORT_PLL_ENABLE(port) _MMIO_PORT(port, _PORT_PLL_A, _PORT_PLL_B)
1819
1820#define _PORT_PLL_EBB_0_A 0x162034
1821#define _PORT_PLL_EBB_0_B 0x6C034
1822#define _PORT_PLL_EBB_0_C 0x6C340
1823#define PORT_PLL_P1_SHIFT 13
1824#define PORT_PLL_P1_MASK (0x07 << PORT_PLL_P1_SHIFT)
1825#define PORT_PLL_P1(x) ((x) << PORT_PLL_P1_SHIFT)
1826#define PORT_PLL_P2_SHIFT 8
1827#define PORT_PLL_P2_MASK (0x1f << PORT_PLL_P2_SHIFT)
1828#define PORT_PLL_P2(x) ((x) << PORT_PLL_P2_SHIFT)
1829#define BXT_PORT_PLL_EBB_0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
1830 _PORT_PLL_EBB_0_B, \
1831 _PORT_PLL_EBB_0_C)
1832
1833#define _PORT_PLL_EBB_4_A 0x162038
1834#define _PORT_PLL_EBB_4_B 0x6C038
1835#define _PORT_PLL_EBB_4_C 0x6C344
1836#define PORT_PLL_10BIT_CLK_ENABLE (1 << 13)
1837#define PORT_PLL_RECALIBRATE (1 << 14)
1838#define BXT_PORT_PLL_EBB_4(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
1839 _PORT_PLL_EBB_4_B, \
1840 _PORT_PLL_EBB_4_C)
1841
1842#define _PORT_PLL_0_A 0x162100
1843#define _PORT_PLL_0_B 0x6C100
1844#define _PORT_PLL_0_C 0x6C380
1845
1846#define PORT_PLL_M2_MASK 0xFF
1847
1848#define PORT_PLL_N_SHIFT 8
1849#define PORT_PLL_N_MASK (0x0F << PORT_PLL_N_SHIFT)
1850#define PORT_PLL_N(x) ((x) << PORT_PLL_N_SHIFT)
1851
1852#define PORT_PLL_M2_FRAC_MASK 0x3FFFFF
1853
1854#define PORT_PLL_M2_FRAC_ENABLE (1 << 16)
1855
1856#define PORT_PLL_PROP_COEFF_MASK 0xF
1857#define PORT_PLL_INT_COEFF_MASK (0x1F << 8)
1858#define PORT_PLL_INT_COEFF(x) ((x) << 8)
1859#define PORT_PLL_GAIN_CTL_MASK (0x07 << 16)
1860#define PORT_PLL_GAIN_CTL(x) ((x) << 16)
1861
1862#define PORT_PLL_TARGET_CNT_MASK 0x3FF
1863
1864#define PORT_PLL_LOCK_THRESHOLD_SHIFT 1
1865#define PORT_PLL_LOCK_THRESHOLD_MASK (0x7 << PORT_PLL_LOCK_THRESHOLD_SHIFT)
1866
1867#define PORT_PLL_DCO_AMP_OVR_EN_H (1 << 27)
1868#define PORT_PLL_DCO_AMP_DEFAULT 15
1869#define PORT_PLL_DCO_AMP_MASK 0x3c00
1870#define PORT_PLL_DCO_AMP(x) ((x) << 10)
1871#define _PORT_PLL_BASE(phy, ch) _BXT_PHY_CH(phy, ch, \
1872 _PORT_PLL_0_B, \
1873 _PORT_PLL_0_C)
1874#define BXT_PORT_PLL(phy, ch, idx) _MMIO(_PORT_PLL_BASE(phy, ch) + \
1875 (idx) * 4)
1876
1877
1878#define _PORT_CL1CM_DW0_A 0x162000
1879#define _PORT_CL1CM_DW0_BC 0x6C000
1880#define PHY_POWER_GOOD (1 << 16)
1881#define PHY_RESERVED (1 << 7)
1882#define BXT_PORT_CL1CM_DW0(phy) _BXT_PHY((phy), _PORT_CL1CM_DW0_BC)
1883
1884#define _PORT_CL1CM_DW9_A 0x162024
1885#define _PORT_CL1CM_DW9_BC 0x6C024
1886#define IREF0RC_OFFSET_SHIFT 8
1887#define IREF0RC_OFFSET_MASK (0xFF << IREF0RC_OFFSET_SHIFT)
1888#define BXT_PORT_CL1CM_DW9(phy) _BXT_PHY((phy), _PORT_CL1CM_DW9_BC)
1889
1890#define _PORT_CL1CM_DW10_A 0x162028
1891#define _PORT_CL1CM_DW10_BC 0x6C028
1892#define IREF1RC_OFFSET_SHIFT 8
1893#define IREF1RC_OFFSET_MASK (0xFF << IREF1RC_OFFSET_SHIFT)
1894#define BXT_PORT_CL1CM_DW10(phy) _BXT_PHY((phy), _PORT_CL1CM_DW10_BC)
1895
1896#define _PORT_CL1CM_DW28_A 0x162070
1897#define _PORT_CL1CM_DW28_BC 0x6C070
1898#define OCL1_POWER_DOWN_EN (1 << 23)
1899#define DW28_OLDO_DYN_PWR_DOWN_EN (1 << 22)
1900#define SUS_CLK_CONFIG 0x3
1901#define BXT_PORT_CL1CM_DW28(phy) _BXT_PHY((phy), _PORT_CL1CM_DW28_BC)
1902
1903#define _PORT_CL1CM_DW30_A 0x162078
1904#define _PORT_CL1CM_DW30_BC 0x6C078
1905#define OCL2_LDOFUSE_PWR_DIS (1 << 6)
1906#define BXT_PORT_CL1CM_DW30(phy) _BXT_PHY((phy), _PORT_CL1CM_DW30_BC)
1907
1908
1909
1910
1911#define _ICL_COMBOPHY_A 0x162000
1912#define _ICL_COMBOPHY_B 0x6C000
1913#define _EHL_COMBOPHY_C 0x160000
1914#define _RKL_COMBOPHY_D 0x161000
1915#define _ADL_COMBOPHY_E 0x16B000
1916
1917#define _ICL_COMBOPHY(phy) _PICK(phy, _ICL_COMBOPHY_A, \
1918 _ICL_COMBOPHY_B, \
1919 _EHL_COMBOPHY_C, \
1920 _RKL_COMBOPHY_D, \
1921 _ADL_COMBOPHY_E)
1922
1923
1924#define _ICL_PORT_CL_DW(dw, phy) (_ICL_COMBOPHY(phy) + \
1925 4 * (dw))
1926
1927#define ICL_PORT_CL_DW5(phy) _MMIO(_ICL_PORT_CL_DW(5, phy))
1928#define CL_POWER_DOWN_ENABLE (1 << 4)
1929#define SUS_CLOCK_CONFIG (3 << 0)
1930
1931#define ICL_PORT_CL_DW10(phy) _MMIO(_ICL_PORT_CL_DW(10, phy))
1932#define PG_SEQ_DELAY_OVERRIDE_MASK (3 << 25)
1933#define PG_SEQ_DELAY_OVERRIDE_SHIFT 25
1934#define PG_SEQ_DELAY_OVERRIDE_ENABLE (1 << 24)
1935#define PWR_UP_ALL_LANES (0x0 << 4)
1936#define PWR_DOWN_LN_3_2_1 (0xe << 4)
1937#define PWR_DOWN_LN_3_2 (0xc << 4)
1938#define PWR_DOWN_LN_3 (0x8 << 4)
1939#define PWR_DOWN_LN_2_1_0 (0x7 << 4)
1940#define PWR_DOWN_LN_1_0 (0x3 << 4)
1941#define PWR_DOWN_LN_3_1 (0xa << 4)
1942#define PWR_DOWN_LN_3_1_0 (0xb << 4)
1943#define PWR_DOWN_LN_MASK (0xf << 4)
1944#define PWR_DOWN_LN_SHIFT 4
1945#define EDP4K2K_MODE_OVRD_EN (1 << 3)
1946#define EDP4K2K_MODE_OVRD_OPTIMIZED (1 << 2)
1947
1948#define ICL_PORT_CL_DW12(phy) _MMIO(_ICL_PORT_CL_DW(12, phy))
1949#define ICL_LANE_ENABLE_AUX (1 << 0)
1950
1951
1952#define _ICL_PORT_COMP 0x100
1953#define _ICL_PORT_COMP_DW(dw, phy) (_ICL_COMBOPHY(phy) + \
1954 _ICL_PORT_COMP + 4 * (dw))
1955
1956#define ICL_PORT_COMP_DW0(phy) _MMIO(_ICL_PORT_COMP_DW(0, phy))
1957#define COMP_INIT (1 << 31)
1958
1959#define ICL_PORT_COMP_DW1(phy) _MMIO(_ICL_PORT_COMP_DW(1, phy))
1960
1961#define ICL_PORT_COMP_DW3(phy) _MMIO(_ICL_PORT_COMP_DW(3, phy))
1962#define PROCESS_INFO_DOT_0 (0 << 26)
1963#define PROCESS_INFO_DOT_1 (1 << 26)
1964#define PROCESS_INFO_DOT_4 (2 << 26)
1965#define PROCESS_INFO_MASK (7 << 26)
1966#define PROCESS_INFO_SHIFT 26
1967#define VOLTAGE_INFO_0_85V (0 << 24)
1968#define VOLTAGE_INFO_0_95V (1 << 24)
1969#define VOLTAGE_INFO_1_05V (2 << 24)
1970#define VOLTAGE_INFO_MASK (3 << 24)
1971#define VOLTAGE_INFO_SHIFT 24
1972
1973#define ICL_PORT_COMP_DW8(phy) _MMIO(_ICL_PORT_COMP_DW(8, phy))
1974#define IREFGEN (1 << 24)
1975
1976#define ICL_PORT_COMP_DW9(phy) _MMIO(_ICL_PORT_COMP_DW(9, phy))
1977
1978#define ICL_PORT_COMP_DW10(phy) _MMIO(_ICL_PORT_COMP_DW(10, phy))
1979
1980
1981#define _ICL_PORT_PCS_AUX 0x300
1982#define _ICL_PORT_PCS_GRP 0x600
1983#define _ICL_PORT_PCS_LN(ln) (0x800 + (ln) * 0x100)
1984#define _ICL_PORT_PCS_DW_AUX(dw, phy) (_ICL_COMBOPHY(phy) + \
1985 _ICL_PORT_PCS_AUX + 4 * (dw))
1986#define _ICL_PORT_PCS_DW_GRP(dw, phy) (_ICL_COMBOPHY(phy) + \
1987 _ICL_PORT_PCS_GRP + 4 * (dw))
1988#define _ICL_PORT_PCS_DW_LN(dw, ln, phy) (_ICL_COMBOPHY(phy) + \
1989 _ICL_PORT_PCS_LN(ln) + 4 * (dw))
1990#define ICL_PORT_PCS_DW1_AUX(phy) _MMIO(_ICL_PORT_PCS_DW_AUX(1, phy))
1991#define ICL_PORT_PCS_DW1_GRP(phy) _MMIO(_ICL_PORT_PCS_DW_GRP(1, phy))
1992#define ICL_PORT_PCS_DW1_LN(ln, phy) _MMIO(_ICL_PORT_PCS_DW_LN(1, ln, phy))
1993#define DCC_MODE_SELECT_MASK (0x3 << 20)
1994#define DCC_MODE_SELECT_CONTINUOSLY (0x3 << 20)
1995#define COMMON_KEEPER_EN (1 << 26)
1996#define LATENCY_OPTIM_MASK (0x3 << 2)
1997#define LATENCY_OPTIM_VAL(x) ((x) << 2)
1998
1999
2000#define _ICL_PORT_TX_AUX 0x380
2001#define _ICL_PORT_TX_GRP 0x680
2002#define _ICL_PORT_TX_LN(ln) (0x880 + (ln) * 0x100)
2003
2004#define _ICL_PORT_TX_DW_AUX(dw, phy) (_ICL_COMBOPHY(phy) + \
2005 _ICL_PORT_TX_AUX + 4 * (dw))
2006#define _ICL_PORT_TX_DW_GRP(dw, phy) (_ICL_COMBOPHY(phy) + \
2007 _ICL_PORT_TX_GRP + 4 * (dw))
2008#define _ICL_PORT_TX_DW_LN(dw, ln, phy) (_ICL_COMBOPHY(phy) + \
2009 _ICL_PORT_TX_LN(ln) + 4 * (dw))
2010
2011#define ICL_PORT_TX_DW2_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(2, phy))
2012#define ICL_PORT_TX_DW2_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(2, phy))
2013#define ICL_PORT_TX_DW2_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(2, ln, phy))
2014#define SWING_SEL_UPPER(x) (((x) >> 3) << 15)
2015#define SWING_SEL_UPPER_MASK (1 << 15)
2016#define SWING_SEL_LOWER(x) (((x) & 0x7) << 11)
2017#define SWING_SEL_LOWER_MASK (0x7 << 11)
2018#define FRC_LATENCY_OPTIM_MASK (0x7 << 8)
2019#define FRC_LATENCY_OPTIM_VAL(x) ((x) << 8)
2020#define RCOMP_SCALAR(x) ((x) << 0)
2021#define RCOMP_SCALAR_MASK (0xFF << 0)
2022
2023#define ICL_PORT_TX_DW4_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(4, phy))
2024#define ICL_PORT_TX_DW4_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(4, phy))
2025#define ICL_PORT_TX_DW4_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(4, ln, phy))
2026#define LOADGEN_SELECT (1 << 31)
2027#define POST_CURSOR_1(x) ((x) << 12)
2028#define POST_CURSOR_1_MASK (0x3F << 12)
2029#define POST_CURSOR_2(x) ((x) << 6)
2030#define POST_CURSOR_2_MASK (0x3F << 6)
2031#define CURSOR_COEFF(x) ((x) << 0)
2032#define CURSOR_COEFF_MASK (0x3F << 0)
2033
2034#define ICL_PORT_TX_DW5_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(5, phy))
2035#define ICL_PORT_TX_DW5_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(5, phy))
2036#define ICL_PORT_TX_DW5_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(5, ln, phy))
2037#define TX_TRAINING_EN (1 << 31)
2038#define TAP2_DISABLE (1 << 30)
2039#define TAP3_DISABLE (1 << 29)
2040#define SCALING_MODE_SEL(x) ((x) << 18)
2041#define SCALING_MODE_SEL_MASK (0x7 << 18)
2042#define RTERM_SELECT(x) ((x) << 3)
2043#define RTERM_SELECT_MASK (0x7 << 3)
2044
2045#define ICL_PORT_TX_DW7_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(7, phy))
2046#define ICL_PORT_TX_DW7_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(7, phy))
2047#define ICL_PORT_TX_DW7_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(7, ln, phy))
2048#define N_SCALAR(x) ((x) << 24)
2049#define N_SCALAR_MASK (0x7F << 24)
2050
2051#define ICL_PORT_TX_DW8_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(8, phy))
2052#define ICL_PORT_TX_DW8_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(8, phy))
2053#define ICL_PORT_TX_DW8_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(8, ln, phy))
2054#define ICL_PORT_TX_DW8_ODCC_CLK_SEL REG_BIT(31)
2055#define ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK REG_GENMASK(30, 29)
2056#define ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2 REG_FIELD_PREP(ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK, 0x1)
2057
2058#define _ICL_DPHY_CHKN_REG 0x194
2059#define ICL_DPHY_CHKN(port) _MMIO(_ICL_COMBOPHY(port) + _ICL_DPHY_CHKN_REG)
2060#define ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP REG_BIT(7)
2061
2062#define MG_PHY_PORT_LN(ln, tc_port, ln0p1, ln0p2, ln1p1) \
2063 _MMIO(_PORT(tc_port, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1)))
2064
2065#define MG_TX_LINK_PARAMS_TX1LN0_PORT1 0x16812C
2066#define MG_TX_LINK_PARAMS_TX1LN1_PORT1 0x16852C
2067#define MG_TX_LINK_PARAMS_TX1LN0_PORT2 0x16912C
2068#define MG_TX_LINK_PARAMS_TX1LN1_PORT2 0x16952C
2069#define MG_TX_LINK_PARAMS_TX1LN0_PORT3 0x16A12C
2070#define MG_TX_LINK_PARAMS_TX1LN1_PORT3 0x16A52C
2071#define MG_TX_LINK_PARAMS_TX1LN0_PORT4 0x16B12C
2072#define MG_TX_LINK_PARAMS_TX1LN1_PORT4 0x16B52C
2073#define MG_TX1_LINK_PARAMS(ln, tc_port) \
2074 MG_PHY_PORT_LN(ln, tc_port, MG_TX_LINK_PARAMS_TX1LN0_PORT1, \
2075 MG_TX_LINK_PARAMS_TX1LN0_PORT2, \
2076 MG_TX_LINK_PARAMS_TX1LN1_PORT1)
2077
2078#define MG_TX_LINK_PARAMS_TX2LN0_PORT1 0x1680AC
2079#define MG_TX_LINK_PARAMS_TX2LN1_PORT1 0x1684AC
2080#define MG_TX_LINK_PARAMS_TX2LN0_PORT2 0x1690AC
2081#define MG_TX_LINK_PARAMS_TX2LN1_PORT2 0x1694AC
2082#define MG_TX_LINK_PARAMS_TX2LN0_PORT3 0x16A0AC
2083#define MG_TX_LINK_PARAMS_TX2LN1_PORT3 0x16A4AC
2084#define MG_TX_LINK_PARAMS_TX2LN0_PORT4 0x16B0AC
2085#define MG_TX_LINK_PARAMS_TX2LN1_PORT4 0x16B4AC
2086#define MG_TX2_LINK_PARAMS(ln, tc_port) \
2087 MG_PHY_PORT_LN(ln, tc_port, MG_TX_LINK_PARAMS_TX2LN0_PORT1, \
2088 MG_TX_LINK_PARAMS_TX2LN0_PORT2, \
2089 MG_TX_LINK_PARAMS_TX2LN1_PORT1)
2090#define CRI_USE_FS32 (1 << 5)
2091
2092#define MG_TX_PISO_READLOAD_TX1LN0_PORT1 0x16814C
2093#define MG_TX_PISO_READLOAD_TX1LN1_PORT1 0x16854C
2094#define MG_TX_PISO_READLOAD_TX1LN0_PORT2 0x16914C
2095#define MG_TX_PISO_READLOAD_TX1LN1_PORT2 0x16954C
2096#define MG_TX_PISO_READLOAD_TX1LN0_PORT3 0x16A14C
2097#define MG_TX_PISO_READLOAD_TX1LN1_PORT3 0x16A54C
2098#define MG_TX_PISO_READLOAD_TX1LN0_PORT4 0x16B14C
2099#define MG_TX_PISO_READLOAD_TX1LN1_PORT4 0x16B54C
2100#define MG_TX1_PISO_READLOAD(ln, tc_port) \
2101 MG_PHY_PORT_LN(ln, tc_port, MG_TX_PISO_READLOAD_TX1LN0_PORT1, \
2102 MG_TX_PISO_READLOAD_TX1LN0_PORT2, \
2103 MG_TX_PISO_READLOAD_TX1LN1_PORT1)
2104
2105#define MG_TX_PISO_READLOAD_TX2LN0_PORT1 0x1680CC
2106#define MG_TX_PISO_READLOAD_TX2LN1_PORT1 0x1684CC
2107#define MG_TX_PISO_READLOAD_TX2LN0_PORT2 0x1690CC
2108#define MG_TX_PISO_READLOAD_TX2LN1_PORT2 0x1694CC
2109#define MG_TX_PISO_READLOAD_TX2LN0_PORT3 0x16A0CC
2110#define MG_TX_PISO_READLOAD_TX2LN1_PORT3 0x16A4CC
2111#define MG_TX_PISO_READLOAD_TX2LN0_PORT4 0x16B0CC
2112#define MG_TX_PISO_READLOAD_TX2LN1_PORT4 0x16B4CC
2113#define MG_TX2_PISO_READLOAD(ln, tc_port) \
2114 MG_PHY_PORT_LN(ln, tc_port, MG_TX_PISO_READLOAD_TX2LN0_PORT1, \
2115 MG_TX_PISO_READLOAD_TX2LN0_PORT2, \
2116 MG_TX_PISO_READLOAD_TX2LN1_PORT1)
2117#define CRI_CALCINIT (1 << 1)
2118
2119#define MG_TX_SWINGCTRL_TX1LN0_PORT1 0x168148
2120#define MG_TX_SWINGCTRL_TX1LN1_PORT1 0x168548
2121#define MG_TX_SWINGCTRL_TX1LN0_PORT2 0x169148
2122#define MG_TX_SWINGCTRL_TX1LN1_PORT2 0x169548
2123#define MG_TX_SWINGCTRL_TX1LN0_PORT3 0x16A148
2124#define MG_TX_SWINGCTRL_TX1LN1_PORT3 0x16A548
2125#define MG_TX_SWINGCTRL_TX1LN0_PORT4 0x16B148
2126#define MG_TX_SWINGCTRL_TX1LN1_PORT4 0x16B548
2127#define MG_TX1_SWINGCTRL(ln, tc_port) \
2128 MG_PHY_PORT_LN(ln, tc_port, MG_TX_SWINGCTRL_TX1LN0_PORT1, \
2129 MG_TX_SWINGCTRL_TX1LN0_PORT2, \
2130 MG_TX_SWINGCTRL_TX1LN1_PORT1)
2131
2132#define MG_TX_SWINGCTRL_TX2LN0_PORT1 0x1680C8
2133#define MG_TX_SWINGCTRL_TX2LN1_PORT1 0x1684C8
2134#define MG_TX_SWINGCTRL_TX2LN0_PORT2 0x1690C8
2135#define MG_TX_SWINGCTRL_TX2LN1_PORT2 0x1694C8
2136#define MG_TX_SWINGCTRL_TX2LN0_PORT3 0x16A0C8
2137#define MG_TX_SWINGCTRL_TX2LN1_PORT3 0x16A4C8
2138#define MG_TX_SWINGCTRL_TX2LN0_PORT4 0x16B0C8
2139#define MG_TX_SWINGCTRL_TX2LN1_PORT4 0x16B4C8
2140#define MG_TX2_SWINGCTRL(ln, tc_port) \
2141 MG_PHY_PORT_LN(ln, tc_port, MG_TX_SWINGCTRL_TX2LN0_PORT1, \
2142 MG_TX_SWINGCTRL_TX2LN0_PORT2, \
2143 MG_TX_SWINGCTRL_TX2LN1_PORT1)
2144#define CRI_TXDEEMPH_OVERRIDE_17_12(x) ((x) << 0)
2145#define CRI_TXDEEMPH_OVERRIDE_17_12_MASK (0x3F << 0)
2146
2147#define MG_TX_DRVCTRL_TX1LN0_TXPORT1 0x168144
2148#define MG_TX_DRVCTRL_TX1LN1_TXPORT1 0x168544
2149#define MG_TX_DRVCTRL_TX1LN0_TXPORT2 0x169144
2150#define MG_TX_DRVCTRL_TX1LN1_TXPORT2 0x169544
2151#define MG_TX_DRVCTRL_TX1LN0_TXPORT3 0x16A144
2152#define MG_TX_DRVCTRL_TX1LN1_TXPORT3 0x16A544
2153#define MG_TX_DRVCTRL_TX1LN0_TXPORT4 0x16B144
2154#define MG_TX_DRVCTRL_TX1LN1_TXPORT4 0x16B544
2155#define MG_TX1_DRVCTRL(ln, tc_port) \
2156 MG_PHY_PORT_LN(ln, tc_port, MG_TX_DRVCTRL_TX1LN0_TXPORT1, \
2157 MG_TX_DRVCTRL_TX1LN0_TXPORT2, \
2158 MG_TX_DRVCTRL_TX1LN1_TXPORT1)
2159
2160#define MG_TX_DRVCTRL_TX2LN0_PORT1 0x1680C4
2161#define MG_TX_DRVCTRL_TX2LN1_PORT1 0x1684C4
2162#define MG_TX_DRVCTRL_TX2LN0_PORT2 0x1690C4
2163#define MG_TX_DRVCTRL_TX2LN1_PORT2 0x1694C4
2164#define MG_TX_DRVCTRL_TX2LN0_PORT3 0x16A0C4
2165#define MG_TX_DRVCTRL_TX2LN1_PORT3 0x16A4C4
2166#define MG_TX_DRVCTRL_TX2LN0_PORT4 0x16B0C4
2167#define MG_TX_DRVCTRL_TX2LN1_PORT4 0x16B4C4
2168#define MG_TX2_DRVCTRL(ln, tc_port) \
2169 MG_PHY_PORT_LN(ln, tc_port, MG_TX_DRVCTRL_TX2LN0_PORT1, \
2170 MG_TX_DRVCTRL_TX2LN0_PORT2, \
2171 MG_TX_DRVCTRL_TX2LN1_PORT1)
2172#define CRI_TXDEEMPH_OVERRIDE_11_6(x) ((x) << 24)
2173#define CRI_TXDEEMPH_OVERRIDE_11_6_MASK (0x3F << 24)
2174#define CRI_TXDEEMPH_OVERRIDE_EN (1 << 22)
2175#define CRI_TXDEEMPH_OVERRIDE_5_0(x) ((x) << 16)
2176#define CRI_TXDEEMPH_OVERRIDE_5_0_MASK (0x3F << 16)
2177#define CRI_LOADGEN_SEL(x) ((x) << 12)
2178#define CRI_LOADGEN_SEL_MASK (0x3 << 12)
2179
2180#define MG_CLKHUB_LN0_PORT1 0x16839C
2181#define MG_CLKHUB_LN1_PORT1 0x16879C
2182#define MG_CLKHUB_LN0_PORT2 0x16939C
2183#define MG_CLKHUB_LN1_PORT2 0x16979C
2184#define MG_CLKHUB_LN0_PORT3 0x16A39C
2185#define MG_CLKHUB_LN1_PORT3 0x16A79C
2186#define MG_CLKHUB_LN0_PORT4 0x16B39C
2187#define MG_CLKHUB_LN1_PORT4 0x16B79C
2188#define MG_CLKHUB(ln, tc_port) \
2189 MG_PHY_PORT_LN(ln, tc_port, MG_CLKHUB_LN0_PORT1, \
2190 MG_CLKHUB_LN0_PORT2, \
2191 MG_CLKHUB_LN1_PORT1)
2192#define CFG_LOW_RATE_LKREN_EN (1 << 11)
2193
2194#define MG_TX_DCC_TX1LN0_PORT1 0x168110
2195#define MG_TX_DCC_TX1LN1_PORT1 0x168510
2196#define MG_TX_DCC_TX1LN0_PORT2 0x169110
2197#define MG_TX_DCC_TX1LN1_PORT2 0x169510
2198#define MG_TX_DCC_TX1LN0_PORT3 0x16A110
2199#define MG_TX_DCC_TX1LN1_PORT3 0x16A510
2200#define MG_TX_DCC_TX1LN0_PORT4 0x16B110
2201#define MG_TX_DCC_TX1LN1_PORT4 0x16B510
2202#define MG_TX1_DCC(ln, tc_port) \
2203 MG_PHY_PORT_LN(ln, tc_port, MG_TX_DCC_TX1LN0_PORT1, \
2204 MG_TX_DCC_TX1LN0_PORT2, \
2205 MG_TX_DCC_TX1LN1_PORT1)
2206#define MG_TX_DCC_TX2LN0_PORT1 0x168090
2207#define MG_TX_DCC_TX2LN1_PORT1 0x168490
2208#define MG_TX_DCC_TX2LN0_PORT2 0x169090
2209#define MG_TX_DCC_TX2LN1_PORT2 0x169490
2210#define MG_TX_DCC_TX2LN0_PORT3 0x16A090
2211#define MG_TX_DCC_TX2LN1_PORT3 0x16A490
2212#define MG_TX_DCC_TX2LN0_PORT4 0x16B090
2213#define MG_TX_DCC_TX2LN1_PORT4 0x16B490
2214#define MG_TX2_DCC(ln, tc_port) \
2215 MG_PHY_PORT_LN(ln, tc_port, MG_TX_DCC_TX2LN0_PORT1, \
2216 MG_TX_DCC_TX2LN0_PORT2, \
2217 MG_TX_DCC_TX2LN1_PORT1)
2218#define CFG_AMI_CK_DIV_OVERRIDE_VAL(x) ((x) << 25)
2219#define CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK (0x3 << 25)
2220#define CFG_AMI_CK_DIV_OVERRIDE_EN (1 << 24)
2221
2222#define MG_DP_MODE_LN0_ACU_PORT1 0x1683A0
2223#define MG_DP_MODE_LN1_ACU_PORT1 0x1687A0
2224#define MG_DP_MODE_LN0_ACU_PORT2 0x1693A0
2225#define MG_DP_MODE_LN1_ACU_PORT2 0x1697A0
2226#define MG_DP_MODE_LN0_ACU_PORT3 0x16A3A0
2227#define MG_DP_MODE_LN1_ACU_PORT3 0x16A7A0
2228#define MG_DP_MODE_LN0_ACU_PORT4 0x16B3A0
2229#define MG_DP_MODE_LN1_ACU_PORT4 0x16B7A0
2230#define MG_DP_MODE(ln, tc_port) \
2231 MG_PHY_PORT_LN(ln, tc_port, MG_DP_MODE_LN0_ACU_PORT1, \
2232 MG_DP_MODE_LN0_ACU_PORT2, \
2233 MG_DP_MODE_LN1_ACU_PORT1)
2234#define MG_DP_MODE_CFG_DP_X2_MODE (1 << 7)
2235#define MG_DP_MODE_CFG_DP_X1_MODE (1 << 6)
2236
2237
2238
2239
2240#define _SNPS_PHY_A_BASE 0x168000
2241#define _SNPS_PHY_B_BASE 0x169000
2242#define _SNPS_PHY(phy) _PHY(phy, \
2243 _SNPS_PHY_A_BASE, \
2244 _SNPS_PHY_B_BASE)
2245#define _SNPS2(phy, reg) (_SNPS_PHY(phy) - \
2246 _SNPS_PHY_A_BASE + (reg))
2247#define _MMIO_SNPS(phy, reg) _MMIO(_SNPS2(phy, reg))
2248#define _MMIO_SNPS_LN(ln, phy, reg) _MMIO(_SNPS2(phy, \
2249 (reg) + (ln) * 0x10))
2250
2251#define SNPS_PHY_MPLLB_CP(phy) _MMIO_SNPS(phy, 0x168000)
2252#define SNPS_PHY_MPLLB_CP_INT REG_GENMASK(31, 25)
2253#define SNPS_PHY_MPLLB_CP_INT_GS REG_GENMASK(23, 17)
2254#define SNPS_PHY_MPLLB_CP_PROP REG_GENMASK(15, 9)
2255#define SNPS_PHY_MPLLB_CP_PROP_GS REG_GENMASK(7, 1)
2256
2257#define SNPS_PHY_MPLLB_DIV(phy) _MMIO_SNPS(phy, 0x168004)
2258#define SNPS_PHY_MPLLB_FORCE_EN REG_BIT(31)
2259#define SNPS_PHY_MPLLB_DIV_CLK_EN REG_BIT(30)
2260#define SNPS_PHY_MPLLB_DIV5_CLK_EN REG_BIT(29)
2261#define SNPS_PHY_MPLLB_V2I REG_GENMASK(27, 26)
2262#define SNPS_PHY_MPLLB_FREQ_VCO REG_GENMASK(25, 24)
2263#define SNPS_PHY_MPLLB_DIV_MULTIPLIER REG_GENMASK(23, 16)
2264#define SNPS_PHY_MPLLB_PMIX_EN REG_BIT(10)
2265#define SNPS_PHY_MPLLB_DP2_MODE REG_BIT(9)
2266#define SNPS_PHY_MPLLB_WORD_DIV2_EN REG_BIT(8)
2267#define SNPS_PHY_MPLLB_TX_CLK_DIV REG_GENMASK(7, 5)
2268#define SNPS_PHY_MPLLB_SHIM_DIV32_CLK_SEL REG_BIT(0)
2269
2270#define SNPS_PHY_MPLLB_FRACN1(phy) _MMIO_SNPS(phy, 0x168008)
2271#define SNPS_PHY_MPLLB_FRACN_EN REG_BIT(31)
2272#define SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN REG_BIT(30)
2273#define SNPS_PHY_MPLLB_FRACN_DEN REG_GENMASK(15, 0)
2274
2275#define SNPS_PHY_MPLLB_FRACN2(phy) _MMIO_SNPS(phy, 0x16800C)
2276#define SNPS_PHY_MPLLB_FRACN_REM REG_GENMASK(31, 16)
2277#define SNPS_PHY_MPLLB_FRACN_QUOT REG_GENMASK(15, 0)
2278
2279#define SNPS_PHY_MPLLB_SSCEN(phy) _MMIO_SNPS(phy, 0x168014)
2280#define SNPS_PHY_MPLLB_SSC_EN REG_BIT(31)
2281#define SNPS_PHY_MPLLB_SSC_UP_SPREAD REG_BIT(30)
2282#define SNPS_PHY_MPLLB_SSC_PEAK REG_GENMASK(29, 10)
2283
2284#define SNPS_PHY_MPLLB_SSCSTEP(phy) _MMIO_SNPS(phy, 0x168018)
2285#define SNPS_PHY_MPLLB_SSC_STEPSIZE REG_GENMASK(31, 11)
2286
2287#define SNPS_PHY_MPLLB_DIV2(phy) _MMIO_SNPS(phy, 0x16801C)
2288#define SNPS_PHY_MPLLB_HDMI_PIXEL_CLK_DIV REG_GENMASK(19, 18)
2289#define SNPS_PHY_MPLLB_HDMI_DIV REG_GENMASK(17, 15)
2290#define SNPS_PHY_MPLLB_REF_CLK_DIV REG_GENMASK(14, 12)
2291#define SNPS_PHY_MPLLB_MULTIPLIER REG_GENMASK(11, 0)
2292
2293#define SNPS_PHY_REF_CONTROL(phy) _MMIO_SNPS(phy, 0x168188)
2294#define SNPS_PHY_REF_CONTROL_REF_RANGE REG_GENMASK(31, 27)
2295
2296#define SNPS_PHY_TX_REQ(phy) _MMIO_SNPS(phy, 0x168200)
2297#define SNPS_PHY_TX_REQ_LN_DIS_PWR_STATE_PSR REG_GENMASK(31, 30)
2298
2299#define SNPS_PHY_TX_EQ(ln, phy) _MMIO_SNPS_LN(ln, phy, 0x168300)
2300#define SNPS_PHY_TX_EQ_MAIN REG_GENMASK(23, 18)
2301#define SNPS_PHY_TX_EQ_POST REG_GENMASK(15, 10)
2302#define SNPS_PHY_TX_EQ_PRE REG_GENMASK(7, 2)
2303
2304
2305
2306
2307#define _PORT_CL2CM_DW6_A 0x162358
2308#define _PORT_CL2CM_DW6_BC 0x6C358
2309#define BXT_PORT_CL2CM_DW6(phy) _BXT_PHY((phy), _PORT_CL2CM_DW6_BC)
2310#define DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28)
2311
2312#define FIA1_BASE 0x163000
2313#define FIA2_BASE 0x16E000
2314#define FIA3_BASE 0x16F000
2315#define _FIA(fia) _PICK((fia), FIA1_BASE, FIA2_BASE, FIA3_BASE)
2316#define _MMIO_FIA(fia, off) _MMIO(_FIA(fia) + (off))
2317
2318
2319#define PORT_TX_DFLEXDPMLE1(fia) _MMIO_FIA((fia), 0x008C0)
2320#define DFLEXDPMLE1_DPMLETC_MASK(idx) (0xf << (4 * (idx)))
2321#define DFLEXDPMLE1_DPMLETC_ML0(idx) (1 << (4 * (idx)))
2322#define DFLEXDPMLE1_DPMLETC_ML1_0(idx) (3 << (4 * (idx)))
2323#define DFLEXDPMLE1_DPMLETC_ML3(idx) (8 << (4 * (idx)))
2324#define DFLEXDPMLE1_DPMLETC_ML3_2(idx) (12 << (4 * (idx)))
2325#define DFLEXDPMLE1_DPMLETC_ML3_0(idx) (15 << (4 * (idx)))
2326
2327
2328#define _PORT_REF_DW3_A 0x16218C
2329#define _PORT_REF_DW3_BC 0x6C18C
2330#define GRC_DONE (1 << 22)
2331#define BXT_PORT_REF_DW3(phy) _BXT_PHY((phy), _PORT_REF_DW3_BC)
2332
2333#define _PORT_REF_DW6_A 0x162198
2334#define _PORT_REF_DW6_BC 0x6C198
2335#define GRC_CODE_SHIFT 24
2336#define GRC_CODE_MASK (0xFF << GRC_CODE_SHIFT)
2337#define GRC_CODE_FAST_SHIFT 16
2338#define GRC_CODE_FAST_MASK (0xFF << GRC_CODE_FAST_SHIFT)
2339#define GRC_CODE_SLOW_SHIFT 8
2340#define GRC_CODE_SLOW_MASK (0xFF << GRC_CODE_SLOW_SHIFT)
2341#define GRC_CODE_NOM_MASK 0xFF
2342#define BXT_PORT_REF_DW6(phy) _BXT_PHY((phy), _PORT_REF_DW6_BC)
2343
2344#define _PORT_REF_DW8_A 0x1621A0
2345#define _PORT_REF_DW8_BC 0x6C1A0
2346#define GRC_DIS (1 << 15)
2347#define GRC_RDY_OVRD (1 << 1)
2348#define BXT_PORT_REF_DW8(phy) _BXT_PHY((phy), _PORT_REF_DW8_BC)
2349
2350
2351#define _PORT_PCS_DW10_LN01_A 0x162428
2352#define _PORT_PCS_DW10_LN01_B 0x6C428
2353#define _PORT_PCS_DW10_LN01_C 0x6C828
2354#define _PORT_PCS_DW10_GRP_A 0x162C28
2355#define _PORT_PCS_DW10_GRP_B 0x6CC28
2356#define _PORT_PCS_DW10_GRP_C 0x6CE28
2357#define BXT_PORT_PCS_DW10_LN01(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2358 _PORT_PCS_DW10_LN01_B, \
2359 _PORT_PCS_DW10_LN01_C)
2360#define BXT_PORT_PCS_DW10_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2361 _PORT_PCS_DW10_GRP_B, \
2362 _PORT_PCS_DW10_GRP_C)
2363
2364#define TX2_SWING_CALC_INIT (1 << 31)
2365#define TX1_SWING_CALC_INIT (1 << 30)
2366
2367#define _PORT_PCS_DW12_LN01_A 0x162430
2368#define _PORT_PCS_DW12_LN01_B 0x6C430
2369#define _PORT_PCS_DW12_LN01_C 0x6C830
2370#define _PORT_PCS_DW12_LN23_A 0x162630
2371#define _PORT_PCS_DW12_LN23_B 0x6C630
2372#define _PORT_PCS_DW12_LN23_C 0x6CA30
2373#define _PORT_PCS_DW12_GRP_A 0x162c30
2374#define _PORT_PCS_DW12_GRP_B 0x6CC30
2375#define _PORT_PCS_DW12_GRP_C 0x6CE30
2376#define LANESTAGGER_STRAP_OVRD (1 << 6)
2377#define LANE_STAGGER_MASK 0x1F
2378#define BXT_PORT_PCS_DW12_LN01(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2379 _PORT_PCS_DW12_LN01_B, \
2380 _PORT_PCS_DW12_LN01_C)
2381#define BXT_PORT_PCS_DW12_LN23(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2382 _PORT_PCS_DW12_LN23_B, \
2383 _PORT_PCS_DW12_LN23_C)
2384#define BXT_PORT_PCS_DW12_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2385 _PORT_PCS_DW12_GRP_B, \
2386 _PORT_PCS_DW12_GRP_C)
2387
2388
2389#define _BXT_LANE_OFFSET(lane) (((lane) >> 1) * 0x200 + \
2390 ((lane) & 1) * 0x80)
2391
2392#define _PORT_TX_DW2_LN0_A 0x162508
2393#define _PORT_TX_DW2_LN0_B 0x6C508
2394#define _PORT_TX_DW2_LN0_C 0x6C908
2395#define _PORT_TX_DW2_GRP_A 0x162D08
2396#define _PORT_TX_DW2_GRP_B 0x6CD08
2397#define _PORT_TX_DW2_GRP_C 0x6CF08
2398#define BXT_PORT_TX_DW2_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2399 _PORT_TX_DW2_LN0_B, \
2400 _PORT_TX_DW2_LN0_C)
2401#define BXT_PORT_TX_DW2_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2402 _PORT_TX_DW2_GRP_B, \
2403 _PORT_TX_DW2_GRP_C)
2404#define MARGIN_000_SHIFT 16
2405#define MARGIN_000 (0xFF << MARGIN_000_SHIFT)
2406#define UNIQ_TRANS_SCALE_SHIFT 8
2407#define UNIQ_TRANS_SCALE (0xFF << UNIQ_TRANS_SCALE_SHIFT)
2408
2409#define _PORT_TX_DW3_LN0_A 0x16250C
2410#define _PORT_TX_DW3_LN0_B 0x6C50C
2411#define _PORT_TX_DW3_LN0_C 0x6C90C
2412#define _PORT_TX_DW3_GRP_A 0x162D0C
2413#define _PORT_TX_DW3_GRP_B 0x6CD0C
2414#define _PORT_TX_DW3_GRP_C 0x6CF0C
2415#define BXT_PORT_TX_DW3_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2416 _PORT_TX_DW3_LN0_B, \
2417 _PORT_TX_DW3_LN0_C)
2418#define BXT_PORT_TX_DW3_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2419 _PORT_TX_DW3_GRP_B, \
2420 _PORT_TX_DW3_GRP_C)
2421#define SCALE_DCOMP_METHOD (1 << 26)
2422#define UNIQUE_TRANGE_EN_METHOD (1 << 27)
2423
2424#define _PORT_TX_DW4_LN0_A 0x162510
2425#define _PORT_TX_DW4_LN0_B 0x6C510
2426#define _PORT_TX_DW4_LN0_C 0x6C910
2427#define _PORT_TX_DW4_GRP_A 0x162D10
2428#define _PORT_TX_DW4_GRP_B 0x6CD10
2429#define _PORT_TX_DW4_GRP_C 0x6CF10
2430#define BXT_PORT_TX_DW4_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2431 _PORT_TX_DW4_LN0_B, \
2432 _PORT_TX_DW4_LN0_C)
2433#define BXT_PORT_TX_DW4_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2434 _PORT_TX_DW4_GRP_B, \
2435 _PORT_TX_DW4_GRP_C)
2436#define DEEMPH_SHIFT 24
2437#define DE_EMPHASIS (0xFF << DEEMPH_SHIFT)
2438
2439#define _PORT_TX_DW5_LN0_A 0x162514
2440#define _PORT_TX_DW5_LN0_B 0x6C514
2441#define _PORT_TX_DW5_LN0_C 0x6C914
2442#define _PORT_TX_DW5_GRP_A 0x162D14
2443#define _PORT_TX_DW5_GRP_B 0x6CD14
2444#define _PORT_TX_DW5_GRP_C 0x6CF14
2445#define BXT_PORT_TX_DW5_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2446 _PORT_TX_DW5_LN0_B, \
2447 _PORT_TX_DW5_LN0_C)
2448#define BXT_PORT_TX_DW5_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2449 _PORT_TX_DW5_GRP_B, \
2450 _PORT_TX_DW5_GRP_C)
2451#define DCC_DELAY_RANGE_1 (1 << 9)
2452#define DCC_DELAY_RANGE_2 (1 << 8)
2453
2454#define _PORT_TX_DW14_LN0_A 0x162538
2455#define _PORT_TX_DW14_LN0_B 0x6C538
2456#define _PORT_TX_DW14_LN0_C 0x6C938
2457#define LATENCY_OPTIM_SHIFT 30
2458#define LATENCY_OPTIM (1 << LATENCY_OPTIM_SHIFT)
2459#define BXT_PORT_TX_DW14_LN(phy, ch, lane) \
2460 _MMIO(_BXT_PHY_CH(phy, ch, _PORT_TX_DW14_LN0_B, \
2461 _PORT_TX_DW14_LN0_C) + \
2462 _BXT_LANE_OFFSET(lane))
2463
2464
2465#define UAIMI_SPR1 _MMIO(0x4F074)
2466
2467#define SKL_VCCIO_MASK 0x1
2468
2469#define DISPIO_CR_TX_BMU_CR0 _MMIO(0x6C00C)
2470
2471#define BALANCE_LEG_SHIFT(port) (8 + 3 * (port))
2472#define BALANCE_LEG_MASK(port) (7 << (8 + 3 * (port)))
2473
2474#define BALANCE_LEG_DISABLE_SHIFT 23
2475#define BALANCE_LEG_DISABLE(port) (1 << (23 + (port)))
2476
2477
2478
2479
2480
2481
2482
2483
2484
2485
2486
2487#define FENCE_REG(i) _MMIO(0x2000 + (((i) & 8) << 9) + ((i) & 7) * 4)
2488#define I830_FENCE_START_MASK 0x07f80000
2489#define I830_FENCE_TILING_Y_SHIFT 12
2490#define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8)
2491#define I830_FENCE_PITCH_SHIFT 4
2492#define I830_FENCE_REG_VALID (1 << 0)
2493#define I915_FENCE_MAX_PITCH_VAL 4
2494#define I830_FENCE_MAX_PITCH_VAL 6
2495#define I830_FENCE_MAX_SIZE_VAL (1 << 8)
2496
2497#define I915_FENCE_START_MASK 0x0ff00000
2498#define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8)
2499
2500#define FENCE_REG_965_LO(i) _MMIO(0x03000 + (i) * 8)
2501#define FENCE_REG_965_HI(i) _MMIO(0x03000 + (i) * 8 + 4)
2502#define I965_FENCE_PITCH_SHIFT 2
2503#define I965_FENCE_TILING_Y_SHIFT 1
2504#define I965_FENCE_REG_VALID (1 << 0)
2505#define I965_FENCE_MAX_PITCH_VAL 0x0400
2506
2507#define FENCE_REG_GEN6_LO(i) _MMIO(0x100000 + (i) * 8)
2508#define FENCE_REG_GEN6_HI(i) _MMIO(0x100000 + (i) * 8 + 4)
2509#define GEN6_FENCE_PITCH_SHIFT 32
2510#define GEN7_FENCE_MAX_PITCH_VAL 0x0800
2511
2512
2513
2514#define TILECTL _MMIO(0x101000)
2515#define TILECTL_SWZCTL (1 << 0)
2516#define TILECTL_TLBPF (1 << 1)
2517#define TILECTL_TLB_PREFETCH_DIS (1 << 2)
2518#define TILECTL_BACKSNOOP_DIS (1 << 3)
2519
2520
2521
2522
2523#define PGTBL_CTL _MMIO(0x02020)
2524#define PGTBL_ADDRESS_LO_MASK 0xfffff000
2525#define PGTBL_ADDRESS_HI_MASK 0x000000f0
2526#define PGTBL_ER _MMIO(0x02024)
2527#define PRB0_BASE (0x2030 - 0x30)
2528#define PRB1_BASE (0x2040 - 0x30)
2529#define PRB2_BASE (0x2050 - 0x30)
2530#define SRB0_BASE (0x2100 - 0x30)
2531#define SRB1_BASE (0x2110 - 0x30)
2532#define SRB2_BASE (0x2120 - 0x30)
2533#define SRB3_BASE (0x2130 - 0x30)
2534#define RENDER_RING_BASE 0x02000
2535#define BSD_RING_BASE 0x04000
2536#define GEN6_BSD_RING_BASE 0x12000
2537#define GEN8_BSD2_RING_BASE 0x1c000
2538#define GEN11_BSD_RING_BASE 0x1c0000
2539#define GEN11_BSD2_RING_BASE 0x1c4000
2540#define GEN11_BSD3_RING_BASE 0x1d0000
2541#define GEN11_BSD4_RING_BASE 0x1d4000
2542#define XEHP_BSD5_RING_BASE 0x1e0000
2543#define XEHP_BSD6_RING_BASE 0x1e4000
2544#define XEHP_BSD7_RING_BASE 0x1f0000
2545#define XEHP_BSD8_RING_BASE 0x1f4000
2546#define VEBOX_RING_BASE 0x1a000
2547#define GEN11_VEBOX_RING_BASE 0x1c8000
2548#define GEN11_VEBOX2_RING_BASE 0x1d8000
2549#define XEHP_VEBOX3_RING_BASE 0x1e8000
2550#define XEHP_VEBOX4_RING_BASE 0x1f8000
2551#define BLT_RING_BASE 0x22000
2552#define RING_TAIL(base) _MMIO((base) + 0x30)
2553#define RING_HEAD(base) _MMIO((base) + 0x34)
2554#define RING_START(base) _MMIO((base) + 0x38)
2555#define RING_CTL(base) _MMIO((base) + 0x3c)
2556#define RING_CTL_SIZE(size) ((size) - PAGE_SIZE)
2557#define RING_SYNC_0(base) _MMIO((base) + 0x40)
2558#define RING_SYNC_1(base) _MMIO((base) + 0x44)
2559#define RING_SYNC_2(base) _MMIO((base) + 0x48)
2560#define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE))
2561#define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE))
2562#define GEN6_RVESYNC (RING_SYNC_2(RENDER_RING_BASE))
2563#define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE))
2564#define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE))
2565#define GEN6_VVESYNC (RING_SYNC_2(GEN6_BSD_RING_BASE))
2566#define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE))
2567#define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE))
2568#define GEN6_BVESYNC (RING_SYNC_2(BLT_RING_BASE))
2569#define GEN6_VEBSYNC (RING_SYNC_0(VEBOX_RING_BASE))
2570#define GEN6_VERSYNC (RING_SYNC_1(VEBOX_RING_BASE))
2571#define GEN6_VEVSYNC (RING_SYNC_2(VEBOX_RING_BASE))
2572#define GEN6_NOSYNC INVALID_MMIO_REG
2573#define RING_PSMI_CTL(base) _MMIO((base) + 0x50)
2574#define RING_MAX_IDLE(base) _MMIO((base) + 0x54)
2575#define RING_HWS_PGA(base) _MMIO((base) + 0x80)
2576#define RING_ID(base) _MMIO((base) + 0x8c)
2577#define RING_HWS_PGA_GEN6(base) _MMIO((base) + 0x2080)
2578
2579#define RING_CMD_CCTL(base) _MMIO((base) + 0xc4)
2580
2581
2582
2583
2584
2585
2586
2587#define CMD_CCTL_WRITE_OVERRIDE_MASK REG_GENMASK(13, 7)
2588#define CMD_CCTL_READ_OVERRIDE_MASK REG_GENMASK(6, 0)
2589#define CMD_CCTL_MOCS_MASK (CMD_CCTL_WRITE_OVERRIDE_MASK | \
2590 CMD_CCTL_READ_OVERRIDE_MASK)
2591#define CMD_CCTL_MOCS_OVERRIDE(write, read) \
2592 (REG_FIELD_PREP(CMD_CCTL_WRITE_OVERRIDE_MASK, (write) << 1) | \
2593 REG_FIELD_PREP(CMD_CCTL_READ_OVERRIDE_MASK, (read) << 1))
2594
2595#define BLIT_CCTL(base) _MMIO((base) + 0x204)
2596#define BLIT_CCTL_DST_MOCS_MASK REG_GENMASK(14, 8)
2597#define BLIT_CCTL_SRC_MOCS_MASK REG_GENMASK(6, 0)
2598#define BLIT_CCTL_MASK (BLIT_CCTL_DST_MOCS_MASK | \
2599 BLIT_CCTL_SRC_MOCS_MASK)
2600#define BLIT_CCTL_MOCS(dst, src) \
2601 (REG_FIELD_PREP(BLIT_CCTL_DST_MOCS_MASK, (dst) << 1) | \
2602 REG_FIELD_PREP(BLIT_CCTL_SRC_MOCS_MASK, (src) << 1))
2603
2604#define RING_RESET_CTL(base) _MMIO((base) + 0xd0)
2605#define RESET_CTL_CAT_ERROR REG_BIT(2)
2606#define RESET_CTL_READY_TO_RESET REG_BIT(1)
2607#define RESET_CTL_REQUEST_RESET REG_BIT(0)
2608
2609#define RING_SEMA_WAIT_POLL(base) _MMIO((base) + 0x24c)
2610
2611#define HSW_GTT_CACHE_EN _MMIO(0x4024)
2612#define GTT_CACHE_EN_ALL 0xF0007FFF
2613#define GEN7_WR_WATERMARK _MMIO(0x4028)
2614#define GEN7_GFX_PRIO_CTRL _MMIO(0x402C)
2615#define ARB_MODE _MMIO(0x4030)
2616#define ARB_MODE_SWIZZLE_SNB (1 << 4)
2617#define ARB_MODE_SWIZZLE_IVB (1 << 5)
2618#define GEN7_GFX_PEND_TLB0 _MMIO(0x4034)
2619#define GEN7_GFX_PEND_TLB1 _MMIO(0x4038)
2620
2621#define GEN7_LRA_LIMITS(i) _MMIO(0x403C + (i) * 4)
2622#define GEN7_LRA_LIMITS_REG_NUM 13
2623#define GEN7_MEDIA_MAX_REQ_COUNT _MMIO(0x4070)
2624#define GEN7_GFX_MAX_REQ_COUNT _MMIO(0x4074)
2625
2626#define GAMTARBMODE _MMIO(0x04a08)
2627#define ARB_MODE_BWGTLB_DISABLE (1 << 9)
2628#define ARB_MODE_SWIZZLE_BDW (1 << 1)
2629#define RENDER_HWS_PGA_GEN7 _MMIO(0x04080)
2630
2631#define _RING_FAULT_REG_RCS 0x4094
2632#define _RING_FAULT_REG_VCS 0x4194
2633#define _RING_FAULT_REG_BCS 0x4294
2634#define _RING_FAULT_REG_VECS 0x4394
2635#define RING_FAULT_REG(engine) _MMIO(_PICK((engine)->class, \
2636 _RING_FAULT_REG_RCS, \
2637 _RING_FAULT_REG_VCS, \
2638 _RING_FAULT_REG_VECS, \
2639 _RING_FAULT_REG_BCS))
2640#define GEN8_RING_FAULT_REG _MMIO(0x4094)
2641#define GEN12_RING_FAULT_REG _MMIO(0xcec4)
2642#define GEN8_RING_FAULT_ENGINE_ID(x) (((x) >> 12) & 0x7)
2643#define RING_FAULT_GTTSEL_MASK (1 << 11)
2644#define RING_FAULT_SRCID(x) (((x) >> 3) & 0xff)
2645#define RING_FAULT_FAULT_TYPE(x) (((x) >> 1) & 0x3)
2646#define RING_FAULT_VALID (1 << 0)
2647#define DONE_REG _MMIO(0x40b0)
2648#define GEN12_GAM_DONE _MMIO(0xcf68)
2649#define GEN8_PRIVATE_PAT_LO _MMIO(0x40e0)
2650#define GEN8_PRIVATE_PAT_HI _MMIO(0x40e0 + 4)
2651#define GEN10_PAT_INDEX(index) _MMIO(0x40e0 + (index) * 4)
2652#define GEN12_PAT_INDEX(index) _MMIO(0x4800 + (index) * 4)
2653#define BSD_HWS_PGA_GEN7 _MMIO(0x04180)
2654#define GEN12_GFX_CCS_AUX_NV _MMIO(0x4208)
2655#define GEN12_VD0_AUX_NV _MMIO(0x4218)
2656#define GEN12_VD1_AUX_NV _MMIO(0x4228)
2657#define GEN12_VD2_AUX_NV _MMIO(0x4298)
2658#define GEN12_VD3_AUX_NV _MMIO(0x42A8)
2659#define GEN12_VE0_AUX_NV _MMIO(0x4238)
2660#define GEN12_VE1_AUX_NV _MMIO(0x42B8)
2661#define AUX_INV REG_BIT(0)
2662#define BLT_HWS_PGA_GEN7 _MMIO(0x04280)
2663#define VEBOX_HWS_PGA_GEN7 _MMIO(0x04380)
2664#define RING_ACTHD(base) _MMIO((base) + 0x74)
2665#define RING_ACTHD_UDW(base) _MMIO((base) + 0x5c)
2666#define RING_NOPID(base) _MMIO((base) + 0x94)
2667#define RING_IMR(base) _MMIO((base) + 0xa8)
2668#define RING_HWSTAM(base) _MMIO((base) + 0x98)
2669#define RING_TIMESTAMP(base) _MMIO((base) + 0x358)
2670#define RING_TIMESTAMP_UDW(base) _MMIO((base) + 0x358 + 4)
2671#define TAIL_ADDR 0x001FFFF8
2672#define HEAD_WRAP_COUNT 0xFFE00000
2673#define HEAD_WRAP_ONE 0x00200000
2674#define HEAD_ADDR 0x001FFFFC
2675#define RING_NR_PAGES 0x001FF000
2676#define RING_REPORT_MASK 0x00000006
2677#define RING_REPORT_64K 0x00000002
2678#define RING_REPORT_128K 0x00000004
2679#define RING_NO_REPORT 0x00000000
2680#define RING_VALID_MASK 0x00000001
2681#define RING_VALID 0x00000001
2682#define RING_INVALID 0x00000000
2683#define RING_WAIT_I8XX (1 << 0)
2684#define RING_WAIT (1 << 11)
2685#define RING_WAIT_SEMAPHORE (1 << 10)
2686
2687#define MISC_STATUS0 _MMIO(0xA500)
2688#define MISC_STATUS1 _MMIO(0xA504)
2689
2690
2691#define GEN8_RING_CS_GPR(base, n) _MMIO((base) + 0x600 + (n) * 8)
2692#define GEN8_RING_CS_GPR_UDW(base, n) _MMIO((base) + 0x600 + (n) * 8 + 4)
2693
2694#define RING_FORCE_TO_NONPRIV(base, i) _MMIO(((base) + 0x4D0) + (i) * 4)
2695#define RING_FORCE_TO_NONPRIV_ADDRESS_MASK REG_GENMASK(25, 2)
2696#define RING_FORCE_TO_NONPRIV_ACCESS_RW (0 << 28)
2697#define RING_FORCE_TO_NONPRIV_ACCESS_RD (1 << 28)
2698#define RING_FORCE_TO_NONPRIV_ACCESS_WR (2 << 28)
2699#define RING_FORCE_TO_NONPRIV_ACCESS_INVALID (3 << 28)
2700#define RING_FORCE_TO_NONPRIV_ACCESS_MASK (3 << 28)
2701#define RING_FORCE_TO_NONPRIV_RANGE_1 (0 << 0)
2702#define RING_FORCE_TO_NONPRIV_RANGE_4 (1 << 0)
2703#define RING_FORCE_TO_NONPRIV_RANGE_16 (2 << 0)
2704#define RING_FORCE_TO_NONPRIV_RANGE_64 (3 << 0)
2705#define RING_FORCE_TO_NONPRIV_RANGE_MASK (3 << 0)
2706#define RING_FORCE_TO_NONPRIV_MASK_VALID \
2707 (RING_FORCE_TO_NONPRIV_RANGE_MASK \
2708 | RING_FORCE_TO_NONPRIV_ACCESS_MASK)
2709#define RING_MAX_NONPRIV_SLOTS 12
2710
2711#define GEN7_TLB_RD_ADDR _MMIO(0x4700)
2712
2713#define GEN9_GAMT_ECO_REG_RW_IA _MMIO(0x4ab0)
2714#define GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS (1 << 18)
2715
2716#define GEN8_GAMW_ECO_DEV_RW_IA _MMIO(0x4080)
2717#define GAMW_ECO_ENABLE_64K_IPS_FIELD 0xF
2718#define GAMW_ECO_DEV_CTX_RELOAD_DISABLE (1 << 7)
2719
2720#define GAMT_CHKN_BIT_REG _MMIO(0x4ab8)
2721#define GAMT_CHKN_DISABLE_L3_COH_PIPE (1 << 31)
2722#define GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING (1 << 28)
2723#define GAMT_CHKN_DISABLE_I2M_CYCLE_ON_WR_PORT (1 << 24)
2724
2725#define GEN8_RTCR _MMIO(0x4260)
2726#define GEN8_M1TCR _MMIO(0x4264)
2727#define GEN8_M2TCR _MMIO(0x4268)
2728#define GEN8_BTCR _MMIO(0x426c)
2729#define GEN8_VTCR _MMIO(0x4270)
2730
2731#if 0
2732#define PRB0_TAIL _MMIO(0x2030)
2733#define PRB0_HEAD _MMIO(0x2034)
2734#define PRB0_START _MMIO(0x2038)
2735#define PRB0_CTL _MMIO(0x203c)
2736#define PRB1_TAIL _MMIO(0x2040)
2737#define PRB1_HEAD _MMIO(0x2044)
2738#define PRB1_START _MMIO(0x2048)
2739#define PRB1_CTL _MMIO(0x204c)
2740#endif
2741#define IPEIR_I965 _MMIO(0x2064)
2742#define IPEHR_I965 _MMIO(0x2068)
2743#define GEN7_SC_INSTDONE _MMIO(0x7100)
2744#define GEN12_SC_INSTDONE_EXTRA _MMIO(0x7104)
2745#define GEN12_SC_INSTDONE_EXTRA2 _MMIO(0x7108)
2746#define GEN7_SAMPLER_INSTDONE _MMIO(0xe160)
2747#define GEN7_ROW_INSTDONE _MMIO(0xe164)
2748#define XEHPG_INSTDONE_GEOM_SVG _MMIO(0x666c)
2749#define MCFG_MCR_SELECTOR _MMIO(0xfd0)
2750#define SF_MCR_SELECTOR _MMIO(0xfd8)
2751#define GEN8_MCR_SELECTOR _MMIO(0xfdc)
2752#define GEN8_MCR_SLICE(slice) (((slice) & 3) << 26)
2753#define GEN8_MCR_SLICE_MASK GEN8_MCR_SLICE(3)
2754#define GEN8_MCR_SUBSLICE(subslice) (((subslice) & 3) << 24)
2755#define GEN8_MCR_SUBSLICE_MASK GEN8_MCR_SUBSLICE(3)
2756#define GEN11_MCR_SLICE(slice) (((slice) & 0xf) << 27)
2757#define GEN11_MCR_SLICE_MASK GEN11_MCR_SLICE(0xf)
2758#define GEN11_MCR_SUBSLICE(subslice) (((subslice) & 0x7) << 24)
2759#define GEN11_MCR_SUBSLICE_MASK GEN11_MCR_SUBSLICE(0x7)
2760#define RING_IPEIR(base) _MMIO((base) + 0x64)
2761#define RING_IPEHR(base) _MMIO((base) + 0x68)
2762#define RING_EIR(base) _MMIO((base) + 0xb0)
2763#define RING_EMR(base) _MMIO((base) + 0xb4)
2764#define RING_ESR(base) _MMIO((base) + 0xb8)
2765
2766
2767
2768
2769
2770#define RING_INSTDONE(base) _MMIO((base) + 0x6c)
2771#define RING_INSTPS(base) _MMIO((base) + 0x70)
2772#define RING_DMA_FADD(base) _MMIO((base) + 0x78)
2773#define RING_DMA_FADD_UDW(base) _MMIO((base) + 0x60)
2774#define RING_INSTPM(base) _MMIO((base) + 0xc0)
2775#define RING_MI_MODE(base) _MMIO((base) + 0x9c)
2776#define RING_CMD_BUF_CCTL(base) _MMIO((base) + 0x84)
2777#define INSTPS _MMIO(0x2070)
2778#define GEN4_INSTDONE1 _MMIO(0x207c)
2779#define ACTHD_I965 _MMIO(0x2074)
2780#define HWS_PGA _MMIO(0x2080)
2781#define HWS_ADDRESS_MASK 0xfffff000
2782#define HWS_START_ADDRESS_SHIFT 4
2783#define PWRCTXA _MMIO(0x2088)
2784#define PWRCTX_EN (1 << 0)
2785#define IPEIR(base) _MMIO((base) + 0x88)
2786#define IPEHR(base) _MMIO((base) + 0x8c)
2787#define GEN2_INSTDONE _MMIO(0x2090)
2788#define NOPID _MMIO(0x2094)
2789#define HWSTAM _MMIO(0x2098)
2790#define DMA_FADD_I8XX(base) _MMIO((base) + 0xd0)
2791#define RING_BBSTATE(base) _MMIO((base) + 0x110)
2792#define RING_BB_PPGTT (1 << 5)
2793#define RING_SBBADDR(base) _MMIO((base) + 0x114)
2794#define RING_SBBSTATE(base) _MMIO((base) + 0x118)
2795#define RING_SBBADDR_UDW(base) _MMIO((base) + 0x11c)
2796#define RING_BBADDR(base) _MMIO((base) + 0x140)
2797#define RING_BBADDR_UDW(base) _MMIO((base) + 0x168)
2798#define RING_BB_PER_CTX_PTR(base) _MMIO((base) + 0x1c0)
2799#define RING_INDIRECT_CTX(base) _MMIO((base) + 0x1c4)
2800#define RING_INDIRECT_CTX_OFFSET(base) _MMIO((base) + 0x1c8)
2801#define RING_CTX_TIMESTAMP(base) _MMIO((base) + 0x3a8)
2802
2803#define VDBOX_CGCTL3F10(base) _MMIO((base) + 0x3f10)
2804#define IECPUNIT_CLKGATE_DIS REG_BIT(22)
2805
2806#define VDBOX_CGCTL3F18(base) _MMIO((base) + 0x3f18)
2807#define ALNUNIT_CLKGATE_DIS REG_BIT(13)
2808
2809#define ERROR_GEN6 _MMIO(0x40a0)
2810#define GEN7_ERR_INT _MMIO(0x44040)
2811#define ERR_INT_POISON (1 << 31)
2812#define ERR_INT_MMIO_UNCLAIMED (1 << 13)
2813#define ERR_INT_PIPE_CRC_DONE_C (1 << 8)
2814#define ERR_INT_FIFO_UNDERRUN_C (1 << 6)
2815#define ERR_INT_PIPE_CRC_DONE_B (1 << 5)
2816#define ERR_INT_FIFO_UNDERRUN_B (1 << 3)
2817#define ERR_INT_PIPE_CRC_DONE_A (1 << 2)
2818#define ERR_INT_PIPE_CRC_DONE(pipe) (1 << (2 + (pipe) * 3))
2819#define ERR_INT_FIFO_UNDERRUN_A (1 << 0)
2820#define ERR_INT_FIFO_UNDERRUN(pipe) (1 << ((pipe) * 3))
2821
2822#define GEN8_FAULT_TLB_DATA0 _MMIO(0x4b10)
2823#define GEN8_FAULT_TLB_DATA1 _MMIO(0x4b14)
2824#define GEN12_FAULT_TLB_DATA0 _MMIO(0xceb8)
2825#define GEN12_FAULT_TLB_DATA1 _MMIO(0xcebc)
2826#define FAULT_VA_HIGH_BITS (0xf << 0)
2827#define FAULT_GTT_SEL (1 << 4)
2828
2829#define GEN12_GFX_TLB_INV_CR _MMIO(0xced8)
2830#define GEN12_VD_TLB_INV_CR _MMIO(0xcedc)
2831#define GEN12_VE_TLB_INV_CR _MMIO(0xcee0)
2832#define GEN12_BLT_TLB_INV_CR _MMIO(0xcee4)
2833
2834#define GEN12_AUX_ERR_DBG _MMIO(0x43f4)
2835
2836#define FPGA_DBG _MMIO(0x42300)
2837#define FPGA_DBG_RM_NOCLAIM REG_BIT(31)
2838
2839#define CLAIM_ER _MMIO(VLV_DISPLAY_BASE + 0x2028)
2840#define CLAIM_ER_CLR REG_BIT(31)
2841#define CLAIM_ER_OVERFLOW REG_BIT(16)
2842#define CLAIM_ER_CTR_MASK REG_GENMASK(15, 0)
2843
2844#define DERRMR _MMIO(0x44050)
2845
2846#define DERRMR_PIPEA_SCANLINE (1 << 0)
2847#define DERRMR_PIPEA_PRI_FLIP_DONE (1 << 1)
2848#define DERRMR_PIPEA_SPR_FLIP_DONE (1 << 2)
2849#define DERRMR_PIPEA_VBLANK (1 << 3)
2850#define DERRMR_PIPEA_HBLANK (1 << 5)
2851#define DERRMR_PIPEB_SCANLINE (1 << 8)
2852#define DERRMR_PIPEB_PRI_FLIP_DONE (1 << 9)
2853#define DERRMR_PIPEB_SPR_FLIP_DONE (1 << 10)
2854#define DERRMR_PIPEB_VBLANK (1 << 11)
2855#define DERRMR_PIPEB_HBLANK (1 << 13)
2856
2857#define DERRMR_PIPEC_SCANLINE (1 << 14)
2858#define DERRMR_PIPEC_PRI_FLIP_DONE (1 << 15)
2859#define DERRMR_PIPEC_SPR_FLIP_DONE (1 << 20)
2860#define DERRMR_PIPEC_VBLANK (1 << 21)
2861#define DERRMR_PIPEC_HBLANK (1 << 22)
2862
2863
2864
2865
2866
2867
2868#define _3D_CHICKEN _MMIO(0x2084)
2869#define _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB (1 << 10)
2870#define _3D_CHICKEN2 _MMIO(0x208c)
2871
2872#define FF_SLICE_CHICKEN _MMIO(0x2088)
2873#define FF_SLICE_CHICKEN_CL_PROVOKING_VERTEX_FIX (1 << 1)
2874
2875
2876
2877
2878
2879# define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14)
2880#define _3D_CHICKEN3 _MMIO(0x2090)
2881#define _3D_CHICKEN_SF_PROVOKING_VERTEX_FIX (1 << 12)
2882#define _3D_CHICKEN_SF_DISABLE_OBJEND_CULL (1 << 10)
2883#define _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE (1 << 5)
2884#define _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL (1 << 5)
2885#define _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x) ((x) << 1)
2886#define _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH (1 << 1)
2887
2888#define MI_MODE _MMIO(0x209c)
2889# define VS_TIMER_DISPATCH (1 << 6)
2890# define MI_FLUSH_ENABLE (1 << 12)
2891# define TGL_NESTED_BB_EN (1 << 12)
2892# define ASYNC_FLIP_PERF_DISABLE (1 << 14)
2893# define MODE_IDLE (1 << 9)
2894# define STOP_RING (1 << 8)
2895
2896#define GEN6_GT_MODE _MMIO(0x20d0)
2897#define GEN7_GT_MODE _MMIO(0x7008)
2898#define GEN6_WIZ_HASHING(hi, lo) (((hi) << 9) | ((lo) << 7))
2899#define GEN6_WIZ_HASHING_8x8 GEN6_WIZ_HASHING(0, 0)
2900#define GEN6_WIZ_HASHING_8x4 GEN6_WIZ_HASHING(0, 1)
2901#define GEN6_WIZ_HASHING_16x4 GEN6_WIZ_HASHING(1, 0)
2902#define GEN6_WIZ_HASHING_MASK GEN6_WIZ_HASHING(1, 1)
2903#define GEN6_TD_FOUR_ROW_DISPATCH_DISABLE (1 << 5)
2904#define GEN9_IZ_HASHING_MASK(slice) (0x3 << ((slice) * 2))
2905#define GEN9_IZ_HASHING(slice, val) ((val) << ((slice) * 2))
2906
2907
2908#define GEN9_CSFE_CHICKEN1_RCS _MMIO(0x20D4)
2909#define GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE (1 << 2)
2910#define GEN11_ENABLE_32_PLANE_MODE (1 << 7)
2911
2912#define SCCGCTL94DC _MMIO(0x94dc)
2913#define CG3DDISURB REG_BIT(14)
2914
2915#define MLTICTXCTL _MMIO(0xb170)
2916#define TDONRENDER REG_BIT(2)
2917
2918#define L3SQCREG1_CCS0 _MMIO(0xb200)
2919#define FLUSHALLNONCOH REG_BIT(5)
2920
2921
2922#define GEN8_STATE_ACK _MMIO(0x20F0)
2923#define GEN9_STATE_ACK_SLICE1 _MMIO(0x20F8)
2924#define GEN9_STATE_ACK_SLICE2 _MMIO(0x2100)
2925#define GEN9_STATE_ACK_TDL0 (1 << 12)
2926#define GEN9_STATE_ACK_TDL1 (1 << 13)
2927#define GEN9_STATE_ACK_TDL2 (1 << 14)
2928#define GEN9_STATE_ACK_TDL3 (1 << 15)
2929#define GEN9_SUBSLICE_TDL_ACK_BITS \
2930 (GEN9_STATE_ACK_TDL3 | GEN9_STATE_ACK_TDL2 | \
2931 GEN9_STATE_ACK_TDL1 | GEN9_STATE_ACK_TDL0)
2932
2933#define GFX_MODE _MMIO(0x2520)
2934#define GFX_MODE_GEN7 _MMIO(0x229c)
2935#define RING_MODE_GEN7(base) _MMIO((base) + 0x29c)
2936#define GFX_RUN_LIST_ENABLE (1 << 15)
2937#define GFX_INTERRUPT_STEERING (1 << 14)
2938#define GFX_TLB_INVALIDATE_EXPLICIT (1 << 13)
2939#define GFX_SURFACE_FAULT_ENABLE (1 << 12)
2940#define GFX_REPLAY_MODE (1 << 11)
2941#define GFX_PSMI_GRANULARITY (1 << 10)
2942#define GFX_PPGTT_ENABLE (1 << 9)
2943#define GEN8_GFX_PPGTT_48B (1 << 7)
2944
2945#define GFX_FORWARD_VBLANK_MASK (3 << 5)
2946#define GFX_FORWARD_VBLANK_NEVER (0 << 5)
2947#define GFX_FORWARD_VBLANK_ALWAYS (1 << 5)
2948#define GFX_FORWARD_VBLANK_COND (2 << 5)
2949
2950#define GEN11_GFX_DISABLE_LEGACY_MODE (1 << 3)
2951
2952#define VLV_GU_CTL0 _MMIO(VLV_DISPLAY_BASE + 0x2030)
2953#define VLV_GU_CTL1 _MMIO(VLV_DISPLAY_BASE + 0x2034)
2954#define SCPD0 _MMIO(0x209c)
2955#define SCPD_FBC_IGNORE_3D (1 << 6)
2956#define CSTATE_RENDER_CLOCK_GATE_DISABLE (1 << 5)
2957#define GEN2_IER _MMIO(0x20a0)
2958#define GEN2_IIR _MMIO(0x20a4)
2959#define GEN2_IMR _MMIO(0x20a8)
2960#define GEN2_ISR _MMIO(0x20ac)
2961#define VLV_GUNIT_CLOCK_GATE _MMIO(VLV_DISPLAY_BASE + 0x2060)
2962#define GINT_DIS (1 << 22)
2963#define GCFG_DIS (1 << 8)
2964#define VLV_GUNIT_CLOCK_GATE2 _MMIO(VLV_DISPLAY_BASE + 0x2064)
2965#define VLV_IIR_RW _MMIO(VLV_DISPLAY_BASE + 0x2084)
2966#define VLV_IER _MMIO(VLV_DISPLAY_BASE + 0x20a0)
2967#define VLV_IIR _MMIO(VLV_DISPLAY_BASE + 0x20a4)
2968#define VLV_IMR _MMIO(VLV_DISPLAY_BASE + 0x20a8)
2969#define VLV_ISR _MMIO(VLV_DISPLAY_BASE + 0x20ac)
2970#define VLV_PCBR _MMIO(VLV_DISPLAY_BASE + 0x2120)
2971#define VLV_PCBR_ADDR_SHIFT 12
2972
2973#define DISPLAY_PLANE_FLIP_PENDING(plane) (1 << (11 - (plane)))
2974#define EIR _MMIO(0x20b0)
2975#define EMR _MMIO(0x20b4)
2976#define ESR _MMIO(0x20b8)
2977#define GM45_ERROR_PAGE_TABLE (1 << 5)
2978#define GM45_ERROR_MEM_PRIV (1 << 4)
2979#define I915_ERROR_PAGE_TABLE (1 << 4)
2980#define GM45_ERROR_CP_PRIV (1 << 3)
2981#define I915_ERROR_MEMORY_REFRESH (1 << 1)
2982#define I915_ERROR_INSTRUCTION (1 << 0)
2983#define INSTPM _MMIO(0x20c0)
2984#define INSTPM_SELF_EN (1 << 12)
2985#define INSTPM_AGPBUSY_INT_EN (1 << 11)
2986
2987
2988#define INSTPM_FORCE_ORDERING (1 << 7)
2989#define INSTPM_TLB_INVALIDATE (1 << 9)
2990#define INSTPM_SYNC_FLUSH (1 << 5)
2991#define ACTHD(base) _MMIO((base) + 0xc8)
2992#define MEM_MODE _MMIO(0x20cc)
2993#define MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1 << 3)
2994#define MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1 << 2)
2995#define MEM_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2)
2996#define FW_BLC _MMIO(0x20d8)
2997#define FW_BLC2 _MMIO(0x20dc)
2998#define FW_BLC_SELF _MMIO(0x20e0)
2999#define FW_BLC_SELF_EN_MASK (1 << 31)
3000#define FW_BLC_SELF_FIFO_MASK (1 << 16)
3001#define FW_BLC_SELF_EN (1 << 15)
3002#define MM_BURST_LENGTH 0x00700000
3003#define MM_FIFO_WATERMARK 0x0001F000
3004#define LM_BURST_LENGTH 0x00000700
3005#define LM_FIFO_WATERMARK 0x0000001F
3006#define MI_ARB_STATE _MMIO(0x20e4)
3007
3008#define _MBUS_ABOX0_CTL 0x45038
3009#define _MBUS_ABOX1_CTL 0x45048
3010#define _MBUS_ABOX2_CTL 0x4504C
3011#define MBUS_ABOX_CTL(x) _MMIO(_PICK(x, _MBUS_ABOX0_CTL, \
3012 _MBUS_ABOX1_CTL, \
3013 _MBUS_ABOX2_CTL))
3014#define MBUS_ABOX_BW_CREDIT_MASK (3 << 20)
3015#define MBUS_ABOX_BW_CREDIT(x) ((x) << 20)
3016#define MBUS_ABOX_B_CREDIT_MASK (0xF << 16)
3017#define MBUS_ABOX_B_CREDIT(x) ((x) << 16)
3018#define MBUS_ABOX_BT_CREDIT_POOL2_MASK (0x1F << 8)
3019#define MBUS_ABOX_BT_CREDIT_POOL2(x) ((x) << 8)
3020#define MBUS_ABOX_BT_CREDIT_POOL1_MASK (0x1F << 0)
3021#define MBUS_ABOX_BT_CREDIT_POOL1(x) ((x) << 0)
3022
3023#define _PIPEA_MBUS_DBOX_CTL 0x7003C
3024#define _PIPEB_MBUS_DBOX_CTL 0x7103C
3025#define PIPE_MBUS_DBOX_CTL(pipe) _MMIO_PIPE(pipe, _PIPEA_MBUS_DBOX_CTL, \
3026 _PIPEB_MBUS_DBOX_CTL)
3027#define MBUS_DBOX_BW_CREDIT_MASK (3 << 14)
3028#define MBUS_DBOX_BW_CREDIT(x) ((x) << 14)
3029#define MBUS_DBOX_B_CREDIT_MASK (0x1F << 8)
3030#define MBUS_DBOX_B_CREDIT(x) ((x) << 8)
3031#define MBUS_DBOX_A_CREDIT_MASK (0xF << 0)
3032#define MBUS_DBOX_A_CREDIT(x) ((x) << 0)
3033
3034#define MBUS_UBOX_CTL _MMIO(0x4503C)
3035#define MBUS_BBOX_CTL_S1 _MMIO(0x45040)
3036#define MBUS_BBOX_CTL_S2 _MMIO(0x45044)
3037
3038#define MBUS_CTL _MMIO(0x4438C)
3039#define MBUS_JOIN REG_BIT(31)
3040#define MBUS_HASHING_MODE_MASK REG_BIT(30)
3041#define MBUS_HASHING_MODE_2x2 REG_FIELD_PREP(MBUS_HASHING_MODE_MASK, 0)
3042#define MBUS_HASHING_MODE_1x4 REG_FIELD_PREP(MBUS_HASHING_MODE_MASK, 1)
3043#define MBUS_JOIN_PIPE_SELECT_MASK REG_GENMASK(28, 26)
3044#define MBUS_JOIN_PIPE_SELECT(pipe) REG_FIELD_PREP(MBUS_JOIN_PIPE_SELECT_MASK, pipe)
3045#define MBUS_JOIN_PIPE_SELECT_NONE MBUS_JOIN_PIPE_SELECT(7)
3046
3047#define HDPORT_STATE _MMIO(0x45050)
3048#define HDPORT_DPLL_USED_MASK REG_GENMASK(15, 12)
3049#define HDPORT_DDI_USED(phy) REG_BIT(2 * (phy) + 1)
3050#define HDPORT_ENABLED REG_BIT(0)
3051
3052
3053
3054
3055#define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15)
3056
3057
3058
3059
3060
3061#define MI_ARB_ISOCH_WAIT_GTT (1 << 14)
3062
3063
3064
3065
3066#define MI_ARB_BLOCK_GRANT_MASK (3 << 12)
3067#define MI_ARB_BLOCK_GRANT_8 (0 << 12)
3068#define MI_ARB_BLOCK_GRANT_4 (1 << 12)
3069#define MI_ARB_BLOCK_GRANT_2 (2 << 12)
3070#define MI_ARB_BLOCK_GRANT_0 (3 << 12)
3071
3072
3073
3074
3075
3076#define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11)
3077
3078
3079
3080
3081#define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10)
3082
3083
3084
3085#define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9)
3086
3087
3088
3089
3090#define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8)
3091
3092
3093#define MI_ARB_TIME_SLICE_MASK (7 << 5)
3094#define MI_ARB_TIME_SLICE_1 (0 << 5)
3095#define MI_ARB_TIME_SLICE_2 (1 << 5)
3096#define MI_ARB_TIME_SLICE_4 (2 << 5)
3097#define MI_ARB_TIME_SLICE_6 (3 << 5)
3098#define MI_ARB_TIME_SLICE_8 (4 << 5)
3099#define MI_ARB_TIME_SLICE_10 (5 << 5)
3100#define MI_ARB_TIME_SLICE_14 (6 << 5)
3101#define MI_ARB_TIME_SLICE_16 (7 << 5)
3102
3103
3104#define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4)
3105#define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4)
3106
3107
3108#define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2)
3109
3110
3111#define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0)
3112#define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0)
3113
3114#define MI_STATE _MMIO(0x20e4)
3115#define MI_AGPBUSY_INT_EN (1 << 1)
3116#define MI_AGPBUSY_830_MODE (1 << 0)
3117
3118#define CACHE_MODE_0 _MMIO(0x2120)
3119#define CM0_PIPELINED_RENDER_FLUSH_DISABLE (1 << 8)
3120#define CM0_IZ_OPT_DISABLE (1 << 6)
3121#define CM0_ZR_OPT_DISABLE (1 << 5)
3122#define CM0_STC_EVICT_DISABLE_LRA_SNB (1 << 5)
3123#define CM0_DEPTH_EVICT_DISABLE (1 << 4)
3124#define CM0_COLOR_EVICT_DISABLE (1 << 3)
3125#define CM0_DEPTH_WRITE_DISABLE (1 << 1)
3126#define CM0_RC_OP_FLUSH_DISABLE (1 << 0)
3127#define GFX_FLSH_CNTL _MMIO(0x2170)
3128#define GFX_FLSH_CNTL_GEN6 _MMIO(0x101008)
3129#define GFX_FLSH_CNTL_EN (1 << 0)
3130#define ECOSKPD _MMIO(0x21d0)
3131#define ECO_CONSTANT_BUFFER_SR_DISABLE REG_BIT(4)
3132#define ECO_GATING_CX_ONLY (1 << 3)
3133#define ECO_FLIP_DONE (1 << 0)
3134
3135#define CACHE_MODE_0_GEN7 _MMIO(0x7000)
3136#define RC_OP_FLUSH_ENABLE (1 << 0)
3137#define HIZ_RAW_STALL_OPT_DISABLE (1 << 2)
3138#define CACHE_MODE_1 _MMIO(0x7004)
3139#define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1 << 6)
3140#define GEN8_4x4_STC_OPTIMIZATION_DISABLE (1 << 6)
3141#define GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE (1 << 1)
3142
3143#define GEN6_BLITTER_ECOSKPD _MMIO(0x221d0)
3144#define GEN6_BLITTER_LOCK_SHIFT 16
3145#define GEN6_BLITTER_FBC_NOTIFY (1 << 3)
3146
3147#define GEN6_RC_SLEEP_PSMI_CONTROL _MMIO(0x2050)
3148#define GEN6_PSMI_SLEEP_MSG_DISABLE (1 << 0)
3149#define GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE REG_BIT(7)
3150#define GEN8_RC_SEMA_IDLE_MSG_DISABLE (1 << 12)
3151#define GEN8_FF_DOP_CLOCK_GATE_DISABLE (1 << 10)
3152
3153#define GEN6_RCS_PWR_FSM _MMIO(0x22ac)
3154#define GEN9_RCS_FE_FSM2 _MMIO(0x22a4)
3155
3156#define GEN10_CACHE_MODE_SS _MMIO(0xe420)
3157#define ENABLE_PREFETCH_INTO_IC REG_BIT(3)
3158#define FLOAT_BLEND_OPTIMIZATION_ENABLE REG_BIT(4)
3159
3160
3161#define HSW_PAVP_FUSE1 _MMIO(0x911C)
3162#define XEHP_SFC_ENABLE_MASK REG_GENMASK(27, 24)
3163#define HSW_F1_EU_DIS_MASK REG_GENMASK(17, 16)
3164#define HSW_F1_EU_DIS_10EUS 0
3165#define HSW_F1_EU_DIS_8EUS 1
3166#define HSW_F1_EU_DIS_6EUS 2
3167
3168#define CHV_FUSE_GT _MMIO(VLV_DISPLAY_BASE + 0x2168)
3169#define CHV_FGT_DISABLE_SS0 (1 << 10)
3170#define CHV_FGT_DISABLE_SS1 (1 << 11)
3171#define CHV_FGT_EU_DIS_SS0_R0_SHIFT 16
3172#define CHV_FGT_EU_DIS_SS0_R0_MASK (0xf << CHV_FGT_EU_DIS_SS0_R0_SHIFT)
3173#define CHV_FGT_EU_DIS_SS0_R1_SHIFT 20
3174#define CHV_FGT_EU_DIS_SS0_R1_MASK (0xf << CHV_FGT_EU_DIS_SS0_R1_SHIFT)
3175#define CHV_FGT_EU_DIS_SS1_R0_SHIFT 24
3176#define CHV_FGT_EU_DIS_SS1_R0_MASK (0xf << CHV_FGT_EU_DIS_SS1_R0_SHIFT)
3177#define CHV_FGT_EU_DIS_SS1_R1_SHIFT 28
3178#define CHV_FGT_EU_DIS_SS1_R1_MASK (0xf << CHV_FGT_EU_DIS_SS1_R1_SHIFT)
3179
3180#define GEN8_FUSE2 _MMIO(0x9120)
3181#define GEN8_F2_SS_DIS_SHIFT 21
3182#define GEN8_F2_SS_DIS_MASK (0x7 << GEN8_F2_SS_DIS_SHIFT)
3183#define GEN8_F2_S_ENA_SHIFT 25
3184#define GEN8_F2_S_ENA_MASK (0x7 << GEN8_F2_S_ENA_SHIFT)
3185
3186#define GEN9_F2_SS_DIS_SHIFT 20
3187#define GEN9_F2_SS_DIS_MASK (0xf << GEN9_F2_SS_DIS_SHIFT)
3188
3189#define GEN10_F2_S_ENA_SHIFT 22
3190#define GEN10_F2_S_ENA_MASK (0x3f << GEN10_F2_S_ENA_SHIFT)
3191#define GEN10_F2_SS_DIS_SHIFT 18
3192#define GEN10_F2_SS_DIS_MASK (0xf << GEN10_F2_SS_DIS_SHIFT)
3193
3194#define GEN10_MIRROR_FUSE3 _MMIO(0x9118)
3195#define GEN10_L3BANK_PAIR_COUNT 4
3196#define GEN10_L3BANK_MASK 0x0F
3197
3198#define GEN12_MAX_MSLICES 4
3199#define GEN12_MEML3_EN_MASK 0x0F
3200
3201#define GEN8_EU_DISABLE0 _MMIO(0x9134)
3202#define GEN8_EU_DIS0_S0_MASK 0xffffff
3203#define GEN8_EU_DIS0_S1_SHIFT 24
3204#define GEN8_EU_DIS0_S1_MASK (0xff << GEN8_EU_DIS0_S1_SHIFT)
3205
3206#define GEN8_EU_DISABLE1 _MMIO(0x9138)
3207#define GEN8_EU_DIS1_S1_MASK 0xffff
3208#define GEN8_EU_DIS1_S2_SHIFT 16
3209#define GEN8_EU_DIS1_S2_MASK (0xffff << GEN8_EU_DIS1_S2_SHIFT)
3210
3211#define GEN8_EU_DISABLE2 _MMIO(0x913c)
3212#define GEN8_EU_DIS2_S2_MASK 0xff
3213
3214#define GEN9_EU_DISABLE(slice) _MMIO(0x9134 + (slice) * 0x4)
3215
3216#define GEN10_EU_DISABLE3 _MMIO(0x9140)
3217#define GEN10_EU_DIS_SS_MASK 0xff
3218
3219#define GEN11_GT_VEBOX_VDBOX_DISABLE _MMIO(0x9140)
3220#define GEN11_GT_VDBOX_DISABLE_MASK 0xff
3221#define GEN11_GT_VEBOX_DISABLE_SHIFT 16
3222#define GEN11_GT_VEBOX_DISABLE_MASK (0x0f << GEN11_GT_VEBOX_DISABLE_SHIFT)
3223
3224#define GEN11_EU_DISABLE _MMIO(0x9134)
3225#define GEN11_EU_DIS_MASK 0xFF
3226
3227#define GEN11_GT_SLICE_ENABLE _MMIO(0x9138)
3228#define GEN11_GT_S_ENA_MASK 0xFF
3229
3230#define GEN11_GT_SUBSLICE_DISABLE _MMIO(0x913C)
3231
3232#define GEN12_GT_GEOMETRY_DSS_ENABLE _MMIO(0x913C)
3233#define GEN12_GT_COMPUTE_DSS_ENABLE _MMIO(0x9144)
3234
3235#define XEHP_EU_ENABLE _MMIO(0x9134)
3236#define XEHP_EU_ENA_MASK 0xFF
3237
3238#define GEN6_BSD_SLEEP_PSMI_CONTROL _MMIO(0x12050)
3239#define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0)
3240#define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2)
3241#define GEN6_BSD_SLEEP_INDICATOR (1 << 3)
3242#define GEN6_BSD_GO_INDICATOR (1 << 4)
3243
3244
3245
3246
3247
3248
3249
3250
3251
3252
3253
3254
3255#define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26)
3256#define GT_BLT_CS_ERROR_INTERRUPT (1 << 25)
3257#define GT_BLT_USER_INTERRUPT (1 << 22)
3258#define GT_BSD_CS_ERROR_INTERRUPT (1 << 15)
3259#define GT_BSD_USER_INTERRUPT (1 << 12)
3260#define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 (1 << 11)
3261#define GT_WAIT_SEMAPHORE_INTERRUPT REG_BIT(11)
3262#define GT_CONTEXT_SWITCH_INTERRUPT (1 << 8)
3263#define GT_RENDER_L3_PARITY_ERROR_INTERRUPT (1 << 5)
3264#define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT (1 << 4)
3265#define GT_CS_MASTER_ERROR_INTERRUPT REG_BIT(3)
3266#define GT_RENDER_SYNC_STATUS_INTERRUPT (1 << 2)
3267#define GT_RENDER_DEBUG_INTERRUPT (1 << 1)
3268#define GT_RENDER_USER_INTERRUPT (1 << 0)
3269
3270#define PM_VEBOX_CS_ERROR_INTERRUPT (1 << 12)
3271#define PM_VEBOX_USER_INTERRUPT (1 << 10)
3272
3273#define GT_PARITY_ERROR(dev_priv) \
3274 (GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \
3275 (IS_HASWELL(dev_priv) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0))
3276
3277
3278#define ILK_BSD_USER_INTERRUPT (1 << 5)
3279
3280#define I915_PM_INTERRUPT (1 << 31)
3281#define I915_ISP_INTERRUPT (1 << 22)
3282#define I915_LPE_PIPE_B_INTERRUPT (1 << 21)
3283#define I915_LPE_PIPE_A_INTERRUPT (1 << 20)
3284#define I915_MIPIC_INTERRUPT (1 << 19)
3285#define I915_MIPIA_INTERRUPT (1 << 18)
3286#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1 << 18)
3287#define I915_DISPLAY_PORT_INTERRUPT (1 << 17)
3288#define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT (1 << 16)
3289#define I915_MASTER_ERROR_INTERRUPT (1 << 15)
3290#define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT (1 << 14)
3291#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1 << 14)
3292#define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT (1 << 13)
3293#define I915_HWB_OOM_INTERRUPT (1 << 13)
3294#define I915_LPE_PIPE_C_INTERRUPT (1 << 12)
3295#define I915_SYNC_STATUS_INTERRUPT (1 << 12)
3296#define I915_MISC_INTERRUPT (1 << 11)
3297#define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1 << 11)
3298#define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT (1 << 10)
3299#define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1 << 10)
3300#define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT (1 << 9)
3301#define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1 << 9)
3302#define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT (1 << 8)
3303#define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1 << 8)
3304#define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1 << 7)
3305#define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1 << 6)
3306#define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1 << 5)
3307#define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1 << 4)
3308#define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT (1 << 3)
3309#define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT (1 << 2)
3310#define I915_DEBUG_INTERRUPT (1 << 2)
3311#define I915_WINVALID_INTERRUPT (1 << 1)
3312#define I915_USER_INTERRUPT (1 << 1)
3313#define I915_ASLE_INTERRUPT (1 << 0)
3314#define I915_BSD_USER_INTERRUPT (1 << 25)
3315
3316#define I915_HDMI_LPE_AUDIO_BASE (VLV_DISPLAY_BASE + 0x65000)
3317#define I915_HDMI_LPE_AUDIO_SIZE 0x1000
3318
3319
3320#define VLV_AUD_CHICKEN_BIT_REG _MMIO(VLV_DISPLAY_BASE + 0x62F38)
3321#define VLV_CHICKEN_BIT_DBG_ENABLE (1 << 0)
3322
3323#define _VLV_AUD_PORT_EN_B_DBG (VLV_DISPLAY_BASE + 0x62F20)
3324#define _VLV_AUD_PORT_EN_C_DBG (VLV_DISPLAY_BASE + 0x62F30)
3325#define _VLV_AUD_PORT_EN_D_DBG (VLV_DISPLAY_BASE + 0x62F34)
3326#define VLV_AUD_PORT_EN_DBG(port) _MMIO_PORT3((port) - PORT_B, \
3327 _VLV_AUD_PORT_EN_B_DBG, \
3328 _VLV_AUD_PORT_EN_C_DBG, \
3329 _VLV_AUD_PORT_EN_D_DBG)
3330#define VLV_AMP_MUTE (1 << 1)
3331
3332#define GEN6_BSD_RNCID _MMIO(0x12198)
3333
3334#define GEN7_FF_THREAD_MODE _MMIO(0x20a0)
3335#define GEN7_FF_SCHED_MASK 0x0077070
3336#define GEN8_FF_DS_REF_CNT_FFME (1 << 19)
3337#define GEN12_FF_TESSELATION_DOP_GATE_DISABLE BIT(19)
3338#define GEN7_FF_TS_SCHED_HS1 (0x5 << 16)
3339#define GEN7_FF_TS_SCHED_HS0 (0x3 << 16)
3340#define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1 << 16)
3341#define GEN7_FF_TS_SCHED_HW (0x0 << 16)
3342#define GEN7_FF_VS_REF_CNT_FFME (1 << 15)
3343#define GEN7_FF_VS_SCHED_HS1 (0x5 << 12)
3344#define GEN7_FF_VS_SCHED_HS0 (0x3 << 12)
3345#define GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1 << 12)
3346#define GEN7_FF_VS_SCHED_HW (0x0 << 12)
3347#define GEN7_FF_DS_SCHED_HS1 (0x5 << 4)
3348#define GEN7_FF_DS_SCHED_HS0 (0x3 << 4)
3349#define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1 << 4)
3350#define GEN7_FF_DS_SCHED_HW (0x0 << 4)
3351
3352
3353
3354
3355
3356#define FBC_CFB_BASE _MMIO(0x3200)
3357#define FBC_LL_BASE _MMIO(0x3204)
3358#define FBC_CONTROL _MMIO(0x3208)
3359#define FBC_CTL_EN REG_BIT(31)
3360#define FBC_CTL_PERIODIC REG_BIT(30)
3361#define FBC_CTL_INTERVAL_MASK REG_GENMASK(29, 16)
3362#define FBC_CTL_INTERVAL(x) REG_FIELD_PREP(FBC_CTL_INTERVAL_MASK, (x))
3363#define FBC_CTL_STOP_ON_MOD REG_BIT(15)
3364#define FBC_CTL_UNCOMPRESSIBLE REG_BIT(14)
3365#define FBC_CTL_C3_IDLE REG_BIT(13)
3366#define FBC_CTL_STRIDE_MASK REG_GENMASK(12, 5)
3367#define FBC_CTL_STRIDE(x) REG_FIELD_PREP(FBC_CTL_STRIDE_MASK, (x))
3368#define FBC_CTL_FENCENO_MASK REG_GENMASK(3, 0)
3369#define FBC_CTL_FENCENO(x) REG_FIELD_PREP(FBC_CTL_FENCENO_MASK, (x))
3370#define FBC_COMMAND _MMIO(0x320c)
3371#define FBC_CMD_COMPRESS REG_BIT(0)
3372#define FBC_STATUS _MMIO(0x3210)
3373#define FBC_STAT_COMPRESSING REG_BIT(31)
3374#define FBC_STAT_COMPRESSED REG_BIT(30)
3375#define FBC_STAT_MODIFIED REG_BIT(29)
3376#define FBC_STAT_CURRENT_LINE_MASK REG_GENMASK(10, 0)
3377#define FBC_CONTROL2 _MMIO(0x3214)
3378#define FBC_CTL_FENCE_DBL REG_BIT(4)
3379#define FBC_CTL_IDLE_MASK REG_GENMASK(3, 2)
3380#define FBC_CTL_IDLE_IMM REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 0)
3381#define FBC_CTL_IDLE_FULL REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 1)
3382#define FBC_CTL_IDLE_LINE REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 2)
3383#define FBC_CTL_IDLE_DEBUG REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 3)
3384#define FBC_CTL_CPU_FENCE_EN REG_BIT(1)
3385#define FBC_CTL_PLANE_MASK REG_GENMASK(1, 0)
3386#define FBC_CTL_PLANE(i9xx_plane) REG_FIELD_PREP(FBC_CTL_PLANE_MASK, (i9xx_plane))
3387#define FBC_FENCE_OFF _MMIO(0x3218)
3388#define FBC_MOD_NUM _MMIO(0x3220)
3389#define FBC_MOD_NUM_MASK REG_GENMASK(31, 1)
3390#define FBC_MOD_NUM_VALID REG_BIT(0)
3391#define FBC_TAG(i) _MMIO(0x3300 + (i) * 4)
3392#define FBC_TAG_MASK REG_GENMASK(1, 0)
3393#define FBC_TAG_MODIFIED REG_FIELD_PREP(FBC_TAG_MASK, 0)
3394#define FBC_TAG_UNCOMPRESSED REG_FIELD_PREP(FBC_TAG_MASK, 1)
3395#define FBC_TAG_UNCOMPRESSIBLE REG_FIELD_PREP(FBC_TAG_MASK, 2)
3396#define FBC_TAG_COMPRESSED REG_FIELD_PREP(FBC_TAG_MASK, 3)
3397
3398#define FBC_LL_SIZE (1536)
3399
3400
3401#define DPFC_CB_BASE _MMIO(0x3200)
3402#define ILK_DPFC_CB_BASE _MMIO(0x43200)
3403#define DPFC_CONTROL _MMIO(0x3208)
3404#define ILK_DPFC_CONTROL _MMIO(0x43208)
3405#define DPFC_CTL_EN REG_BIT(31)
3406#define DPFC_CTL_PLANE_MASK_G4X REG_BIT(30)
3407#define DPFC_CTL_PLANE_G4X(i9xx_plane) REG_FIELD_PREP(DPFC_CTL_PLANE_MASK_G4X, (i9xx_plane))
3408#define DPFC_CTL_FENCE_EN_G4X REG_BIT(29)
3409#define DPFC_CTL_PLANE_MASK_IVB REG_GENMASK(30, 29)
3410#define DPFC_CTL_PLANE_IVB(i9xx_plane) REG_FIELD_PREP(DPFC_CTL_PLANE_MASK_IVB, (i9xx_plane))
3411#define DPFC_CTL_FENCE_EN_IVB REG_BIT(28)
3412#define DPFC_CTL_PERSISTENT_MODE REG_BIT(25)
3413#define DPFC_CTL_FALSE_COLOR REG_BIT(10)
3414#define DPFC_CTL_SR_EN REG_BIT(10)
3415#define DPFC_CTL_SR_EXIT_DIS REG_BIT(9)
3416#define DPFC_CTL_LIMIT_MASK REG_GENMASK(7, 6)
3417#define DPFC_CTL_LIMIT_1X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 0)
3418#define DPFC_CTL_LIMIT_2X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 1)
3419#define DPFC_CTL_LIMIT_4X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 2)
3420#define DPFC_CTL_FENCENO_MASK REG_GENMASK(3, 0)
3421#define DPFC_CTL_FENCENO(fence) REG_FIELD_PREP(DPFC_CTL_FENCENO_MASK, (fence))
3422#define DPFC_RECOMP_CTL _MMIO(0x320c)
3423#define ILK_DPFC_RECOMP_CTL _MMIO(0x4320c)
3424#define DPFC_RECOMP_STALL_EN REG_BIT(27)
3425#define DPFC_RECOMP_STALL_WM_MASK REG_GENMASK(26, 16)
3426#define DPFC_RECOMP_TIMER_COUNT_MASK REG_GENMASK(5, 0)
3427#define DPFC_STATUS _MMIO(0x3210)
3428#define ILK_DPFC_STATUS _MMIO(0x43210)
3429#define DPFC_INVAL_SEG_MASK REG_GENMASK(26, 16)
3430#define DPFC_COMP_SEG_MASK REG_GENMASK(10, 0)
3431#define DPFC_STATUS2 _MMIO(0x3214)
3432#define ILK_DPFC_STATUS2 _MMIO(0x43214)
3433#define DPFC_COMP_SEG_MASK_IVB REG_GENMASK(11, 0)
3434#define DPFC_FENCE_YOFF _MMIO(0x3218)
3435#define ILK_DPFC_FENCE_YOFF _MMIO(0x43218)
3436#define DPFC_CHICKEN _MMIO(0x3224)
3437#define ILK_DPFC_CHICKEN _MMIO(0x43224)
3438#define DPFC_HT_MODIFY REG_BIT(31)
3439#define DPFC_NUKE_ON_ANY_MODIFICATION REG_BIT(23)
3440#define DPFC_CHICKEN_COMP_DUMMY_PIXEL REG_BIT(14)
3441#define DPFC_DISABLE_DUMMY0 REG_BIT(8)
3442
3443#define GLK_FBC_STRIDE _MMIO(0x43228)
3444#define FBC_STRIDE_OVERRIDE REG_BIT(15)
3445#define FBC_STRIDE_MASK REG_GENMASK(14, 0)
3446#define FBC_STRIDE(x) REG_FIELD_PREP(FBC_STRIDE_MASK, (x))
3447
3448#define ILK_FBC_RT_BASE _MMIO(0x2128)
3449#define ILK_FBC_RT_VALID REG_BIT(0)
3450#define SNB_FBC_FRONT_BUFFER REG_BIT(1)
3451
3452#define ILK_DISPLAY_CHICKEN1 _MMIO(0x42000)
3453#define ILK_FBCQ_DIS (1 << 22)
3454#define ILK_PABSTRETCH_DIS REG_BIT(21)
3455#define ILK_SABSTRETCH_DIS REG_BIT(20)
3456#define IVB_PRI_STRETCH_MAX_MASK REG_GENMASK(21, 20)
3457#define IVB_PRI_STRETCH_MAX_X8 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 0)
3458#define IVB_PRI_STRETCH_MAX_X4 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 1)
3459#define IVB_PRI_STRETCH_MAX_X2 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 2)
3460#define IVB_PRI_STRETCH_MAX_X1 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 3)
3461#define IVB_SPR_STRETCH_MAX_MASK REG_GENMASK(19, 18)
3462#define IVB_SPR_STRETCH_MAX_X8 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 0)
3463#define IVB_SPR_STRETCH_MAX_X4 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 1)
3464#define IVB_SPR_STRETCH_MAX_X2 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 2)
3465#define IVB_SPR_STRETCH_MAX_X1 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 3)
3466
3467
3468
3469
3470
3471
3472
3473#define SNB_DPFC_CTL_SA _MMIO(0x100100)
3474#define SNB_DPFC_FENCE_EN REG_BIT(29)
3475#define SNB_DPFC_FENCENO_MASK REG_GENMASK(4, 0)
3476#define SNB_DPFC_FENCENO(fence) REG_FIELD_PREP(SNB_DPFC_FENCENO_MASK, (fence))
3477#define SNB_DPFC_CPU_FENCE_OFFSET _MMIO(0x100104)
3478
3479
3480#define IVB_FBC_RT_BASE _MMIO(0x7020)
3481#define IVB_FBC_RT_BASE_UPPER _MMIO(0x7024)
3482
3483#define IPS_CTL _MMIO(0x43408)
3484#define IPS_ENABLE (1 << 31)
3485
3486#define MSG_FBC_REND_STATE _MMIO(0x50380)
3487#define FBC_REND_NUKE REG_BIT(2)
3488#define FBC_REND_CACHE_CLEAN REG_BIT(1)
3489
3490
3491
3492
3493#define GPIO(gpio) _MMIO(dev_priv->gpio_mmio_base + 0x5010 + \
3494 4 * (gpio))
3495
3496# define GPIO_CLOCK_DIR_MASK (1 << 0)
3497# define GPIO_CLOCK_DIR_IN (0 << 1)
3498# define GPIO_CLOCK_DIR_OUT (1 << 1)
3499# define GPIO_CLOCK_VAL_MASK (1 << 2)
3500# define GPIO_CLOCK_VAL_OUT (1 << 3)
3501# define GPIO_CLOCK_VAL_IN (1 << 4)
3502# define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
3503# define GPIO_DATA_DIR_MASK (1 << 8)
3504# define GPIO_DATA_DIR_IN (0 << 9)
3505# define GPIO_DATA_DIR_OUT (1 << 9)
3506# define GPIO_DATA_VAL_MASK (1 << 10)
3507# define GPIO_DATA_VAL_OUT (1 << 11)
3508# define GPIO_DATA_VAL_IN (1 << 12)
3509# define GPIO_DATA_PULLUP_DISABLE (1 << 13)
3510
3511#define GMBUS0 _MMIO(dev_priv->gpio_mmio_base + 0x5100)
3512#define GMBUS_AKSV_SELECT (1 << 11)
3513#define GMBUS_RATE_100KHZ (0 << 8)
3514#define GMBUS_RATE_50KHZ (1 << 8)
3515#define GMBUS_RATE_400KHZ (2 << 8)
3516#define GMBUS_RATE_1MHZ (3 << 8)
3517#define GMBUS_HOLD_EXT (1 << 7)
3518#define GMBUS_BYTE_CNT_OVERRIDE (1 << 6)
3519
3520#define GMBUS1 _MMIO(dev_priv->gpio_mmio_base + 0x5104)
3521#define GMBUS_SW_CLR_INT (1 << 31)
3522#define GMBUS_SW_RDY (1 << 30)
3523#define GMBUS_ENT (1 << 29)
3524#define GMBUS_CYCLE_NONE (0 << 25)
3525#define GMBUS_CYCLE_WAIT (1 << 25)
3526#define GMBUS_CYCLE_INDEX (2 << 25)
3527#define GMBUS_CYCLE_STOP (4 << 25)
3528#define GMBUS_BYTE_COUNT_SHIFT 16
3529#define GMBUS_BYTE_COUNT_MAX 256U
3530#define GEN9_GMBUS_BYTE_COUNT_MAX 511U
3531#define GMBUS_SLAVE_INDEX_SHIFT 8
3532#define GMBUS_SLAVE_ADDR_SHIFT 1
3533#define GMBUS_SLAVE_READ (1 << 0)
3534#define GMBUS_SLAVE_WRITE (0 << 0)
3535#define GMBUS2 _MMIO(dev_priv->gpio_mmio_base + 0x5108)
3536#define GMBUS_INUSE (1 << 15)
3537#define GMBUS_HW_WAIT_PHASE (1 << 14)
3538#define GMBUS_STALL_TIMEOUT (1 << 13)
3539#define GMBUS_INT (1 << 12)
3540#define GMBUS_HW_RDY (1 << 11)
3541#define GMBUS_SATOER (1 << 10)
3542#define GMBUS_ACTIVE (1 << 9)
3543#define GMBUS3 _MMIO(dev_priv->gpio_mmio_base + 0x510c)
3544#define GMBUS4 _MMIO(dev_priv->gpio_mmio_base + 0x5110)
3545#define GMBUS_SLAVE_TIMEOUT_EN (1 << 4)
3546#define GMBUS_NAK_EN (1 << 3)
3547#define GMBUS_IDLE_EN (1 << 2)
3548#define GMBUS_HW_WAIT_EN (1 << 1)
3549#define GMBUS_HW_RDY_EN (1 << 0)
3550#define GMBUS5 _MMIO(dev_priv->gpio_mmio_base + 0x5120)
3551#define GMBUS_2BYTE_INDEX_EN (1 << 31)
3552
3553
3554
3555
3556#define _DPLL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x6014)
3557#define _DPLL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x6018)
3558#define _CHV_DPLL_C (DISPLAY_MMIO_BASE(dev_priv) + 0x6030)
3559#define DPLL(pipe) _MMIO_PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C)
3560
3561#define VGA0 _MMIO(0x6000)
3562#define VGA1 _MMIO(0x6004)
3563#define VGA_PD _MMIO(0x6010)
3564#define VGA0_PD_P2_DIV_4 (1 << 7)
3565#define VGA0_PD_P1_DIV_2 (1 << 5)
3566#define VGA0_PD_P1_SHIFT 0
3567#define VGA0_PD_P1_MASK (0x1f << 0)
3568#define VGA1_PD_P2_DIV_4 (1 << 15)
3569#define VGA1_PD_P1_DIV_2 (1 << 13)
3570#define VGA1_PD_P1_SHIFT 8
3571#define VGA1_PD_P1_MASK (0x1f << 8)
3572#define DPLL_VCO_ENABLE (1 << 31)
3573#define DPLL_SDVO_HIGH_SPEED (1 << 30)
3574#define DPLL_DVO_2X_MODE (1 << 30)
3575#define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30)
3576#define DPLL_SYNCLOCK_ENABLE (1 << 29)
3577#define DPLL_REF_CLK_ENABLE_VLV (1 << 29)
3578#define DPLL_VGA_MODE_DIS (1 << 28)
3579#define DPLLB_MODE_DAC_SERIAL (1 << 26)
3580#define DPLLB_MODE_LVDS (2 << 26)
3581#define DPLL_MODE_MASK (3 << 26)
3582#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24)
3583#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24)
3584#define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24)
3585#define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24)
3586#define DPLL_P2_CLOCK_DIV_MASK 0x03000000
3587#define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000
3588#define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000
3589#define DPLL_LOCK_VLV (1 << 15)
3590#define DPLL_INTEGRATED_CRI_CLK_VLV (1 << 14)
3591#define DPLL_INTEGRATED_REF_CLK_VLV (1 << 13)
3592#define DPLL_SSC_REF_CLK_CHV (1 << 13)
3593#define DPLL_PORTC_READY_MASK (0xf << 4)
3594#define DPLL_PORTB_READY_MASK (0xf)
3595
3596#define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
3597
3598
3599#define DPIO_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x6240)
3600#define DPLL_PORTD_READY_MASK (0xf)
3601#define DISPLAY_PHY_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x60100)
3602#define PHY_CH_POWER_DOWN_OVRD_EN(phy, ch) (1 << (2 * (phy) + (ch) + 27))
3603#define PHY_LDO_DELAY_0NS 0x0
3604#define PHY_LDO_DELAY_200NS 0x1
3605#define PHY_LDO_DELAY_600NS 0x2
3606#define PHY_LDO_SEQ_DELAY(delay, phy) ((delay) << (2 * (phy) + 23))
3607#define PHY_CH_POWER_DOWN_OVRD(mask, phy, ch) ((mask) << (8 * (phy) + 4 * (ch) + 11))
3608#define PHY_CH_SU_PSR 0x1
3609#define PHY_CH_DEEP_PSR 0x7
3610#define PHY_CH_POWER_MODE(mode, phy, ch) ((mode) << (6 * (phy) + 3 * (ch) + 2))
3611#define PHY_COM_LANE_RESET_DEASSERT(phy) (1 << (phy))
3612#define DISPLAY_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x60104)
3613#define PHY_POWERGOOD(phy) (((phy) == DPIO_PHY0) ? (1 << 31) : (1 << 30))
3614#define PHY_STATUS_CMN_LDO(phy, ch) (1 << (6 - (6 * (phy) + 3 * (ch))))
3615#define PHY_STATUS_SPLINE_LDO(phy, ch, spline) (1 << (8 - (6 * (phy) + 3 * (ch) + (spline))))
3616
3617
3618
3619
3620
3621#define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
3622#define DPLL_FPA01_P1_POST_DIV_SHIFT 16
3623#define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15
3624
3625#define PLL_P2_DIVIDE_BY_4 (1 << 23)
3626#define PLL_P1_DIVIDE_BY_TWO (1 << 21)
3627#define PLL_REF_INPUT_DREFCLK (0 << 13)
3628#define PLL_REF_INPUT_TVCLKINA (1 << 13)
3629#define PLL_REF_INPUT_TVCLKINBC (2 << 13)
3630#define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
3631#define PLL_REF_INPUT_MASK (3 << 13)
3632#define PLL_LOAD_PULSE_PHASE_SHIFT 9
3633
3634# define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9
3635# define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9)
3636# define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x) - 1) << 9)
3637# define DPLL_FPA1_P1_POST_DIV_SHIFT 0
3638# define DPLL_FPA1_P1_POST_DIV_MASK 0xff
3639
3640
3641
3642
3643
3644
3645
3646#define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
3647#define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
3648
3649
3650
3651#define SDVO_MULTIPLIER_MASK 0x000000ff
3652#define SDVO_MULTIPLIER_SHIFT_HIRES 4
3653#define SDVO_MULTIPLIER_SHIFT_VGA 0
3654
3655#define _DPLL_A_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x601c)
3656#define _DPLL_B_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x6020)
3657#define _CHV_DPLL_C_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x603c)
3658#define DPLL_MD(pipe) _MMIO_PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD)
3659
3660
3661
3662
3663
3664
3665#define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
3666#define DPLL_MD_UDI_DIVIDER_SHIFT 24
3667
3668#define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000
3669#define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16
3670
3671
3672
3673
3674
3675
3676
3677
3678
3679
3680
3681
3682
3683
3684
3685
3686
3687#define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
3688#define DPLL_MD_UDI_MULTIPLIER_SHIFT 8
3689
3690
3691
3692
3693
3694#define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
3695#define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
3696
3697#define RAWCLK_FREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6024)
3698
3699#define _FPA0 0x6040
3700#define _FPA1 0x6044
3701#define _FPB0 0x6048
3702#define _FPB1 0x604c
3703#define FP0(pipe) _MMIO_PIPE(pipe, _FPA0, _FPB0)
3704#define FP1(pipe) _MMIO_PIPE(pipe, _FPA1, _FPB1)
3705#define FP_N_DIV_MASK 0x003f0000
3706#define FP_N_PINEVIEW_DIV_MASK 0x00ff0000
3707#define FP_N_DIV_SHIFT 16
3708#define FP_M1_DIV_MASK 0x00003f00
3709#define FP_M1_DIV_SHIFT 8
3710#define FP_M2_DIV_MASK 0x0000003f
3711#define FP_M2_PINEVIEW_DIV_MASK 0x000000ff
3712#define FP_M2_DIV_SHIFT 0
3713#define DPLL_TEST _MMIO(0x606c)
3714#define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
3715#define DPLLB_TEST_SDVO_DIV_2 (1 << 22)
3716#define DPLLB_TEST_SDVO_DIV_4 (2 << 22)
3717#define DPLLB_TEST_SDVO_DIV_MASK (3 << 22)
3718#define DPLLB_TEST_N_BYPASS (1 << 19)
3719#define DPLLB_TEST_M_BYPASS (1 << 18)
3720#define DPLLB_INPUT_BUFFER_ENABLE (1 << 16)
3721#define DPLLA_TEST_N_BYPASS (1 << 3)
3722#define DPLLA_TEST_M_BYPASS (1 << 2)
3723#define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
3724#define D_STATE _MMIO(0x6104)
3725#define DSTATE_GFX_RESET_I830 (1 << 6)
3726#define DSTATE_PLL_D3_OFF (1 << 3)
3727#define DSTATE_GFX_CLOCK_GATING (1 << 1)
3728#define DSTATE_DOT_CLOCK_GATING (1 << 0)
3729#define DSPCLK_GATE_D _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x6200)
3730# define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30)
3731# define VSUNIT_CLOCK_GATE_DISABLE (1 << 29)
3732# define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28)
3733# define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27)
3734# define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26)
3735# define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25)
3736# define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24)
3737# define PNV_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 24)
3738# define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23)
3739# define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22)
3740# define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21)
3741# define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20)
3742# define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19)
3743# define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18)
3744# define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17)
3745# define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16)
3746# define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15)
3747# define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14)
3748# define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13)
3749# define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12)
3750# define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11)
3751# define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10)
3752# define DCUNIT_CLOCK_GATE_DISABLE (1 << 9)
3753# define DPUNIT_CLOCK_GATE_DISABLE (1 << 8)
3754# define VRUNIT_CLOCK_GATE_DISABLE (1 << 7)
3755# define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6)
3756# define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6)
3757# define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5)
3758# define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4)
3759
3760
3761
3762
3763# define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3)
3764# define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2)
3765# define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1)
3766# define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0)
3767# define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0)
3768
3769#define RENCLK_GATE_D1 _MMIO(0x6204)
3770# define BLITTER_CLOCK_GATE_DISABLE (1 << 13)
3771# define MPEG_CLOCK_GATE_DISABLE (1 << 12)
3772# define PC_FE_CLOCK_GATE_DISABLE (1 << 11)
3773# define PC_BE_CLOCK_GATE_DISABLE (1 << 10)
3774# define WINDOWER_CLOCK_GATE_DISABLE (1 << 9)
3775# define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8)
3776# define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7)
3777# define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6)
3778# define MAG_CLOCK_GATE_DISABLE (1 << 5)
3779
3780# define MECI_CLOCK_GATE_DISABLE (1 << 4)
3781# define DCMP_CLOCK_GATE_DISABLE (1 << 3)
3782# define MEC_CLOCK_GATE_DISABLE (1 << 2)
3783# define MECO_CLOCK_GATE_DISABLE (1 << 1)
3784
3785# define SV_CLOCK_GATE_DISABLE (1 << 0)
3786# define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16)
3787# define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15)
3788# define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14)
3789# define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13)
3790# define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12)
3791# define I915_WM_CLOCK_GATE_DISABLE (1 << 11)
3792# define I915_IZ_CLOCK_GATE_DISABLE (1 << 10)
3793# define I915_PI_CLOCK_GATE_DISABLE (1 << 9)
3794# define I915_DI_CLOCK_GATE_DISABLE (1 << 8)
3795# define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7)
3796# define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6)
3797# define I915_SC_CLOCK_GATE_DISABLE (1 << 5)
3798# define I915_FL_CLOCK_GATE_DISABLE (1 << 4)
3799# define I915_DM_CLOCK_GATE_DISABLE (1 << 3)
3800# define I915_PS_CLOCK_GATE_DISABLE (1 << 2)
3801# define I915_CC_CLOCK_GATE_DISABLE (1 << 1)
3802# define I915_BY_CLOCK_GATE_DISABLE (1 << 0)
3803
3804# define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30)
3805
3806# define I965_RCC_CLOCK_GATE_DISABLE (1 << 29)
3807# define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28)
3808# define I965_DAP_CLOCK_GATE_DISABLE (1 << 27)
3809# define I965_ROC_CLOCK_GATE_DISABLE (1 << 26)
3810# define I965_GW_CLOCK_GATE_DISABLE (1 << 25)
3811# define I965_TD_CLOCK_GATE_DISABLE (1 << 24)
3812
3813# define I965_ISC_CLOCK_GATE_DISABLE (1 << 23)
3814# define I965_IC_CLOCK_GATE_DISABLE (1 << 22)
3815# define I965_EU_CLOCK_GATE_DISABLE (1 << 21)
3816# define I965_IF_CLOCK_GATE_DISABLE (1 << 20)
3817# define I965_TC_CLOCK_GATE_DISABLE (1 << 19)
3818# define I965_SO_CLOCK_GATE_DISABLE (1 << 17)
3819# define I965_FBC_CLOCK_GATE_DISABLE (1 << 16)
3820# define I965_MARI_CLOCK_GATE_DISABLE (1 << 15)
3821# define I965_MASF_CLOCK_GATE_DISABLE (1 << 14)
3822# define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13)
3823# define I965_EM_CLOCK_GATE_DISABLE (1 << 12)
3824# define I965_UC_CLOCK_GATE_DISABLE (1 << 11)
3825# define I965_SI_CLOCK_GATE_DISABLE (1 << 6)
3826# define I965_MT_CLOCK_GATE_DISABLE (1 << 5)
3827# define I965_PL_CLOCK_GATE_DISABLE (1 << 4)
3828# define I965_DG_CLOCK_GATE_DISABLE (1 << 3)
3829# define I965_QC_CLOCK_GATE_DISABLE (1 << 2)
3830# define I965_FT_CLOCK_GATE_DISABLE (1 << 1)
3831# define I965_DM_CLOCK_GATE_DISABLE (1 << 0)
3832
3833#define RENCLK_GATE_D2 _MMIO(0x6208)
3834#define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9)
3835#define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7)
3836#define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6)
3837
3838#define VDECCLK_GATE_D _MMIO(0x620C)
3839#define VCP_UNIT_CLOCK_GATE_DISABLE (1 << 4)
3840
3841#define RAMCLK_GATE_D _MMIO(0x6210)
3842#define DEUC _MMIO(0x6214)
3843
3844#define FW_BLC_SELF_VLV _MMIO(VLV_DISPLAY_BASE + 0x6500)
3845#define FW_CSPWRDWNEN (1 << 15)
3846
3847#define MI_ARB_VLV _MMIO(VLV_DISPLAY_BASE + 0x6504)
3848
3849#define CZCLK_CDCLK_FREQ_RATIO _MMIO(VLV_DISPLAY_BASE + 0x6508)
3850#define CDCLK_FREQ_SHIFT 4
3851#define CDCLK_FREQ_MASK (0x1f << CDCLK_FREQ_SHIFT)
3852#define CZCLK_FREQ_MASK 0xf
3853
3854#define GCI_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x650C)
3855#define PFI_CREDIT_63 (9 << 28)
3856#define PFI_CREDIT_31 (8 << 28)
3857#define PFI_CREDIT(x) (((x) - 8) << 28)
3858#define PFI_CREDIT_RESEND (1 << 27)
3859#define VGA_FAST_MODE_DISABLE (1 << 14)
3860
3861#define GMBUSFREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6510)
3862
3863
3864
3865
3866#define _PALETTE_A 0xa000
3867#define _PALETTE_B 0xa800
3868#define _CHV_PALETTE_C 0xc000
3869#define PALETTE_RED_MASK REG_GENMASK(23, 16)
3870#define PALETTE_GREEN_MASK REG_GENMASK(15, 8)
3871#define PALETTE_BLUE_MASK REG_GENMASK(7, 0)
3872#define PALETTE(pipe, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \
3873 _PICK((pipe), _PALETTE_A, \
3874 _PALETTE_B, _CHV_PALETTE_C) + \
3875 (i) * 4)
3876
3877
3878
3879
3880
3881
3882
3883
3884
3885
3886
3887
3888
3889#define MCHBAR_MIRROR_BASE 0x10000
3890
3891#define MCHBAR_MIRROR_BASE_SNB 0x140000
3892
3893#define CTG_STOLEN_RESERVED _MMIO(MCHBAR_MIRROR_BASE + 0x34)
3894#define ELK_STOLEN_RESERVED _MMIO(MCHBAR_MIRROR_BASE + 0x48)
3895#define G4X_STOLEN_RESERVED_ADDR1_MASK (0xFFFF << 16)
3896#define G4X_STOLEN_RESERVED_ADDR2_MASK (0xFFF << 4)
3897#define G4X_STOLEN_RESERVED_ENABLE (1 << 0)
3898
3899
3900#define DCLK _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5e04)
3901
3902
3903#define DCC _MMIO(MCHBAR_MIRROR_BASE + 0x200)
3904#define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0)
3905#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0)
3906#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0)
3907#define DCC_ADDRESSING_MODE_MASK (3 << 0)
3908#define DCC_CHANNEL_XOR_DISABLE (1 << 10)
3909#define DCC_CHANNEL_XOR_BIT_17 (1 << 9)
3910#define DCC2 _MMIO(MCHBAR_MIRROR_BASE + 0x204)
3911#define DCC2_MODIFIED_ENHANCED_DISABLE (1 << 20)
3912
3913
3914#define CSHRDDR3CTL _MMIO(MCHBAR_MIRROR_BASE + 0x1a8)
3915#define CSHRDDR3CTL_DDR3 (1 << 2)
3916
3917
3918#define C0DRB3_BW _MMIO(MCHBAR_MIRROR_BASE + 0x206)
3919#define C1DRB3_BW _MMIO(MCHBAR_MIRROR_BASE + 0x606)
3920
3921
3922#define MAD_DIMM_C0 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5004)
3923#define MAD_DIMM_C1 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5008)
3924#define MAD_DIMM_C2 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C)
3925#define MAD_DIMM_ECC_MASK (0x3 << 24)
3926#define MAD_DIMM_ECC_OFF (0x0 << 24)
3927#define MAD_DIMM_ECC_IO_ON_LOGIC_OFF (0x1 << 24)
3928#define MAD_DIMM_ECC_IO_OFF_LOGIC_ON (0x2 << 24)
3929#define MAD_DIMM_ECC_ON (0x3 << 24)
3930#define MAD_DIMM_ENH_INTERLEAVE (0x1 << 22)
3931#define MAD_DIMM_RANK_INTERLEAVE (0x1 << 21)
3932#define MAD_DIMM_B_WIDTH_X16 (0x1 << 20)
3933#define MAD_DIMM_A_WIDTH_X16 (0x1 << 19)
3934#define MAD_DIMM_B_DUAL_RANK (0x1 << 18)
3935#define MAD_DIMM_A_DUAL_RANK (0x1 << 17)
3936#define MAD_DIMM_A_SELECT (0x1 << 16)
3937
3938#define MAD_DIMM_B_SIZE_SHIFT 8
3939#define MAD_DIMM_B_SIZE_MASK (0xff << MAD_DIMM_B_SIZE_SHIFT)
3940#define MAD_DIMM_A_SIZE_SHIFT 0
3941#define MAD_DIMM_A_SIZE_MASK (0xff << MAD_DIMM_A_SIZE_SHIFT)
3942
3943
3944#define MCH_SSKPD _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5d10)
3945#define MCH_SSKPD_WM0_MASK 0x3f
3946#define MCH_SSKPD_WM0_VAL 0xc
3947
3948
3949#define CLKCFG _MMIO(MCHBAR_MIRROR_BASE + 0xc00)
3950#define CLKCFG_FSB_400 (0 << 0)
3951#define CLKCFG_FSB_400_ALT (5 << 0)
3952#define CLKCFG_FSB_533 (1 << 0)
3953#define CLKCFG_FSB_667 (3 << 0)
3954#define CLKCFG_FSB_800 (2 << 0)
3955#define CLKCFG_FSB_1067 (6 << 0)
3956#define CLKCFG_FSB_1067_ALT (0 << 0)
3957#define CLKCFG_FSB_1333 (7 << 0)
3958#define CLKCFG_FSB_1333_ALT (4 << 0)
3959#define CLKCFG_FSB_1600_ALT (6 << 0)
3960#define CLKCFG_FSB_MASK (7 << 0)
3961#define CLKCFG_MEM_533 (1 << 4)
3962#define CLKCFG_MEM_667 (2 << 4)
3963#define CLKCFG_MEM_800 (3 << 4)
3964#define CLKCFG_MEM_MASK (7 << 4)
3965
3966#define HPLLVCO _MMIO(MCHBAR_MIRROR_BASE + 0xc38)
3967#define HPLLVCO_MOBILE _MMIO(MCHBAR_MIRROR_BASE + 0xc0f)
3968
3969#define TSC1 _MMIO(0x11001)
3970#define TSE (1 << 0)
3971#define TR1 _MMIO(0x11006)
3972#define TSFS _MMIO(0x11020)
3973#define TSFS_SLOPE_MASK 0x0000ff00
3974#define TSFS_SLOPE_SHIFT 8
3975#define TSFS_INTR_MASK 0x000000ff
3976
3977#define CRSTANDVID _MMIO(0x11100)
3978#define PXVFREQ(fstart) _MMIO(0x11110 + (fstart) * 4)
3979#define PXVFREQ_PX_MASK 0x7f000000
3980#define PXVFREQ_PX_SHIFT 24
3981#define VIDFREQ_BASE _MMIO(0x11110)
3982#define VIDFREQ1 _MMIO(0x11110)
3983#define VIDFREQ2 _MMIO(0x11114)
3984#define VIDFREQ3 _MMIO(0x11118)
3985#define VIDFREQ4 _MMIO(0x1111c)
3986#define VIDFREQ_P0_MASK 0x1f000000
3987#define VIDFREQ_P0_SHIFT 24
3988#define VIDFREQ_P0_CSCLK_MASK 0x00f00000
3989#define VIDFREQ_P0_CSCLK_SHIFT 20
3990#define VIDFREQ_P0_CRCLK_MASK 0x000f0000
3991#define VIDFREQ_P0_CRCLK_SHIFT 16
3992#define VIDFREQ_P1_MASK 0x00001f00
3993#define VIDFREQ_P1_SHIFT 8
3994#define VIDFREQ_P1_CSCLK_MASK 0x000000f0
3995#define VIDFREQ_P1_CSCLK_SHIFT 4
3996#define VIDFREQ_P1_CRCLK_MASK 0x0000000f
3997#define INTTOEXT_BASE_ILK _MMIO(0x11300)
3998#define INTTOEXT_BASE _MMIO(0x11120)
3999#define INTTOEXT_MAP3_SHIFT 24
4000#define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT)
4001#define INTTOEXT_MAP2_SHIFT 16
4002#define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT)
4003#define INTTOEXT_MAP1_SHIFT 8
4004#define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT)
4005#define INTTOEXT_MAP0_SHIFT 0
4006#define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT)
4007#define MEMSWCTL _MMIO(0x11170)
4008#define MEMCTL_CMD_MASK 0xe000
4009#define MEMCTL_CMD_SHIFT 13
4010#define MEMCTL_CMD_RCLK_OFF 0
4011#define MEMCTL_CMD_RCLK_ON 1
4012#define MEMCTL_CMD_CHFREQ 2
4013#define MEMCTL_CMD_CHVID 3
4014#define MEMCTL_CMD_VMMOFF 4
4015#define MEMCTL_CMD_VMMON 5
4016#define MEMCTL_CMD_STS (1 << 12)
4017
4018#define MEMCTL_FREQ_MASK 0x0f00
4019#define MEMCTL_FREQ_SHIFT 8
4020#define MEMCTL_SFCAVM (1 << 7)
4021#define MEMCTL_TGT_VID_MASK 0x007f
4022#define MEMIHYST _MMIO(0x1117c)
4023#define MEMINTREN _MMIO(0x11180)
4024#define MEMINT_RSEXIT_EN (1 << 8)
4025#define MEMINT_CX_SUPR_EN (1 << 7)
4026#define MEMINT_CONT_BUSY_EN (1 << 6)
4027#define MEMINT_AVG_BUSY_EN (1 << 5)
4028#define MEMINT_EVAL_CHG_EN (1 << 4)
4029#define MEMINT_MON_IDLE_EN (1 << 3)
4030#define MEMINT_UP_EVAL_EN (1 << 2)
4031#define MEMINT_DOWN_EVAL_EN (1 << 1)
4032#define MEMINT_SW_CMD_EN (1 << 0)
4033#define MEMINTRSTR _MMIO(0x11182)
4034#define MEM_RSEXIT_MASK 0xc000
4035#define MEM_RSEXIT_SHIFT 14
4036#define MEM_CONT_BUSY_MASK 0x3000
4037#define MEM_CONT_BUSY_SHIFT 12
4038#define MEM_AVG_BUSY_MASK 0x0c00
4039#define MEM_AVG_BUSY_SHIFT 10
4040#define MEM_EVAL_CHG_MASK 0x0300
4041#define MEM_EVAL_BUSY_SHIFT 8
4042#define MEM_MON_IDLE_MASK 0x00c0
4043#define MEM_MON_IDLE_SHIFT 6
4044#define MEM_UP_EVAL_MASK 0x0030
4045#define MEM_UP_EVAL_SHIFT 4
4046#define MEM_DOWN_EVAL_MASK 0x000c
4047#define MEM_DOWN_EVAL_SHIFT 2
4048#define MEM_SW_CMD_MASK 0x0003
4049#define MEM_INT_STEER_GFX 0
4050#define MEM_INT_STEER_CMR 1
4051#define MEM_INT_STEER_SMI 2
4052#define MEM_INT_STEER_SCI 3
4053#define MEMINTRSTS _MMIO(0x11184)
4054#define MEMINT_RSEXIT (1 << 7)
4055#define MEMINT_CONT_BUSY (1 << 6)
4056#define MEMINT_AVG_BUSY (1 << 5)
4057#define MEMINT_EVAL_CHG (1 << 4)
4058#define MEMINT_MON_IDLE (1 << 3)
4059#define MEMINT_UP_EVAL (1 << 2)
4060#define MEMINT_DOWN_EVAL (1 << 1)
4061#define MEMINT_SW_CMD (1 << 0)
4062#define MEMMODECTL _MMIO(0x11190)
4063#define MEMMODE_BOOST_EN (1 << 31)
4064#define MEMMODE_BOOST_FREQ_MASK 0x0f000000
4065#define MEMMODE_BOOST_FREQ_SHIFT 24
4066#define MEMMODE_IDLE_MODE_MASK 0x00030000
4067#define MEMMODE_IDLE_MODE_SHIFT 16
4068#define MEMMODE_IDLE_MODE_EVAL 0
4069#define MEMMODE_IDLE_MODE_CONT 1
4070#define MEMMODE_HWIDLE_EN (1 << 15)
4071#define MEMMODE_SWMODE_EN (1 << 14)
4072#define MEMMODE_RCLK_GATE (1 << 13)
4073#define MEMMODE_HW_UPDATE (1 << 12)
4074#define MEMMODE_FSTART_MASK 0x00000f00
4075#define MEMMODE_FSTART_SHIFT 8
4076#define MEMMODE_FMAX_MASK 0x000000f0
4077#define MEMMODE_FMAX_SHIFT 4
4078#define MEMMODE_FMIN_MASK 0x0000000f
4079#define RCBMAXAVG _MMIO(0x1119c)
4080#define MEMSWCTL2 _MMIO(0x1119e)
4081#define SWMEMCMD_RENDER_OFF (0 << 13)
4082#define SWMEMCMD_RENDER_ON (1 << 13)
4083#define SWMEMCMD_SWFREQ (2 << 13)
4084#define SWMEMCMD_TARVID (3 << 13)
4085#define SWMEMCMD_VRM_OFF (4 << 13)
4086#define SWMEMCMD_VRM_ON (5 << 13)
4087#define CMDSTS (1 << 12)
4088#define SFCAVM (1 << 11)
4089#define SWFREQ_MASK 0x0380
4090#define SWFREQ_SHIFT 7
4091#define TARVID_MASK 0x001f
4092#define MEMSTAT_CTG _MMIO(0x111a0)
4093#define RCBMINAVG _MMIO(0x111a0)
4094#define RCUPEI _MMIO(0x111b0)
4095#define RCDNEI _MMIO(0x111b4)
4096#define RSTDBYCTL _MMIO(0x111b8)
4097#define RS1EN (1 << 31)
4098#define RS2EN (1 << 30)
4099#define RS3EN (1 << 29)
4100#define D3RS3EN (1 << 28)
4101#define SWPROMORSX (1 << 27)
4102#define RCWAKERW (1 << 26)
4103#define DPRSLPVREN (1 << 25)
4104#define GFXTGHYST (1 << 24)
4105#define RCX_SW_EXIT (1 << 23)
4106#define RSX_STATUS_MASK (7 << 20)
4107#define RSX_STATUS_ON (0 << 20)
4108#define RSX_STATUS_RC1 (1 << 20)
4109#define RSX_STATUS_RC1E (2 << 20)
4110#define RSX_STATUS_RS1 (3 << 20)
4111#define RSX_STATUS_RS2 (4 << 20)
4112#define RSX_STATUS_RSVD (5 << 20)
4113#define RSX_STATUS_RS3 (6 << 20)
4114#define RSX_STATUS_RSVD2 (7 << 20)
4115#define UWRCRSXE (1 << 19)
4116#define RSCRP (1 << 18)
4117#define JRSC (1 << 17)
4118#define RS2INC0 (1 << 16)
4119#define RS1CONTSAV_MASK (3 << 14)
4120#define RS1CONTSAV_NO_RS1 (0 << 14)
4121#define RS1CONTSAV_RSVD (1 << 14)
4122#define RS1CONTSAV_SAVE_RS1 (2 << 14)
4123#define RS1CONTSAV_FULL_RS1 (3 << 14)
4124#define NORMSLEXLAT_MASK (3 << 12)
4125#define SLOW_RS123 (0 << 12)
4126#define SLOW_RS23 (1 << 12)
4127#define SLOW_RS3 (2 << 12)
4128#define NORMAL_RS123 (3 << 12)
4129#define RCMODE_TIMEOUT (1 << 11)
4130#define IMPROMOEN (1 << 10)
4131#define RCENTSYNC (1 << 9)
4132#define STATELOCK (1 << 7)
4133#define RS_CSTATE_MASK (3 << 4)
4134#define RS_CSTATE_C367_RS1 (0 << 4)
4135#define RS_CSTATE_C36_RS1_C7_RS2 (1 << 4)
4136#define RS_CSTATE_RSVD (2 << 4)
4137#define RS_CSTATE_C367_RS2 (3 << 4)
4138#define REDSAVES (1 << 3)
4139#define REDRESTORES (1 << 2)
4140#define VIDCTL _MMIO(0x111c0)
4141#define VIDSTS _MMIO(0x111c8)
4142#define VIDSTART _MMIO(0x111cc)
4143#define MEMSTAT_ILK _MMIO(0x111f8)
4144#define MEMSTAT_VID_MASK 0x7f00
4145#define MEMSTAT_VID_SHIFT 8
4146#define MEMSTAT_PSTATE_MASK 0x00f8
4147#define MEMSTAT_PSTATE_SHIFT 3
4148#define MEMSTAT_MON_ACTV (1 << 2)
4149#define MEMSTAT_SRC_CTL_MASK 0x0003
4150#define MEMSTAT_SRC_CTL_CORE 0
4151#define MEMSTAT_SRC_CTL_TRB 1
4152#define MEMSTAT_SRC_CTL_THM 2
4153#define MEMSTAT_SRC_CTL_STDBY 3
4154#define RCPREVBSYTUPAVG _MMIO(0x113b8)
4155#define RCPREVBSYTDNAVG _MMIO(0x113bc)
4156#define PMMISC _MMIO(0x11214)
4157#define MCPPCE_EN (1 << 0)
4158#define SDEW _MMIO(0x1124c)
4159#define CSIEW0 _MMIO(0x11250)
4160#define CSIEW1 _MMIO(0x11254)
4161#define CSIEW2 _MMIO(0x11258)
4162#define PEW(i) _MMIO(0x1125c + (i) * 4)
4163#define DEW(i) _MMIO(0x11270 + (i) * 4)
4164#define MCHAFE _MMIO(0x112c0)
4165#define CSIEC _MMIO(0x112e0)
4166#define DMIEC _MMIO(0x112e4)
4167#define DDREC _MMIO(0x112e8)
4168#define PEG0EC _MMIO(0x112ec)
4169#define PEG1EC _MMIO(0x112f0)
4170#define GFXEC _MMIO(0x112f4)
4171#define RPPREVBSYTUPAVG _MMIO(0x113b8)
4172#define RPPREVBSYTDNAVG _MMIO(0x113bc)
4173#define ECR _MMIO(0x11600)
4174#define ECR_GPFE (1 << 31)
4175#define ECR_IMONE (1 << 30)
4176#define ECR_CAP_MASK 0x0000001f
4177#define OGW0 _MMIO(0x11608)
4178#define OGW1 _MMIO(0x1160c)
4179#define EG0 _MMIO(0x11610)
4180#define EG1 _MMIO(0x11614)
4181#define EG2 _MMIO(0x11618)
4182#define EG3 _MMIO(0x1161c)
4183#define EG4 _MMIO(0x11620)
4184#define EG5 _MMIO(0x11624)
4185#define EG6 _MMIO(0x11628)
4186#define EG7 _MMIO(0x1162c)
4187#define PXW(i) _MMIO(0x11664 + (i) * 4)
4188#define PXWL(i) _MMIO(0x11680 + (i) * 8)
4189#define LCFUSE02 _MMIO(0x116c0)
4190#define LCFUSE_HIV_MASK 0x000000ff
4191#define CSIPLL0 _MMIO(0x12c10)
4192#define DDRMPLL1 _MMIO(0X12c20)
4193#define PEG_BAND_GAP_DATA _MMIO(0x14d68)
4194
4195#define GEN6_GT_THREAD_STATUS_REG _MMIO(0x13805c)
4196#define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7
4197
4198#define GEN6_GT_PERF_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5948)
4199#define BXT_GT_PERF_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x7070)
4200#define GEN6_RP_STATE_LIMITS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5994)
4201#define GEN6_RP_STATE_CAP _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5998)
4202#define RP0_CAP_MASK REG_GENMASK(7, 0)
4203#define RP1_CAP_MASK REG_GENMASK(15, 8)
4204#define RPN_CAP_MASK REG_GENMASK(23, 16)
4205#define BXT_RP_STATE_CAP _MMIO(0x138170)
4206#define GEN9_RP_STATE_LIMITS _MMIO(0x138148)
4207#define XEHPSDV_RP_STATE_CAP _MMIO(0x250014)
4208
4209
4210
4211
4212#define CCID(base) _MMIO((base) + 0x180)
4213#define CCID_EN BIT(0)
4214#define CCID_EXTENDED_STATE_RESTORE BIT(2)
4215#define CCID_EXTENDED_STATE_SAVE BIT(3)
4216
4217
4218
4219
4220
4221
4222
4223
4224
4225
4226
4227
4228
4229#define CXT_SIZE _MMIO(0x21a0)
4230#define GEN6_CXT_POWER_SIZE(cxt_reg) (((cxt_reg) >> 24) & 0x3f)
4231#define GEN6_CXT_RING_SIZE(cxt_reg) (((cxt_reg) >> 18) & 0x3f)
4232#define GEN6_CXT_RENDER_SIZE(cxt_reg) (((cxt_reg) >> 12) & 0x3f)
4233#define GEN6_CXT_EXTENDED_SIZE(cxt_reg) (((cxt_reg) >> 6) & 0x3f)
4234#define GEN6_CXT_PIPELINE_SIZE(cxt_reg) (((cxt_reg) >> 0) & 0x3f)
4235#define GEN6_CXT_TOTAL_SIZE(cxt_reg) (GEN6_CXT_RING_SIZE(cxt_reg) + \
4236 GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \
4237 GEN6_CXT_PIPELINE_SIZE(cxt_reg))
4238#define GEN7_CXT_SIZE _MMIO(0x21a8)
4239#define GEN7_CXT_POWER_SIZE(ctx_reg) (((ctx_reg) >> 25) & 0x7f)
4240#define GEN7_CXT_RING_SIZE(ctx_reg) (((ctx_reg) >> 22) & 0x7)
4241#define GEN7_CXT_RENDER_SIZE(ctx_reg) (((ctx_reg) >> 16) & 0x3f)
4242#define GEN7_CXT_EXTENDED_SIZE(ctx_reg) (((ctx_reg) >> 9) & 0x7f)
4243#define GEN7_CXT_GT1_SIZE(ctx_reg) (((ctx_reg) >> 6) & 0x7)
4244#define GEN7_CXT_VFSTATE_SIZE(ctx_reg) (((ctx_reg) >> 0) & 0x3f)
4245#define GEN7_CXT_TOTAL_SIZE(ctx_reg) (GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \
4246 GEN7_CXT_VFSTATE_SIZE(ctx_reg))
4247
4248enum {
4249 INTEL_ADVANCED_CONTEXT = 0,
4250 INTEL_LEGACY_32B_CONTEXT,
4251 INTEL_ADVANCED_AD_CONTEXT,
4252 INTEL_LEGACY_64B_CONTEXT
4253};
4254
4255enum {
4256 FAULT_AND_HANG = 0,
4257 FAULT_AND_HALT,
4258 FAULT_AND_STREAM,
4259 FAULT_AND_CONTINUE
4260};
4261
4262#define CTX_GTT_ADDRESS_MASK GENMASK(31, 12)
4263#define GEN8_CTX_VALID (1 << 0)
4264#define GEN8_CTX_FORCE_PD_RESTORE (1 << 1)
4265#define GEN8_CTX_FORCE_RESTORE (1 << 2)
4266#define GEN8_CTX_L3LLC_COHERENT (1 << 5)
4267#define GEN8_CTX_PRIVILEGE (1 << 8)
4268#define GEN8_CTX_ADDRESSING_MODE_SHIFT 3
4269
4270#define GEN8_CTX_ID_SHIFT 32
4271#define GEN8_CTX_ID_WIDTH 21
4272#define GEN11_SW_CTX_ID_SHIFT 37
4273#define GEN11_SW_CTX_ID_WIDTH 11
4274#define GEN11_ENGINE_CLASS_SHIFT 61
4275#define GEN11_ENGINE_CLASS_WIDTH 3
4276#define GEN11_ENGINE_INSTANCE_SHIFT 48
4277#define GEN11_ENGINE_INSTANCE_WIDTH 6
4278
4279#define XEHP_SW_CTX_ID_SHIFT 39
4280#define XEHP_SW_CTX_ID_WIDTH 16
4281#define XEHP_SW_COUNTER_SHIFT 58
4282#define XEHP_SW_COUNTER_WIDTH 6
4283
4284#define CHV_CLK_CTL1 _MMIO(0x101100)
4285#define VLV_CLK_CTL2 _MMIO(0x101104)
4286#define CLK_CTL2_CZCOUNT_30NS_SHIFT 28
4287
4288
4289
4290
4291
4292#define OVADD _MMIO(0x30000)
4293#define DOVSTA _MMIO(0x30008)
4294#define OC_BUF (0x3 << 20)
4295#define OGAMC5 _MMIO(0x30010)
4296#define OGAMC4 _MMIO(0x30014)
4297#define OGAMC3 _MMIO(0x30018)
4298#define OGAMC2 _MMIO(0x3001c)
4299#define OGAMC1 _MMIO(0x30020)
4300#define OGAMC0 _MMIO(0x30024)
4301
4302
4303
4304
4305#define GEN9_CLKGATE_DIS_0 _MMIO(0x46530)
4306#define DARBF_GATING_DIS (1 << 27)
4307#define PWM2_GATING_DIS (1 << 14)
4308#define PWM1_GATING_DIS (1 << 13)
4309
4310#define GEN9_CLKGATE_DIS_3 _MMIO(0x46538)
4311#define TGL_VRH_GATING_DIS REG_BIT(31)
4312#define DPT_GATING_DIS REG_BIT(22)
4313
4314#define GEN9_CLKGATE_DIS_4 _MMIO(0x4653C)
4315#define BXT_GMBUS_GATING_DIS (1 << 14)
4316
4317#define GEN9_CLKGATE_DIS_5 _MMIO(0x46540)
4318#define DPCE_GATING_DIS REG_BIT(17)
4319
4320#define _CLKGATE_DIS_PSL_A 0x46520
4321#define _CLKGATE_DIS_PSL_B 0x46524
4322#define _CLKGATE_DIS_PSL_C 0x46528
4323#define DUPS1_GATING_DIS (1 << 15)
4324#define DUPS2_GATING_DIS (1 << 19)
4325#define DUPS3_GATING_DIS (1 << 23)
4326#define CURSOR_GATING_DIS REG_BIT(28)
4327#define DPF_GATING_DIS (1 << 10)
4328#define DPF_RAM_GATING_DIS (1 << 9)
4329#define DPFR_GATING_DIS (1 << 8)
4330
4331#define CLKGATE_DIS_PSL(pipe) \
4332 _MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_A, _CLKGATE_DIS_PSL_B)
4333
4334
4335
4336
4337
4338#define UNSLCGCTL9440 _MMIO(0x9440)
4339#define GAMTLBOACS_CLKGATE_DIS REG_BIT(28)
4340#define GAMTLBVDBOX5_CLKGATE_DIS REG_BIT(27)
4341#define GAMTLBVDBOX6_CLKGATE_DIS REG_BIT(26)
4342#define GAMTLBVDBOX3_CLKGATE_DIS REG_BIT(24)
4343#define GAMTLBVDBOX4_CLKGATE_DIS REG_BIT(23)
4344#define GAMTLBVDBOX7_CLKGATE_DIS REG_BIT(22)
4345#define GAMTLBVDBOX2_CLKGATE_DIS REG_BIT(21)
4346#define GAMTLBVDBOX0_CLKGATE_DIS REG_BIT(17)
4347#define GAMTLBKCR_CLKGATE_DIS REG_BIT(16)
4348#define GAMTLBGUC_CLKGATE_DIS REG_BIT(15)
4349#define GAMTLBBLT_CLKGATE_DIS REG_BIT(14)
4350#define GAMTLBVDBOX1_CLKGATE_DIS REG_BIT(6)
4351
4352#define UNSLCGCTL9444 _MMIO(0x9444)
4353#define GAMTLBGFXA0_CLKGATE_DIS REG_BIT(30)
4354#define GAMTLBGFXA1_CLKGATE_DIS REG_BIT(29)
4355#define GAMTLBCOMPA0_CLKGATE_DIS REG_BIT(28)
4356#define GAMTLBCOMPA1_CLKGATE_DIS REG_BIT(27)
4357#define GAMTLBCOMPB0_CLKGATE_DIS REG_BIT(26)
4358#define GAMTLBCOMPB1_CLKGATE_DIS REG_BIT(25)
4359#define GAMTLBCOMPC0_CLKGATE_DIS REG_BIT(24)
4360#define GAMTLBCOMPC1_CLKGATE_DIS REG_BIT(23)
4361#define GAMTLBCOMPD0_CLKGATE_DIS REG_BIT(22)
4362#define GAMTLBCOMPD1_CLKGATE_DIS REG_BIT(21)
4363#define GAMTLBMERT_CLKGATE_DIS REG_BIT(20)
4364#define GAMTLBVEBOX3_CLKGATE_DIS REG_BIT(19)
4365#define GAMTLBVEBOX2_CLKGATE_DIS REG_BIT(18)
4366#define GAMTLBVEBOX1_CLKGATE_DIS REG_BIT(17)
4367#define GAMTLBVEBOX0_CLKGATE_DIS REG_BIT(16)
4368#define LTCDD_CLKGATE_DIS REG_BIT(10)
4369
4370#define SLICE_UNIT_LEVEL_CLKGATE _MMIO(0x94d4)
4371#define SARBUNIT_CLKGATE_DIS (1 << 5)
4372#define RCCUNIT_CLKGATE_DIS (1 << 7)
4373#define MSCUNIT_CLKGATE_DIS (1 << 10)
4374#define NODEDSS_CLKGATE_DIS REG_BIT(12)
4375#define L3_CLKGATE_DIS REG_BIT(16)
4376#define L3_CR2X_CLKGATE_DIS REG_BIT(17)
4377
4378#define SUBSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9524)
4379#define DSS_ROUTER_CLKGATE_DIS REG_BIT(28)
4380#define GWUNIT_CLKGATE_DIS REG_BIT(16)
4381
4382#define SUBSLICE_UNIT_LEVEL_CLKGATE2 _MMIO(0x9528)
4383#define CPSSUNIT_CLKGATE_DIS REG_BIT(9)
4384
4385#define SSMCGCTL9530 _MMIO(0x9530)
4386#define RTFUNIT_CLKGATE_DIS REG_BIT(18)
4387
4388#define UNSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9434)
4389#define VFUNIT_CLKGATE_DIS REG_BIT(20)
4390#define TSGUNIT_CLKGATE_DIS REG_BIT(17)
4391#define CG3DDISCFEG_CLKGATE_DIS REG_BIT(17)
4392#define GAMEDIA_CLKGATE_DIS REG_BIT(11)
4393#define HSUNIT_CLKGATE_DIS REG_BIT(8)
4394#define VSUNIT_CLKGATE_DIS REG_BIT(3)
4395
4396#define UNSLICE_UNIT_LEVEL_CLKGATE2 _MMIO(0x94e4)
4397#define VSUNIT_CLKGATE_DIS_TGL REG_BIT(19)
4398#define PSDUNIT_CLKGATE_DIS REG_BIT(5)
4399
4400#define INF_UNIT_LEVEL_CLKGATE _MMIO(0x9560)
4401#define CGPSF_CLKGATE_DIS (1 << 3)
4402
4403
4404
4405
4406
4407
4408#define _PIPE_CRC_CTL_A 0x60050
4409#define PIPE_CRC_ENABLE REG_BIT(31)
4410
4411#define PIPE_CRC_SOURCE_MASK_SKL REG_GENMASK(30, 28)
4412#define PIPE_CRC_SOURCE_PLANE_1_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 0)
4413#define PIPE_CRC_SOURCE_PLANE_2_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 2)
4414#define PIPE_CRC_SOURCE_DMUX_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 4)
4415#define PIPE_CRC_SOURCE_PLANE_3_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 6)
4416#define PIPE_CRC_SOURCE_PLANE_4_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 7)
4417#define PIPE_CRC_SOURCE_PLANE_5_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 5)
4418#define PIPE_CRC_SOURCE_PLANE_6_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 3)
4419#define PIPE_CRC_SOURCE_PLANE_7_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 1)
4420
4421#define PIPE_CRC_SOURCE_MASK_IVB REG_GENMASK(30, 29)
4422#define PIPE_CRC_SOURCE_PRIMARY_IVB REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_IVB, 0)
4423#define PIPE_CRC_SOURCE_SPRITE_IVB REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_IVB, 1)
4424#define PIPE_CRC_SOURCE_PF_IVB REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_IVB, 2)
4425
4426#define PIPE_CRC_SOURCE_MASK_ILK REG_GENMASK(30, 28)
4427#define PIPE_CRC_SOURCE_PRIMARY_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 0)
4428#define PIPE_CRC_SOURCE_SPRITE_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 1)
4429#define PIPE_CRC_SOURCE_PIPE_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 2)
4430
4431#define PIPE_CRC_SOURCE_PORT_A_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 4)
4432#define PIPE_CRC_SOURCE_FDI_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 5)
4433
4434#define PIPE_CRC_SOURCE_MASK_VLV REG_GENMASK(30, 27)
4435#define PIPE_CRC_SOURCE_PIPE_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 0)
4436#define PIPE_CRC_SOURCE_HDMIB_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 1)
4437#define PIPE_CRC_SOURCE_HDMIC_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 2)
4438
4439#define PIPE_CRC_SOURCE_DP_D_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 3)
4440#define PIPE_CRC_SOURCE_DP_B_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 6)
4441#define PIPE_CRC_SOURCE_DP_C_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 7)
4442
4443#define PIPE_CRC_SOURCE_MASK_I9XX REG_GENMASK(30, 28)
4444#define PIPE_CRC_SOURCE_PIPE_I9XX REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 0)
4445#define PIPE_CRC_SOURCE_SDVOB_I9XX REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 1)
4446#define PIPE_CRC_SOURCE_SDVOC_I9XX REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 2)
4447
4448#define PIPE_CRC_SOURCE_DP_D_G4X REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 3)
4449#define PIPE_CRC_SOURCE_TV_PRE REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 4)
4450#define PIPE_CRC_SOURCE_TV_POST REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 5)
4451#define PIPE_CRC_SOURCE_DP_B_G4X REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 6)
4452#define PIPE_CRC_SOURCE_DP_C_G4X REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 7)
4453
4454#define PIPE_CRC_INCLUDE_BORDER_I8XX REG_BIT(30)
4455
4456#define _PIPE_CRC_RES_1_A_IVB 0x60064
4457#define _PIPE_CRC_RES_2_A_IVB 0x60068
4458#define _PIPE_CRC_RES_3_A_IVB 0x6006c
4459#define _PIPE_CRC_RES_4_A_IVB 0x60070
4460#define _PIPE_CRC_RES_5_A_IVB 0x60074
4461
4462#define _PIPE_CRC_RES_RED_A 0x60060
4463#define _PIPE_CRC_RES_GREEN_A 0x60064
4464#define _PIPE_CRC_RES_BLUE_A 0x60068
4465#define _PIPE_CRC_RES_RES1_A_I915 0x6006c
4466#define _PIPE_CRC_RES_RES2_A_G4X 0x60080
4467
4468
4469#define _PIPE_CRC_RES_1_B_IVB 0x61064
4470#define _PIPE_CRC_RES_2_B_IVB 0x61068
4471#define _PIPE_CRC_RES_3_B_IVB 0x6106c
4472#define _PIPE_CRC_RES_4_B_IVB 0x61070
4473#define _PIPE_CRC_RES_5_B_IVB 0x61074
4474
4475#define PIPE_CRC_CTL(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_CTL_A)
4476#define PIPE_CRC_RES_1_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_1_A_IVB)
4477#define PIPE_CRC_RES_2_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_2_A_IVB)
4478#define PIPE_CRC_RES_3_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_3_A_IVB)
4479#define PIPE_CRC_RES_4_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_4_A_IVB)
4480#define PIPE_CRC_RES_5_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_5_A_IVB)
4481
4482#define PIPE_CRC_RES_RED(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RED_A)
4483#define PIPE_CRC_RES_GREEN(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_GREEN_A)
4484#define PIPE_CRC_RES_BLUE(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_BLUE_A)
4485#define PIPE_CRC_RES_RES1_I915(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES1_A_I915)
4486#define PIPE_CRC_RES_RES2_G4X(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES2_A_G4X)
4487
4488
4489#define _HTOTAL_A 0x60000
4490#define _HBLANK_A 0x60004
4491#define _HSYNC_A 0x60008
4492#define _VTOTAL_A 0x6000c
4493#define _VBLANK_A 0x60010
4494#define _VSYNC_A 0x60014
4495#define _EXITLINE_A 0x60018
4496#define _PIPEASRC 0x6001c
4497#define _BCLRPAT_A 0x60020
4498#define _VSYNCSHIFT_A 0x60028
4499#define _PIPE_MULT_A 0x6002c
4500
4501
4502#define _HTOTAL_B 0x61000
4503#define _HBLANK_B 0x61004
4504#define _HSYNC_B 0x61008
4505#define _VTOTAL_B 0x6100c
4506#define _VBLANK_B 0x61010
4507#define _VSYNC_B 0x61014
4508#define _PIPEBSRC 0x6101c
4509#define _BCLRPAT_B 0x61020
4510#define _VSYNCSHIFT_B 0x61028
4511#define _PIPE_MULT_B 0x6102c
4512
4513
4514#define _HTOTAL_DSI0 0x6b000
4515#define _HSYNC_DSI0 0x6b008
4516#define _VTOTAL_DSI0 0x6b00c
4517#define _VSYNC_DSI0 0x6b014
4518#define _VSYNCSHIFT_DSI0 0x6b028
4519
4520
4521#define _HTOTAL_DSI1 0x6b800
4522#define _HSYNC_DSI1 0x6b808
4523#define _VTOTAL_DSI1 0x6b80c
4524#define _VSYNC_DSI1 0x6b814
4525#define _VSYNCSHIFT_DSI1 0x6b828
4526
4527#define TRANSCODER_A_OFFSET 0x60000
4528#define TRANSCODER_B_OFFSET 0x61000
4529#define TRANSCODER_C_OFFSET 0x62000
4530#define CHV_TRANSCODER_C_OFFSET 0x63000
4531#define TRANSCODER_D_OFFSET 0x63000
4532#define TRANSCODER_EDP_OFFSET 0x6f000
4533#define TRANSCODER_DSI0_OFFSET 0x6b000
4534#define TRANSCODER_DSI1_OFFSET 0x6b800
4535
4536#define HTOTAL(trans) _MMIO_TRANS2(trans, _HTOTAL_A)
4537#define HBLANK(trans) _MMIO_TRANS2(trans, _HBLANK_A)
4538#define HSYNC(trans) _MMIO_TRANS2(trans, _HSYNC_A)
4539#define VTOTAL(trans) _MMIO_TRANS2(trans, _VTOTAL_A)
4540#define VBLANK(trans) _MMIO_TRANS2(trans, _VBLANK_A)
4541#define VSYNC(trans) _MMIO_TRANS2(trans, _VSYNC_A)
4542#define BCLRPAT(trans) _MMIO_TRANS2(trans, _BCLRPAT_A)
4543#define VSYNCSHIFT(trans) _MMIO_TRANS2(trans, _VSYNCSHIFT_A)
4544#define PIPESRC(trans) _MMIO_TRANS2(trans, _PIPEASRC)
4545#define PIPE_MULT(trans) _MMIO_TRANS2(trans, _PIPE_MULT_A)
4546
4547#define EXITLINE(trans) _MMIO_TRANS2(trans, _EXITLINE_A)
4548#define EXITLINE_ENABLE REG_BIT(31)
4549#define EXITLINE_MASK REG_GENMASK(12, 0)
4550#define EXITLINE_SHIFT 0
4551
4552
4553#define _TRANS_VRR_CTL_A 0x60420
4554#define _TRANS_VRR_CTL_B 0x61420
4555#define _TRANS_VRR_CTL_C 0x62420
4556#define _TRANS_VRR_CTL_D 0x63420
4557#define TRANS_VRR_CTL(trans) _MMIO_TRANS2(trans, _TRANS_VRR_CTL_A)
4558#define VRR_CTL_VRR_ENABLE REG_BIT(31)
4559#define VRR_CTL_IGN_MAX_SHIFT REG_BIT(30)
4560#define VRR_CTL_FLIP_LINE_EN REG_BIT(29)
4561#define VRR_CTL_PIPELINE_FULL_MASK REG_GENMASK(10, 3)
4562#define VRR_CTL_PIPELINE_FULL(x) REG_FIELD_PREP(VRR_CTL_PIPELINE_FULL_MASK, (x))
4563#define VRR_CTL_PIPELINE_FULL_OVERRIDE REG_BIT(0)
4564#define XELPD_VRR_CTL_VRR_GUARDBAND_MASK REG_GENMASK(15, 0)
4565#define XELPD_VRR_CTL_VRR_GUARDBAND(x) REG_FIELD_PREP(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, (x))
4566
4567#define _TRANS_VRR_VMAX_A 0x60424
4568#define _TRANS_VRR_VMAX_B 0x61424
4569#define _TRANS_VRR_VMAX_C 0x62424
4570#define _TRANS_VRR_VMAX_D 0x63424
4571#define TRANS_VRR_VMAX(trans) _MMIO_TRANS2(trans, _TRANS_VRR_VMAX_A)
4572#define VRR_VMAX_MASK REG_GENMASK(19, 0)
4573
4574#define _TRANS_VRR_VMIN_A 0x60434
4575#define _TRANS_VRR_VMIN_B 0x61434
4576#define _TRANS_VRR_VMIN_C 0x62434
4577#define _TRANS_VRR_VMIN_D 0x63434
4578#define TRANS_VRR_VMIN(trans) _MMIO_TRANS2(trans, _TRANS_VRR_VMIN_A)
4579#define VRR_VMIN_MASK REG_GENMASK(15, 0)
4580
4581#define _TRANS_VRR_VMAXSHIFT_A 0x60428
4582#define _TRANS_VRR_VMAXSHIFT_B 0x61428
4583#define _TRANS_VRR_VMAXSHIFT_C 0x62428
4584#define _TRANS_VRR_VMAXSHIFT_D 0x63428
4585#define TRANS_VRR_VMAXSHIFT(trans) _MMIO_TRANS2(trans, \
4586 _TRANS_VRR_VMAXSHIFT_A)
4587#define VRR_VMAXSHIFT_DEC_MASK REG_GENMASK(29, 16)
4588#define VRR_VMAXSHIFT_DEC REG_BIT(16)
4589#define VRR_VMAXSHIFT_INC_MASK REG_GENMASK(12, 0)
4590
4591#define _TRANS_VRR_STATUS_A 0x6042C
4592#define _TRANS_VRR_STATUS_B 0x6142C
4593#define _TRANS_VRR_STATUS_C 0x6242C
4594#define _TRANS_VRR_STATUS_D 0x6342C
4595#define TRANS_VRR_STATUS(trans) _MMIO_TRANS2(trans, _TRANS_VRR_STATUS_A)
4596#define VRR_STATUS_VMAX_REACHED REG_BIT(31)
4597#define VRR_STATUS_NOFLIP_TILL_BNDR REG_BIT(30)
4598#define VRR_STATUS_FLIP_BEF_BNDR REG_BIT(29)
4599#define VRR_STATUS_NO_FLIP_FRAME REG_BIT(28)
4600#define VRR_STATUS_VRR_EN_LIVE REG_BIT(27)
4601#define VRR_STATUS_FLIPS_SERVICED REG_BIT(26)
4602#define VRR_STATUS_VBLANK_MASK REG_GENMASK(22, 20)
4603#define STATUS_FSM_IDLE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 0)
4604#define STATUS_FSM_WAIT_TILL_FDB REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 1)
4605#define STATUS_FSM_WAIT_TILL_FS REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 2)
4606#define STATUS_FSM_WAIT_TILL_FLIP REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 3)
4607#define STATUS_FSM_PIPELINE_FILL REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 4)
4608#define STATUS_FSM_ACTIVE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 5)
4609#define STATUS_FSM_LEGACY_VBLANK REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 6)
4610
4611#define _TRANS_VRR_VTOTAL_PREV_A 0x60480
4612#define _TRANS_VRR_VTOTAL_PREV_B 0x61480
4613#define _TRANS_VRR_VTOTAL_PREV_C 0x62480
4614#define _TRANS_VRR_VTOTAL_PREV_D 0x63480
4615#define TRANS_VRR_VTOTAL_PREV(trans) _MMIO_TRANS2(trans, \
4616 _TRANS_VRR_VTOTAL_PREV_A)
4617#define VRR_VTOTAL_FLIP_BEFR_BNDR REG_BIT(31)
4618#define VRR_VTOTAL_FLIP_AFTER_BNDR REG_BIT(30)
4619#define VRR_VTOTAL_FLIP_AFTER_DBLBUF REG_BIT(29)
4620#define VRR_VTOTAL_PREV_FRAME_MASK REG_GENMASK(19, 0)
4621
4622#define _TRANS_VRR_FLIPLINE_A 0x60438
4623#define _TRANS_VRR_FLIPLINE_B 0x61438
4624#define _TRANS_VRR_FLIPLINE_C 0x62438
4625#define _TRANS_VRR_FLIPLINE_D 0x63438
4626#define TRANS_VRR_FLIPLINE(trans) _MMIO_TRANS2(trans, \
4627 _TRANS_VRR_FLIPLINE_A)
4628#define VRR_FLIPLINE_MASK REG_GENMASK(19, 0)
4629
4630#define _TRANS_VRR_STATUS2_A 0x6043C
4631#define _TRANS_VRR_STATUS2_B 0x6143C
4632#define _TRANS_VRR_STATUS2_C 0x6243C
4633#define _TRANS_VRR_STATUS2_D 0x6343C
4634#define TRANS_VRR_STATUS2(trans) _MMIO_TRANS2(trans, _TRANS_VRR_STATUS2_A)
4635#define VRR_STATUS2_VERT_LN_CNT_MASK REG_GENMASK(19, 0)
4636
4637#define _TRANS_PUSH_A 0x60A70
4638#define _TRANS_PUSH_B 0x61A70
4639#define _TRANS_PUSH_C 0x62A70
4640#define _TRANS_PUSH_D 0x63A70
4641#define TRANS_PUSH(trans) _MMIO_TRANS2(trans, _TRANS_PUSH_A)
4642#define TRANS_PUSH_EN REG_BIT(31)
4643#define TRANS_PUSH_SEND REG_BIT(30)
4644
4645
4646
4647
4648
4649
4650
4651#define _SRD_CTL_A 0x60800
4652#define _SRD_CTL_EDP 0x6f800
4653#define EDP_PSR_CTL(tran) _MMIO(_TRANS2(tran, _SRD_CTL_A))
4654#define EDP_PSR_ENABLE (1 << 31)
4655#define BDW_PSR_SINGLE_FRAME (1 << 30)
4656#define EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK (1 << 29)
4657#define EDP_PSR_LINK_STANDBY (1 << 27)
4658#define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK (3 << 25)
4659#define EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES (0 << 25)
4660#define EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES (1 << 25)
4661#define EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES (2 << 25)
4662#define EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES (3 << 25)
4663#define EDP_PSR_MAX_SLEEP_TIME_SHIFT 20
4664#define EDP_PSR_SKIP_AUX_EXIT (1 << 12)
4665#define EDP_PSR_TP1_TP2_SEL (0 << 11)
4666#define EDP_PSR_TP1_TP3_SEL (1 << 11)
4667#define EDP_PSR_CRC_ENABLE (1 << 10)
4668#define EDP_PSR_TP2_TP3_TIME_500us (0 << 8)
4669#define EDP_PSR_TP2_TP3_TIME_100us (1 << 8)
4670#define EDP_PSR_TP2_TP3_TIME_2500us (2 << 8)
4671#define EDP_PSR_TP2_TP3_TIME_0us (3 << 8)
4672#define EDP_PSR_TP4_TIME_0US (3 << 6)
4673#define EDP_PSR_TP1_TIME_500us (0 << 4)
4674#define EDP_PSR_TP1_TIME_100us (1 << 4)
4675#define EDP_PSR_TP1_TIME_2500us (2 << 4)
4676#define EDP_PSR_TP1_TIME_0us (3 << 4)
4677#define EDP_PSR_IDLE_FRAME_SHIFT 0
4678
4679
4680
4681
4682
4683
4684#define EDP_PSR_IMR _MMIO(0x64834)
4685#define EDP_PSR_IIR _MMIO(0x64838)
4686#define _PSR_IMR_A 0x60814
4687#define _PSR_IIR_A 0x60818
4688#define TRANS_PSR_IMR(tran) _MMIO_TRANS2(tran, _PSR_IMR_A)
4689#define TRANS_PSR_IIR(tran) _MMIO_TRANS2(tran, _PSR_IIR_A)
4690#define _EDP_PSR_TRANS_SHIFT(trans) ((trans) == TRANSCODER_EDP ? \
4691 0 : ((trans) - TRANSCODER_A + 1) * 8)
4692#define EDP_PSR_TRANS_MASK(trans) (0x7 << _EDP_PSR_TRANS_SHIFT(trans))
4693#define EDP_PSR_ERROR(trans) (0x4 << _EDP_PSR_TRANS_SHIFT(trans))
4694#define EDP_PSR_POST_EXIT(trans) (0x2 << _EDP_PSR_TRANS_SHIFT(trans))
4695#define EDP_PSR_PRE_ENTRY(trans) (0x1 << _EDP_PSR_TRANS_SHIFT(trans))
4696
4697#define _SRD_AUX_DATA_A 0x60814
4698#define _SRD_AUX_DATA_EDP 0x6f814
4699#define EDP_PSR_AUX_DATA(tran, i) _MMIO(_TRANS2(tran, _SRD_AUX_DATA_A) + (i) + 4)
4700
4701#define _SRD_STATUS_A 0x60840
4702#define _SRD_STATUS_EDP 0x6f840
4703#define EDP_PSR_STATUS(tran) _MMIO(_TRANS2(tran, _SRD_STATUS_A))
4704#define EDP_PSR_STATUS_STATE_MASK (7 << 29)
4705#define EDP_PSR_STATUS_STATE_SHIFT 29
4706#define EDP_PSR_STATUS_STATE_IDLE (0 << 29)
4707#define EDP_PSR_STATUS_STATE_SRDONACK (1 << 29)
4708#define EDP_PSR_STATUS_STATE_SRDENT (2 << 29)
4709#define EDP_PSR_STATUS_STATE_BUFOFF (3 << 29)
4710#define EDP_PSR_STATUS_STATE_BUFON (4 << 29)
4711#define EDP_PSR_STATUS_STATE_AUXACK (5 << 29)
4712#define EDP_PSR_STATUS_STATE_SRDOFFACK (6 << 29)
4713#define EDP_PSR_STATUS_LINK_MASK (3 << 26)
4714#define EDP_PSR_STATUS_LINK_FULL_OFF (0 << 26)
4715#define EDP_PSR_STATUS_LINK_FULL_ON (1 << 26)
4716#define EDP_PSR_STATUS_LINK_STANDBY (2 << 26)
4717#define EDP_PSR_STATUS_MAX_SLEEP_TIMER_SHIFT 20
4718#define EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK 0x1f
4719#define EDP_PSR_STATUS_COUNT_SHIFT 16
4720#define EDP_PSR_STATUS_COUNT_MASK 0xf
4721#define EDP_PSR_STATUS_AUX_ERROR (1 << 15)
4722#define EDP_PSR_STATUS_AUX_SENDING (1 << 12)
4723#define EDP_PSR_STATUS_SENDING_IDLE (1 << 9)
4724#define EDP_PSR_STATUS_SENDING_TP2_TP3 (1 << 8)
4725#define EDP_PSR_STATUS_SENDING_TP1 (1 << 4)
4726#define EDP_PSR_STATUS_IDLE_MASK 0xf
4727
4728#define _SRD_PERF_CNT_A 0x60844
4729#define _SRD_PERF_CNT_EDP 0x6f844
4730#define EDP_PSR_PERF_CNT(tran) _MMIO(_TRANS2(tran, _SRD_PERF_CNT_A))
4731#define EDP_PSR_PERF_CNT_MASK 0xffffff
4732
4733
4734#define _SRD_DEBUG_A 0x60860
4735#define _SRD_DEBUG_EDP 0x6f860
4736#define EDP_PSR_DEBUG(tran) _MMIO(_TRANS2(tran, _SRD_DEBUG_A))
4737#define EDP_PSR_DEBUG_MASK_MAX_SLEEP (1 << 28)
4738#define EDP_PSR_DEBUG_MASK_LPSP (1 << 27)
4739#define EDP_PSR_DEBUG_MASK_MEMUP (1 << 26)
4740#define EDP_PSR_DEBUG_MASK_HPD (1 << 25)
4741#define EDP_PSR_DEBUG_MASK_DISP_REG_WRITE (1 << 16)
4742#define EDP_PSR_DEBUG_EXIT_ON_PIXEL_UNDERRUN (1 << 15)
4743
4744#define _PSR2_CTL_A 0x60900
4745#define _PSR2_CTL_EDP 0x6f900
4746#define EDP_PSR2_CTL(tran) _MMIO_TRANS2(tran, _PSR2_CTL_A)
4747#define EDP_PSR2_ENABLE (1 << 31)
4748#define EDP_SU_TRACK_ENABLE (1 << 30)
4749#define TGL_EDP_PSR2_BLOCK_COUNT_NUM_2 (0 << 28)
4750#define TGL_EDP_PSR2_BLOCK_COUNT_NUM_3 (1 << 28)
4751#define EDP_Y_COORDINATE_ENABLE REG_BIT(25)
4752#define EDP_PSR2_SU_SDP_SCANLINE REG_BIT(25)
4753#define EDP_MAX_SU_DISABLE_TIME(t) ((t) << 20)
4754#define EDP_MAX_SU_DISABLE_TIME_MASK (0x1f << 20)
4755#define EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES 8
4756#define EDP_PSR2_IO_BUFFER_WAKE(lines) ((EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES - (lines)) << 13)
4757#define EDP_PSR2_IO_BUFFER_WAKE_MASK (3 << 13)
4758#define TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES 5
4759#define TGL_EDP_PSR2_IO_BUFFER_WAKE_SHIFT 13
4760#define TGL_EDP_PSR2_IO_BUFFER_WAKE(lines) (((lines) - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES) << TGL_EDP_PSR2_IO_BUFFER_WAKE_SHIFT)
4761#define TGL_EDP_PSR2_IO_BUFFER_WAKE_MASK (7 << 13)
4762#define EDP_PSR2_FAST_WAKE_MAX_LINES 8
4763#define EDP_PSR2_FAST_WAKE(lines) ((EDP_PSR2_FAST_WAKE_MAX_LINES - (lines)) << 11)
4764#define EDP_PSR2_FAST_WAKE_MASK (3 << 11)
4765#define TGL_EDP_PSR2_FAST_WAKE_MIN_LINES 5
4766#define TGL_EDP_PSR2_FAST_WAKE_MIN_SHIFT 10
4767#define TGL_EDP_PSR2_FAST_WAKE(lines) (((lines) - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES) << TGL_EDP_PSR2_FAST_WAKE_MIN_SHIFT)
4768#define TGL_EDP_PSR2_FAST_WAKE_MASK (7 << 10)
4769#define EDP_PSR2_TP2_TIME_500us (0 << 8)
4770#define EDP_PSR2_TP2_TIME_100us (1 << 8)
4771#define EDP_PSR2_TP2_TIME_2500us (2 << 8)
4772#define EDP_PSR2_TP2_TIME_50us (3 << 8)
4773#define EDP_PSR2_TP2_TIME_MASK (3 << 8)
4774#define EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
4775#define EDP_PSR2_FRAME_BEFORE_SU_MASK (0xf << 4)
4776#define EDP_PSR2_FRAME_BEFORE_SU(a) ((a) << 4)
4777#define EDP_PSR2_IDLE_FRAME_MASK 0xf
4778#define EDP_PSR2_IDLE_FRAME_SHIFT 0
4779
4780#define _PSR_EVENT_TRANS_A 0x60848
4781#define _PSR_EVENT_TRANS_B 0x61848
4782#define _PSR_EVENT_TRANS_C 0x62848
4783#define _PSR_EVENT_TRANS_D 0x63848
4784#define _PSR_EVENT_TRANS_EDP 0x6f848
4785#define PSR_EVENT(tran) _MMIO_TRANS2(tran, _PSR_EVENT_TRANS_A)
4786#define PSR_EVENT_PSR2_WD_TIMER_EXPIRE (1 << 17)
4787#define PSR_EVENT_PSR2_DISABLED (1 << 16)
4788#define PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN (1 << 15)
4789#define PSR_EVENT_SU_CRC_FIFO_UNDERRUN (1 << 14)
4790#define PSR_EVENT_GRAPHICS_RESET (1 << 12)
4791#define PSR_EVENT_PCH_INTERRUPT (1 << 11)
4792#define PSR_EVENT_MEMORY_UP (1 << 10)
4793#define PSR_EVENT_FRONT_BUFFER_MODIFY (1 << 9)
4794#define PSR_EVENT_WD_TIMER_EXPIRE (1 << 8)
4795#define PSR_EVENT_PIPE_REGISTERS_UPDATE (1 << 6)
4796#define PSR_EVENT_REGISTER_UPDATE (1 << 5)
4797#define PSR_EVENT_HDCP_ENABLE (1 << 4)
4798#define PSR_EVENT_KVMR_SESSION_ENABLE (1 << 3)
4799#define PSR_EVENT_VBI_ENABLE (1 << 2)
4800#define PSR_EVENT_LPSP_MODE_EXIT (1 << 1)
4801#define PSR_EVENT_PSR_DISABLE (1 << 0)
4802
4803#define _PSR2_STATUS_A 0x60940
4804#define _PSR2_STATUS_EDP 0x6f940
4805#define EDP_PSR2_STATUS(tran) _MMIO_TRANS2(tran, _PSR2_STATUS_A)
4806#define EDP_PSR2_STATUS_STATE_MASK REG_GENMASK(31, 28)
4807#define EDP_PSR2_STATUS_STATE_DEEP_SLEEP REG_FIELD_PREP(EDP_PSR2_STATUS_STATE_MASK, 0x8)
4808
4809#define _PSR2_SU_STATUS_A 0x60914
4810#define _PSR2_SU_STATUS_EDP 0x6f914
4811#define _PSR2_SU_STATUS(tran, index) _MMIO(_TRANS2(tran, _PSR2_SU_STATUS_A) + (index) * 4)
4812#define PSR2_SU_STATUS(tran, frame) (_PSR2_SU_STATUS(tran, (frame) / 3))
4813#define PSR2_SU_STATUS_SHIFT(frame) (((frame) % 3) * 10)
4814#define PSR2_SU_STATUS_MASK(frame) (0x3ff << PSR2_SU_STATUS_SHIFT(frame))
4815#define PSR2_SU_STATUS_FRAMES 8
4816
4817#define _PSR2_MAN_TRK_CTL_A 0x60910
4818#define _PSR2_MAN_TRK_CTL_EDP 0x6f910
4819#define PSR2_MAN_TRK_CTL(tran) _MMIO_TRANS2(tran, _PSR2_MAN_TRK_CTL_A)
4820#define PSR2_MAN_TRK_CTL_ENABLE REG_BIT(31)
4821#define PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK REG_GENMASK(30, 21)
4822#define PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val) REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val)
4823#define PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK REG_GENMASK(20, 11)
4824#define PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val) REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK, val)
4825#define PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME REG_BIT(3)
4826#define PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME REG_BIT(2)
4827#define PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE REG_BIT(1)
4828#define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK REG_GENMASK(28, 16)
4829#define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val) REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val)
4830#define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK REG_GENMASK(12, 0)
4831#define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val) REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK, val)
4832#define ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE REG_BIT(31)
4833#define ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME REG_BIT(14)
4834#define ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME REG_BIT(13)
4835
4836
4837#define DSCA_RC_RANGE_PARAMETERS_0 _MMIO(0x6B240)
4838#define DSCA_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6B240 + 4)
4839#define DSCC_RC_RANGE_PARAMETERS_0 _MMIO(0x6BA40)
4840#define DSCC_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6BA40 + 4)
4841#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB (0x78208)
4842#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB (0x78208 + 4)
4843#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB (0x78308)
4844#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB (0x78308 + 4)
4845#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC (0x78408)
4846#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC (0x78408 + 4)
4847#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC (0x78508)
4848#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC (0x78508 + 4)
4849#define ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
4850 _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB, \
4851 _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC)
4852#define ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
4853 _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB, \
4854 _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC)
4855#define ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
4856 _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB, \
4857 _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC)
4858#define ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
4859 _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB, \
4860 _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC)
4861#define RC_BPG_OFFSET_SHIFT 10
4862#define RC_MAX_QP_SHIFT 5
4863#define RC_MIN_QP_SHIFT 0
4864
4865#define DSCA_RC_RANGE_PARAMETERS_1 _MMIO(0x6B248)
4866#define DSCA_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6B248 + 4)
4867#define DSCC_RC_RANGE_PARAMETERS_1 _MMIO(0x6BA48)
4868#define DSCC_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6BA48 + 4)
4869#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB (0x78210)
4870#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB (0x78210 + 4)
4871#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB (0x78310)
4872#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB (0x78310 + 4)
4873#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC (0x78410)
4874#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC (0x78410 + 4)
4875#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC (0x78510)
4876#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC (0x78510 + 4)
4877#define ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
4878 _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB, \
4879 _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC)
4880#define ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
4881 _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB, \
4882 _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC)
4883#define ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
4884 _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB, \
4885 _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC)
4886#define ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
4887 _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB, \
4888 _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC)
4889
4890#define DSCA_RC_RANGE_PARAMETERS_2 _MMIO(0x6B250)
4891#define DSCA_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6B250 + 4)
4892#define DSCC_RC_RANGE_PARAMETERS_2 _MMIO(0x6BA50)
4893#define DSCC_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6BA50 + 4)
4894#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB (0x78218)
4895#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB (0x78218 + 4)
4896#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB (0x78318)
4897#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB (0x78318 + 4)
4898#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC (0x78418)
4899#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC (0x78418 + 4)
4900#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC (0x78518)
4901#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC (0x78518 + 4)
4902#define ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
4903 _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB, \
4904 _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC)
4905#define ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
4906 _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB, \
4907 _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC)
4908#define ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
4909 _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB, \
4910 _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC)
4911#define ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
4912 _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB, \
4913 _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC)
4914
4915#define DSCA_RC_RANGE_PARAMETERS_3 _MMIO(0x6B258)
4916#define DSCA_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6B258 + 4)
4917#define DSCC_RC_RANGE_PARAMETERS_3 _MMIO(0x6BA58)
4918#define DSCC_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6BA58 + 4)
4919#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB (0x78220)
4920#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB (0x78220 + 4)
4921#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB (0x78320)
4922#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB (0x78320 + 4)
4923#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC (0x78420)
4924#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC (0x78420 + 4)
4925#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC (0x78520)
4926#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC (0x78520 + 4)
4927#define ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
4928 _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB, \
4929 _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC)
4930#define ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
4931 _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB, \
4932 _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC)
4933#define ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
4934 _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB, \
4935 _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC)
4936#define ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
4937 _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB, \
4938 _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC)
4939
4940
4941#define ADPA _MMIO(0x61100)
4942#define PCH_ADPA _MMIO(0xe1100)
4943#define VLV_ADPA _MMIO(VLV_DISPLAY_BASE + 0x61100)
4944
4945#define ADPA_DAC_ENABLE (1 << 31)
4946#define ADPA_DAC_DISABLE 0
4947#define ADPA_PIPE_SEL_SHIFT 30
4948#define ADPA_PIPE_SEL_MASK (1 << 30)
4949#define ADPA_PIPE_SEL(pipe) ((pipe) << 30)
4950#define ADPA_PIPE_SEL_SHIFT_CPT 29
4951#define ADPA_PIPE_SEL_MASK_CPT (3 << 29)
4952#define ADPA_PIPE_SEL_CPT(pipe) ((pipe) << 29)
4953#define ADPA_CRT_HOTPLUG_MASK 0x03ff0000
4954#define ADPA_CRT_HOTPLUG_MONITOR_NONE (0 << 24)
4955#define ADPA_CRT_HOTPLUG_MONITOR_MASK (3 << 24)
4956#define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3 << 24)
4957#define ADPA_CRT_HOTPLUG_MONITOR_MONO (2 << 24)
4958#define ADPA_CRT_HOTPLUG_ENABLE (1 << 23)
4959#define ADPA_CRT_HOTPLUG_PERIOD_64 (0 << 22)
4960#define ADPA_CRT_HOTPLUG_PERIOD_128 (1 << 22)
4961#define ADPA_CRT_HOTPLUG_WARMUP_5MS (0 << 21)
4962#define ADPA_CRT_HOTPLUG_WARMUP_10MS (1 << 21)
4963#define ADPA_CRT_HOTPLUG_SAMPLE_2S (0 << 20)
4964#define ADPA_CRT_HOTPLUG_SAMPLE_4S (1 << 20)
4965#define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0 << 18)
4966#define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1 << 18)
4967#define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2 << 18)
4968#define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3 << 18)
4969#define ADPA_CRT_HOTPLUG_VOLREF_325MV (0 << 17)
4970#define ADPA_CRT_HOTPLUG_VOLREF_475MV (1 << 17)
4971#define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1 << 16)
4972#define ADPA_USE_VGA_HVPOLARITY (1 << 15)
4973#define ADPA_SETS_HVPOLARITY 0
4974#define ADPA_VSYNC_CNTL_DISABLE (1 << 10)
4975#define ADPA_VSYNC_CNTL_ENABLE 0
4976#define ADPA_HSYNC_CNTL_DISABLE (1 << 11)
4977#define ADPA_HSYNC_CNTL_ENABLE 0
4978#define ADPA_VSYNC_ACTIVE_HIGH (1 << 4)
4979#define ADPA_VSYNC_ACTIVE_LOW 0
4980#define ADPA_HSYNC_ACTIVE_HIGH (1 << 3)
4981#define ADPA_HSYNC_ACTIVE_LOW 0
4982#define ADPA_DPMS_MASK (~(3 << 10))
4983#define ADPA_DPMS_ON (0 << 10)
4984#define ADPA_DPMS_SUSPEND (1 << 10)
4985#define ADPA_DPMS_STANDBY (2 << 10)
4986#define ADPA_DPMS_OFF (3 << 10)
4987
4988
4989
4990#define PORT_HOTPLUG_EN _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61110)
4991#define PORTB_HOTPLUG_INT_EN (1 << 29)
4992#define PORTC_HOTPLUG_INT_EN (1 << 28)
4993#define PORTD_HOTPLUG_INT_EN (1 << 27)
4994#define SDVOB_HOTPLUG_INT_EN (1 << 26)
4995#define SDVOC_HOTPLUG_INT_EN (1 << 25)
4996#define TV_HOTPLUG_INT_EN (1 << 18)
4997#define CRT_HOTPLUG_INT_EN (1 << 9)
4998#define HOTPLUG_INT_EN_MASK (PORTB_HOTPLUG_INT_EN | \
4999 PORTC_HOTPLUG_INT_EN | \
5000 PORTD_HOTPLUG_INT_EN | \
5001 SDVOC_HOTPLUG_INT_EN | \
5002 SDVOB_HOTPLUG_INT_EN | \
5003 CRT_HOTPLUG_INT_EN)
5004#define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
5005#define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8)
5006
5007#define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8)
5008#define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7)
5009#define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7)
5010#define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5)
5011#define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5)
5012#define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5)
5013#define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5)
5014#define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5)
5015#define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4)
5016#define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4)
5017#define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2)
5018#define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)
5019
5020#define PORT_HOTPLUG_STAT _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61114)
5021
5022
5023
5024
5025
5026
5027
5028
5029#define PORTD_HOTPLUG_LIVE_STATUS_GM45 (1 << 29)
5030#define PORTC_HOTPLUG_LIVE_STATUS_GM45 (1 << 28)
5031#define PORTB_HOTPLUG_LIVE_STATUS_GM45 (1 << 27)
5032
5033#define PORTD_HOTPLUG_LIVE_STATUS_G4X (1 << 27)
5034#define PORTC_HOTPLUG_LIVE_STATUS_G4X (1 << 28)
5035#define PORTB_HOTPLUG_LIVE_STATUS_G4X (1 << 29)
5036#define PORTD_HOTPLUG_INT_STATUS (3 << 21)
5037#define PORTD_HOTPLUG_INT_LONG_PULSE (2 << 21)
5038#define PORTD_HOTPLUG_INT_SHORT_PULSE (1 << 21)
5039#define PORTC_HOTPLUG_INT_STATUS (3 << 19)
5040#define PORTC_HOTPLUG_INT_LONG_PULSE (2 << 19)
5041#define PORTC_HOTPLUG_INT_SHORT_PULSE (1 << 19)
5042#define PORTB_HOTPLUG_INT_STATUS (3 << 17)
5043#define PORTB_HOTPLUG_INT_LONG_PULSE (2 << 17)
5044#define PORTB_HOTPLUG_INT_SHORT_PLUSE (1 << 17)
5045
5046#define CRT_HOTPLUG_INT_STATUS (1 << 11)
5047#define TV_HOTPLUG_INT_STATUS (1 << 10)
5048#define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
5049#define CRT_HOTPLUG_MONITOR_COLOR (3 << 8)
5050#define CRT_HOTPLUG_MONITOR_MONO (2 << 8)
5051#define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
5052#define DP_AUX_CHANNEL_D_INT_STATUS_G4X (1 << 6)
5053#define DP_AUX_CHANNEL_C_INT_STATUS_G4X (1 << 5)
5054#define DP_AUX_CHANNEL_B_INT_STATUS_G4X (1 << 4)
5055#define DP_AUX_CHANNEL_MASK_INT_STATUS_G4X (7 << 4)
5056
5057
5058#define SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3)
5059#define SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2)
5060
5061
5062
5063
5064
5065
5066#define SDVOC_HOTPLUG_INT_STATUS_I965 (3 << 4)
5067#define SDVOB_HOTPLUG_INT_STATUS_I965 (3 << 2)
5068#define SDVOC_HOTPLUG_INT_STATUS_I915 (1 << 7)
5069#define SDVOB_HOTPLUG_INT_STATUS_I915 (1 << 6)
5070#define HOTPLUG_INT_STATUS_G4X (CRT_HOTPLUG_INT_STATUS | \
5071 SDVOB_HOTPLUG_INT_STATUS_G4X | \
5072 SDVOC_HOTPLUG_INT_STATUS_G4X | \
5073 PORTB_HOTPLUG_INT_STATUS | \
5074 PORTC_HOTPLUG_INT_STATUS | \
5075 PORTD_HOTPLUG_INT_STATUS)
5076
5077#define HOTPLUG_INT_STATUS_I915 (CRT_HOTPLUG_INT_STATUS | \
5078 SDVOB_HOTPLUG_INT_STATUS_I915 | \
5079 SDVOC_HOTPLUG_INT_STATUS_I915 | \
5080 PORTB_HOTPLUG_INT_STATUS | \
5081 PORTC_HOTPLUG_INT_STATUS | \
5082 PORTD_HOTPLUG_INT_STATUS)
5083
5084
5085
5086#define _GEN3_SDVOB 0x61140
5087#define _GEN3_SDVOC 0x61160
5088#define GEN3_SDVOB _MMIO(_GEN3_SDVOB)
5089#define GEN3_SDVOC _MMIO(_GEN3_SDVOC)
5090#define GEN4_HDMIB GEN3_SDVOB
5091#define GEN4_HDMIC GEN3_SDVOC
5092#define VLV_HDMIB _MMIO(VLV_DISPLAY_BASE + 0x61140)
5093#define VLV_HDMIC _MMIO(VLV_DISPLAY_BASE + 0x61160)
5094#define CHV_HDMID _MMIO(VLV_DISPLAY_BASE + 0x6116C)
5095#define PCH_SDVOB _MMIO(0xe1140)
5096#define PCH_HDMIB PCH_SDVOB
5097#define PCH_HDMIC _MMIO(0xe1150)
5098#define PCH_HDMID _MMIO(0xe1160)
5099
5100#define PORT_DFT_I9XX _MMIO(0x61150)
5101#define DC_BALANCE_RESET (1 << 25)
5102#define PORT_DFT2_G4X _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61154)
5103#define DC_BALANCE_RESET_VLV (1 << 31)
5104#define PIPE_SCRAMBLE_RESET_MASK ((1 << 14) | (0x3 << 0))
5105#define PIPE_C_SCRAMBLE_RESET REG_BIT(14)
5106#define PIPE_B_SCRAMBLE_RESET REG_BIT(1)
5107#define PIPE_A_SCRAMBLE_RESET REG_BIT(0)
5108
5109
5110#define SDVO_ENABLE (1 << 31)
5111#define SDVO_PIPE_SEL_SHIFT 30
5112#define SDVO_PIPE_SEL_MASK (1 << 30)
5113#define SDVO_PIPE_SEL(pipe) ((pipe) << 30)
5114#define SDVO_STALL_SELECT (1 << 29)
5115#define SDVO_INTERRUPT_ENABLE (1 << 26)
5116
5117
5118
5119
5120
5121#define SDVO_PORT_MULTIPLY_MASK (7 << 23)
5122#define SDVO_PORT_MULTIPLY_SHIFT 23
5123#define SDVO_PHASE_SELECT_MASK (15 << 19)
5124#define SDVO_PHASE_SELECT_DEFAULT (6 << 19)
5125#define SDVO_CLOCK_OUTPUT_INVERT (1 << 18)
5126#define SDVOC_GANG_MODE (1 << 16)
5127#define SDVO_BORDER_ENABLE (1 << 7)
5128#define SDVOB_PCIE_CONCURRENCY (1 << 3)
5129#define SDVO_DETECTED (1 << 2)
5130
5131#define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | \
5132 SDVO_INTERRUPT_ENABLE)
5133#define SDVOC_PRESERVE_MASK ((1 << 17) | SDVO_INTERRUPT_ENABLE)
5134
5135
5136#define SDVO_COLOR_FORMAT_8bpc (0 << 26)
5137#define SDVO_COLOR_FORMAT_MASK (7 << 26)
5138#define SDVO_ENCODING_SDVO (0 << 10)
5139#define SDVO_ENCODING_HDMI (2 << 10)
5140#define HDMI_MODE_SELECT_HDMI (1 << 9)
5141#define HDMI_MODE_SELECT_DVI (0 << 9)
5142#define HDMI_COLOR_RANGE_16_235 (1 << 8)
5143#define HDMI_AUDIO_ENABLE (1 << 6)
5144
5145#define SDVO_VSYNC_ACTIVE_HIGH (1 << 4)
5146#define SDVO_HSYNC_ACTIVE_HIGH (1 << 3)
5147
5148
5149#define HDMI_COLOR_FORMAT_12bpc (3 << 26)
5150#define SDVOB_HOTPLUG_ENABLE (1 << 23)
5151
5152
5153#define SDVO_PIPE_SEL_SHIFT_CPT 29
5154#define SDVO_PIPE_SEL_MASK_CPT (3 << 29)
5155#define SDVO_PIPE_SEL_CPT(pipe) ((pipe) << 29)
5156
5157
5158#define SDVO_PIPE_SEL_SHIFT_CHV 24
5159#define SDVO_PIPE_SEL_MASK_CHV (3 << 24)
5160#define SDVO_PIPE_SEL_CHV(pipe) ((pipe) << 24)
5161
5162
5163
5164#define _DVOA 0x61120
5165#define DVOA _MMIO(_DVOA)
5166#define _DVOB 0x61140
5167#define DVOB _MMIO(_DVOB)
5168#define _DVOC 0x61160
5169#define DVOC _MMIO(_DVOC)
5170#define DVO_ENABLE (1 << 31)
5171#define DVO_PIPE_SEL_SHIFT 30
5172#define DVO_PIPE_SEL_MASK (1 << 30)
5173#define DVO_PIPE_SEL(pipe) ((pipe) << 30)
5174#define DVO_PIPE_STALL_UNUSED (0 << 28)
5175#define DVO_PIPE_STALL (1 << 28)
5176#define DVO_PIPE_STALL_TV (2 << 28)
5177#define DVO_PIPE_STALL_MASK (3 << 28)
5178#define DVO_USE_VGA_SYNC (1 << 15)
5179#define DVO_DATA_ORDER_I740 (0 << 14)
5180#define DVO_DATA_ORDER_FP (1 << 14)
5181#define DVO_VSYNC_DISABLE (1 << 11)
5182#define DVO_HSYNC_DISABLE (1 << 10)
5183#define DVO_VSYNC_TRISTATE (1 << 9)
5184#define DVO_HSYNC_TRISTATE (1 << 8)
5185#define DVO_BORDER_ENABLE (1 << 7)
5186#define DVO_DATA_ORDER_GBRG (1 << 6)
5187#define DVO_DATA_ORDER_RGGB (0 << 6)
5188#define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6)
5189#define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6)
5190#define DVO_VSYNC_ACTIVE_HIGH (1 << 4)
5191#define DVO_HSYNC_ACTIVE_HIGH (1 << 3)
5192#define DVO_BLANK_ACTIVE_HIGH (1 << 2)
5193#define DVO_OUTPUT_CSTATE_PIXELS (1 << 1)
5194#define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0)
5195#define DVO_PRESERVE_MASK (0x7 << 24)
5196#define DVOA_SRCDIM _MMIO(0x61124)
5197#define DVOB_SRCDIM _MMIO(0x61144)
5198#define DVOC_SRCDIM _MMIO(0x61164)
5199#define DVO_SRCDIM_HORIZONTAL_SHIFT 12
5200#define DVO_SRCDIM_VERTICAL_SHIFT 0
5201
5202
5203#define LVDS _MMIO(0x61180)
5204
5205
5206
5207
5208#define LVDS_PORT_EN (1 << 31)
5209
5210#define LVDS_PIPE_SEL_SHIFT 30
5211#define LVDS_PIPE_SEL_MASK (1 << 30)
5212#define LVDS_PIPE_SEL(pipe) ((pipe) << 30)
5213#define LVDS_PIPE_SEL_SHIFT_CPT 29
5214#define LVDS_PIPE_SEL_MASK_CPT (3 << 29)
5215#define LVDS_PIPE_SEL_CPT(pipe) ((pipe) << 29)
5216
5217#define LVDS_ENABLE_DITHER (1 << 25)
5218
5219#define LVDS_VSYNC_POLARITY (1 << 21)
5220#define LVDS_HSYNC_POLARITY (1 << 20)
5221
5222
5223#define LVDS_BORDER_ENABLE (1 << 15)
5224
5225
5226
5227
5228#define LVDS_A0A2_CLKA_POWER_MASK (3 << 8)
5229#define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8)
5230#define LVDS_A0A2_CLKA_POWER_UP (3 << 8)
5231
5232
5233
5234
5235
5236#define LVDS_A3_POWER_MASK (3 << 6)
5237#define LVDS_A3_POWER_DOWN (0 << 6)
5238#define LVDS_A3_POWER_UP (3 << 6)
5239
5240
5241
5242
5243#define LVDS_CLKB_POWER_MASK (3 << 4)
5244#define LVDS_CLKB_POWER_DOWN (0 << 4)
5245#define LVDS_CLKB_POWER_UP (3 << 4)
5246
5247
5248
5249
5250
5251#define LVDS_B0B3_POWER_MASK (3 << 2)
5252#define LVDS_B0B3_POWER_DOWN (0 << 2)
5253#define LVDS_B0B3_POWER_UP (3 << 2)
5254
5255
5256#define VIDEO_DIP_DATA _MMIO(0x61178)
5257
5258
5259
5260#define VIDEO_DIP_DATA_SIZE 32
5261#define VIDEO_DIP_GMP_DATA_SIZE 36
5262#define VIDEO_DIP_VSC_DATA_SIZE 36
5263#define VIDEO_DIP_PPS_DATA_SIZE 132
5264#define VIDEO_DIP_CTL _MMIO(0x61170)
5265
5266#define VIDEO_DIP_ENABLE (1 << 31)
5267#define VIDEO_DIP_PORT(port) ((port) << 29)
5268#define VIDEO_DIP_PORT_MASK (3 << 29)
5269#define VIDEO_DIP_ENABLE_GCP (1 << 25)
5270#define VIDEO_DIP_ENABLE_AVI (1 << 21)
5271#define VIDEO_DIP_ENABLE_VENDOR (2 << 21)
5272#define VIDEO_DIP_ENABLE_GAMUT (4 << 21)
5273#define VIDEO_DIP_ENABLE_SPD (8 << 21)
5274#define VIDEO_DIP_SELECT_AVI (0 << 19)
5275#define VIDEO_DIP_SELECT_VENDOR (1 << 19)
5276#define VIDEO_DIP_SELECT_GAMUT (2 << 19)
5277#define VIDEO_DIP_SELECT_SPD (3 << 19)
5278#define VIDEO_DIP_SELECT_MASK (3 << 19)
5279#define VIDEO_DIP_FREQ_ONCE (0 << 16)
5280#define VIDEO_DIP_FREQ_VSYNC (1 << 16)
5281#define VIDEO_DIP_FREQ_2VSYNC (2 << 16)
5282#define VIDEO_DIP_FREQ_MASK (3 << 16)
5283
5284#define VIDEO_DIP_ENABLE_DRM_GLK (1 << 28)
5285#define PSR_VSC_BIT_7_SET (1 << 27)
5286#define VSC_SELECT_MASK (0x3 << 25)
5287#define VSC_SELECT_SHIFT 25
5288#define VSC_DIP_HW_HEA_DATA (0 << 25)
5289#define VSC_DIP_HW_HEA_SW_DATA (1 << 25)
5290#define VSC_DIP_HW_DATA_SW_HEA (2 << 25)
5291#define VSC_DIP_SW_HEA_DATA (3 << 25)
5292#define VDIP_ENABLE_PPS (1 << 24)
5293#define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20)
5294#define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16)
5295#define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12)
5296#define VIDEO_DIP_ENABLE_VS_HSW (1 << 8)
5297#define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4)
5298#define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0)
5299
5300
5301#define PPS_BASE 0x61200
5302#define VLV_PPS_BASE (VLV_DISPLAY_BASE + PPS_BASE)
5303#define PCH_PPS_BASE 0xC7200
5304
5305#define _MMIO_PPS(pps_idx, reg) _MMIO(dev_priv->pps_mmio_base - \
5306 PPS_BASE + (reg) + \
5307 (pps_idx) * 0x100)
5308
5309#define _PP_STATUS 0x61200
5310#define PP_STATUS(pps_idx) _MMIO_PPS(pps_idx, _PP_STATUS)
5311#define PP_ON REG_BIT(31)
5312
5313
5314
5315
5316
5317
5318
5319#define PP_READY REG_BIT(30)
5320#define PP_SEQUENCE_MASK REG_GENMASK(29, 28)
5321#define PP_SEQUENCE_NONE REG_FIELD_PREP(PP_SEQUENCE_MASK, 0)
5322#define PP_SEQUENCE_POWER_UP REG_FIELD_PREP(PP_SEQUENCE_MASK, 1)
5323#define PP_SEQUENCE_POWER_DOWN REG_FIELD_PREP(PP_SEQUENCE_MASK, 2)
5324#define PP_CYCLE_DELAY_ACTIVE REG_BIT(27)
5325#define PP_SEQUENCE_STATE_MASK REG_GENMASK(3, 0)
5326#define PP_SEQUENCE_STATE_OFF_IDLE REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x0)
5327#define PP_SEQUENCE_STATE_OFF_S0_1 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x1)
5328#define PP_SEQUENCE_STATE_OFF_S0_2 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x2)
5329#define PP_SEQUENCE_STATE_OFF_S0_3 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x3)
5330#define PP_SEQUENCE_STATE_ON_IDLE REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x8)
5331#define PP_SEQUENCE_STATE_ON_S1_1 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x9)
5332#define PP_SEQUENCE_STATE_ON_S1_2 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xa)
5333#define PP_SEQUENCE_STATE_ON_S1_3 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xb)
5334#define PP_SEQUENCE_STATE_RESET REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xf)
5335
5336#define _PP_CONTROL 0x61204
5337#define PP_CONTROL(pps_idx) _MMIO_PPS(pps_idx, _PP_CONTROL)
5338#define PANEL_UNLOCK_MASK REG_GENMASK(31, 16)
5339#define PANEL_UNLOCK_REGS REG_FIELD_PREP(PANEL_UNLOCK_MASK, 0xabcd)
5340#define BXT_POWER_CYCLE_DELAY_MASK REG_GENMASK(8, 4)
5341#define EDP_FORCE_VDD REG_BIT(3)
5342#define EDP_BLC_ENABLE REG_BIT(2)
5343#define PANEL_POWER_RESET REG_BIT(1)
5344#define PANEL_POWER_ON REG_BIT(0)
5345
5346#define _PP_ON_DELAYS 0x61208
5347#define PP_ON_DELAYS(pps_idx) _MMIO_PPS(pps_idx, _PP_ON_DELAYS)
5348#define PANEL_PORT_SELECT_MASK REG_GENMASK(31, 30)
5349#define PANEL_PORT_SELECT_LVDS REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 0)
5350#define PANEL_PORT_SELECT_DPA REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 1)
5351#define PANEL_PORT_SELECT_DPC REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 2)
5352#define PANEL_PORT_SELECT_DPD REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 3)
5353#define PANEL_PORT_SELECT_VLV(port) REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, port)
5354#define PANEL_POWER_UP_DELAY_MASK REG_GENMASK(28, 16)
5355#define PANEL_LIGHT_ON_DELAY_MASK REG_GENMASK(12, 0)
5356
5357#define _PP_OFF_DELAYS 0x6120C
5358#define PP_OFF_DELAYS(pps_idx) _MMIO_PPS(pps_idx, _PP_OFF_DELAYS)
5359#define PANEL_POWER_DOWN_DELAY_MASK REG_GENMASK(28, 16)
5360#define PANEL_LIGHT_OFF_DELAY_MASK REG_GENMASK(12, 0)
5361
5362#define _PP_DIVISOR 0x61210
5363#define PP_DIVISOR(pps_idx) _MMIO_PPS(pps_idx, _PP_DIVISOR)
5364#define PP_REFERENCE_DIVIDER_MASK REG_GENMASK(31, 8)
5365#define PANEL_POWER_CYCLE_DELAY_MASK REG_GENMASK(4, 0)
5366
5367
5368#define PFIT_CONTROL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61230)
5369#define PFIT_ENABLE (1 << 31)
5370#define PFIT_PIPE_MASK (3 << 29)
5371#define PFIT_PIPE_SHIFT 29
5372#define PFIT_PIPE(pipe) ((pipe) << 29)
5373#define VERT_INTERP_DISABLE (0 << 10)
5374#define VERT_INTERP_BILINEAR (1 << 10)
5375#define VERT_INTERP_MASK (3 << 10)
5376#define VERT_AUTO_SCALE (1 << 9)
5377#define HORIZ_INTERP_DISABLE (0 << 6)
5378#define HORIZ_INTERP_BILINEAR (1 << 6)
5379#define HORIZ_INTERP_MASK (3 << 6)
5380#define HORIZ_AUTO_SCALE (1 << 5)
5381#define PANEL_8TO6_DITHER_ENABLE (1 << 3)
5382#define PFIT_FILTER_FUZZY (0 << 24)
5383#define PFIT_SCALING_AUTO (0 << 26)
5384#define PFIT_SCALING_PROGRAMMED (1 << 26)
5385#define PFIT_SCALING_PILLAR (2 << 26)
5386#define PFIT_SCALING_LETTER (3 << 26)
5387#define PFIT_PGM_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61234)
5388
5389#define PFIT_VERT_SCALE_SHIFT 20
5390#define PFIT_VERT_SCALE_MASK 0xfff00000
5391#define PFIT_HORIZ_SCALE_SHIFT 4
5392#define PFIT_HORIZ_SCALE_MASK 0x0000fff0
5393
5394#define PFIT_VERT_SCALE_SHIFT_965 16
5395#define PFIT_VERT_SCALE_MASK_965 0x1fff0000
5396#define PFIT_HORIZ_SCALE_SHIFT_965 0
5397#define PFIT_HORIZ_SCALE_MASK_965 0x00001fff
5398
5399#define PFIT_AUTO_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61238)
5400
5401#define _VLV_BLC_PWM_CTL2_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61250)
5402#define _VLV_BLC_PWM_CTL2_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61350)
5403#define VLV_BLC_PWM_CTL2(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \
5404 _VLV_BLC_PWM_CTL2_B)
5405
5406#define _VLV_BLC_PWM_CTL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61254)
5407#define _VLV_BLC_PWM_CTL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61354)
5408#define VLV_BLC_PWM_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL_A, \
5409 _VLV_BLC_PWM_CTL_B)
5410
5411#define _VLV_BLC_HIST_CTL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61260)
5412#define _VLV_BLC_HIST_CTL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61360)
5413#define VLV_BLC_HIST_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_HIST_CTL_A, \
5414 _VLV_BLC_HIST_CTL_B)
5415
5416
5417#define BLC_PWM_CTL2 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61250)
5418#define BLM_PWM_ENABLE (1 << 31)
5419#define BLM_COMBINATION_MODE (1 << 30)
5420#define BLM_PIPE_SELECT (1 << 29)
5421#define BLM_PIPE_SELECT_IVB (3 << 29)
5422#define BLM_PIPE_A (0 << 29)
5423#define BLM_PIPE_B (1 << 29)
5424#define BLM_PIPE_C (2 << 29)
5425#define BLM_TRANSCODER_A BLM_PIPE_A
5426#define BLM_TRANSCODER_B BLM_PIPE_B
5427#define BLM_TRANSCODER_C BLM_PIPE_C
5428#define BLM_TRANSCODER_EDP (3 << 29)
5429#define BLM_PIPE(pipe) ((pipe) << 29)
5430#define BLM_POLARITY_I965 (1 << 28)
5431#define BLM_PHASE_IN_INTERUPT_STATUS (1 << 26)
5432#define BLM_PHASE_IN_ENABLE (1 << 25)
5433#define BLM_PHASE_IN_INTERUPT_ENABL (1 << 24)
5434#define BLM_PHASE_IN_TIME_BASE_SHIFT (16)
5435#define BLM_PHASE_IN_TIME_BASE_MASK (0xff << 16)
5436#define BLM_PHASE_IN_COUNT_SHIFT (8)
5437#define BLM_PHASE_IN_COUNT_MASK (0xff << 8)
5438#define BLM_PHASE_IN_INCR_SHIFT (0)
5439#define BLM_PHASE_IN_INCR_MASK (0xff << 0)
5440#define BLC_PWM_CTL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61254)
5441
5442
5443
5444
5445
5446
5447#define BACKLIGHT_MODULATION_FREQ_SHIFT (17)
5448#define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17)
5449#define BLM_LEGACY_MODE (1 << 16)
5450
5451
5452
5453
5454
5455
5456
5457#define BACKLIGHT_DUTY_CYCLE_SHIFT (0)
5458#define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)
5459#define BACKLIGHT_DUTY_CYCLE_MASK_PNV (0xfffe)
5460#define BLM_POLARITY_PNV (1 << 0)
5461
5462#define BLC_HIST_CTL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61260)
5463#define BLM_HISTOGRAM_ENABLE (1 << 31)
5464
5465
5466
5467#define BLC_PWM_CPU_CTL2 _MMIO(0x48250)
5468#define BLC_PWM_CPU_CTL _MMIO(0x48254)
5469
5470#define HSW_BLC_PWM2_CTL _MMIO(0x48350)
5471
5472
5473
5474#define BLC_PWM_PCH_CTL1 _MMIO(0xc8250)
5475#define BLM_PCH_PWM_ENABLE (1 << 31)
5476#define BLM_PCH_OVERRIDE_ENABLE (1 << 30)
5477#define BLM_PCH_POLARITY (1 << 29)
5478#define BLC_PWM_PCH_CTL2 _MMIO(0xc8254)
5479
5480#define UTIL_PIN_CTL _MMIO(0x48400)
5481#define UTIL_PIN_ENABLE (1 << 31)
5482#define UTIL_PIN_PIPE_MASK (3 << 29)
5483#define UTIL_PIN_PIPE(x) ((x) << 29)
5484#define UTIL_PIN_MODE_MASK (0xf << 24)
5485#define UTIL_PIN_MODE_DATA (0 << 24)
5486#define UTIL_PIN_MODE_PWM (1 << 24)
5487#define UTIL_PIN_MODE_VBLANK (4 << 24)
5488#define UTIL_PIN_MODE_VSYNC (5 << 24)
5489#define UTIL_PIN_MODE_EYE_LEVEL (8 << 24)
5490#define UTIL_PIN_OUTPUT_DATA (1 << 23)
5491#define UTIL_PIN_POLARITY (1 << 22)
5492#define UTIL_PIN_DIRECTION_INPUT (1 << 19)
5493#define UTIL_PIN_INPUT_DATA (1 << 16)
5494
5495
5496#define _BXT_BLC_PWM_CTL1 0xC8250
5497#define BXT_BLC_PWM_ENABLE (1 << 31)
5498#define BXT_BLC_PWM_POLARITY (1 << 29)
5499#define _BXT_BLC_PWM_FREQ1 0xC8254
5500#define _BXT_BLC_PWM_DUTY1 0xC8258
5501
5502#define _BXT_BLC_PWM_CTL2 0xC8350
5503#define _BXT_BLC_PWM_FREQ2 0xC8354
5504#define _BXT_BLC_PWM_DUTY2 0xC8358
5505
5506#define BXT_BLC_PWM_CTL(controller) _MMIO_PIPE(controller, \
5507 _BXT_BLC_PWM_CTL1, _BXT_BLC_PWM_CTL2)
5508#define BXT_BLC_PWM_FREQ(controller) _MMIO_PIPE(controller, \
5509 _BXT_BLC_PWM_FREQ1, _BXT_BLC_PWM_FREQ2)
5510#define BXT_BLC_PWM_DUTY(controller) _MMIO_PIPE(controller, \
5511 _BXT_BLC_PWM_DUTY1, _BXT_BLC_PWM_DUTY2)
5512
5513#define PCH_GTC_CTL _MMIO(0xe7000)
5514#define PCH_GTC_ENABLE (1 << 31)
5515
5516
5517#define TV_CTL _MMIO(0x68000)
5518
5519# define TV_ENC_ENABLE (1 << 31)
5520
5521# define TV_ENC_PIPE_SEL_SHIFT 30
5522# define TV_ENC_PIPE_SEL_MASK (1 << 30)
5523# define TV_ENC_PIPE_SEL(pipe) ((pipe) << 30)
5524
5525# define TV_ENC_OUTPUT_COMPOSITE (0 << 28)
5526
5527# define TV_ENC_OUTPUT_SVIDEO (1 << 28)
5528
5529# define TV_ENC_OUTPUT_COMPONENT (2 << 28)
5530
5531# define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28)
5532# define TV_TRILEVEL_SYNC (1 << 21)
5533
5534# define TV_SLOW_SYNC (1 << 20)
5535
5536# define TV_OVERSAMPLE_4X (0 << 18)
5537
5538# define TV_OVERSAMPLE_2X (1 << 18)
5539
5540# define TV_OVERSAMPLE_NONE (2 << 18)
5541
5542# define TV_OVERSAMPLE_8X (3 << 18)
5543# define TV_OVERSAMPLE_MASK (3 << 18)
5544
5545# define TV_PROGRESSIVE (1 << 17)
5546
5547# define TV_PAL_BURST (1 << 16)
5548
5549# define TV_YC_SKEW_MASK (7 << 12)
5550
5551# define TV_ENC_SDP_FIX (1 << 11)
5552
5553
5554
5555
5556
5557# define TV_ENC_C0_FIX (1 << 10)
5558
5559# define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf)
5560# define TV_FUSE_STATE_MASK (3 << 4)
5561
5562# define TV_FUSE_STATE_ENABLED (0 << 4)
5563
5564# define TV_FUSE_STATE_NO_MACROVISION (1 << 4)
5565
5566# define TV_FUSE_STATE_DISABLED (2 << 4)
5567
5568# define TV_TEST_MODE_NORMAL (0 << 0)
5569
5570# define TV_TEST_MODE_PATTERN_1 (1 << 0)
5571
5572# define TV_TEST_MODE_PATTERN_2 (2 << 0)
5573
5574# define TV_TEST_MODE_PATTERN_3 (3 << 0)
5575
5576# define TV_TEST_MODE_PATTERN_4 (4 << 0)
5577
5578# define TV_TEST_MODE_PATTERN_5 (5 << 0)
5579
5580
5581
5582
5583
5584# define TV_TEST_MODE_MONITOR_DETECT (7 << 0)
5585# define TV_TEST_MODE_MASK (7 << 0)
5586
5587#define TV_DAC _MMIO(0x68004)
5588# define TV_DAC_SAVE 0x00ffff00
5589
5590
5591
5592
5593
5594# define TVDAC_STATE_CHG (1 << 31)
5595# define TVDAC_SENSE_MASK (7 << 28)
5596
5597# define TVDAC_A_SENSE (1 << 30)
5598
5599# define TVDAC_B_SENSE (1 << 29)
5600
5601# define TVDAC_C_SENSE (1 << 28)
5602
5603
5604
5605
5606
5607
5608# define TVDAC_STATE_CHG_EN (1 << 27)
5609
5610# define TVDAC_A_SENSE_CTL (1 << 26)
5611
5612# define TVDAC_B_SENSE_CTL (1 << 25)
5613
5614# define TVDAC_C_SENSE_CTL (1 << 24)
5615
5616# define DAC_CTL_OVERRIDE (1 << 7)
5617
5618# define ENC_TVDAC_SLEW_FAST (1 << 6)
5619# define DAC_A_1_3_V (0 << 4)
5620# define DAC_A_1_1_V (1 << 4)
5621# define DAC_A_0_7_V (2 << 4)
5622# define DAC_A_MASK (3 << 4)
5623# define DAC_B_1_3_V (0 << 2)
5624# define DAC_B_1_1_V (1 << 2)
5625# define DAC_B_0_7_V (2 << 2)
5626# define DAC_B_MASK (3 << 2)
5627# define DAC_C_1_3_V (0 << 0)
5628# define DAC_C_1_1_V (1 << 0)
5629# define DAC_C_0_7_V (2 << 0)
5630# define DAC_C_MASK (3 << 0)
5631
5632
5633
5634
5635
5636
5637
5638#define TV_CSC_Y _MMIO(0x68010)
5639# define TV_RY_MASK 0x07ff0000
5640# define TV_RY_SHIFT 16
5641# define TV_GY_MASK 0x00000fff
5642# define TV_GY_SHIFT 0
5643
5644#define TV_CSC_Y2 _MMIO(0x68014)
5645# define TV_BY_MASK 0x07ff0000
5646# define TV_BY_SHIFT 16
5647
5648
5649
5650
5651
5652# define TV_AY_MASK 0x000003ff
5653# define TV_AY_SHIFT 0
5654
5655#define TV_CSC_U _MMIO(0x68018)
5656# define TV_RU_MASK 0x07ff0000
5657# define TV_RU_SHIFT 16
5658# define TV_GU_MASK 0x000007ff
5659# define TV_GU_SHIFT 0
5660
5661#define TV_CSC_U2 _MMIO(0x6801c)
5662# define TV_BU_MASK 0x07ff0000
5663# define TV_BU_SHIFT 16
5664
5665
5666
5667
5668
5669# define TV_AU_MASK 0x000003ff
5670# define TV_AU_SHIFT 0
5671
5672#define TV_CSC_V _MMIO(0x68020)
5673# define TV_RV_MASK 0x0fff0000
5674# define TV_RV_SHIFT 16
5675# define TV_GV_MASK 0x000007ff
5676# define TV_GV_SHIFT 0
5677
5678#define TV_CSC_V2 _MMIO(0x68024)
5679# define TV_BV_MASK 0x07ff0000
5680# define TV_BV_SHIFT 16
5681
5682
5683
5684
5685
5686# define TV_AV_MASK 0x000007ff
5687# define TV_AV_SHIFT 0
5688
5689#define TV_CLR_KNOBS _MMIO(0x68028)
5690
5691# define TV_BRIGHTNESS_MASK 0xff000000
5692# define TV_BRIGHTNESS_SHIFT 24
5693
5694# define TV_CONTRAST_MASK 0x00ff0000
5695# define TV_CONTRAST_SHIFT 16
5696
5697# define TV_SATURATION_MASK 0x0000ff00
5698# define TV_SATURATION_SHIFT 8
5699
5700# define TV_HUE_MASK 0x000000ff
5701# define TV_HUE_SHIFT 0
5702
5703#define TV_CLR_LEVEL _MMIO(0x6802c)
5704
5705# define TV_BLACK_LEVEL_MASK 0x01ff0000
5706# define TV_BLACK_LEVEL_SHIFT 16
5707
5708# define TV_BLANK_LEVEL_MASK 0x000001ff
5709# define TV_BLANK_LEVEL_SHIFT 0
5710
5711#define TV_H_CTL_1 _MMIO(0x68030)
5712
5713# define TV_HSYNC_END_MASK 0x1fff0000
5714# define TV_HSYNC_END_SHIFT 16
5715
5716# define TV_HTOTAL_MASK 0x00001fff
5717# define TV_HTOTAL_SHIFT 0
5718
5719#define TV_H_CTL_2 _MMIO(0x68034)
5720
5721# define TV_BURST_ENA (1 << 31)
5722
5723# define TV_HBURST_START_SHIFT 16
5724# define TV_HBURST_START_MASK 0x1fff0000
5725
5726# define TV_HBURST_LEN_SHIFT 0
5727# define TV_HBURST_LEN_MASK 0x0001fff
5728
5729#define TV_H_CTL_3 _MMIO(0x68038)
5730
5731# define TV_HBLANK_END_SHIFT 16
5732# define TV_HBLANK_END_MASK 0x1fff0000
5733
5734# define TV_HBLANK_START_SHIFT 0
5735# define TV_HBLANK_START_MASK 0x0001fff
5736
5737#define TV_V_CTL_1 _MMIO(0x6803c)
5738
5739# define TV_NBR_END_SHIFT 16
5740# define TV_NBR_END_MASK 0x07ff0000
5741
5742# define TV_VI_END_F1_SHIFT 8
5743# define TV_VI_END_F1_MASK 0x00003f00
5744
5745# define TV_VI_END_F2_SHIFT 0
5746# define TV_VI_END_F2_MASK 0x0000003f
5747
5748#define TV_V_CTL_2 _MMIO(0x68040)
5749
5750# define TV_VSYNC_LEN_MASK 0x07ff0000
5751# define TV_VSYNC_LEN_SHIFT 16
5752
5753
5754
5755# define TV_VSYNC_START_F1_MASK 0x00007f00
5756# define TV_VSYNC_START_F1_SHIFT 8
5757
5758
5759
5760
5761# define TV_VSYNC_START_F2_MASK 0x0000007f
5762# define TV_VSYNC_START_F2_SHIFT 0
5763
5764#define TV_V_CTL_3 _MMIO(0x68044)
5765
5766# define TV_EQUAL_ENA (1 << 31)
5767
5768# define TV_VEQ_LEN_MASK 0x007f0000
5769# define TV_VEQ_LEN_SHIFT 16
5770
5771
5772
5773# define TV_VEQ_START_F1_MASK 0x0007f00
5774# define TV_VEQ_START_F1_SHIFT 8
5775
5776
5777
5778
5779# define TV_VEQ_START_F2_MASK 0x000007f
5780# define TV_VEQ_START_F2_SHIFT 0
5781
5782#define TV_V_CTL_4 _MMIO(0x68048)
5783
5784
5785
5786
5787# define TV_VBURST_START_F1_MASK 0x003f0000
5788# define TV_VBURST_START_F1_SHIFT 16
5789
5790
5791
5792
5793# define TV_VBURST_END_F1_MASK 0x000000ff
5794# define TV_VBURST_END_F1_SHIFT 0
5795
5796#define TV_V_CTL_5 _MMIO(0x6804c)
5797
5798
5799
5800
5801# define TV_VBURST_START_F2_MASK 0x003f0000
5802# define TV_VBURST_START_F2_SHIFT 16
5803
5804
5805
5806
5807# define TV_VBURST_END_F2_MASK 0x000000ff
5808# define TV_VBURST_END_F2_SHIFT 0
5809
5810#define TV_V_CTL_6 _MMIO(0x68050)
5811
5812
5813
5814
5815# define TV_VBURST_START_F3_MASK 0x003f0000
5816# define TV_VBURST_START_F3_SHIFT 16
5817
5818
5819
5820
5821# define TV_VBURST_END_F3_MASK 0x000000ff
5822# define TV_VBURST_END_F3_SHIFT 0
5823
5824#define TV_V_CTL_7 _MMIO(0x68054)
5825
5826
5827
5828
5829# define TV_VBURST_START_F4_MASK 0x003f0000
5830# define TV_VBURST_START_F4_SHIFT 16
5831
5832
5833
5834
5835# define TV_VBURST_END_F4_MASK 0x000000ff
5836# define TV_VBURST_END_F4_SHIFT 0
5837
5838#define TV_SC_CTL_1 _MMIO(0x68060)
5839
5840# define TV_SC_DDA1_EN (1 << 31)
5841
5842# define TV_SC_DDA2_EN (1 << 30)
5843
5844# define TV_SC_DDA3_EN (1 << 29)
5845
5846# define TV_SC_RESET_EVERY_2 (0 << 24)
5847
5848# define TV_SC_RESET_EVERY_4 (1 << 24)
5849
5850# define TV_SC_RESET_EVERY_8 (2 << 24)
5851
5852# define TV_SC_RESET_NEVER (3 << 24)
5853
5854# define TV_BURST_LEVEL_MASK 0x00ff0000
5855# define TV_BURST_LEVEL_SHIFT 16
5856
5857# define TV_SCDDA1_INC_MASK 0x00000fff
5858# define TV_SCDDA1_INC_SHIFT 0
5859
5860#define TV_SC_CTL_2 _MMIO(0x68064)
5861
5862# define TV_SCDDA2_SIZE_MASK 0x7fff0000
5863# define TV_SCDDA2_SIZE_SHIFT 16
5864
5865# define TV_SCDDA2_INC_MASK 0x00007fff
5866# define TV_SCDDA2_INC_SHIFT 0
5867
5868#define TV_SC_CTL_3 _MMIO(0x68068)
5869
5870# define TV_SCDDA3_SIZE_MASK 0x7fff0000
5871# define TV_SCDDA3_SIZE_SHIFT 16
5872
5873# define TV_SCDDA3_INC_MASK 0x00007fff
5874# define TV_SCDDA3_INC_SHIFT 0
5875
5876#define TV_WIN_POS _MMIO(0x68070)
5877
5878# define TV_XPOS_MASK 0x1fff0000
5879# define TV_XPOS_SHIFT 16
5880
5881# define TV_YPOS_MASK 0x00000fff
5882# define TV_YPOS_SHIFT 0
5883
5884#define TV_WIN_SIZE _MMIO(0x68074)
5885
5886# define TV_XSIZE_MASK 0x1fff0000
5887# define TV_XSIZE_SHIFT 16
5888
5889
5890
5891
5892
5893# define TV_YSIZE_MASK 0x00000fff
5894# define TV_YSIZE_SHIFT 0
5895
5896#define TV_FILTER_CTL_1 _MMIO(0x68080)
5897
5898
5899
5900
5901
5902
5903# define TV_AUTO_SCALE (1 << 31)
5904
5905
5906
5907
5908# define TV_V_FILTER_BYPASS (1 << 29)
5909
5910# define TV_VADAPT (1 << 28)
5911# define TV_VADAPT_MODE_MASK (3 << 26)
5912
5913# define TV_VADAPT_MODE_LEAST (0 << 26)
5914
5915# define TV_VADAPT_MODE_MODERATE (1 << 26)
5916
5917# define TV_VADAPT_MODE_MOST (3 << 26)
5918
5919
5920
5921
5922
5923
5924
5925
5926# define TV_HSCALE_FRAC_MASK 0x00003fff
5927# define TV_HSCALE_FRAC_SHIFT 0
5928
5929#define TV_FILTER_CTL_2 _MMIO(0x68084)
5930
5931
5932
5933
5934
5935# define TV_VSCALE_INT_MASK 0x00038000
5936# define TV_VSCALE_INT_SHIFT 15
5937
5938
5939
5940
5941
5942# define TV_VSCALE_FRAC_MASK 0x00007fff
5943# define TV_VSCALE_FRAC_SHIFT 0
5944
5945#define TV_FILTER_CTL_3 _MMIO(0x68088)
5946
5947
5948
5949
5950
5951
5952
5953# define TV_VSCALE_IP_INT_MASK 0x00038000
5954# define TV_VSCALE_IP_INT_SHIFT 15
5955
5956
5957
5958
5959
5960
5961
5962# define TV_VSCALE_IP_FRAC_MASK 0x00007fff
5963# define TV_VSCALE_IP_FRAC_SHIFT 0
5964
5965#define TV_CC_CONTROL _MMIO(0x68090)
5966# define TV_CC_ENABLE (1 << 31)
5967
5968
5969
5970
5971
5972# define TV_CC_FID_MASK (1 << 27)
5973# define TV_CC_FID_SHIFT 27
5974
5975# define TV_CC_HOFF_MASK 0x03ff0000
5976# define TV_CC_HOFF_SHIFT 16
5977
5978# define TV_CC_LINE_MASK 0x0000003f
5979# define TV_CC_LINE_SHIFT 0
5980
5981#define TV_CC_DATA _MMIO(0x68094)
5982# define TV_CC_RDY (1 << 31)
5983
5984# define TV_CC_DATA_2_MASK 0x007f0000
5985# define TV_CC_DATA_2_SHIFT 16
5986
5987# define TV_CC_DATA_1_MASK 0x0000007f
5988# define TV_CC_DATA_1_SHIFT 0
5989
5990#define TV_H_LUMA(i) _MMIO(0x68100 + (i) * 4)
5991#define TV_H_CHROMA(i) _MMIO(0x68200 + (i) * 4)
5992#define TV_V_LUMA(i) _MMIO(0x68300 + (i) * 4)
5993#define TV_V_CHROMA(i) _MMIO(0x68400 + (i) * 4)
5994
5995
5996#define DP_A _MMIO(0x64000)
5997#define DP_B _MMIO(0x64100)
5998#define DP_C _MMIO(0x64200)
5999#define DP_D _MMIO(0x64300)
6000
6001#define VLV_DP_B _MMIO(VLV_DISPLAY_BASE + 0x64100)
6002#define VLV_DP_C _MMIO(VLV_DISPLAY_BASE + 0x64200)
6003#define CHV_DP_D _MMIO(VLV_DISPLAY_BASE + 0x64300)
6004
6005#define DP_PORT_EN (1 << 31)
6006#define DP_PIPE_SEL_SHIFT 30
6007#define DP_PIPE_SEL_MASK (1 << 30)
6008#define DP_PIPE_SEL(pipe) ((pipe) << 30)
6009#define DP_PIPE_SEL_SHIFT_IVB 29
6010#define DP_PIPE_SEL_MASK_IVB (3 << 29)
6011#define DP_PIPE_SEL_IVB(pipe) ((pipe) << 29)
6012#define DP_PIPE_SEL_SHIFT_CHV 16
6013#define DP_PIPE_SEL_MASK_CHV (3 << 16)
6014#define DP_PIPE_SEL_CHV(pipe) ((pipe) << 16)
6015
6016
6017#define DP_LINK_TRAIN_PAT_1 (0 << 28)
6018#define DP_LINK_TRAIN_PAT_2 (1 << 28)
6019#define DP_LINK_TRAIN_PAT_IDLE (2 << 28)
6020#define DP_LINK_TRAIN_OFF (3 << 28)
6021#define DP_LINK_TRAIN_MASK (3 << 28)
6022#define DP_LINK_TRAIN_SHIFT 28
6023
6024
6025#define DP_LINK_TRAIN_PAT_1_CPT (0 << 8)
6026#define DP_LINK_TRAIN_PAT_2_CPT (1 << 8)
6027#define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8)
6028#define DP_LINK_TRAIN_OFF_CPT (3 << 8)
6029#define DP_LINK_TRAIN_MASK_CPT (7 << 8)
6030#define DP_LINK_TRAIN_SHIFT_CPT 8
6031
6032
6033#define DP_VOLTAGE_0_4 (0 << 25)
6034#define DP_VOLTAGE_0_6 (1 << 25)
6035#define DP_VOLTAGE_0_8 (2 << 25)
6036#define DP_VOLTAGE_1_2 (3 << 25)
6037#define DP_VOLTAGE_MASK (7 << 25)
6038#define DP_VOLTAGE_SHIFT 25
6039
6040
6041
6042
6043#define DP_PRE_EMPHASIS_0 (0 << 22)
6044#define DP_PRE_EMPHASIS_3_5 (1 << 22)
6045#define DP_PRE_EMPHASIS_6 (2 << 22)
6046#define DP_PRE_EMPHASIS_9_5 (3 << 22)
6047#define DP_PRE_EMPHASIS_MASK (7 << 22)
6048#define DP_PRE_EMPHASIS_SHIFT 22
6049
6050
6051#define DP_PORT_WIDTH(width) (((width) - 1) << 19)
6052#define DP_PORT_WIDTH_MASK (7 << 19)
6053#define DP_PORT_WIDTH_SHIFT 19
6054
6055
6056#define DP_ENHANCED_FRAMING (1 << 18)
6057
6058
6059#define DP_PLL_FREQ_270MHZ (0 << 16)
6060#define DP_PLL_FREQ_162MHZ (1 << 16)
6061#define DP_PLL_FREQ_MASK (3 << 16)
6062
6063
6064#define DP_PORT_REVERSAL (1 << 15)
6065
6066
6067#define DP_PLL_ENABLE (1 << 14)
6068
6069
6070#define DP_CLOCK_OUTPUT_ENABLE (1 << 13)
6071
6072#define DP_SCRAMBLING_DISABLE (1 << 12)
6073#define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7)
6074
6075
6076#define DP_COLOR_RANGE_16_235 (1 << 8)
6077
6078
6079#define DP_AUDIO_OUTPUT_ENABLE (1 << 6)
6080
6081
6082#define DP_SYNC_VS_HIGH (1 << 4)
6083#define DP_SYNC_HS_HIGH (1 << 3)
6084
6085
6086#define DP_DETECTED (1 << 2)
6087
6088
6089
6090
6091
6092
6093#define _DPA_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64010)
6094#define _DPA_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64014)
6095
6096#define _DPB_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64110)
6097#define _DPB_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64114)
6098
6099#define DP_AUX_CH_CTL(aux_ch) _MMIO_PORT(aux_ch, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL)
6100#define DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT(aux_ch, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4)
6101
6102#define DP_AUX_CH_CTL_SEND_BUSY (1 << 31)
6103#define DP_AUX_CH_CTL_DONE (1 << 30)
6104#define DP_AUX_CH_CTL_INTERRUPT (1 << 29)
6105#define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28)
6106#define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26)
6107#define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26)
6108#define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26)
6109#define DP_AUX_CH_CTL_TIME_OUT_MAX (3 << 26)
6110#define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26)
6111#define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25)
6112#define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20)
6113#define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20
6114#define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16)
6115#define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16
6116#define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15)
6117#define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14)
6118#define DP_AUX_CH_CTL_SYNC_TEST (1 << 13)
6119#define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12)
6120#define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11)
6121#define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff)
6122#define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0
6123#define DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL (1 << 14)
6124#define DP_AUX_CH_CTL_FS_DATA_AUX_REG_SKL (1 << 13)
6125#define DP_AUX_CH_CTL_GTC_DATA_AUX_REG_SKL (1 << 12)
6126#define DP_AUX_CH_CTL_TBT_IO (1 << 11)
6127#define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK (0x1f << 5)
6128#define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5)
6129#define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) ((c) - 1)
6130
6131
6132
6133
6134
6135
6136
6137
6138
6139
6140
6141
6142
6143
6144#define _PIPEA_DATA_M_G4X 0x70050
6145#define _PIPEB_DATA_M_G4X 0x71050
6146
6147
6148#define TU_SIZE(x) (((x) - 1) << 25)
6149#define TU_SIZE_SHIFT 25
6150#define TU_SIZE_MASK (0x3f << 25)
6151
6152#define DATA_LINK_M_N_MASK (0xffffff)
6153#define DATA_LINK_N_MAX (0x800000)
6154
6155#define _PIPEA_DATA_N_G4X 0x70054
6156#define _PIPEB_DATA_N_G4X 0x71054
6157#define PIPE_GMCH_DATA_N_MASK (0xffffff)
6158
6159
6160
6161
6162
6163
6164
6165
6166
6167
6168
6169
6170#define _PIPEA_LINK_M_G4X 0x70060
6171#define _PIPEB_LINK_M_G4X 0x71060
6172#define PIPEA_DP_LINK_M_MASK (0xffffff)
6173
6174#define _PIPEA_LINK_N_G4X 0x70064
6175#define _PIPEB_LINK_N_G4X 0x71064
6176#define PIPEA_DP_LINK_N_MASK (0xffffff)
6177
6178#define PIPE_DATA_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X)
6179#define PIPE_DATA_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X)
6180#define PIPE_LINK_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X)
6181#define PIPE_LINK_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X)
6182
6183
6184
6185
6186#define _PIPEADSL 0x70000
6187#define DSL_LINEMASK_GEN2 0x00000fff
6188#define DSL_LINEMASK_GEN3 0x00001fff
6189#define _PIPEACONF 0x70008
6190#define PIPECONF_ENABLE (1 << 31)
6191#define PIPECONF_DISABLE 0
6192#define PIPECONF_DOUBLE_WIDE (1 << 30)
6193#define I965_PIPECONF_ACTIVE (1 << 30)
6194#define PIPECONF_DSI_PLL_LOCKED (1 << 29)
6195#define PIPECONF_FRAME_START_DELAY_MASK (3 << 27)
6196#define PIPECONF_FRAME_START_DELAY(x) ((x) << 27)
6197#define PIPECONF_SINGLE_WIDE 0
6198#define PIPECONF_PIPE_UNLOCKED 0
6199#define PIPECONF_PIPE_LOCKED (1 << 25)
6200#define PIPECONF_FORCE_BORDER (1 << 25)
6201#define PIPECONF_GAMMA_MODE_MASK_I9XX (1 << 24)
6202#define PIPECONF_GAMMA_MODE_MASK_ILK (3 << 24)
6203#define PIPECONF_GAMMA_MODE_8BIT (0 << 24)
6204#define PIPECONF_GAMMA_MODE_10BIT (1 << 24)
6205#define PIPECONF_GAMMA_MODE_12BIT (2 << 24)
6206#define PIPECONF_GAMMA_MODE_SPLIT (3 << 24)
6207#define PIPECONF_GAMMA_MODE(x) ((x) << 24)
6208#define PIPECONF_GAMMA_MODE_SHIFT 24
6209#define PIPECONF_INTERLACE_MASK (7 << 21)
6210#define PIPECONF_INTERLACE_MASK_HSW (3 << 21)
6211
6212
6213#define PIPECONF_PROGRESSIVE (0 << 21)
6214#define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL (4 << 21)
6215#define PIPECONF_INTERLACE_W_SYNC_SHIFT (5 << 21)
6216#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
6217#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21)
6218
6219
6220
6221#define PIPECONF_PFIT_PF_INTERLACED_ILK (1 << 21)
6222#define PIPECONF_INTERLACED_ILK (3 << 21)
6223#define PIPECONF_INTERLACED_DBL_ILK (4 << 21)
6224#define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21)
6225#define PIPECONF_INTERLACE_MODE_MASK (7 << 21)
6226#define PIPECONF_EDP_RR_MODE_SWITCH (1 << 20)
6227#define PIPECONF_CXSR_DOWNCLOCK (1 << 16)
6228#define PIPECONF_EDP_RR_MODE_SWITCH_VLV (1 << 14)
6229#define PIPECONF_COLOR_RANGE_SELECT (1 << 13)
6230#define PIPECONF_OUTPUT_COLORSPACE_MASK (3 << 11)
6231#define PIPECONF_OUTPUT_COLORSPACE_RGB (0 << 11)
6232#define PIPECONF_OUTPUT_COLORSPACE_YUV601 (1 << 11)
6233#define PIPECONF_OUTPUT_COLORSPACE_YUV709 (2 << 11)
6234#define PIPECONF_OUTPUT_COLORSPACE_YUV_HSW (1 << 11)
6235#define PIPECONF_BPC_MASK (0x7 << 5)
6236#define PIPECONF_8BPC (0 << 5)
6237#define PIPECONF_10BPC (1 << 5)
6238#define PIPECONF_6BPC (2 << 5)
6239#define PIPECONF_12BPC (3 << 5)
6240#define PIPECONF_DITHER_EN (1 << 4)
6241#define PIPECONF_DITHER_TYPE_MASK (0x0000000c)
6242#define PIPECONF_DITHER_TYPE_SP (0 << 2)
6243#define PIPECONF_DITHER_TYPE_ST1 (1 << 2)
6244#define PIPECONF_DITHER_TYPE_ST2 (2 << 2)
6245#define PIPECONF_DITHER_TYPE_TEMP (3 << 2)
6246#define _PIPEASTAT 0x70024
6247#define PIPE_FIFO_UNDERRUN_STATUS (1UL << 31)
6248#define SPRITE1_FLIP_DONE_INT_EN_VLV (1UL << 30)
6249#define PIPE_CRC_ERROR_ENABLE (1UL << 29)
6250#define PIPE_CRC_DONE_ENABLE (1UL << 28)
6251#define PERF_COUNTER2_INTERRUPT_EN (1UL << 27)
6252#define PIPE_GMBUS_EVENT_ENABLE (1UL << 27)
6253#define PLANE_FLIP_DONE_INT_EN_VLV (1UL << 26)
6254#define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL << 26)
6255#define PIPE_VSYNC_INTERRUPT_ENABLE (1UL << 25)
6256#define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL << 24)
6257#define PIPE_DPST_EVENT_ENABLE (1UL << 23)
6258#define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL << 22)
6259#define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL << 22)
6260#define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL << 21)
6261#define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL << 20)
6262#define PIPE_B_PSR_INTERRUPT_ENABLE_VLV (1UL << 19)
6263#define PERF_COUNTER_INTERRUPT_EN (1UL << 19)
6264#define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL << 18)
6265#define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL << 18)
6266#define PIPE_FRAMESTART_INTERRUPT_ENABLE (1UL << 17)
6267#define PIPE_VBLANK_INTERRUPT_ENABLE (1UL << 17)
6268#define PIPEA_HBLANK_INT_EN_VLV (1UL << 16)
6269#define PIPE_OVERLAY_UPDATED_ENABLE (1UL << 16)
6270#define SPRITE1_FLIP_DONE_INT_STATUS_VLV (1UL << 15)
6271#define SPRITE0_FLIP_DONE_INT_STATUS_VLV (1UL << 14)
6272#define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL << 13)
6273#define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL << 12)
6274#define PERF_COUNTER2_INTERRUPT_STATUS (1UL << 11)
6275#define PIPE_GMBUS_INTERRUPT_STATUS (1UL << 11)
6276#define PLANE_FLIP_DONE_INT_STATUS_VLV (1UL << 10)
6277#define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL << 10)
6278#define PIPE_VSYNC_INTERRUPT_STATUS (1UL << 9)
6279#define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL << 8)
6280#define PIPE_DPST_EVENT_STATUS (1UL << 7)
6281#define PIPE_A_PSR_STATUS_VLV (1UL << 6)
6282#define PIPE_LEGACY_BLC_EVENT_STATUS (1UL << 6)
6283#define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL << 5)
6284#define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL << 4)
6285#define PIPE_B_PSR_STATUS_VLV (1UL << 3)
6286#define PERF_COUNTER_INTERRUPT_STATUS (1UL << 3)
6287#define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL << 2)
6288#define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL << 2)
6289#define PIPE_FRAMESTART_INTERRUPT_STATUS (1UL << 1)
6290#define PIPE_VBLANK_INTERRUPT_STATUS (1UL << 1)
6291#define PIPE_HBLANK_INT_STATUS (1UL << 0)
6292#define PIPE_OVERLAY_UPDATED_STATUS (1UL << 0)
6293
6294#define PIPESTAT_INT_ENABLE_MASK 0x7fff0000
6295#define PIPESTAT_INT_STATUS_MASK 0x0000ffff
6296
6297#define PIPE_A_OFFSET 0x70000
6298#define PIPE_B_OFFSET 0x71000
6299#define PIPE_C_OFFSET 0x72000
6300#define PIPE_D_OFFSET 0x73000
6301#define CHV_PIPE_C_OFFSET 0x74000
6302
6303
6304
6305
6306
6307
6308#define PIPE_EDP_OFFSET 0x7f000
6309
6310
6311#define PIPE_DSI0_OFFSET 0x7b000
6312#define PIPE_DSI1_OFFSET 0x7b800
6313
6314#define PIPECONF(pipe) _MMIO_PIPE2(pipe, _PIPEACONF)
6315#define PIPEDSL(pipe) _MMIO_PIPE2(pipe, _PIPEADSL)
6316#define PIPEFRAME(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEHIGH)
6317#define PIPEFRAMEPIXEL(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEPIXEL)
6318#define PIPESTAT(pipe) _MMIO_PIPE2(pipe, _PIPEASTAT)
6319
6320#define _PIPEAGCMAX 0x70010
6321#define _PIPEBGCMAX 0x71010
6322#define PIPEGCMAX(pipe, i) _MMIO_PIPE2(pipe, _PIPEAGCMAX + (i) * 4)
6323
6324#define _PIPE_ARB_CTL_A 0x70028
6325#define PIPE_ARB_CTL(pipe) _MMIO_PIPE2(pipe, _PIPE_ARB_CTL_A)
6326#define PIPE_ARB_USE_PROG_SLOTS REG_BIT(13)
6327
6328#define _PIPE_MISC_A 0x70030
6329#define _PIPE_MISC_B 0x71030
6330#define PIPEMISC_YUV420_ENABLE (1 << 27)
6331#define PIPEMISC_YUV420_MODE_FULL_BLEND (1 << 26)
6332#define PIPEMISC_HDR_MODE_PRECISION (1 << 23)
6333#define PIPEMISC_OUTPUT_COLORSPACE_YUV (1 << 11)
6334#define PIPEMISC_PIXEL_ROUNDING_TRUNC REG_BIT(8)
6335
6336
6337
6338
6339
6340
6341#define PIPEMISC_BPC_MASK (7 << 5)
6342#define PIPEMISC_8_BPC (0 << 5)
6343#define PIPEMISC_10_BPC (1 << 5)
6344#define PIPEMISC_6_BPC (2 << 5)
6345#define PIPEMISC_12_BPC_ADLP (4 << 5)
6346#define PIPEMISC_DITHER_ENABLE (1 << 4)
6347#define PIPEMISC_DITHER_TYPE_MASK (3 << 2)
6348#define PIPEMISC_DITHER_TYPE_SP (0 << 2)
6349#define PIPEMISC(pipe) _MMIO_PIPE2(pipe, _PIPE_MISC_A)
6350
6351#define _PIPE_MISC2_A 0x7002C
6352#define _PIPE_MISC2_B 0x7102C
6353#define PIPE_MISC2_BUBBLE_COUNTER_SCALER_EN (0x50 << 24)
6354#define PIPE_MISC2_BUBBLE_COUNTER_SCALER_DIS (0x14 << 24)
6355#define PIPE_MISC2_UNDERRUN_BUBBLE_COUNTER_MASK (0xff << 24)
6356#define PIPE_MISC2(pipe) _MMIO_PIPE2(pipe, _PIPE_MISC2_A)
6357
6358
6359#define _SKL_BOTTOM_COLOR_A 0x70034
6360#define SKL_BOTTOM_COLOR_GAMMA_ENABLE (1 << 31)
6361#define SKL_BOTTOM_COLOR_CSC_ENABLE (1 << 30)
6362#define SKL_BOTTOM_COLOR(pipe) _MMIO_PIPE2(pipe, _SKL_BOTTOM_COLOR_A)
6363
6364#define _ICL_PIPE_A_STATUS 0x70058
6365#define ICL_PIPESTATUS(pipe) _MMIO_PIPE2(pipe, _ICL_PIPE_A_STATUS)
6366#define PIPE_STATUS_UNDERRUN REG_BIT(31)
6367#define PIPE_STATUS_SOFT_UNDERRUN_XELPD REG_BIT(28)
6368#define PIPE_STATUS_HARD_UNDERRUN_XELPD REG_BIT(27)
6369#define PIPE_STATUS_PORT_UNDERRUN_XELPD REG_BIT(26)
6370
6371#define VLV_DPFLIPSTAT _MMIO(VLV_DISPLAY_BASE + 0x70028)
6372#define PIPEB_LINE_COMPARE_INT_EN REG_BIT(29)
6373#define PIPEB_HLINE_INT_EN REG_BIT(28)
6374#define PIPEB_VBLANK_INT_EN REG_BIT(27)
6375#define SPRITED_FLIP_DONE_INT_EN REG_BIT(26)
6376#define SPRITEC_FLIP_DONE_INT_EN REG_BIT(25)
6377#define PLANEB_FLIP_DONE_INT_EN REG_BIT(24)
6378#define PIPE_PSR_INT_EN REG_BIT(22)
6379#define PIPEA_LINE_COMPARE_INT_EN REG_BIT(21)
6380#define PIPEA_HLINE_INT_EN REG_BIT(20)
6381#define PIPEA_VBLANK_INT_EN REG_BIT(19)
6382#define SPRITEB_FLIP_DONE_INT_EN REG_BIT(18)
6383#define SPRITEA_FLIP_DONE_INT_EN REG_BIT(17)
6384#define PLANEA_FLIPDONE_INT_EN REG_BIT(16)
6385#define PIPEC_LINE_COMPARE_INT_EN REG_BIT(13)
6386#define PIPEC_HLINE_INT_EN REG_BIT(12)
6387#define PIPEC_VBLANK_INT_EN REG_BIT(11)
6388#define SPRITEF_FLIPDONE_INT_EN REG_BIT(10)
6389#define SPRITEE_FLIPDONE_INT_EN REG_BIT(9)
6390#define PLANEC_FLIPDONE_INT_EN REG_BIT(8)
6391
6392#define DPINVGTT _MMIO(VLV_DISPLAY_BASE + 0x7002c)
6393#define DPINVGTT_EN_MASK_CHV REG_GENMASK(27, 16)
6394#define DPINVGTT_EN_MASK_VLV REG_GENMASK(23, 16)
6395#define SPRITEF_INVALID_GTT_INT_EN REG_BIT(27)
6396#define SPRITEE_INVALID_GTT_INT_EN REG_BIT(26)
6397#define PLANEC_INVALID_GTT_INT_EN REG_BIT(25)
6398#define CURSORC_INVALID_GTT_INT_EN REG_BIT(24)
6399#define CURSORB_INVALID_GTT_INT_EN REG_BIT(23)
6400#define CURSORA_INVALID_GTT_INT_EN REG_BIT(22)
6401#define SPRITED_INVALID_GTT_INT_EN REG_BIT(21)
6402#define SPRITEC_INVALID_GTT_INT_EN REG_BIT(20)
6403#define PLANEB_INVALID_GTT_INT_EN REG_BIT(19)
6404#define SPRITEB_INVALID_GTT_INT_EN REG_BIT(18)
6405#define SPRITEA_INVALID_GTT_INT_EN REG_BIT(17)
6406#define PLANEA_INVALID_GTT_INT_EN REG_BIT(16)
6407#define DPINVGTT_STATUS_MASK_CHV REG_GENMASK(11, 0)
6408#define DPINVGTT_STATUS_MASK_VLV REG_GENMASK(7, 0)
6409#define SPRITEF_INVALID_GTT_STATUS REG_BIT(11)
6410#define SPRITEE_INVALID_GTT_STATUS REG_BIT(10)
6411#define PLANEC_INVALID_GTT_STATUS REG_BIT(9)
6412#define CURSORC_INVALID_GTT_STATUS REG_BIT(8)
6413#define CURSORB_INVALID_GTT_STATUS REG_BIT(7)
6414#define CURSORA_INVALID_GTT_STATUS REG_BIT(6)
6415#define SPRITED_INVALID_GTT_STATUS REG_BIT(5)
6416#define SPRITEC_INVALID_GTT_STATUS REG_BIT(4)
6417#define PLANEB_INVALID_GTT_STATUS REG_BIT(3)
6418#define SPRITEB_INVALID_GTT_STATUS REG_BIT(2)
6419#define SPRITEA_INVALID_GTT_STATUS REG_BIT(1)
6420#define PLANEA_INVALID_GTT_STATUS REG_BIT(0)
6421
6422#define DSPARB _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70030)
6423#define DSPARB_CSTART_MASK (0x7f << 7)
6424#define DSPARB_CSTART_SHIFT 7
6425#define DSPARB_BSTART_MASK (0x7f)
6426#define DSPARB_BSTART_SHIFT 0
6427#define DSPARB_BEND_SHIFT 9
6428#define DSPARB_AEND_SHIFT 0
6429#define DSPARB_SPRITEA_SHIFT_VLV 0
6430#define DSPARB_SPRITEA_MASK_VLV (0xff << 0)
6431#define DSPARB_SPRITEB_SHIFT_VLV 8
6432#define DSPARB_SPRITEB_MASK_VLV (0xff << 8)
6433#define DSPARB_SPRITEC_SHIFT_VLV 16
6434#define DSPARB_SPRITEC_MASK_VLV (0xff << 16)
6435#define DSPARB_SPRITED_SHIFT_VLV 24
6436#define DSPARB_SPRITED_MASK_VLV (0xff << 24)
6437#define DSPARB2 _MMIO(VLV_DISPLAY_BASE + 0x70060)
6438#define DSPARB_SPRITEA_HI_SHIFT_VLV 0
6439#define DSPARB_SPRITEA_HI_MASK_VLV (0x1 << 0)
6440#define DSPARB_SPRITEB_HI_SHIFT_VLV 4
6441#define DSPARB_SPRITEB_HI_MASK_VLV (0x1 << 4)
6442#define DSPARB_SPRITEC_HI_SHIFT_VLV 8
6443#define DSPARB_SPRITEC_HI_MASK_VLV (0x1 << 8)
6444#define DSPARB_SPRITED_HI_SHIFT_VLV 12
6445#define DSPARB_SPRITED_HI_MASK_VLV (0x1 << 12)
6446#define DSPARB_SPRITEE_HI_SHIFT_VLV 16
6447#define DSPARB_SPRITEE_HI_MASK_VLV (0x1 << 16)
6448#define DSPARB_SPRITEF_HI_SHIFT_VLV 20
6449#define DSPARB_SPRITEF_HI_MASK_VLV (0x1 << 20)
6450#define DSPARB3 _MMIO(VLV_DISPLAY_BASE + 0x7006c)
6451#define DSPARB_SPRITEE_SHIFT_VLV 0
6452#define DSPARB_SPRITEE_MASK_VLV (0xff << 0)
6453#define DSPARB_SPRITEF_SHIFT_VLV 8
6454#define DSPARB_SPRITEF_MASK_VLV (0xff << 8)
6455
6456
6457#define DSPFW1 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70034)
6458#define DSPFW_SR_SHIFT 23
6459#define DSPFW_SR_MASK (0x1ff << 23)
6460#define DSPFW_CURSORB_SHIFT 16
6461#define DSPFW_CURSORB_MASK (0x3f << 16)
6462#define DSPFW_PLANEB_SHIFT 8
6463#define DSPFW_PLANEB_MASK (0x7f << 8)
6464#define DSPFW_PLANEB_MASK_VLV (0xff << 8)
6465#define DSPFW_PLANEA_SHIFT 0
6466#define DSPFW_PLANEA_MASK (0x7f << 0)
6467#define DSPFW_PLANEA_MASK_VLV (0xff << 0)
6468#define DSPFW2 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70038)
6469#define DSPFW_FBC_SR_EN (1 << 31)
6470#define DSPFW_FBC_SR_SHIFT 28
6471#define DSPFW_FBC_SR_MASK (0x7 << 28)
6472#define DSPFW_FBC_HPLL_SR_SHIFT 24
6473#define DSPFW_FBC_HPLL_SR_MASK (0xf << 24)
6474#define DSPFW_SPRITEB_SHIFT (16)
6475#define DSPFW_SPRITEB_MASK (0x7f << 16)
6476#define DSPFW_SPRITEB_MASK_VLV (0xff << 16)
6477#define DSPFW_CURSORA_SHIFT 8
6478#define DSPFW_CURSORA_MASK (0x3f << 8)
6479#define DSPFW_PLANEC_OLD_SHIFT 0
6480#define DSPFW_PLANEC_OLD_MASK (0x7f << 0)
6481#define DSPFW_SPRITEA_SHIFT 0
6482#define DSPFW_SPRITEA_MASK (0x7f << 0)
6483#define DSPFW_SPRITEA_MASK_VLV (0xff << 0)
6484#define DSPFW3 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x7003c)
6485#define DSPFW_HPLL_SR_EN (1 << 31)
6486#define PINEVIEW_SELF_REFRESH_EN (1 << 30)
6487#define DSPFW_CURSOR_SR_SHIFT 24
6488#define DSPFW_CURSOR_SR_MASK (0x3f << 24)
6489#define DSPFW_HPLL_CURSOR_SHIFT 16
6490#define DSPFW_HPLL_CURSOR_MASK (0x3f << 16)
6491#define DSPFW_HPLL_SR_SHIFT 0
6492#define DSPFW_HPLL_SR_MASK (0x1ff << 0)
6493
6494
6495#define DSPFW4 _MMIO(VLV_DISPLAY_BASE + 0x70070)
6496#define DSPFW_SPRITEB_WM1_SHIFT 16
6497#define DSPFW_SPRITEB_WM1_MASK (0xff << 16)
6498#define DSPFW_CURSORA_WM1_SHIFT 8
6499#define DSPFW_CURSORA_WM1_MASK (0x3f << 8)
6500#define DSPFW_SPRITEA_WM1_SHIFT 0
6501#define DSPFW_SPRITEA_WM1_MASK (0xff << 0)
6502#define DSPFW5 _MMIO(VLV_DISPLAY_BASE + 0x70074)
6503#define DSPFW_PLANEB_WM1_SHIFT 24
6504#define DSPFW_PLANEB_WM1_MASK (0xff << 24)
6505#define DSPFW_PLANEA_WM1_SHIFT 16
6506#define DSPFW_PLANEA_WM1_MASK (0xff << 16)
6507#define DSPFW_CURSORB_WM1_SHIFT 8
6508#define DSPFW_CURSORB_WM1_MASK (0x3f << 8)
6509#define DSPFW_CURSOR_SR_WM1_SHIFT 0
6510#define DSPFW_CURSOR_SR_WM1_MASK (0x3f << 0)
6511#define DSPFW6 _MMIO(VLV_DISPLAY_BASE + 0x70078)
6512#define DSPFW_SR_WM1_SHIFT 0
6513#define DSPFW_SR_WM1_MASK (0x1ff << 0)
6514#define DSPFW7 _MMIO(VLV_DISPLAY_BASE + 0x7007c)
6515#define DSPFW7_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b4)
6516#define DSPFW_SPRITED_WM1_SHIFT 24
6517#define DSPFW_SPRITED_WM1_MASK (0xff << 24)
6518#define DSPFW_SPRITED_SHIFT 16
6519#define DSPFW_SPRITED_MASK_VLV (0xff << 16)
6520#define DSPFW_SPRITEC_WM1_SHIFT 8
6521#define DSPFW_SPRITEC_WM1_MASK (0xff << 8)
6522#define DSPFW_SPRITEC_SHIFT 0
6523#define DSPFW_SPRITEC_MASK_VLV (0xff << 0)
6524#define DSPFW8_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b8)
6525#define DSPFW_SPRITEF_WM1_SHIFT 24
6526#define DSPFW_SPRITEF_WM1_MASK (0xff << 24)
6527#define DSPFW_SPRITEF_SHIFT 16
6528#define DSPFW_SPRITEF_MASK_VLV (0xff << 16)
6529#define DSPFW_SPRITEE_WM1_SHIFT 8
6530#define DSPFW_SPRITEE_WM1_MASK (0xff << 8)
6531#define DSPFW_SPRITEE_SHIFT 0
6532#define DSPFW_SPRITEE_MASK_VLV (0xff << 0)
6533#define DSPFW9_CHV _MMIO(VLV_DISPLAY_BASE + 0x7007c)
6534#define DSPFW_PLANEC_WM1_SHIFT 24
6535#define DSPFW_PLANEC_WM1_MASK (0xff << 24)
6536#define DSPFW_PLANEC_SHIFT 16
6537#define DSPFW_PLANEC_MASK_VLV (0xff << 16)
6538#define DSPFW_CURSORC_WM1_SHIFT 8
6539#define DSPFW_CURSORC_WM1_MASK (0x3f << 16)
6540#define DSPFW_CURSORC_SHIFT 0
6541#define DSPFW_CURSORC_MASK (0x3f << 0)
6542
6543
6544#define DSPHOWM _MMIO(VLV_DISPLAY_BASE + 0x70064)
6545#define DSPFW_SR_HI_SHIFT 24
6546#define DSPFW_SR_HI_MASK (3 << 24)
6547#define DSPFW_SPRITEF_HI_SHIFT 23
6548#define DSPFW_SPRITEF_HI_MASK (1 << 23)
6549#define DSPFW_SPRITEE_HI_SHIFT 22
6550#define DSPFW_SPRITEE_HI_MASK (1 << 22)
6551#define DSPFW_PLANEC_HI_SHIFT 21
6552#define DSPFW_PLANEC_HI_MASK (1 << 21)
6553#define DSPFW_SPRITED_HI_SHIFT 20
6554#define DSPFW_SPRITED_HI_MASK (1 << 20)
6555#define DSPFW_SPRITEC_HI_SHIFT 16
6556#define DSPFW_SPRITEC_HI_MASK (1 << 16)
6557#define DSPFW_PLANEB_HI_SHIFT 12
6558#define DSPFW_PLANEB_HI_MASK (1 << 12)
6559#define DSPFW_SPRITEB_HI_SHIFT 8
6560#define DSPFW_SPRITEB_HI_MASK (1 << 8)
6561#define DSPFW_SPRITEA_HI_SHIFT 4
6562#define DSPFW_SPRITEA_HI_MASK (1 << 4)
6563#define DSPFW_PLANEA_HI_SHIFT 0
6564#define DSPFW_PLANEA_HI_MASK (1 << 0)
6565#define DSPHOWM1 _MMIO(VLV_DISPLAY_BASE + 0x70068)
6566#define DSPFW_SR_WM1_HI_SHIFT 24
6567#define DSPFW_SR_WM1_HI_MASK (3 << 24)
6568#define DSPFW_SPRITEF_WM1_HI_SHIFT 23
6569#define DSPFW_SPRITEF_WM1_HI_MASK (1 << 23)
6570#define DSPFW_SPRITEE_WM1_HI_SHIFT 22
6571#define DSPFW_SPRITEE_WM1_HI_MASK (1 << 22)
6572#define DSPFW_PLANEC_WM1_HI_SHIFT 21
6573#define DSPFW_PLANEC_WM1_HI_MASK (1 << 21)
6574#define DSPFW_SPRITED_WM1_HI_SHIFT 20
6575#define DSPFW_SPRITED_WM1_HI_MASK (1 << 20)
6576#define DSPFW_SPRITEC_WM1_HI_SHIFT 16
6577#define DSPFW_SPRITEC_WM1_HI_MASK (1 << 16)
6578#define DSPFW_PLANEB_WM1_HI_SHIFT 12
6579#define DSPFW_PLANEB_WM1_HI_MASK (1 << 12)
6580#define DSPFW_SPRITEB_WM1_HI_SHIFT 8
6581#define DSPFW_SPRITEB_WM1_HI_MASK (1 << 8)
6582#define DSPFW_SPRITEA_WM1_HI_SHIFT 4
6583#define DSPFW_SPRITEA_WM1_HI_MASK (1 << 4)
6584#define DSPFW_PLANEA_WM1_HI_SHIFT 0
6585#define DSPFW_PLANEA_WM1_HI_MASK (1 << 0)
6586
6587
6588#define VLV_DDL(pipe) _MMIO(VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe))
6589#define DDL_CURSOR_SHIFT 24
6590#define DDL_SPRITE_SHIFT(sprite) (8 + 8 * (sprite))
6591#define DDL_PLANE_SHIFT 0
6592#define DDL_PRECISION_HIGH (1 << 7)
6593#define DDL_PRECISION_LOW (0 << 7)
6594#define DRAIN_LATENCY_MASK 0x7f
6595
6596#define CBR1_VLV _MMIO(VLV_DISPLAY_BASE + 0x70400)
6597#define CBR_PND_DEADLINE_DISABLE (1 << 31)
6598#define CBR_PWM_CLOCK_MUX_SELECT (1 << 30)
6599
6600#define CBR4_VLV _MMIO(VLV_DISPLAY_BASE + 0x70450)
6601#define CBR_DPLLBMD_PIPE(pipe) (1 << (7 + (pipe) * 11))
6602
6603
6604#define G4X_FIFO_LINE_SIZE 64
6605#define I915_FIFO_LINE_SIZE 64
6606#define I830_FIFO_LINE_SIZE 32
6607
6608#define VALLEYVIEW_FIFO_SIZE 255
6609#define G4X_FIFO_SIZE 127
6610#define I965_FIFO_SIZE 512
6611#define I945_FIFO_SIZE 127
6612#define I915_FIFO_SIZE 95
6613#define I855GM_FIFO_SIZE 127
6614#define I830_FIFO_SIZE 95
6615
6616#define VALLEYVIEW_MAX_WM 0xff
6617#define G4X_MAX_WM 0x3f
6618#define I915_MAX_WM 0x3f
6619
6620#define PINEVIEW_DISPLAY_FIFO 512
6621#define PINEVIEW_FIFO_LINE_SIZE 64
6622#define PINEVIEW_MAX_WM 0x1ff
6623#define PINEVIEW_DFT_WM 0x3f
6624#define PINEVIEW_DFT_HPLLOFF_WM 0
6625#define PINEVIEW_GUARD_WM 10
6626#define PINEVIEW_CURSOR_FIFO 64
6627#define PINEVIEW_CURSOR_MAX_WM 0x3f
6628#define PINEVIEW_CURSOR_DFT_WM 0
6629#define PINEVIEW_CURSOR_GUARD_WM 5
6630
6631#define VALLEYVIEW_CURSOR_MAX_WM 64
6632#define I965_CURSOR_FIFO 64
6633#define I965_CURSOR_MAX_WM 32
6634#define I965_CURSOR_DFT_WM 8
6635
6636
6637#define _CUR_WM_A_0 0x70140
6638#define _CUR_WM_B_0 0x71140
6639#define _CUR_WM_SAGV_A 0x70158
6640#define _CUR_WM_SAGV_B 0x71158
6641#define _CUR_WM_SAGV_TRANS_A 0x7015C
6642#define _CUR_WM_SAGV_TRANS_B 0x7115C
6643#define _CUR_WM_TRANS_A 0x70168
6644#define _CUR_WM_TRANS_B 0x71168
6645#define _PLANE_WM_1_A_0 0x70240
6646#define _PLANE_WM_1_B_0 0x71240
6647#define _PLANE_WM_2_A_0 0x70340
6648#define _PLANE_WM_2_B_0 0x71340
6649#define _PLANE_WM_SAGV_1_A 0x70258
6650#define _PLANE_WM_SAGV_1_B 0x71258
6651#define _PLANE_WM_SAGV_2_A 0x70358
6652#define _PLANE_WM_SAGV_2_B 0x71358
6653#define _PLANE_WM_SAGV_TRANS_1_A 0x7025C
6654#define _PLANE_WM_SAGV_TRANS_1_B 0x7125C
6655#define _PLANE_WM_SAGV_TRANS_2_A 0x7035C
6656#define _PLANE_WM_SAGV_TRANS_2_B 0x7135C
6657#define _PLANE_WM_TRANS_1_A 0x70268
6658#define _PLANE_WM_TRANS_1_B 0x71268
6659#define _PLANE_WM_TRANS_2_A 0x70368
6660#define _PLANE_WM_TRANS_2_B 0x71368
6661#define PLANE_WM_EN (1 << 31)
6662#define PLANE_WM_IGNORE_LINES (1 << 30)
6663#define PLANE_WM_LINES_MASK REG_GENMASK(26, 14)
6664#define PLANE_WM_BLOCKS_MASK REG_GENMASK(11, 0)
6665
6666#define _CUR_WM_0(pipe) _PIPE(pipe, _CUR_WM_A_0, _CUR_WM_B_0)
6667#define CUR_WM(pipe, level) _MMIO(_CUR_WM_0(pipe) + ((4) * (level)))
6668#define CUR_WM_SAGV(pipe) _MMIO_PIPE(pipe, _CUR_WM_SAGV_A, _CUR_WM_SAGV_B)
6669#define CUR_WM_SAGV_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_SAGV_TRANS_A, _CUR_WM_SAGV_TRANS_B)
6670#define CUR_WM_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_TRANS_A, _CUR_WM_TRANS_B)
6671#define _PLANE_WM_1(pipe) _PIPE(pipe, _PLANE_WM_1_A_0, _PLANE_WM_1_B_0)
6672#define _PLANE_WM_2(pipe) _PIPE(pipe, _PLANE_WM_2_A_0, _PLANE_WM_2_B_0)
6673#define _PLANE_WM_BASE(pipe, plane) \
6674 _PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe))
6675#define PLANE_WM(pipe, plane, level) \
6676 _MMIO(_PLANE_WM_BASE(pipe, plane) + ((4) * (level)))
6677#define _PLANE_WM_SAGV_1(pipe) \
6678 _PIPE(pipe, _PLANE_WM_SAGV_1_A, _PLANE_WM_SAGV_1_B)
6679#define _PLANE_WM_SAGV_2(pipe) \
6680 _PIPE(pipe, _PLANE_WM_SAGV_2_A, _PLANE_WM_SAGV_2_B)
6681#define PLANE_WM_SAGV(pipe, plane) \
6682 _MMIO(_PLANE(plane, _PLANE_WM_SAGV_1(pipe), _PLANE_WM_SAGV_2(pipe)))
6683#define _PLANE_WM_SAGV_TRANS_1(pipe) \
6684 _PIPE(pipe, _PLANE_WM_SAGV_TRANS_1_A, _PLANE_WM_SAGV_TRANS_1_B)
6685#define _PLANE_WM_SAGV_TRANS_2(pipe) \
6686 _PIPE(pipe, _PLANE_WM_SAGV_TRANS_2_A, _PLANE_WM_SAGV_TRANS_2_B)
6687#define PLANE_WM_SAGV_TRANS(pipe, plane) \
6688 _MMIO(_PLANE(plane, _PLANE_WM_SAGV_TRANS_1(pipe), _PLANE_WM_SAGV_TRANS_2(pipe)))
6689#define _PLANE_WM_TRANS_1(pipe) \
6690 _PIPE(pipe, _PLANE_WM_TRANS_1_A, _PLANE_WM_TRANS_1_B)
6691#define _PLANE_WM_TRANS_2(pipe) \
6692 _PIPE(pipe, _PLANE_WM_TRANS_2_A, _PLANE_WM_TRANS_2_B)
6693#define PLANE_WM_TRANS(pipe, plane) \
6694 _MMIO(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe)))
6695
6696
6697#define _WM0_PIPEA_ILK 0x45100
6698#define _WM0_PIPEB_ILK 0x45104
6699#define _WM0_PIPEC_IVB 0x45200
6700#define WM0_PIPE_ILK(pipe) _MMIO_PIPE3((pipe), _WM0_PIPEA_ILK, \
6701 _WM0_PIPEB_ILK, _WM0_PIPEC_IVB)
6702#define WM0_PIPE_PLANE_MASK (0xffff << 16)
6703#define WM0_PIPE_PLANE_SHIFT 16
6704#define WM0_PIPE_SPRITE_MASK (0xff << 8)
6705#define WM0_PIPE_SPRITE_SHIFT 8
6706#define WM0_PIPE_CURSOR_MASK (0xff)
6707#define WM1_LP_ILK _MMIO(0x45108)
6708#define WM1_LP_SR_EN (1 << 31)
6709#define WM1_LP_LATENCY_SHIFT 24
6710#define WM1_LP_LATENCY_MASK (0x7f << 24)
6711#define WM1_LP_FBC_MASK (0xf << 20)
6712#define WM1_LP_FBC_SHIFT 20
6713#define WM1_LP_FBC_SHIFT_BDW 19
6714#define WM1_LP_SR_MASK (0x7ff << 8)
6715#define WM1_LP_SR_SHIFT 8
6716#define WM1_LP_CURSOR_MASK (0xff)
6717#define WM2_LP_ILK _MMIO(0x4510c)
6718#define WM2_LP_EN (1 << 31)
6719#define WM3_LP_ILK _MMIO(0x45110)
6720#define WM3_LP_EN (1 << 31)
6721#define WM1S_LP_ILK _MMIO(0x45120)
6722#define WM2S_LP_IVB _MMIO(0x45124)
6723#define WM3S_LP_IVB _MMIO(0x45128)
6724#define WM1S_LP_EN (1 << 31)
6725
6726#define HSW_WM_LP_VAL(lat, fbc, pri, cur) \
6727 (WM3_LP_EN | ((lat) << WM1_LP_LATENCY_SHIFT) | \
6728 ((fbc) << WM1_LP_FBC_SHIFT) | ((pri) << WM1_LP_SR_SHIFT) | (cur))
6729
6730
6731#define MLTR_ILK _MMIO(0x11222)
6732#define MLTR_WM1_SHIFT 0
6733#define MLTR_WM2_SHIFT 8
6734
6735#define ILK_SRLT_MASK 0x3f
6736
6737
6738
6739#define SSKPD _MMIO(0x5d10)
6740#define SSKPD_WM_MASK 0x3f
6741#define SSKPD_WM0_SHIFT 0
6742#define SSKPD_WM1_SHIFT 8
6743#define SSKPD_WM2_SHIFT 16
6744#define SSKPD_WM3_SHIFT 24
6745
6746
6747
6748
6749
6750
6751
6752
6753
6754
6755
6756
6757
6758
6759
6760
6761#define _PIPEAFRAMEHIGH 0x70040
6762#define PIPE_FRAME_HIGH_MASK 0x0000ffff
6763#define PIPE_FRAME_HIGH_SHIFT 0
6764#define _PIPEAFRAMEPIXEL 0x70044
6765#define PIPE_FRAME_LOW_MASK 0xff000000
6766#define PIPE_FRAME_LOW_SHIFT 24
6767#define PIPE_PIXEL_MASK 0x00ffffff
6768#define PIPE_PIXEL_SHIFT 0
6769
6770#define _PIPEA_FRMCOUNT_G4X 0x70040
6771#define _PIPEA_FLIPCOUNT_G4X 0x70044
6772#define PIPE_FRMCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FRMCOUNT_G4X)
6773#define PIPE_FLIPCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FLIPCOUNT_G4X)
6774
6775
6776#define _CURACNTR 0x70080
6777
6778#define CURSOR_ENABLE 0x80000000
6779#define CURSOR_GAMMA_ENABLE 0x40000000
6780#define CURSOR_STRIDE_SHIFT 28
6781#define CURSOR_STRIDE(x) ((ffs(x) - 9) << CURSOR_STRIDE_SHIFT)
6782#define CURSOR_FORMAT_SHIFT 24
6783#define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT)
6784#define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT)
6785#define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT)
6786#define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT)
6787#define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT)
6788#define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT)
6789
6790#define MCURSOR_MODE 0x27
6791#define MCURSOR_MODE_DISABLE 0x00
6792#define MCURSOR_MODE_128_32B_AX 0x02
6793#define MCURSOR_MODE_256_32B_AX 0x03
6794#define MCURSOR_MODE_64_32B_AX 0x07
6795#define MCURSOR_MODE_128_ARGB_AX ((1 << 5) | MCURSOR_MODE_128_32B_AX)
6796#define MCURSOR_MODE_256_ARGB_AX ((1 << 5) | MCURSOR_MODE_256_32B_AX)
6797#define MCURSOR_MODE_64_ARGB_AX ((1 << 5) | MCURSOR_MODE_64_32B_AX)
6798#define MCURSOR_ARB_SLOTS_MASK REG_GENMASK(30, 28)
6799#define MCURSOR_ARB_SLOTS(x) REG_FIELD_PREP(MCURSOR_ARB_SLOTS_MASK, (x))
6800#define MCURSOR_PIPE_SELECT_MASK (0x3 << 28)
6801#define MCURSOR_PIPE_SELECT_SHIFT 28
6802#define MCURSOR_PIPE_SELECT(pipe) ((pipe) << 28)
6803#define MCURSOR_GAMMA_ENABLE (1 << 26)
6804#define MCURSOR_PIPE_CSC_ENABLE (1 << 24)
6805#define MCURSOR_ROTATE_180 (1 << 15)
6806#define MCURSOR_TRICKLE_FEED_DISABLE (1 << 14)
6807#define _CURABASE 0x70084
6808#define _CURAPOS 0x70088
6809#define CURSOR_POS_MASK 0x007FF
6810#define CURSOR_POS_SIGN 0x8000
6811#define CURSOR_X_SHIFT 0
6812#define CURSOR_Y_SHIFT 16
6813#define CURSIZE _MMIO(0x700a0)
6814#define _CUR_FBC_CTL_A 0x700a0
6815#define CUR_FBC_CTL_EN (1 << 31)
6816#define _CURASURFLIVE 0x700ac
6817#define _CURBCNTR 0x700c0
6818#define _CURBBASE 0x700c4
6819#define _CURBPOS 0x700c8
6820
6821#define _CURBCNTR_IVB 0x71080
6822#define _CURBBASE_IVB 0x71084
6823#define _CURBPOS_IVB 0x71088
6824
6825#define CURCNTR(pipe) _CURSOR2(pipe, _CURACNTR)
6826#define CURBASE(pipe) _CURSOR2(pipe, _CURABASE)
6827#define CURPOS(pipe) _CURSOR2(pipe, _CURAPOS)
6828#define CUR_FBC_CTL(pipe) _CURSOR2(pipe, _CUR_FBC_CTL_A)
6829#define CURSURFLIVE(pipe) _CURSOR2(pipe, _CURASURFLIVE)
6830
6831#define CURSOR_A_OFFSET 0x70080
6832#define CURSOR_B_OFFSET 0x700c0
6833#define CHV_CURSOR_C_OFFSET 0x700e0
6834#define IVB_CURSOR_B_OFFSET 0x71080
6835#define IVB_CURSOR_C_OFFSET 0x72080
6836#define TGL_CURSOR_D_OFFSET 0x73080
6837
6838
6839#define _DSPAADDR_VLV 0x7017C
6840#define _DSPACNTR 0x70180
6841#define DISPLAY_PLANE_ENABLE (1 << 31)
6842#define DISPLAY_PLANE_DISABLE 0
6843#define DISPPLANE_GAMMA_ENABLE (1 << 30)
6844#define DISPPLANE_GAMMA_DISABLE 0
6845#define DISPPLANE_PIXFORMAT_MASK (0xf << 26)
6846#define DISPPLANE_YUV422 (0x0 << 26)
6847#define DISPPLANE_8BPP (0x2 << 26)
6848#define DISPPLANE_BGRA555 (0x3 << 26)
6849#define DISPPLANE_BGRX555 (0x4 << 26)
6850#define DISPPLANE_BGRX565 (0x5 << 26)
6851#define DISPPLANE_BGRX888 (0x6 << 26)
6852#define DISPPLANE_BGRA888 (0x7 << 26)
6853#define DISPPLANE_RGBX101010 (0x8 << 26)
6854#define DISPPLANE_RGBA101010 (0x9 << 26)
6855#define DISPPLANE_BGRX101010 (0xa << 26)
6856#define DISPPLANE_BGRA101010 (0xb << 26)
6857#define DISPPLANE_RGBX161616 (0xc << 26)
6858#define DISPPLANE_RGBX888 (0xe << 26)
6859#define DISPPLANE_RGBA888 (0xf << 26)
6860#define DISPPLANE_STEREO_ENABLE (1 << 25)
6861#define DISPPLANE_STEREO_DISABLE 0
6862#define DISPPLANE_PIPE_CSC_ENABLE (1 << 24)
6863#define DISPPLANE_SEL_PIPE_SHIFT 24
6864#define DISPPLANE_SEL_PIPE_MASK (3 << DISPPLANE_SEL_PIPE_SHIFT)
6865#define DISPPLANE_SEL_PIPE(pipe) ((pipe) << DISPPLANE_SEL_PIPE_SHIFT)
6866#define DISPPLANE_SRC_KEY_ENABLE (1 << 22)
6867#define DISPPLANE_SRC_KEY_DISABLE 0
6868#define DISPPLANE_LINE_DOUBLE (1 << 20)
6869#define DISPPLANE_NO_LINE_DOUBLE 0
6870#define DISPPLANE_STEREO_POLARITY_FIRST 0
6871#define DISPPLANE_STEREO_POLARITY_SECOND (1 << 18)
6872#define DISPPLANE_ALPHA_PREMULTIPLY (1 << 16)
6873#define DISPPLANE_ROTATE_180 (1 << 15)
6874#define DISPPLANE_TRICKLE_FEED_DISABLE (1 << 14)
6875#define DISPPLANE_TILED (1 << 10)
6876#define DISPPLANE_ASYNC_FLIP (1 << 9)
6877#define DISPPLANE_MIRROR (1 << 8)
6878#define _DSPAADDR 0x70184
6879#define _DSPASTRIDE 0x70188
6880#define _DSPAPOS 0x7018C
6881#define _DSPASIZE 0x70190
6882#define _DSPASURF 0x7019C
6883#define _DSPATILEOFF 0x701A4
6884#define _DSPAOFFSET 0x701A4
6885#define _DSPASURFLIVE 0x701AC
6886#define _DSPAGAMC 0x701E0
6887
6888#define DSPADDR_VLV(plane) _MMIO_PIPE2(plane, _DSPAADDR_VLV)
6889#define DSPCNTR(plane) _MMIO_PIPE2(plane, _DSPACNTR)
6890#define DSPADDR(plane) _MMIO_PIPE2(plane, _DSPAADDR)
6891#define DSPSTRIDE(plane) _MMIO_PIPE2(plane, _DSPASTRIDE)
6892#define DSPPOS(plane) _MMIO_PIPE2(plane, _DSPAPOS)
6893#define DSPSIZE(plane) _MMIO_PIPE2(plane, _DSPASIZE)
6894#define DSPSURF(plane) _MMIO_PIPE2(plane, _DSPASURF)
6895#define DSPTILEOFF(plane) _MMIO_PIPE2(plane, _DSPATILEOFF)
6896#define DSPLINOFF(plane) DSPADDR(plane)
6897#define DSPOFFSET(plane) _MMIO_PIPE2(plane, _DSPAOFFSET)
6898#define DSPSURFLIVE(plane) _MMIO_PIPE2(plane, _DSPASURFLIVE)
6899#define DSPGAMC(plane, i) _MMIO(_PIPE2(plane, _DSPAGAMC) + (5 - (i)) * 4)
6900
6901
6902#define _CHV_BLEND_A 0x60a00
6903#define CHV_BLEND_LEGACY (0 << 30)
6904#define CHV_BLEND_ANDROID (1 << 30)
6905#define CHV_BLEND_MPO (2 << 30)
6906#define CHV_BLEND_MASK (3 << 30)
6907#define _CHV_CANVAS_A 0x60a04
6908#define _PRIMPOS_A 0x60a08
6909#define _PRIMSIZE_A 0x60a0c
6910#define _PRIMCNSTALPHA_A 0x60a10
6911#define PRIM_CONST_ALPHA_ENABLE (1 << 31)
6912
6913#define CHV_BLEND(pipe) _MMIO_TRANS2(pipe, _CHV_BLEND_A)
6914#define CHV_CANVAS(pipe) _MMIO_TRANS2(pipe, _CHV_CANVAS_A)
6915#define PRIMPOS(plane) _MMIO_TRANS2(plane, _PRIMPOS_A)
6916#define PRIMSIZE(plane) _MMIO_TRANS2(plane, _PRIMSIZE_A)
6917#define PRIMCNSTALPHA(plane) _MMIO_TRANS2(plane, _PRIMCNSTALPHA_A)
6918
6919
6920#define DISP_BASEADDR_MASK (0xfffff000)
6921#define I915_LO_DISPBASE(val) ((val) & ~DISP_BASEADDR_MASK)
6922#define I915_HI_DISPBASE(val) ((val) & DISP_BASEADDR_MASK)
6923
6924
6925
6926
6927
6928
6929
6930
6931
6932
6933
6934
6935#define SWF0(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70410 + (i) * 4)
6936#define SWF1(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x71410 + (i) * 4)
6937#define SWF3(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x72414 + (i) * 4)
6938#define SWF_ILK(i) _MMIO(0x4F000 + (i) * 4)
6939
6940
6941#define _PIPEBDSL (DISPLAY_MMIO_BASE(dev_priv) + 0x71000)
6942#define _PIPEBCONF (DISPLAY_MMIO_BASE(dev_priv) + 0x71008)
6943#define _PIPEBSTAT (DISPLAY_MMIO_BASE(dev_priv) + 0x71024)
6944#define _PIPEBFRAMEHIGH 0x71040
6945#define _PIPEBFRAMEPIXEL 0x71044
6946#define _PIPEB_FRMCOUNT_G4X (DISPLAY_MMIO_BASE(dev_priv) + 0x71040)
6947#define _PIPEB_FLIPCOUNT_G4X (DISPLAY_MMIO_BASE(dev_priv) + 0x71044)
6948
6949
6950
6951#define _DSPBCNTR (DISPLAY_MMIO_BASE(dev_priv) + 0x71180)
6952#define DISPPLANE_ALPHA_TRANS_ENABLE (1 << 15)
6953#define DISPPLANE_ALPHA_TRANS_DISABLE 0
6954#define DISPPLANE_SPRITE_ABOVE_DISPLAY 0
6955#define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
6956#define _DSPBADDR (DISPLAY_MMIO_BASE(dev_priv) + 0x71184)
6957#define _DSPBSTRIDE (DISPLAY_MMIO_BASE(dev_priv) + 0x71188)
6958#define _DSPBPOS (DISPLAY_MMIO_BASE(dev_priv) + 0x7118C)
6959#define _DSPBSIZE (DISPLAY_MMIO_BASE(dev_priv) + 0x71190)
6960#define _DSPBSURF (DISPLAY_MMIO_BASE(dev_priv) + 0x7119C)
6961#define _DSPBTILEOFF (DISPLAY_MMIO_BASE(dev_priv) + 0x711A4)
6962#define _DSPBOFFSET (DISPLAY_MMIO_BASE(dev_priv) + 0x711A4)
6963#define _DSPBSURFLIVE (DISPLAY_MMIO_BASE(dev_priv) + 0x711AC)
6964
6965
6966#define _PIPEDSI0CONF 0x7b008
6967#define _PIPEDSI1CONF 0x7b808
6968
6969
6970#define _DVSACNTR 0x72180
6971#define DVS_ENABLE (1 << 31)
6972#define DVS_GAMMA_ENABLE (1 << 30)
6973#define DVS_YUV_RANGE_CORRECTION_DISABLE (1 << 27)
6974#define DVS_PIXFORMAT_MASK (3 << 25)
6975#define DVS_FORMAT_YUV422 (0 << 25)
6976#define DVS_FORMAT_RGBX101010 (1 << 25)
6977#define DVS_FORMAT_RGBX888 (2 << 25)
6978#define DVS_FORMAT_RGBX161616 (3 << 25)
6979#define DVS_PIPE_CSC_ENABLE (1 << 24)
6980#define DVS_SOURCE_KEY (1 << 22)
6981#define DVS_RGB_ORDER_XBGR (1 << 20)
6982#define DVS_YUV_FORMAT_BT709 (1 << 18)
6983#define DVS_YUV_ORDER_MASK (3 << 16)
6984#define DVS_YUV_ORDER_YUYV (0 << 16)
6985#define DVS_YUV_ORDER_UYVY (1 << 16)
6986#define DVS_YUV_ORDER_YVYU (2 << 16)
6987#define DVS_YUV_ORDER_VYUY (3 << 16)
6988#define DVS_ROTATE_180 (1 << 15)
6989#define DVS_DEST_KEY (1 << 2)
6990#define DVS_TRICKLE_FEED_DISABLE (1 << 14)
6991#define DVS_TILED (1 << 10)
6992#define _DVSALINOFF 0x72184
6993#define _DVSASTRIDE 0x72188
6994#define _DVSAPOS 0x7218c
6995#define _DVSASIZE 0x72190
6996#define _DVSAKEYVAL 0x72194
6997#define _DVSAKEYMSK 0x72198
6998#define _DVSASURF 0x7219c
6999#define _DVSAKEYMAXVAL 0x721a0
7000#define _DVSATILEOFF 0x721a4
7001#define _DVSASURFLIVE 0x721ac
7002#define _DVSAGAMC_G4X 0x721e0
7003#define _DVSASCALE 0x72204
7004#define DVS_SCALE_ENABLE (1 << 31)
7005#define DVS_FILTER_MASK (3 << 29)
7006#define DVS_FILTER_MEDIUM (0 << 29)
7007#define DVS_FILTER_ENHANCING (1 << 29)
7008#define DVS_FILTER_SOFTENING (2 << 29)
7009#define DVS_VERTICAL_OFFSET_HALF (1 << 28)
7010#define DVS_VERTICAL_OFFSET_ENABLE (1 << 27)
7011#define _DVSAGAMC_ILK 0x72300
7012#define _DVSAGAMCMAX_ILK 0x72340
7013
7014#define _DVSBCNTR 0x73180
7015#define _DVSBLINOFF 0x73184
7016#define _DVSBSTRIDE 0x73188
7017#define _DVSBPOS 0x7318c
7018#define _DVSBSIZE 0x73190
7019#define _DVSBKEYVAL 0x73194
7020#define _DVSBKEYMSK 0x73198
7021#define _DVSBSURF 0x7319c
7022#define _DVSBKEYMAXVAL 0x731a0
7023#define _DVSBTILEOFF 0x731a4
7024#define _DVSBSURFLIVE 0x731ac
7025#define _DVSBGAMC_G4X 0x731e0
7026#define _DVSBSCALE 0x73204
7027#define _DVSBGAMC_ILK 0x73300
7028#define _DVSBGAMCMAX_ILK 0x73340
7029
7030#define DVSCNTR(pipe) _MMIO_PIPE(pipe, _DVSACNTR, _DVSBCNTR)
7031#define DVSLINOFF(pipe) _MMIO_PIPE(pipe, _DVSALINOFF, _DVSBLINOFF)
7032#define DVSSTRIDE(pipe) _MMIO_PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE)
7033#define DVSPOS(pipe) _MMIO_PIPE(pipe, _DVSAPOS, _DVSBPOS)
7034#define DVSSURF(pipe) _MMIO_PIPE(pipe, _DVSASURF, _DVSBSURF)
7035#define DVSKEYMAX(pipe) _MMIO_PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL)
7036#define DVSSIZE(pipe) _MMIO_PIPE(pipe, _DVSASIZE, _DVSBSIZE)
7037#define DVSSCALE(pipe) _MMIO_PIPE(pipe, _DVSASCALE, _DVSBSCALE)
7038#define DVSTILEOFF(pipe) _MMIO_PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF)
7039#define DVSKEYVAL(pipe) _MMIO_PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL)
7040#define DVSKEYMSK(pipe) _MMIO_PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)
7041#define DVSSURFLIVE(pipe) _MMIO_PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE)
7042#define DVSGAMC_G4X(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_G4X, _DVSBGAMC_G4X) + (5 - (i)) * 4)
7043#define DVSGAMC_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_ILK, _DVSBGAMC_ILK) + (i) * 4)
7044#define DVSGAMCMAX_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMCMAX_ILK, _DVSBGAMCMAX_ILK) + (i) * 4)
7045
7046#define _SPRA_CTL 0x70280
7047#define SPRITE_ENABLE (1 << 31)
7048#define SPRITE_GAMMA_ENABLE (1 << 30)
7049#define SPRITE_YUV_RANGE_CORRECTION_DISABLE (1 << 28)
7050#define SPRITE_PIXFORMAT_MASK (7 << 25)
7051#define SPRITE_FORMAT_YUV422 (0 << 25)
7052#define SPRITE_FORMAT_RGBX101010 (1 << 25)
7053#define SPRITE_FORMAT_RGBX888 (2 << 25)
7054#define SPRITE_FORMAT_RGBX161616 (3 << 25)
7055#define SPRITE_FORMAT_YUV444 (4 << 25)
7056#define SPRITE_FORMAT_XR_BGR101010 (5 << 25)
7057#define SPRITE_PIPE_CSC_ENABLE (1 << 24)
7058#define SPRITE_SOURCE_KEY (1 << 22)
7059#define SPRITE_RGB_ORDER_RGBX (1 << 20)
7060#define SPRITE_YUV_TO_RGB_CSC_DISABLE (1 << 19)
7061#define SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709 (1 << 18)
7062#define SPRITE_YUV_ORDER_MASK (3 << 16)
7063#define SPRITE_YUV_ORDER_YUYV (0 << 16)
7064#define SPRITE_YUV_ORDER_UYVY (1 << 16)
7065#define SPRITE_YUV_ORDER_YVYU (2 << 16)
7066#define SPRITE_YUV_ORDER_VYUY (3 << 16)
7067#define SPRITE_ROTATE_180 (1 << 15)
7068#define SPRITE_TRICKLE_FEED_DISABLE (1 << 14)
7069#define SPRITE_INT_GAMMA_DISABLE (1 << 13)
7070#define SPRITE_TILED (1 << 10)
7071#define SPRITE_DEST_KEY (1 << 2)
7072#define _SPRA_LINOFF 0x70284
7073#define _SPRA_STRIDE 0x70288
7074#define _SPRA_POS 0x7028c
7075#define _SPRA_SIZE 0x70290
7076#define _SPRA_KEYVAL 0x70294
7077#define _SPRA_KEYMSK 0x70298
7078#define _SPRA_SURF 0x7029c
7079#define _SPRA_KEYMAX 0x702a0
7080#define _SPRA_TILEOFF 0x702a4
7081#define _SPRA_OFFSET 0x702a4
7082#define _SPRA_SURFLIVE 0x702ac
7083#define _SPRA_SCALE 0x70304
7084#define SPRITE_SCALE_ENABLE (1 << 31)
7085#define SPRITE_FILTER_MASK (3 << 29)
7086#define SPRITE_FILTER_MEDIUM (0 << 29)
7087#define SPRITE_FILTER_ENHANCING (1 << 29)
7088#define SPRITE_FILTER_SOFTENING (2 << 29)
7089#define SPRITE_VERTICAL_OFFSET_HALF (1 << 28)
7090#define SPRITE_VERTICAL_OFFSET_ENABLE (1 << 27)
7091#define _SPRA_GAMC 0x70400
7092#define _SPRA_GAMC16 0x70440
7093#define _SPRA_GAMC17 0x7044c
7094
7095#define _SPRB_CTL 0x71280
7096#define _SPRB_LINOFF 0x71284
7097#define _SPRB_STRIDE 0x71288
7098#define _SPRB_POS 0x7128c
7099#define _SPRB_SIZE 0x71290
7100#define _SPRB_KEYVAL 0x71294
7101#define _SPRB_KEYMSK 0x71298
7102#define _SPRB_SURF 0x7129c
7103#define _SPRB_KEYMAX 0x712a0
7104#define _SPRB_TILEOFF 0x712a4
7105#define _SPRB_OFFSET 0x712a4
7106#define _SPRB_SURFLIVE 0x712ac
7107#define _SPRB_SCALE 0x71304
7108#define _SPRB_GAMC 0x71400
7109#define _SPRB_GAMC16 0x71440
7110#define _SPRB_GAMC17 0x7144c
7111
7112#define SPRCTL(pipe) _MMIO_PIPE(pipe, _SPRA_CTL, _SPRB_CTL)
7113#define SPRLINOFF(pipe) _MMIO_PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF)
7114#define SPRSTRIDE(pipe) _MMIO_PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE)
7115#define SPRPOS(pipe) _MMIO_PIPE(pipe, _SPRA_POS, _SPRB_POS)
7116#define SPRSIZE(pipe) _MMIO_PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE)
7117#define SPRKEYVAL(pipe) _MMIO_PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL)
7118#define SPRKEYMSK(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK)
7119#define SPRSURF(pipe) _MMIO_PIPE(pipe, _SPRA_SURF, _SPRB_SURF)
7120#define SPRKEYMAX(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX)
7121#define SPRTILEOFF(pipe) _MMIO_PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)
7122#define SPROFFSET(pipe) _MMIO_PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET)
7123#define SPRSCALE(pipe) _MMIO_PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)
7124#define SPRGAMC(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC) + (i) * 4)
7125#define SPRGAMC16(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC16, _SPRB_GAMC16) + (i) * 4)
7126#define SPRGAMC17(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC17, _SPRB_GAMC17) + (i) * 4)
7127#define SPRSURFLIVE(pipe) _MMIO_PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
7128
7129#define _SPACNTR (VLV_DISPLAY_BASE + 0x72180)
7130#define SP_ENABLE (1 << 31)
7131#define SP_GAMMA_ENABLE (1 << 30)
7132#define SP_PIXFORMAT_MASK (0xf << 26)
7133#define SP_FORMAT_YUV422 (0x0 << 26)
7134#define SP_FORMAT_8BPP (0x2 << 26)
7135#define SP_FORMAT_BGR565 (0x5 << 26)
7136#define SP_FORMAT_BGRX8888 (0x6 << 26)
7137#define SP_FORMAT_BGRA8888 (0x7 << 26)
7138#define SP_FORMAT_RGBX1010102 (0x8 << 26)
7139#define SP_FORMAT_RGBA1010102 (0x9 << 26)
7140#define SP_FORMAT_BGRX1010102 (0xa << 26)
7141#define SP_FORMAT_BGRA1010102 (0xb << 26)
7142#define SP_FORMAT_RGBX8888 (0xe << 26)
7143#define SP_FORMAT_RGBA8888 (0xf << 26)
7144#define SP_ALPHA_PREMULTIPLY (1 << 23)
7145#define SP_SOURCE_KEY (1 << 22)
7146#define SP_YUV_FORMAT_BT709 (1 << 18)
7147#define SP_YUV_ORDER_MASK (3 << 16)
7148#define SP_YUV_ORDER_YUYV (0 << 16)
7149#define SP_YUV_ORDER_UYVY (1 << 16)
7150#define SP_YUV_ORDER_YVYU (2 << 16)
7151#define SP_YUV_ORDER_VYUY (3 << 16)
7152#define SP_ROTATE_180 (1 << 15)
7153#define SP_TILED (1 << 10)
7154#define SP_MIRROR (1 << 8)
7155#define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184)
7156#define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188)
7157#define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c)
7158#define _SPASIZE (VLV_DISPLAY_BASE + 0x72190)
7159#define _SPAKEYMINVAL (VLV_DISPLAY_BASE + 0x72194)
7160#define _SPAKEYMSK (VLV_DISPLAY_BASE + 0x72198)
7161#define _SPASURF (VLV_DISPLAY_BASE + 0x7219c)
7162#define _SPAKEYMAXVAL (VLV_DISPLAY_BASE + 0x721a0)
7163#define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4)
7164#define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8)
7165#define SP_CONST_ALPHA_ENABLE (1 << 31)
7166#define _SPACLRC0 (VLV_DISPLAY_BASE + 0x721d0)
7167#define SP_CONTRAST(x) ((x) << 18)
7168#define SP_BRIGHTNESS(x) ((x) & 0xff)
7169#define _SPACLRC1 (VLV_DISPLAY_BASE + 0x721d4)
7170#define SP_SH_SIN(x) (((x) & 0x7ff) << 16)
7171#define SP_SH_COS(x) (x)
7172#define _SPAGAMC (VLV_DISPLAY_BASE + 0x721e0)
7173
7174#define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280)
7175#define _SPBLINOFF (VLV_DISPLAY_BASE + 0x72284)
7176#define _SPBSTRIDE (VLV_DISPLAY_BASE + 0x72288)
7177#define _SPBPOS (VLV_DISPLAY_BASE + 0x7228c)
7178#define _SPBSIZE (VLV_DISPLAY_BASE + 0x72290)
7179#define _SPBKEYMINVAL (VLV_DISPLAY_BASE + 0x72294)
7180#define _SPBKEYMSK (VLV_DISPLAY_BASE + 0x72298)
7181#define _SPBSURF (VLV_DISPLAY_BASE + 0x7229c)
7182#define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0)
7183#define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4)
7184#define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8)
7185#define _SPBCLRC0 (VLV_DISPLAY_BASE + 0x722d0)
7186#define _SPBCLRC1 (VLV_DISPLAY_BASE + 0x722d4)
7187#define _SPBGAMC (VLV_DISPLAY_BASE + 0x722e0)
7188
7189#define _VLV_SPR(pipe, plane_id, reg_a, reg_b) \
7190 _PIPE((pipe) * 2 + (plane_id) - PLANE_SPRITE0, (reg_a), (reg_b))
7191#define _MMIO_VLV_SPR(pipe, plane_id, reg_a, reg_b) \
7192 _MMIO(_VLV_SPR((pipe), (plane_id), (reg_a), (reg_b)))
7193
7194#define SPCNTR(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACNTR, _SPBCNTR)
7195#define SPLINOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPALINOFF, _SPBLINOFF)
7196#define SPSTRIDE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASTRIDE, _SPBSTRIDE)
7197#define SPPOS(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAPOS, _SPBPOS)
7198#define SPSIZE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASIZE, _SPBSIZE)
7199#define SPKEYMINVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMINVAL, _SPBKEYMINVAL)
7200#define SPKEYMSK(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMSK, _SPBKEYMSK)
7201#define SPSURF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASURF, _SPBSURF)
7202#define SPKEYMAXVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMAXVAL, _SPBKEYMAXVAL)
7203#define SPTILEOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPATILEOFF, _SPBTILEOFF)
7204#define SPCONSTALPHA(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACONSTALPHA, _SPBCONSTALPHA)
7205#define SPCLRC0(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC0, _SPBCLRC0)
7206#define SPCLRC1(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC1, _SPBCLRC1)
7207#define SPGAMC(pipe, plane_id, i) _MMIO(_VLV_SPR((pipe), (plane_id), _SPAGAMC, _SPBGAMC) + (5 - (i)) * 4)
7208
7209
7210
7211
7212
7213
7214
7215
7216#define _MMIO_CHV_SPCSC(plane_id, reg) \
7217 _MMIO(VLV_DISPLAY_BASE + ((plane_id) - PLANE_SPRITE0) * 0x1000 + (reg))
7218
7219#define SPCSCYGOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d900)
7220#define SPCSCCBOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d904)
7221#define SPCSCCROFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d908)
7222#define SPCSC_OOFF(x) (((x) & 0x7ff) << 16)
7223#define SPCSC_IOFF(x) (((x) & 0x7ff) << 0)
7224
7225#define SPCSCC01(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d90c)
7226#define SPCSCC23(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d910)
7227#define SPCSCC45(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d914)
7228#define SPCSCC67(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d918)
7229#define SPCSCC8(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d91c)
7230#define SPCSC_C1(x) (((x) & 0x7fff) << 16)
7231#define SPCSC_C0(x) (((x) & 0x7fff) << 0)
7232
7233#define SPCSCYGICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d920)
7234#define SPCSCCBICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d924)
7235#define SPCSCCRICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d928)
7236#define SPCSC_IMAX(x) (((x) & 0x7ff) << 16)
7237#define SPCSC_IMIN(x) (((x) & 0x7ff) << 0)
7238
7239#define SPCSCYGOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d92c)
7240#define SPCSCCBOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d930)
7241#define SPCSCCROCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d934)
7242#define SPCSC_OMAX(x) ((x) << 16)
7243#define SPCSC_OMIN(x) ((x) << 0)
7244
7245
7246
7247#define _PLANE_CTL_1_A 0x70180
7248#define _PLANE_CTL_2_A 0x70280
7249#define _PLANE_CTL_3_A 0x70380
7250#define PLANE_CTL_ENABLE (1 << 31)
7251#define PLANE_CTL_ARB_SLOTS_MASK REG_GENMASK(30, 28)
7252#define PLANE_CTL_ARB_SLOTS(x) REG_FIELD_PREP(PLANE_CTL_ARB_SLOTS_MASK, (x))
7253#define PLANE_CTL_PIPE_GAMMA_ENABLE (1 << 30)
7254#define PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE (1 << 28)
7255
7256
7257
7258
7259
7260#define PLANE_CTL_FORMAT_MASK (0xf << 24)
7261#define PLANE_CTL_FORMAT_YUV422 (0 << 24)
7262#define PLANE_CTL_FORMAT_NV12 (1 << 24)
7263#define PLANE_CTL_FORMAT_XRGB_2101010 (2 << 24)
7264#define PLANE_CTL_FORMAT_P010 (3 << 24)
7265#define PLANE_CTL_FORMAT_XRGB_8888 (4 << 24)
7266#define PLANE_CTL_FORMAT_P012 (5 << 24)
7267#define PLANE_CTL_FORMAT_XRGB_16161616F (6 << 24)
7268#define PLANE_CTL_FORMAT_P016 (7 << 24)
7269#define PLANE_CTL_FORMAT_XYUV (8 << 24)
7270#define PLANE_CTL_FORMAT_INDEXED (12 << 24)
7271#define PLANE_CTL_FORMAT_RGB_565 (14 << 24)
7272#define ICL_PLANE_CTL_FORMAT_MASK (0x1f << 23)
7273#define PLANE_CTL_PIPE_CSC_ENABLE (1 << 23)
7274#define PLANE_CTL_FORMAT_Y210 (1 << 23)
7275#define PLANE_CTL_FORMAT_Y212 (3 << 23)
7276#define PLANE_CTL_FORMAT_Y216 (5 << 23)
7277#define PLANE_CTL_FORMAT_Y410 (7 << 23)
7278#define PLANE_CTL_FORMAT_Y412 (9 << 23)
7279#define PLANE_CTL_FORMAT_Y416 (0xb << 23)
7280#define PLANE_CTL_KEY_ENABLE_MASK (0x3 << 21)
7281#define PLANE_CTL_KEY_ENABLE_SOURCE (1 << 21)
7282#define PLANE_CTL_KEY_ENABLE_DESTINATION (2 << 21)
7283#define PLANE_CTL_ORDER_BGRX (0 << 20)
7284#define PLANE_CTL_ORDER_RGBX (1 << 20)
7285#define PLANE_CTL_YUV420_Y_PLANE (1 << 19)
7286#define PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709 (1 << 18)
7287#define PLANE_CTL_YUV422_ORDER_MASK (0x3 << 16)
7288#define PLANE_CTL_YUV422_ORDER_YUYV (0 << 16)
7289#define PLANE_CTL_YUV422_ORDER_UYVY (1 << 16)
7290#define PLANE_CTL_YUV422_ORDER_YVYU (2 << 16)
7291#define PLANE_CTL_YUV422_ORDER_VYUY (3 << 16)
7292#define PLANE_CTL_RENDER_DECOMPRESSION_ENABLE (1 << 15)
7293#define PLANE_CTL_TRICKLE_FEED_DISABLE (1 << 14)
7294#define PLANE_CTL_CLEAR_COLOR_DISABLE (1 << 13)
7295#define PLANE_CTL_PLANE_GAMMA_DISABLE (1 << 13)
7296#define PLANE_CTL_TILED_MASK (0x7 << 10)
7297#define PLANE_CTL_TILED_LINEAR (0 << 10)
7298#define PLANE_CTL_TILED_X (1 << 10)
7299#define PLANE_CTL_TILED_Y (4 << 10)
7300#define PLANE_CTL_TILED_YF (5 << 10)
7301#define PLANE_CTL_ASYNC_FLIP (1 << 9)
7302#define PLANE_CTL_FLIP_HORIZONTAL (1 << 8)
7303#define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE (1 << 4)
7304#define PLANE_CTL_ALPHA_MASK (0x3 << 4)
7305#define PLANE_CTL_ALPHA_DISABLE (0 << 4)
7306#define PLANE_CTL_ALPHA_SW_PREMULTIPLY (2 << 4)
7307#define PLANE_CTL_ALPHA_HW_PREMULTIPLY (3 << 4)
7308#define PLANE_CTL_ROTATE_MASK 0x3
7309#define PLANE_CTL_ROTATE_0 0x0
7310#define PLANE_CTL_ROTATE_90 0x1
7311#define PLANE_CTL_ROTATE_180 0x2
7312#define PLANE_CTL_ROTATE_270 0x3
7313#define _PLANE_STRIDE_1_A 0x70188
7314#define _PLANE_STRIDE_2_A 0x70288
7315#define _PLANE_STRIDE_3_A 0x70388
7316#define _PLANE_POS_1_A 0x7018c
7317#define _PLANE_POS_2_A 0x7028c
7318#define _PLANE_POS_3_A 0x7038c
7319#define _PLANE_SIZE_1_A 0x70190
7320#define _PLANE_SIZE_2_A 0x70290
7321#define _PLANE_SIZE_3_A 0x70390
7322#define _PLANE_SURF_1_A 0x7019c
7323#define _PLANE_SURF_2_A 0x7029c
7324#define _PLANE_SURF_3_A 0x7039c
7325#define _PLANE_OFFSET_1_A 0x701a4
7326#define _PLANE_OFFSET_2_A 0x702a4
7327#define _PLANE_OFFSET_3_A 0x703a4
7328#define _PLANE_KEYVAL_1_A 0x70194
7329#define _PLANE_KEYVAL_2_A 0x70294
7330#define _PLANE_KEYMSK_1_A 0x70198
7331#define _PLANE_KEYMSK_2_A 0x70298
7332#define PLANE_KEYMSK_ALPHA_ENABLE (1 << 31)
7333#define _PLANE_KEYMAX_1_A 0x701a0
7334#define _PLANE_KEYMAX_2_A 0x702a0
7335#define PLANE_KEYMAX_ALPHA(a) ((a) << 24)
7336#define _PLANE_CC_VAL_1_A 0x701b4
7337#define _PLANE_CC_VAL_2_A 0x702b4
7338#define _PLANE_AUX_DIST_1_A 0x701c0
7339#define _PLANE_AUX_DIST_2_A 0x702c0
7340#define _PLANE_AUX_OFFSET_1_A 0x701c4
7341#define _PLANE_AUX_OFFSET_2_A 0x702c4
7342#define _PLANE_CUS_CTL_1_A 0x701c8
7343#define _PLANE_CUS_CTL_2_A 0x702c8
7344#define PLANE_CUS_ENABLE (1 << 31)
7345#define PLANE_CUS_Y_PLANE_4_RKL (0 << 30)
7346#define PLANE_CUS_Y_PLANE_5_RKL (1 << 30)
7347#define PLANE_CUS_Y_PLANE_6_ICL (0 << 30)
7348#define PLANE_CUS_Y_PLANE_7_ICL (1 << 30)
7349#define PLANE_CUS_HPHASE_SIGN_NEGATIVE (1 << 19)
7350#define PLANE_CUS_HPHASE_0 (0 << 16)
7351#define PLANE_CUS_HPHASE_0_25 (1 << 16)
7352#define PLANE_CUS_HPHASE_0_5 (2 << 16)
7353#define PLANE_CUS_VPHASE_SIGN_NEGATIVE (1 << 15)
7354#define PLANE_CUS_VPHASE_0 (0 << 12)
7355#define PLANE_CUS_VPHASE_0_25 (1 << 12)
7356#define PLANE_CUS_VPHASE_0_5 (2 << 12)
7357#define _PLANE_COLOR_CTL_1_A 0x701CC
7358#define _PLANE_COLOR_CTL_2_A 0x702CC
7359#define _PLANE_COLOR_CTL_3_A 0x703CC
7360#define PLANE_COLOR_PIPE_GAMMA_ENABLE (1 << 30)
7361#define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE (1 << 28)
7362#define PLANE_COLOR_PLANE_CSC_ENABLE REG_BIT(21)
7363#define PLANE_COLOR_INPUT_CSC_ENABLE (1 << 20)
7364#define PLANE_COLOR_PIPE_CSC_ENABLE (1 << 23)
7365#define PLANE_COLOR_CSC_MODE_BYPASS (0 << 17)
7366#define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB601 (1 << 17)
7367#define PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709 (2 << 17)
7368#define PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020 (3 << 17)
7369#define PLANE_COLOR_CSC_MODE_RGB709_TO_RGB2020 (4 << 17)
7370#define PLANE_COLOR_PLANE_GAMMA_DISABLE (1 << 13)
7371#define PLANE_COLOR_ALPHA_MASK (0x3 << 4)
7372#define PLANE_COLOR_ALPHA_DISABLE (0 << 4)
7373#define PLANE_COLOR_ALPHA_SW_PREMULTIPLY (2 << 4)
7374#define PLANE_COLOR_ALPHA_HW_PREMULTIPLY (3 << 4)
7375#define _PLANE_BUF_CFG_1_A 0x7027c
7376#define _PLANE_BUF_CFG_2_A 0x7037c
7377#define _PLANE_NV12_BUF_CFG_1_A 0x70278
7378#define _PLANE_NV12_BUF_CFG_2_A 0x70378
7379
7380#define _PLANE_CC_VAL_1_B 0x711b4
7381#define _PLANE_CC_VAL_2_B 0x712b4
7382#define _PLANE_CC_VAL_1(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_1_A, _PLANE_CC_VAL_1_B) + (dw) * 4)
7383#define _PLANE_CC_VAL_2(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_2_A, _PLANE_CC_VAL_2_B) + (dw) * 4)
7384#define PLANE_CC_VAL(pipe, plane, dw) \
7385 _MMIO_PLANE((plane), _PLANE_CC_VAL_1((pipe), (dw)), _PLANE_CC_VAL_2((pipe), (dw)))
7386
7387
7388#define _PLANE_INPUT_CSC_RY_GY_1_A 0x701E0
7389#define _PLANE_INPUT_CSC_RY_GY_2_A 0x702E0
7390
7391#define _PLANE_INPUT_CSC_RY_GY_1_B 0x711E0
7392#define _PLANE_INPUT_CSC_RY_GY_2_B 0x712E0
7393
7394#define _PLANE_INPUT_CSC_RY_GY_1(pipe) \
7395 _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_1_A, \
7396 _PLANE_INPUT_CSC_RY_GY_1_B)
7397#define _PLANE_INPUT_CSC_RY_GY_2(pipe) \
7398 _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_2_A, \
7399 _PLANE_INPUT_CSC_RY_GY_2_B)
7400
7401#define PLANE_INPUT_CSC_COEFF(pipe, plane, index) \
7402 _MMIO_PLANE(plane, _PLANE_INPUT_CSC_RY_GY_1(pipe) + (index) * 4, \
7403 _PLANE_INPUT_CSC_RY_GY_2(pipe) + (index) * 4)
7404
7405#define _PLANE_INPUT_CSC_PREOFF_HI_1_A 0x701F8
7406#define _PLANE_INPUT_CSC_PREOFF_HI_2_A 0x702F8
7407
7408#define _PLANE_INPUT_CSC_PREOFF_HI_1_B 0x711F8
7409#define _PLANE_INPUT_CSC_PREOFF_HI_2_B 0x712F8
7410
7411#define _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) \
7412 _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_1_A, \
7413 _PLANE_INPUT_CSC_PREOFF_HI_1_B)
7414#define _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) \
7415 _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_2_A, \
7416 _PLANE_INPUT_CSC_PREOFF_HI_2_B)
7417#define PLANE_INPUT_CSC_PREOFF(pipe, plane, index) \
7418 _MMIO_PLANE(plane, _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) + (index) * 4, \
7419 _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) + (index) * 4)
7420
7421#define _PLANE_INPUT_CSC_POSTOFF_HI_1_A 0x70204
7422#define _PLANE_INPUT_CSC_POSTOFF_HI_2_A 0x70304
7423
7424#define _PLANE_INPUT_CSC_POSTOFF_HI_1_B 0x71204
7425#define _PLANE_INPUT_CSC_POSTOFF_HI_2_B 0x71304
7426
7427#define _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) \
7428 _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_1_A, \
7429 _PLANE_INPUT_CSC_POSTOFF_HI_1_B)
7430#define _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) \
7431 _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_2_A, \
7432 _PLANE_INPUT_CSC_POSTOFF_HI_2_B)
7433#define PLANE_INPUT_CSC_POSTOFF(pipe, plane, index) \
7434 _MMIO_PLANE(plane, _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) + (index) * 4, \
7435 _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) + (index) * 4)
7436
7437#define _PLANE_CTL_1_B 0x71180
7438#define _PLANE_CTL_2_B 0x71280
7439#define _PLANE_CTL_3_B 0x71380
7440#define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B)
7441#define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B)
7442#define _PLANE_CTL_3(pipe) _PIPE(pipe, _PLANE_CTL_3_A, _PLANE_CTL_3_B)
7443#define PLANE_CTL(pipe, plane) \
7444 _MMIO_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe))
7445
7446#define _PLANE_STRIDE_1_B 0x71188
7447#define _PLANE_STRIDE_2_B 0x71288
7448#define _PLANE_STRIDE_3_B 0x71388
7449#define _PLANE_STRIDE_1(pipe) \
7450 _PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B)
7451#define _PLANE_STRIDE_2(pipe) \
7452 _PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B)
7453#define _PLANE_STRIDE_3(pipe) \
7454 _PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B)
7455#define PLANE_STRIDE(pipe, plane) \
7456 _MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe))
7457#define PLANE_STRIDE_MASK REG_GENMASK(10, 0)
7458#define PLANE_STRIDE_MASK_XELPD REG_GENMASK(11, 0)
7459
7460#define _PLANE_POS_1_B 0x7118c
7461#define _PLANE_POS_2_B 0x7128c
7462#define _PLANE_POS_3_B 0x7138c
7463#define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B)
7464#define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B)
7465#define _PLANE_POS_3(pipe) _PIPE(pipe, _PLANE_POS_3_A, _PLANE_POS_3_B)
7466#define PLANE_POS(pipe, plane) \
7467 _MMIO_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe))
7468
7469#define _PLANE_SIZE_1_B 0x71190
7470#define _PLANE_SIZE_2_B 0x71290
7471#define _PLANE_SIZE_3_B 0x71390
7472#define _PLANE_SIZE_1(pipe) _PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B)
7473#define _PLANE_SIZE_2(pipe) _PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B)
7474#define _PLANE_SIZE_3(pipe) _PIPE(pipe, _PLANE_SIZE_3_A, _PLANE_SIZE_3_B)
7475#define PLANE_SIZE(pipe, plane) \
7476 _MMIO_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe))
7477
7478#define _PLANE_SURF_1_B 0x7119c
7479#define _PLANE_SURF_2_B 0x7129c
7480#define _PLANE_SURF_3_B 0x7139c
7481#define _PLANE_SURF_1(pipe) _PIPE(pipe, _PLANE_SURF_1_A, _PLANE_SURF_1_B)
7482#define _PLANE_SURF_2(pipe) _PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B)
7483#define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B)
7484#define PLANE_SURF(pipe, plane) \
7485 _MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
7486#define PLANE_SURF_DECRYPT REG_BIT(2)
7487
7488#define _PLANE_OFFSET_1_B 0x711a4
7489#define _PLANE_OFFSET_2_B 0x712a4
7490#define _PLANE_OFFSET_1(pipe) _PIPE(pipe, _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B)
7491#define _PLANE_OFFSET_2(pipe) _PIPE(pipe, _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B)
7492#define PLANE_OFFSET(pipe, plane) \
7493 _MMIO_PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe))
7494
7495#define _PLANE_KEYVAL_1_B 0x71194
7496#define _PLANE_KEYVAL_2_B 0x71294
7497#define _PLANE_KEYVAL_1(pipe) _PIPE(pipe, _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B)
7498#define _PLANE_KEYVAL_2(pipe) _PIPE(pipe, _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B)
7499#define PLANE_KEYVAL(pipe, plane) \
7500 _MMIO_PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe))
7501
7502#define _PLANE_KEYMSK_1_B 0x71198
7503#define _PLANE_KEYMSK_2_B 0x71298
7504#define _PLANE_KEYMSK_1(pipe) _PIPE(pipe, _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B)
7505#define _PLANE_KEYMSK_2(pipe) _PIPE(pipe, _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B)
7506#define PLANE_KEYMSK(pipe, plane) \
7507 _MMIO_PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe))
7508
7509#define _PLANE_KEYMAX_1_B 0x711a0
7510#define _PLANE_KEYMAX_2_B 0x712a0
7511#define _PLANE_KEYMAX_1(pipe) _PIPE(pipe, _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B)
7512#define _PLANE_KEYMAX_2(pipe) _PIPE(pipe, _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B)
7513#define PLANE_KEYMAX(pipe, plane) \
7514 _MMIO_PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe))
7515
7516#define _PLANE_BUF_CFG_1_B 0x7127c
7517#define _PLANE_BUF_CFG_2_B 0x7137c
7518#define DDB_ENTRY_MASK 0xFFF
7519#define DDB_ENTRY_END_SHIFT 16
7520#define _PLANE_BUF_CFG_1(pipe) \
7521 _PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B)
7522#define _PLANE_BUF_CFG_2(pipe) \
7523 _PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B)
7524#define PLANE_BUF_CFG(pipe, plane) \
7525 _MMIO_PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe))
7526
7527#define _PLANE_NV12_BUF_CFG_1_B 0x71278
7528#define _PLANE_NV12_BUF_CFG_2_B 0x71378
7529#define _PLANE_NV12_BUF_CFG_1(pipe) \
7530 _PIPE(pipe, _PLANE_NV12_BUF_CFG_1_A, _PLANE_NV12_BUF_CFG_1_B)
7531#define _PLANE_NV12_BUF_CFG_2(pipe) \
7532 _PIPE(pipe, _PLANE_NV12_BUF_CFG_2_A, _PLANE_NV12_BUF_CFG_2_B)
7533#define PLANE_NV12_BUF_CFG(pipe, plane) \
7534 _MMIO_PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe))
7535
7536#define _PLANE_AUX_DIST_1_B 0x711c0
7537#define _PLANE_AUX_DIST_2_B 0x712c0
7538#define _PLANE_AUX_DIST_1(pipe) \
7539 _PIPE(pipe, _PLANE_AUX_DIST_1_A, _PLANE_AUX_DIST_1_B)
7540#define _PLANE_AUX_DIST_2(pipe) \
7541 _PIPE(pipe, _PLANE_AUX_DIST_2_A, _PLANE_AUX_DIST_2_B)
7542#define PLANE_AUX_DIST(pipe, plane) \
7543 _MMIO_PLANE(plane, _PLANE_AUX_DIST_1(pipe), _PLANE_AUX_DIST_2(pipe))
7544
7545#define _PLANE_AUX_OFFSET_1_B 0x711c4
7546#define _PLANE_AUX_OFFSET_2_B 0x712c4
7547#define _PLANE_AUX_OFFSET_1(pipe) \
7548 _PIPE(pipe, _PLANE_AUX_OFFSET_1_A, _PLANE_AUX_OFFSET_1_B)
7549#define _PLANE_AUX_OFFSET_2(pipe) \
7550 _PIPE(pipe, _PLANE_AUX_OFFSET_2_A, _PLANE_AUX_OFFSET_2_B)
7551#define PLANE_AUX_OFFSET(pipe, plane) \
7552 _MMIO_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe), _PLANE_AUX_OFFSET_2(pipe))
7553
7554#define _PLANE_CUS_CTL_1_B 0x711c8
7555#define _PLANE_CUS_CTL_2_B 0x712c8
7556#define _PLANE_CUS_CTL_1(pipe) \
7557 _PIPE(pipe, _PLANE_CUS_CTL_1_A, _PLANE_CUS_CTL_1_B)
7558#define _PLANE_CUS_CTL_2(pipe) \
7559 _PIPE(pipe, _PLANE_CUS_CTL_2_A, _PLANE_CUS_CTL_2_B)
7560#define PLANE_CUS_CTL(pipe, plane) \
7561 _MMIO_PLANE(plane, _PLANE_CUS_CTL_1(pipe), _PLANE_CUS_CTL_2(pipe))
7562
7563#define _PLANE_COLOR_CTL_1_B 0x711CC
7564#define _PLANE_COLOR_CTL_2_B 0x712CC
7565#define _PLANE_COLOR_CTL_3_B 0x713CC
7566#define _PLANE_COLOR_CTL_1(pipe) \
7567 _PIPE(pipe, _PLANE_COLOR_CTL_1_A, _PLANE_COLOR_CTL_1_B)
7568#define _PLANE_COLOR_CTL_2(pipe) \
7569 _PIPE(pipe, _PLANE_COLOR_CTL_2_A, _PLANE_COLOR_CTL_2_B)
7570#define PLANE_COLOR_CTL(pipe, plane) \
7571 _MMIO_PLANE(plane, _PLANE_COLOR_CTL_1(pipe), _PLANE_COLOR_CTL_2(pipe))
7572
7573#define _SEL_FETCH_PLANE_BASE_1_A 0x70890
7574#define _SEL_FETCH_PLANE_BASE_2_A 0x708B0
7575#define _SEL_FETCH_PLANE_BASE_3_A 0x708D0
7576#define _SEL_FETCH_PLANE_BASE_4_A 0x708F0
7577#define _SEL_FETCH_PLANE_BASE_5_A 0x70920
7578#define _SEL_FETCH_PLANE_BASE_6_A 0x70940
7579#define _SEL_FETCH_PLANE_BASE_7_A 0x70960
7580#define _SEL_FETCH_PLANE_BASE_CUR_A 0x70880
7581#define _SEL_FETCH_PLANE_BASE_1_B 0x70990
7582
7583#define _SEL_FETCH_PLANE_BASE_A(plane) _PICK(plane, \
7584 _SEL_FETCH_PLANE_BASE_1_A, \
7585 _SEL_FETCH_PLANE_BASE_2_A, \
7586 _SEL_FETCH_PLANE_BASE_3_A, \
7587 _SEL_FETCH_PLANE_BASE_4_A, \
7588 _SEL_FETCH_PLANE_BASE_5_A, \
7589 _SEL_FETCH_PLANE_BASE_6_A, \
7590 _SEL_FETCH_PLANE_BASE_7_A, \
7591 _SEL_FETCH_PLANE_BASE_CUR_A)
7592#define _SEL_FETCH_PLANE_BASE_1(pipe) _PIPE(pipe, _SEL_FETCH_PLANE_BASE_1_A, _SEL_FETCH_PLANE_BASE_1_B)
7593#define _SEL_FETCH_PLANE_BASE(pipe, plane) (_SEL_FETCH_PLANE_BASE_1(pipe) - \
7594 _SEL_FETCH_PLANE_BASE_1_A + \
7595 _SEL_FETCH_PLANE_BASE_A(plane))
7596
7597#define _SEL_FETCH_PLANE_CTL_1_A 0x70890
7598#define PLANE_SEL_FETCH_CTL(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \
7599 _SEL_FETCH_PLANE_CTL_1_A - \
7600 _SEL_FETCH_PLANE_BASE_1_A)
7601#define PLANE_SEL_FETCH_CTL_ENABLE REG_BIT(31)
7602
7603#define _SEL_FETCH_PLANE_POS_1_A 0x70894
7604#define PLANE_SEL_FETCH_POS(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \
7605 _SEL_FETCH_PLANE_POS_1_A - \
7606 _SEL_FETCH_PLANE_BASE_1_A)
7607
7608#define _SEL_FETCH_PLANE_SIZE_1_A 0x70898
7609#define PLANE_SEL_FETCH_SIZE(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \
7610 _SEL_FETCH_PLANE_SIZE_1_A - \
7611 _SEL_FETCH_PLANE_BASE_1_A)
7612
7613#define _SEL_FETCH_PLANE_OFFSET_1_A 0x7089C
7614#define PLANE_SEL_FETCH_OFFSET(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \
7615 _SEL_FETCH_PLANE_OFFSET_1_A - \
7616 _SEL_FETCH_PLANE_BASE_1_A)
7617
7618
7619#define _CUR_BUF_CFG_A 0x7017c
7620#define _CUR_BUF_CFG_B 0x7117c
7621#define CUR_BUF_CFG(pipe) _MMIO_PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B)
7622
7623
7624#define VGACNTRL _MMIO(0x71400)
7625# define VGA_DISP_DISABLE (1 << 31)
7626# define VGA_2X_MODE (1 << 30)
7627# define VGA_PIPE_B_SELECT (1 << 29)
7628
7629#define VLV_VGACNTRL _MMIO(VLV_DISPLAY_BASE + 0x71400)
7630
7631
7632
7633#define CPU_VGACNTRL _MMIO(0x41000)
7634
7635#define DIGITAL_PORT_HOTPLUG_CNTRL _MMIO(0x44030)
7636#define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4)
7637#define DIGITAL_PORTA_PULSE_DURATION_2ms (0 << 2)
7638#define DIGITAL_PORTA_PULSE_DURATION_4_5ms (1 << 2)
7639#define DIGITAL_PORTA_PULSE_DURATION_6ms (2 << 2)
7640#define DIGITAL_PORTA_PULSE_DURATION_100ms (3 << 2)
7641#define DIGITAL_PORTA_PULSE_DURATION_MASK (3 << 2)
7642#define DIGITAL_PORTA_HOTPLUG_STATUS_MASK (3 << 0)
7643#define DIGITAL_PORTA_HOTPLUG_NO_DETECT (0 << 0)
7644#define DIGITAL_PORTA_HOTPLUG_SHORT_DETECT (1 << 0)
7645#define DIGITAL_PORTA_HOTPLUG_LONG_DETECT (2 << 0)
7646
7647
7648#define RR_HW_CTL _MMIO(0x45300)
7649#define RR_HW_LOW_POWER_FRAMES_MASK 0xff
7650#define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00
7651
7652#define FDI_PLL_BIOS_0 _MMIO(0x46000)
7653#define FDI_PLL_FB_CLOCK_MASK 0xff
7654#define FDI_PLL_BIOS_1 _MMIO(0x46004)
7655#define FDI_PLL_BIOS_2 _MMIO(0x46008)
7656#define DISPLAY_PORT_PLL_BIOS_0 _MMIO(0x4600c)
7657#define DISPLAY_PORT_PLL_BIOS_1 _MMIO(0x46010)
7658#define DISPLAY_PORT_PLL_BIOS_2 _MMIO(0x46014)
7659
7660#define PCH_3DCGDIS0 _MMIO(0x46020)
7661# define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18)
7662# define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1)
7663
7664#define PCH_3DCGDIS1 _MMIO(0x46024)
7665# define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11)
7666
7667#define FDI_PLL_FREQ_CTL _MMIO(0x46030)
7668#define FDI_PLL_FREQ_CHANGE_REQUEST (1 << 24)
7669#define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00
7670#define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff
7671
7672
7673#define _PIPEA_DATA_M1 0x60030
7674#define PIPE_DATA_M1_OFFSET 0
7675#define _PIPEA_DATA_N1 0x60034
7676#define PIPE_DATA_N1_OFFSET 0
7677
7678#define _PIPEA_DATA_M2 0x60038
7679#define PIPE_DATA_M2_OFFSET 0
7680#define _PIPEA_DATA_N2 0x6003c
7681#define PIPE_DATA_N2_OFFSET 0
7682
7683#define _PIPEA_LINK_M1 0x60040
7684#define PIPE_LINK_M1_OFFSET 0
7685#define _PIPEA_LINK_N1 0x60044
7686#define PIPE_LINK_N1_OFFSET 0
7687
7688#define _PIPEA_LINK_M2 0x60048
7689#define PIPE_LINK_M2_OFFSET 0
7690#define _PIPEA_LINK_N2 0x6004c
7691#define PIPE_LINK_N2_OFFSET 0
7692
7693
7694
7695#define _PIPEB_DATA_M1 0x61030
7696#define _PIPEB_DATA_N1 0x61034
7697#define _PIPEB_DATA_M2 0x61038
7698#define _PIPEB_DATA_N2 0x6103c
7699#define _PIPEB_LINK_M1 0x61040
7700#define _PIPEB_LINK_N1 0x61044
7701#define _PIPEB_LINK_M2 0x61048
7702#define _PIPEB_LINK_N2 0x6104c
7703
7704#define PIPE_DATA_M1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M1)
7705#define PIPE_DATA_N1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N1)
7706#define PIPE_DATA_M2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M2)
7707#define PIPE_DATA_N2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N2)
7708#define PIPE_LINK_M1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M1)
7709#define PIPE_LINK_N1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N1)
7710#define PIPE_LINK_M2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M2)
7711#define PIPE_LINK_N2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N2)
7712
7713
7714
7715#define _PFA_CTL_1 0x68080
7716#define _PFB_CTL_1 0x68880
7717#define PF_ENABLE (1 << 31)
7718#define PF_PIPE_SEL_MASK_IVB (3 << 29)
7719#define PF_PIPE_SEL_IVB(pipe) ((pipe) << 29)
7720#define PF_FILTER_MASK (3 << 23)
7721#define PF_FILTER_PROGRAMMED (0 << 23)
7722#define PF_FILTER_MED_3x3 (1 << 23)
7723#define PF_FILTER_EDGE_ENHANCE (2 << 23)
7724#define PF_FILTER_EDGE_SOFTEN (3 << 23)
7725#define _PFA_WIN_SZ 0x68074
7726#define _PFB_WIN_SZ 0x68874
7727#define _PFA_WIN_POS 0x68070
7728#define _PFB_WIN_POS 0x68870
7729#define _PFA_VSCALE 0x68084
7730#define _PFB_VSCALE 0x68884
7731#define _PFA_HSCALE 0x68090
7732#define _PFB_HSCALE 0x68890
7733
7734#define PF_CTL(pipe) _MMIO_PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1)
7735#define PF_WIN_SZ(pipe) _MMIO_PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ)
7736#define PF_WIN_POS(pipe) _MMIO_PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS)
7737#define PF_VSCALE(pipe) _MMIO_PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE)
7738#define PF_HSCALE(pipe) _MMIO_PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)
7739
7740#define _PSA_CTL 0x68180
7741#define _PSB_CTL 0x68980
7742#define PS_ENABLE (1 << 31)
7743#define _PSA_WIN_SZ 0x68174
7744#define _PSB_WIN_SZ 0x68974
7745#define _PSA_WIN_POS 0x68170
7746#define _PSB_WIN_POS 0x68970
7747
7748#define PS_CTL(pipe) _MMIO_PIPE(pipe, _PSA_CTL, _PSB_CTL)
7749#define PS_WIN_SZ(pipe) _MMIO_PIPE(pipe, _PSA_WIN_SZ, _PSB_WIN_SZ)
7750#define PS_WIN_POS(pipe) _MMIO_PIPE(pipe, _PSA_WIN_POS, _PSB_WIN_POS)
7751
7752
7753
7754
7755#define _PS_1A_CTRL 0x68180
7756#define _PS_2A_CTRL 0x68280
7757#define _PS_1B_CTRL 0x68980
7758#define _PS_2B_CTRL 0x68A80
7759#define _PS_1C_CTRL 0x69180
7760#define PS_SCALER_EN (1 << 31)
7761#define SKL_PS_SCALER_MODE_MASK (3 << 28)
7762#define SKL_PS_SCALER_MODE_DYN (0 << 28)
7763#define SKL_PS_SCALER_MODE_HQ (1 << 28)
7764#define SKL_PS_SCALER_MODE_NV12 (2 << 28)
7765#define PS_SCALER_MODE_PLANAR (1 << 29)
7766#define PS_SCALER_MODE_NORMAL (0 << 29)
7767#define PS_PLANE_SEL_MASK (7 << 25)
7768#define PS_PLANE_SEL(plane) (((plane) + 1) << 25)
7769#define PS_FILTER_MASK (3 << 23)
7770#define PS_FILTER_MEDIUM (0 << 23)
7771#define PS_FILTER_PROGRAMMED (1 << 23)
7772#define PS_FILTER_EDGE_ENHANCE (2 << 23)
7773#define PS_FILTER_BILINEAR (3 << 23)
7774#define PS_VERT3TAP (1 << 21)
7775#define PS_VERT_INT_INVERT_FIELD1 (0 << 20)
7776#define PS_VERT_INT_INVERT_FIELD0 (1 << 20)
7777#define PS_PWRUP_PROGRESS (1 << 17)
7778#define PS_V_FILTER_BYPASS (1 << 8)
7779#define PS_VADAPT_EN (1 << 7)
7780#define PS_VADAPT_MODE_MASK (3 << 5)
7781#define PS_VADAPT_MODE_LEAST_ADAPT (0 << 5)
7782#define PS_VADAPT_MODE_MOD_ADAPT (1 << 5)
7783#define PS_VADAPT_MODE_MOST_ADAPT (3 << 5)
7784#define PS_PLANE_Y_SEL_MASK (7 << 5)
7785#define PS_PLANE_Y_SEL(plane) (((plane) + 1) << 5)
7786#define PS_Y_VERT_FILTER_SELECT(set) ((set) << 4)
7787#define PS_Y_HORZ_FILTER_SELECT(set) ((set) << 3)
7788#define PS_UV_VERT_FILTER_SELECT(set) ((set) << 2)
7789#define PS_UV_HORZ_FILTER_SELECT(set) ((set) << 1)
7790
7791#define _PS_PWR_GATE_1A 0x68160
7792#define _PS_PWR_GATE_2A 0x68260
7793#define _PS_PWR_GATE_1B 0x68960
7794#define _PS_PWR_GATE_2B 0x68A60
7795#define _PS_PWR_GATE_1C 0x69160
7796#define PS_PWR_GATE_DIS_OVERRIDE (1 << 31)
7797#define PS_PWR_GATE_SETTLING_TIME_32 (0 << 3)
7798#define PS_PWR_GATE_SETTLING_TIME_64 (1 << 3)
7799#define PS_PWR_GATE_SETTLING_TIME_96 (2 << 3)
7800#define PS_PWR_GATE_SETTLING_TIME_128 (3 << 3)
7801#define PS_PWR_GATE_SLPEN_8 0
7802#define PS_PWR_GATE_SLPEN_16 1
7803#define PS_PWR_GATE_SLPEN_24 2
7804#define PS_PWR_GATE_SLPEN_32 3
7805
7806#define _PS_WIN_POS_1A 0x68170
7807#define _PS_WIN_POS_2A 0x68270
7808#define _PS_WIN_POS_1B 0x68970
7809#define _PS_WIN_POS_2B 0x68A70
7810#define _PS_WIN_POS_1C 0x69170
7811
7812#define _PS_WIN_SZ_1A 0x68174
7813#define _PS_WIN_SZ_2A 0x68274
7814#define _PS_WIN_SZ_1B 0x68974
7815#define _PS_WIN_SZ_2B 0x68A74
7816#define _PS_WIN_SZ_1C 0x69174
7817
7818#define _PS_VSCALE_1A 0x68184
7819#define _PS_VSCALE_2A 0x68284
7820#define _PS_VSCALE_1B 0x68984
7821#define _PS_VSCALE_2B 0x68A84
7822#define _PS_VSCALE_1C 0x69184
7823
7824#define _PS_HSCALE_1A 0x68190
7825#define _PS_HSCALE_2A 0x68290
7826#define _PS_HSCALE_1B 0x68990
7827#define _PS_HSCALE_2B 0x68A90
7828#define _PS_HSCALE_1C 0x69190
7829
7830#define _PS_VPHASE_1A 0x68188
7831#define _PS_VPHASE_2A 0x68288
7832#define _PS_VPHASE_1B 0x68988
7833#define _PS_VPHASE_2B 0x68A88
7834#define _PS_VPHASE_1C 0x69188
7835#define PS_Y_PHASE(x) ((x) << 16)
7836#define PS_UV_RGB_PHASE(x) ((x) << 0)
7837#define PS_PHASE_MASK (0x7fff << 1)
7838#define PS_PHASE_TRIP (1 << 0)
7839
7840#define _PS_HPHASE_1A 0x68194
7841#define _PS_HPHASE_2A 0x68294
7842#define _PS_HPHASE_1B 0x68994
7843#define _PS_HPHASE_2B 0x68A94
7844#define _PS_HPHASE_1C 0x69194
7845
7846#define _PS_ECC_STAT_1A 0x681D0
7847#define _PS_ECC_STAT_2A 0x682D0
7848#define _PS_ECC_STAT_1B 0x689D0
7849#define _PS_ECC_STAT_2B 0x68AD0
7850#define _PS_ECC_STAT_1C 0x691D0
7851
7852#define _PS_COEF_SET0_INDEX_1A 0x68198
7853#define _PS_COEF_SET0_INDEX_2A 0x68298
7854#define _PS_COEF_SET0_INDEX_1B 0x68998
7855#define _PS_COEF_SET0_INDEX_2B 0x68A98
7856#define PS_COEE_INDEX_AUTO_INC (1 << 10)
7857
7858#define _PS_COEF_SET0_DATA_1A 0x6819C
7859#define _PS_COEF_SET0_DATA_2A 0x6829C
7860#define _PS_COEF_SET0_DATA_1B 0x6899C
7861#define _PS_COEF_SET0_DATA_2B 0x68A9C
7862
7863#define _ID(id, a, b) _PICK_EVEN(id, a, b)
7864#define SKL_PS_CTRL(pipe, id) _MMIO_PIPE(pipe, \
7865 _ID(id, _PS_1A_CTRL, _PS_2A_CTRL), \
7866 _ID(id, _PS_1B_CTRL, _PS_2B_CTRL))
7867#define SKL_PS_PWR_GATE(pipe, id) _MMIO_PIPE(pipe, \
7868 _ID(id, _PS_PWR_GATE_1A, _PS_PWR_GATE_2A), \
7869 _ID(id, _PS_PWR_GATE_1B, _PS_PWR_GATE_2B))
7870#define SKL_PS_WIN_POS(pipe, id) _MMIO_PIPE(pipe, \
7871 _ID(id, _PS_WIN_POS_1A, _PS_WIN_POS_2A), \
7872 _ID(id, _PS_WIN_POS_1B, _PS_WIN_POS_2B))
7873#define SKL_PS_WIN_SZ(pipe, id) _MMIO_PIPE(pipe, \
7874 _ID(id, _PS_WIN_SZ_1A, _PS_WIN_SZ_2A), \
7875 _ID(id, _PS_WIN_SZ_1B, _PS_WIN_SZ_2B))
7876#define SKL_PS_VSCALE(pipe, id) _MMIO_PIPE(pipe, \
7877 _ID(id, _PS_VSCALE_1A, _PS_VSCALE_2A), \
7878 _ID(id, _PS_VSCALE_1B, _PS_VSCALE_2B))
7879#define SKL_PS_HSCALE(pipe, id) _MMIO_PIPE(pipe, \
7880 _ID(id, _PS_HSCALE_1A, _PS_HSCALE_2A), \
7881 _ID(id, _PS_HSCALE_1B, _PS_HSCALE_2B))
7882#define SKL_PS_VPHASE(pipe, id) _MMIO_PIPE(pipe, \
7883 _ID(id, _PS_VPHASE_1A, _PS_VPHASE_2A), \
7884 _ID(id, _PS_VPHASE_1B, _PS_VPHASE_2B))
7885#define SKL_PS_HPHASE(pipe, id) _MMIO_PIPE(pipe, \
7886 _ID(id, _PS_HPHASE_1A, _PS_HPHASE_2A), \
7887 _ID(id, _PS_HPHASE_1B, _PS_HPHASE_2B))
7888#define SKL_PS_ECC_STAT(pipe, id) _MMIO_PIPE(pipe, \
7889 _ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A), \
7890 _ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B))
7891#define GLK_PS_COEF_INDEX_SET(pipe, id, set) _MMIO_PIPE(pipe, \
7892 _ID(id, _PS_COEF_SET0_INDEX_1A, _PS_COEF_SET0_INDEX_2A) + (set) * 8, \
7893 _ID(id, _PS_COEF_SET0_INDEX_1B, _PS_COEF_SET0_INDEX_2B) + (set) * 8)
7894
7895#define GLK_PS_COEF_DATA_SET(pipe, id, set) _MMIO_PIPE(pipe, \
7896 _ID(id, _PS_COEF_SET0_DATA_1A, _PS_COEF_SET0_DATA_2A) + (set) * 8, \
7897 _ID(id, _PS_COEF_SET0_DATA_1B, _PS_COEF_SET0_DATA_2B) + (set) * 8)
7898
7899#define _LGC_PALETTE_A 0x4a000
7900#define _LGC_PALETTE_B 0x4a800
7901#define LGC_PALETTE_RED_MASK REG_GENMASK(23, 16)
7902#define LGC_PALETTE_GREEN_MASK REG_GENMASK(15, 8)
7903#define LGC_PALETTE_BLUE_MASK REG_GENMASK(7, 0)
7904#define LGC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) + (i) * 4)
7905
7906
7907#define _PREC_PALETTE_A 0x4b000
7908#define _PREC_PALETTE_B 0x4c000
7909#define PREC_PALETTE_RED_MASK REG_GENMASK(29, 20)
7910#define PREC_PALETTE_GREEN_MASK REG_GENMASK(19, 10)
7911#define PREC_PALETTE_BLUE_MASK REG_GENMASK(9, 0)
7912#define PREC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _PREC_PALETTE_A, _PREC_PALETTE_B) + (i) * 4)
7913
7914#define _PREC_PIPEAGCMAX 0x4d000
7915#define _PREC_PIPEBGCMAX 0x4d010
7916#define PREC_PIPEGCMAX(pipe, i) _MMIO(_PIPE(pipe, _PIPEAGCMAX, _PIPEBGCMAX) + (i) * 4)
7917
7918#define _GAMMA_MODE_A 0x4a480
7919#define _GAMMA_MODE_B 0x4ac80
7920#define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B)
7921#define PRE_CSC_GAMMA_ENABLE (1 << 31)
7922#define POST_CSC_GAMMA_ENABLE (1 << 30)
7923#define GAMMA_MODE_MODE_MASK (3 << 0)
7924#define GAMMA_MODE_MODE_8BIT (0 << 0)
7925#define GAMMA_MODE_MODE_10BIT (1 << 0)
7926#define GAMMA_MODE_MODE_12BIT (2 << 0)
7927#define GAMMA_MODE_MODE_SPLIT (3 << 0)
7928#define GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED (3 << 0)
7929
7930
7931#define DMC_PROGRAM(addr, i) _MMIO((addr) + (i) * 4)
7932#define DMC_SSP_BASE_ADDR_GEN9 0x00002FC0
7933#define DMC_HTP_ADDR_SKL 0x00500034
7934#define DMC_SSP_BASE _MMIO(0x8F074)
7935#define DMC_HTP_SKL _MMIO(0x8F004)
7936#define DMC_LAST_WRITE _MMIO(0x8F034)
7937#define DMC_LAST_WRITE_VALUE 0xc003b400
7938
7939#define DMC_MMIO_START_RANGE 0x80000
7940#define DMC_MMIO_END_RANGE 0x8FFFF
7941#define SKL_DMC_DC3_DC5_COUNT _MMIO(0x80030)
7942#define SKL_DMC_DC5_DC6_COUNT _MMIO(0x8002C)
7943#define BXT_DMC_DC3_DC5_COUNT _MMIO(0x80038)
7944#define TGL_DMC_DEBUG_DC5_COUNT _MMIO(0x101084)
7945#define TGL_DMC_DEBUG_DC6_COUNT _MMIO(0x101088)
7946#define DG1_DMC_DEBUG_DC5_COUNT _MMIO(0x134154)
7947
7948#define DMC_DEBUG3 _MMIO(0x101090)
7949
7950
7951#define RM_TIMEOUT _MMIO(0x42060)
7952#define MMIO_TIMEOUT_US(us) ((us) << 0)
7953
7954
7955#define DE_MASTER_IRQ_CONTROL (1 << 31)
7956#define DE_SPRITEB_FLIP_DONE (1 << 29)
7957#define DE_SPRITEA_FLIP_DONE (1 << 28)
7958#define DE_PLANEB_FLIP_DONE (1 << 27)
7959#define DE_PLANEA_FLIP_DONE (1 << 26)
7960#define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane)))
7961#define DE_PCU_EVENT (1 << 25)
7962#define DE_GTT_FAULT (1 << 24)
7963#define DE_POISON (1 << 23)
7964#define DE_PERFORM_COUNTER (1 << 22)
7965#define DE_PCH_EVENT (1 << 21)
7966#define DE_AUX_CHANNEL_A (1 << 20)
7967#define DE_DP_A_HOTPLUG (1 << 19)
7968#define DE_GSE (1 << 18)
7969#define DE_PIPEB_VBLANK (1 << 15)
7970#define DE_PIPEB_EVEN_FIELD (1 << 14)
7971#define DE_PIPEB_ODD_FIELD (1 << 13)
7972#define DE_PIPEB_LINE_COMPARE (1 << 12)
7973#define DE_PIPEB_VSYNC (1 << 11)
7974#define DE_PIPEB_CRC_DONE (1 << 10)
7975#define DE_PIPEB_FIFO_UNDERRUN (1 << 8)
7976#define DE_PIPEA_VBLANK (1 << 7)
7977#define DE_PIPE_VBLANK(pipe) (1 << (7 + 8 * (pipe)))
7978#define DE_PIPEA_EVEN_FIELD (1 << 6)
7979#define DE_PIPEA_ODD_FIELD (1 << 5)
7980#define DE_PIPEA_LINE_COMPARE (1 << 4)
7981#define DE_PIPEA_VSYNC (1 << 3)
7982#define DE_PIPEA_CRC_DONE (1 << 2)
7983#define DE_PIPE_CRC_DONE(pipe) (1 << (2 + 8 * (pipe)))
7984#define DE_PIPEA_FIFO_UNDERRUN (1 << 0)
7985#define DE_PIPE_FIFO_UNDERRUN(pipe) (1 << (8 * (pipe)))
7986
7987
7988#define DE_ERR_INT_IVB (1 << 30)
7989#define DE_GSE_IVB (1 << 29)
7990#define DE_PCH_EVENT_IVB (1 << 28)
7991#define DE_DP_A_HOTPLUG_IVB (1 << 27)
7992#define DE_AUX_CHANNEL_A_IVB (1 << 26)
7993#define DE_EDP_PSR_INT_HSW (1 << 19)
7994#define DE_SPRITEC_FLIP_DONE_IVB (1 << 14)
7995#define DE_PLANEC_FLIP_DONE_IVB (1 << 13)
7996#define DE_PIPEC_VBLANK_IVB (1 << 10)
7997#define DE_SPRITEB_FLIP_DONE_IVB (1 << 9)
7998#define DE_PLANEB_FLIP_DONE_IVB (1 << 8)
7999#define DE_PIPEB_VBLANK_IVB (1 << 5)
8000#define DE_SPRITEA_FLIP_DONE_IVB (1 << 4)
8001#define DE_PLANEA_FLIP_DONE_IVB (1 << 3)
8002#define DE_PLANE_FLIP_DONE_IVB(plane) (1 << (3 + 5 * (plane)))
8003#define DE_PIPEA_VBLANK_IVB (1 << 0)
8004#define DE_PIPE_VBLANK_IVB(pipe) (1 << ((pipe) * 5))
8005
8006#define VLV_MASTER_IER _MMIO(0x4400c)
8007#define MASTER_INTERRUPT_ENABLE (1 << 31)
8008
8009#define DEISR _MMIO(0x44000)
8010#define DEIMR _MMIO(0x44004)
8011#define DEIIR _MMIO(0x44008)
8012#define DEIER _MMIO(0x4400c)
8013
8014#define GTISR _MMIO(0x44010)
8015#define GTIMR _MMIO(0x44014)
8016#define GTIIR _MMIO(0x44018)
8017#define GTIER _MMIO(0x4401c)
8018
8019#define GEN8_MASTER_IRQ _MMIO(0x44200)
8020#define GEN8_MASTER_IRQ_CONTROL (1 << 31)
8021#define GEN8_PCU_IRQ (1 << 30)
8022#define GEN8_DE_PCH_IRQ (1 << 23)
8023#define GEN8_DE_MISC_IRQ (1 << 22)
8024#define GEN8_DE_PORT_IRQ (1 << 20)
8025#define GEN8_DE_PIPE_C_IRQ (1 << 18)
8026#define GEN8_DE_PIPE_B_IRQ (1 << 17)
8027#define GEN8_DE_PIPE_A_IRQ (1 << 16)
8028#define GEN8_DE_PIPE_IRQ(pipe) (1 << (16 + (pipe)))
8029#define GEN8_GT_VECS_IRQ (1 << 6)
8030#define GEN8_GT_GUC_IRQ (1 << 5)
8031#define GEN8_GT_PM_IRQ (1 << 4)
8032#define GEN8_GT_VCS1_IRQ (1 << 3)
8033#define GEN8_GT_VCS0_IRQ (1 << 2)
8034#define GEN8_GT_BCS_IRQ (1 << 1)
8035#define GEN8_GT_RCS_IRQ (1 << 0)
8036
8037#define XELPD_DISPLAY_ERR_FATAL_MASK _MMIO(0x4421c)
8038
8039#define GEN8_GT_ISR(which) _MMIO(0x44300 + (0x10 * (which)))
8040#define GEN8_GT_IMR(which) _MMIO(0x44304 + (0x10 * (which)))
8041#define GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which)))
8042#define GEN8_GT_IER(which) _MMIO(0x4430c + (0x10 * (which)))
8043
8044#define GEN8_RCS_IRQ_SHIFT 0
8045#define GEN8_BCS_IRQ_SHIFT 16
8046#define GEN8_VCS0_IRQ_SHIFT 0
8047#define GEN8_VCS1_IRQ_SHIFT 16
8048#define GEN8_VECS_IRQ_SHIFT 0
8049#define GEN8_WD_IRQ_SHIFT 16
8050
8051#define GEN8_DE_PIPE_ISR(pipe) _MMIO(0x44400 + (0x10 * (pipe)))
8052#define GEN8_DE_PIPE_IMR(pipe) _MMIO(0x44404 + (0x10 * (pipe)))
8053#define GEN8_DE_PIPE_IIR(pipe) _MMIO(0x44408 + (0x10 * (pipe)))
8054#define GEN8_DE_PIPE_IER(pipe) _MMIO(0x4440c + (0x10 * (pipe)))
8055#define GEN8_PIPE_FIFO_UNDERRUN (1 << 31)
8056#define GEN8_PIPE_CDCLK_CRC_ERROR (1 << 29)
8057#define GEN8_PIPE_CDCLK_CRC_DONE (1 << 28)
8058#define XELPD_PIPE_SOFT_UNDERRUN (1 << 22)
8059#define XELPD_PIPE_HARD_UNDERRUN (1 << 21)
8060#define GEN8_PIPE_CURSOR_FAULT (1 << 10)
8061#define GEN8_PIPE_SPRITE_FAULT (1 << 9)
8062#define GEN8_PIPE_PRIMARY_FAULT (1 << 8)
8063#define GEN8_PIPE_SPRITE_FLIP_DONE (1 << 5)
8064#define GEN8_PIPE_PRIMARY_FLIP_DONE (1 << 4)
8065#define GEN8_PIPE_SCAN_LINE_EVENT (1 << 2)
8066#define GEN8_PIPE_VSYNC (1 << 1)
8067#define GEN8_PIPE_VBLANK (1 << 0)
8068#define GEN9_PIPE_CURSOR_FAULT (1 << 11)
8069#define GEN11_PIPE_PLANE7_FAULT (1 << 22)
8070#define GEN11_PIPE_PLANE6_FAULT (1 << 21)
8071#define GEN11_PIPE_PLANE5_FAULT (1 << 20)
8072#define GEN9_PIPE_PLANE4_FAULT (1 << 10)
8073#define GEN9_PIPE_PLANE3_FAULT (1 << 9)
8074#define GEN9_PIPE_PLANE2_FAULT (1 << 8)
8075#define GEN9_PIPE_PLANE1_FAULT (1 << 7)
8076#define GEN9_PIPE_PLANE4_FLIP_DONE (1 << 6)
8077#define GEN9_PIPE_PLANE3_FLIP_DONE (1 << 5)
8078#define GEN9_PIPE_PLANE2_FLIP_DONE (1 << 4)
8079#define GEN9_PIPE_PLANE1_FLIP_DONE (1 << 3)
8080#define GEN9_PIPE_PLANE_FLIP_DONE(p) (1 << (3 + (p)))
8081#define GEN8_DE_PIPE_IRQ_FAULT_ERRORS \
8082 (GEN8_PIPE_CURSOR_FAULT | \
8083 GEN8_PIPE_SPRITE_FAULT | \
8084 GEN8_PIPE_PRIMARY_FAULT)
8085#define GEN9_DE_PIPE_IRQ_FAULT_ERRORS \
8086 (GEN9_PIPE_CURSOR_FAULT | \
8087 GEN9_PIPE_PLANE4_FAULT | \
8088 GEN9_PIPE_PLANE3_FAULT | \
8089 GEN9_PIPE_PLANE2_FAULT | \
8090 GEN9_PIPE_PLANE1_FAULT)
8091#define GEN11_DE_PIPE_IRQ_FAULT_ERRORS \
8092 (GEN9_DE_PIPE_IRQ_FAULT_ERRORS | \
8093 GEN11_PIPE_PLANE7_FAULT | \
8094 GEN11_PIPE_PLANE6_FAULT | \
8095 GEN11_PIPE_PLANE5_FAULT)
8096#define RKL_DE_PIPE_IRQ_FAULT_ERRORS \
8097 (GEN9_DE_PIPE_IRQ_FAULT_ERRORS | \
8098 GEN11_PIPE_PLANE5_FAULT)
8099
8100#define _HPD_PIN_DDI(hpd_pin) ((hpd_pin) - HPD_PORT_A)
8101#define _HPD_PIN_TC(hpd_pin) ((hpd_pin) - HPD_PORT_TC1)
8102
8103#define GEN8_DE_PORT_ISR _MMIO(0x44440)
8104#define GEN8_DE_PORT_IMR _MMIO(0x44444)
8105#define GEN8_DE_PORT_IIR _MMIO(0x44448)
8106#define GEN8_DE_PORT_IER _MMIO(0x4444c)
8107#define DSI1_NON_TE (1 << 31)
8108#define DSI0_NON_TE (1 << 30)
8109#define ICL_AUX_CHANNEL_E (1 << 29)
8110#define ICL_AUX_CHANNEL_F (1 << 28)
8111#define GEN9_AUX_CHANNEL_D (1 << 27)
8112#define GEN9_AUX_CHANNEL_C (1 << 26)
8113#define GEN9_AUX_CHANNEL_B (1 << 25)
8114#define DSI1_TE (1 << 24)
8115#define DSI0_TE (1 << 23)
8116#define GEN8_DE_PORT_HOTPLUG(hpd_pin) REG_BIT(3 + _HPD_PIN_DDI(hpd_pin))
8117#define BXT_DE_PORT_HOTPLUG_MASK (GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) | \
8118 GEN8_DE_PORT_HOTPLUG(HPD_PORT_B) | \
8119 GEN8_DE_PORT_HOTPLUG(HPD_PORT_C))
8120#define BDW_DE_PORT_HOTPLUG_MASK GEN8_DE_PORT_HOTPLUG(HPD_PORT_A)
8121#define BXT_DE_PORT_GMBUS (1 << 1)
8122#define GEN8_AUX_CHANNEL_A (1 << 0)
8123#define TGL_DE_PORT_AUX_USBC6 REG_BIT(13)
8124#define XELPD_DE_PORT_AUX_DDIE REG_BIT(13)
8125#define TGL_DE_PORT_AUX_USBC5 REG_BIT(12)
8126#define XELPD_DE_PORT_AUX_DDID REG_BIT(12)
8127#define TGL_DE_PORT_AUX_USBC4 REG_BIT(11)
8128#define TGL_DE_PORT_AUX_USBC3 REG_BIT(10)
8129#define TGL_DE_PORT_AUX_USBC2 REG_BIT(9)
8130#define TGL_DE_PORT_AUX_USBC1 REG_BIT(8)
8131#define TGL_DE_PORT_AUX_DDIC REG_BIT(2)
8132#define TGL_DE_PORT_AUX_DDIB REG_BIT(1)
8133#define TGL_DE_PORT_AUX_DDIA REG_BIT(0)
8134
8135#define GEN8_DE_MISC_ISR _MMIO(0x44460)
8136#define GEN8_DE_MISC_IMR _MMIO(0x44464)
8137#define GEN8_DE_MISC_IIR _MMIO(0x44468)
8138#define GEN8_DE_MISC_IER _MMIO(0x4446c)
8139#define GEN8_DE_MISC_GSE (1 << 27)
8140#define GEN8_DE_EDP_PSR (1 << 19)
8141
8142#define GEN8_PCU_ISR _MMIO(0x444e0)
8143#define GEN8_PCU_IMR _MMIO(0x444e4)
8144#define GEN8_PCU_IIR _MMIO(0x444e8)
8145#define GEN8_PCU_IER _MMIO(0x444ec)
8146
8147#define GEN11_GU_MISC_ISR _MMIO(0x444f0)
8148#define GEN11_GU_MISC_IMR _MMIO(0x444f4)
8149#define GEN11_GU_MISC_IIR _MMIO(0x444f8)
8150#define GEN11_GU_MISC_IER _MMIO(0x444fc)
8151#define GEN11_GU_MISC_GSE (1 << 27)
8152
8153#define GEN11_GFX_MSTR_IRQ _MMIO(0x190010)
8154#define GEN11_MASTER_IRQ (1 << 31)
8155#define GEN11_PCU_IRQ (1 << 30)
8156#define GEN11_GU_MISC_IRQ (1 << 29)
8157#define GEN11_DISPLAY_IRQ (1 << 16)
8158#define GEN11_GT_DW_IRQ(x) (1 << (x))
8159#define GEN11_GT_DW1_IRQ (1 << 1)
8160#define GEN11_GT_DW0_IRQ (1 << 0)
8161
8162#define DG1_MSTR_TILE_INTR _MMIO(0x190008)
8163#define DG1_MSTR_IRQ REG_BIT(31)
8164#define DG1_MSTR_TILE(t) REG_BIT(t)
8165
8166#define GEN11_DISPLAY_INT_CTL _MMIO(0x44200)
8167#define GEN11_DISPLAY_IRQ_ENABLE (1 << 31)
8168#define GEN11_AUDIO_CODEC_IRQ (1 << 24)
8169#define GEN11_DE_PCH_IRQ (1 << 23)
8170#define GEN11_DE_MISC_IRQ (1 << 22)
8171#define GEN11_DE_HPD_IRQ (1 << 21)
8172#define GEN11_DE_PORT_IRQ (1 << 20)
8173#define GEN11_DE_PIPE_C (1 << 18)
8174#define GEN11_DE_PIPE_B (1 << 17)
8175#define GEN11_DE_PIPE_A (1 << 16)
8176
8177#define GEN11_DE_HPD_ISR _MMIO(0x44470)
8178#define GEN11_DE_HPD_IMR _MMIO(0x44474)
8179#define GEN11_DE_HPD_IIR _MMIO(0x44478)
8180#define GEN11_DE_HPD_IER _MMIO(0x4447c)
8181#define GEN11_TC_HOTPLUG(hpd_pin) REG_BIT(16 + _HPD_PIN_TC(hpd_pin))
8182#define GEN11_DE_TC_HOTPLUG_MASK (GEN11_TC_HOTPLUG(HPD_PORT_TC6) | \
8183 GEN11_TC_HOTPLUG(HPD_PORT_TC5) | \
8184 GEN11_TC_HOTPLUG(HPD_PORT_TC4) | \
8185 GEN11_TC_HOTPLUG(HPD_PORT_TC3) | \
8186 GEN11_TC_HOTPLUG(HPD_PORT_TC2) | \
8187 GEN11_TC_HOTPLUG(HPD_PORT_TC1))
8188#define GEN11_TBT_HOTPLUG(hpd_pin) REG_BIT(_HPD_PIN_TC(hpd_pin))
8189#define GEN11_DE_TBT_HOTPLUG_MASK (GEN11_TBT_HOTPLUG(HPD_PORT_TC6) | \
8190 GEN11_TBT_HOTPLUG(HPD_PORT_TC5) | \
8191 GEN11_TBT_HOTPLUG(HPD_PORT_TC4) | \
8192 GEN11_TBT_HOTPLUG(HPD_PORT_TC3) | \
8193 GEN11_TBT_HOTPLUG(HPD_PORT_TC2) | \
8194 GEN11_TBT_HOTPLUG(HPD_PORT_TC1))
8195
8196#define GEN11_TBT_HOTPLUG_CTL _MMIO(0x44030)
8197#define GEN11_TC_HOTPLUG_CTL _MMIO(0x44038)
8198#define GEN11_HOTPLUG_CTL_ENABLE(hpd_pin) (8 << (_HPD_PIN_TC(hpd_pin) * 4))
8199#define GEN11_HOTPLUG_CTL_LONG_DETECT(hpd_pin) (2 << (_HPD_PIN_TC(hpd_pin) * 4))
8200#define GEN11_HOTPLUG_CTL_SHORT_DETECT(hpd_pin) (1 << (_HPD_PIN_TC(hpd_pin) * 4))
8201#define GEN11_HOTPLUG_CTL_NO_DETECT(hpd_pin) (0 << (_HPD_PIN_TC(hpd_pin) * 4))
8202
8203#define GEN11_GT_INTR_DW0 _MMIO(0x190018)
8204#define GEN11_CSME (31)
8205#define GEN11_GUNIT (28)
8206#define GEN11_GUC (25)
8207#define GEN11_WDPERF (20)
8208#define GEN11_KCR (19)
8209#define GEN11_GTPM (16)
8210#define GEN11_BCS (15)
8211#define GEN11_RCS0 (0)
8212
8213#define GEN11_GT_INTR_DW1 _MMIO(0x19001c)
8214#define GEN11_VECS(x) (31 - (x))
8215#define GEN11_VCS(x) (x)
8216
8217#define GEN11_GT_INTR_DW(x) _MMIO(0x190018 + ((x) * 4))
8218
8219#define GEN11_INTR_IDENTITY_REG0 _MMIO(0x190060)
8220#define GEN11_INTR_IDENTITY_REG1 _MMIO(0x190064)
8221#define GEN11_INTR_DATA_VALID (1 << 31)
8222#define GEN11_INTR_ENGINE_CLASS(x) (((x) & GENMASK(18, 16)) >> 16)
8223#define GEN11_INTR_ENGINE_INSTANCE(x) (((x) & GENMASK(25, 20)) >> 20)
8224#define GEN11_INTR_ENGINE_INTR(x) ((x) & 0xffff)
8225
8226#define OTHER_GUC_INSTANCE 0
8227#define OTHER_GTPM_INSTANCE 1
8228#define OTHER_KCR_INSTANCE 4
8229
8230#define GEN11_INTR_IDENTITY_REG(x) _MMIO(0x190060 + ((x) * 4))
8231
8232#define GEN11_IIR_REG0_SELECTOR _MMIO(0x190070)
8233#define GEN11_IIR_REG1_SELECTOR _MMIO(0x190074)
8234
8235#define GEN11_IIR_REG_SELECTOR(x) _MMIO(0x190070 + ((x) * 4))
8236
8237#define GEN11_RENDER_COPY_INTR_ENABLE _MMIO(0x190030)
8238#define GEN11_VCS_VECS_INTR_ENABLE _MMIO(0x190034)
8239#define GEN11_GUC_SG_INTR_ENABLE _MMIO(0x190038)
8240#define GEN11_GPM_WGBOXPERF_INTR_ENABLE _MMIO(0x19003c)
8241#define GEN11_CRYPTO_RSVD_INTR_ENABLE _MMIO(0x190040)
8242#define GEN11_GUNIT_CSME_INTR_ENABLE _MMIO(0x190044)
8243
8244#define GEN11_RCS0_RSVD_INTR_MASK _MMIO(0x190090)
8245#define GEN11_BCS_RSVD_INTR_MASK _MMIO(0x1900a0)
8246#define GEN11_VCS0_VCS1_INTR_MASK _MMIO(0x1900a8)
8247#define GEN11_VCS2_VCS3_INTR_MASK _MMIO(0x1900ac)
8248#define GEN12_VCS4_VCS5_INTR_MASK _MMIO(0x1900b0)
8249#define GEN12_VCS6_VCS7_INTR_MASK _MMIO(0x1900b4)
8250#define GEN11_VECS0_VECS1_INTR_MASK _MMIO(0x1900d0)
8251#define GEN12_VECS2_VECS3_INTR_MASK _MMIO(0x1900d4)
8252#define GEN11_GUC_SG_INTR_MASK _MMIO(0x1900e8)
8253#define GEN11_GPM_WGBOXPERF_INTR_MASK _MMIO(0x1900ec)
8254#define GEN11_CRYPTO_RSVD_INTR_MASK _MMIO(0x1900f0)
8255#define GEN11_GUNIT_CSME_INTR_MASK _MMIO(0x1900f4)
8256
8257#define ENGINE1_MASK REG_GENMASK(31, 16)
8258#define ENGINE0_MASK REG_GENMASK(15, 0)
8259
8260#define ILK_DISPLAY_CHICKEN2 _MMIO(0x42004)
8261
8262#define ILK_ELPIN_409_SELECT (1 << 25)
8263#define ILK_DPARB_GATE (1 << 22)
8264#define ILK_VSDPFD_FULL (1 << 21)
8265#define FUSE_STRAP _MMIO(0x42014)
8266#define ILK_INTERNAL_GRAPHICS_DISABLE (1 << 31)
8267#define ILK_INTERNAL_DISPLAY_DISABLE (1 << 30)
8268#define ILK_DISPLAY_DEBUG_DISABLE (1 << 29)
8269#define IVB_PIPE_C_DISABLE (1 << 28)
8270#define ILK_HDCP_DISABLE (1 << 25)
8271#define ILK_eDP_A_DISABLE (1 << 24)
8272#define HSW_CDCLK_LIMIT (1 << 24)
8273#define ILK_DESKTOP (1 << 23)
8274#define HSW_CPU_SSC_ENABLE (1 << 21)
8275
8276#define FUSE_STRAP3 _MMIO(0x42020)
8277#define HSW_REF_CLK_SELECT (1 << 1)
8278
8279#define ILK_DSPCLK_GATE_D _MMIO(0x42020)
8280#define ILK_VRHUNIT_CLOCK_GATE_DISABLE (1 << 28)
8281#define ILK_DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9)
8282#define ILK_DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8)
8283#define ILK_DPFDUNIT_CLOCK_GATE_ENABLE (1 << 7)
8284#define ILK_DPARBUNIT_CLOCK_GATE_ENABLE (1 << 5)
8285
8286#define IVB_CHICKEN3 _MMIO(0x4200c)
8287# define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5)
8288# define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2)
8289
8290#define CHICKEN_PAR1_1 _MMIO(0x42080)
8291#define IGNORE_KVMR_PIPE_A REG_BIT(23)
8292#define KBL_ARB_FILL_SPARE_22 REG_BIT(22)
8293#define DIS_RAM_BYPASS_PSR2_MAN_TRACK (1 << 16)
8294#define SKL_DE_COMPRESSED_HASH_MODE (1 << 15)
8295#define DPA_MASK_VBLANK_SRD (1 << 15)
8296#define FORCE_ARB_IDLE_PLANES (1 << 14)
8297#define SKL_EDP_PSR_FIX_RDWRAP (1 << 3)
8298#define IGNORE_PSR2_HW_TRACKING (1 << 1)
8299
8300#define CHICKEN_PAR2_1 _MMIO(0x42090)
8301#define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT (1 << 14)
8302
8303#define CHICKEN_MISC_2 _MMIO(0x42084)
8304#define KBL_ARB_FILL_SPARE_14 REG_BIT(14)
8305#define KBL_ARB_FILL_SPARE_13 REG_BIT(13)
8306#define GLK_CL2_PWR_DOWN (1 << 12)
8307#define GLK_CL1_PWR_DOWN (1 << 11)
8308#define GLK_CL0_PWR_DOWN (1 << 10)
8309
8310#define CHICKEN_MISC_4 _MMIO(0x4208c)
8311#define CHICKEN_FBC_STRIDE_OVERRIDE REG_BIT(13)
8312#define CHICKEN_FBC_STRIDE_MASK REG_GENMASK(12, 0)
8313#define CHICKEN_FBC_STRIDE(x) REG_FIELD_PREP(CHICKEN_FBC_STRIDE_MASK, (x))
8314
8315#define _CHICKEN_PIPESL_1_A 0x420b0
8316#define _CHICKEN_PIPESL_1_B 0x420b4
8317#define HSW_PRI_STRETCH_MAX_MASK REG_GENMASK(28, 27)
8318#define HSW_PRI_STRETCH_MAX_X8 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 0)
8319#define HSW_PRI_STRETCH_MAX_X4 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 1)
8320#define HSW_PRI_STRETCH_MAX_X2 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 2)
8321#define HSW_PRI_STRETCH_MAX_X1 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 3)
8322#define HSW_SPR_STRETCH_MAX_MASK REG_GENMASK(26, 25)
8323#define HSW_SPR_STRETCH_MAX_X8 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 0)
8324#define HSW_SPR_STRETCH_MAX_X4 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 1)
8325#define HSW_SPR_STRETCH_MAX_X2 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 2)
8326#define HSW_SPR_STRETCH_MAX_X1 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 3)
8327#define HSW_FBCQ_DIS (1 << 22)
8328#define BDW_DPRS_MASK_VBLANK_SRD (1 << 0)
8329#define SKL_PLANE1_STRETCH_MAX_MASK REG_GENMASK(1, 0)
8330#define SKL_PLANE1_STRETCH_MAX_X8 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 0)
8331#define SKL_PLANE1_STRETCH_MAX_X4 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 1)
8332#define SKL_PLANE1_STRETCH_MAX_X2 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 2)
8333#define SKL_PLANE1_STRETCH_MAX_X1 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 3)
8334#define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
8335
8336#define _CHICKEN_TRANS_A 0x420c0
8337#define _CHICKEN_TRANS_B 0x420c4
8338#define _CHICKEN_TRANS_C 0x420c8
8339#define _CHICKEN_TRANS_EDP 0x420cc
8340#define _CHICKEN_TRANS_D 0x420d8
8341#define CHICKEN_TRANS(trans) _MMIO(_PICK((trans), \
8342 [TRANSCODER_EDP] = _CHICKEN_TRANS_EDP, \
8343 [TRANSCODER_A] = _CHICKEN_TRANS_A, \
8344 [TRANSCODER_B] = _CHICKEN_TRANS_B, \
8345 [TRANSCODER_C] = _CHICKEN_TRANS_C, \
8346 [TRANSCODER_D] = _CHICKEN_TRANS_D))
8347#define HSW_FRAME_START_DELAY_MASK REG_GENMASK(28, 27)
8348#define HSW_FRAME_START_DELAY(x) REG_FIELD_PREP(HSW_FRAME_START_DELAY_MASK, x)
8349#define VSC_DATA_SEL_SOFTWARE_CONTROL REG_BIT(25)
8350#define FECSTALL_DIS_DPTSTREAM_DPTTG REG_BIT(23)
8351#define DDI_TRAINING_OVERRIDE_ENABLE REG_BIT(19)
8352#define ADLP_1_BASED_X_GRANULARITY REG_BIT(18)
8353#define DDI_TRAINING_OVERRIDE_VALUE REG_BIT(18)
8354#define DDIE_TRAINING_OVERRIDE_ENABLE REG_BIT(17)
8355#define DDIE_TRAINING_OVERRIDE_VALUE REG_BIT(16)
8356#define PSR2_ADD_VERTICAL_LINE_COUNT REG_BIT(15)
8357#define PSR2_VSC_ENABLE_PROG_HEADER REG_BIT(12)
8358
8359#define DISP_ARB_CTL _MMIO(0x45000)
8360#define DISP_FBC_MEMORY_WAKE (1 << 31)
8361#define DISP_TILE_SURFACE_SWIZZLING (1 << 13)
8362#define DISP_FBC_WM_DIS (1 << 15)
8363#define DISP_ARB_CTL2 _MMIO(0x45004)
8364#define DISP_DATA_PARTITION_5_6 (1 << 6)
8365#define DISP_IPC_ENABLE (1 << 3)
8366
8367
8368
8369
8370
8371
8372
8373
8374
8375#define _DBUF_CTL_S0 0x45008
8376#define _DBUF_CTL_S1 0x44FE8
8377#define _DBUF_CTL_S2 0x44300
8378#define _DBUF_CTL_S3 0x44304
8379#define DBUF_CTL_S(slice) _MMIO(_PICK(slice, \
8380 _DBUF_CTL_S0, \
8381 _DBUF_CTL_S1, \
8382 _DBUF_CTL_S2, \
8383 _DBUF_CTL_S3))
8384#define DBUF_POWER_REQUEST REG_BIT(31)
8385#define DBUF_POWER_STATE REG_BIT(30)
8386#define DBUF_TRACKER_STATE_SERVICE_MASK REG_GENMASK(23, 19)
8387#define DBUF_TRACKER_STATE_SERVICE(x) REG_FIELD_PREP(DBUF_TRACKER_STATE_SERVICE_MASK, x)
8388#define DBUF_MIN_TRACKER_STATE_SERVICE_MASK REG_GENMASK(18, 16)
8389#define DBUF_MIN_TRACKER_STATE_SERVICE(x) REG_FIELD_PREP(DBUF_MIN_TRACKER_STATE_SERVICE_MASK, x)
8390
8391#define GEN7_MSG_CTL _MMIO(0x45010)
8392#define WAIT_FOR_PCH_RESET_ACK (1 << 1)
8393#define WAIT_FOR_PCH_FLR_ACK (1 << 0)
8394
8395#define _BW_BUDDY0_CTL 0x45130
8396#define _BW_BUDDY1_CTL 0x45140
8397#define BW_BUDDY_CTL(x) _MMIO(_PICK_EVEN(x, \
8398 _BW_BUDDY0_CTL, \
8399 _BW_BUDDY1_CTL))
8400#define BW_BUDDY_DISABLE REG_BIT(31)
8401#define BW_BUDDY_TLB_REQ_TIMER_MASK REG_GENMASK(21, 16)
8402#define BW_BUDDY_TLB_REQ_TIMER(x) REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, x)
8403
8404#define _BW_BUDDY0_PAGE_MASK 0x45134
8405#define _BW_BUDDY1_PAGE_MASK 0x45144
8406#define BW_BUDDY_PAGE_MASK(x) _MMIO(_PICK_EVEN(x, \
8407 _BW_BUDDY0_PAGE_MASK, \
8408 _BW_BUDDY1_PAGE_MASK))
8409
8410#define HSW_NDE_RSTWRN_OPT _MMIO(0x46408)
8411#define RESET_PCH_HANDSHAKE_ENABLE (1 << 4)
8412
8413#define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430)
8414#define SKL_SELECT_ALTERNATE_DC_EXIT REG_BIT(30)
8415#define ICL_DELAY_PMRSP REG_BIT(22)
8416#define DISABLE_FLR_SRC REG_BIT(15)
8417#define MASK_WAKEMEM REG_BIT(13)
8418
8419#define GEN11_CHICKEN_DCPR_2 _MMIO(0x46434)
8420#define DCPR_MASK_MAXLATENCY_MEMUP_CLR REG_BIT(27)
8421#define DCPR_MASK_LPMODE REG_BIT(26)
8422#define DCPR_SEND_RESP_IMM REG_BIT(25)
8423#define DCPR_CLEAR_MEMSTAT_DIS REG_BIT(24)
8424
8425#define SKL_DFSM _MMIO(0x51000)
8426#define SKL_DFSM_DISPLAY_PM_DISABLE (1 << 27)
8427#define SKL_DFSM_DISPLAY_HDCP_DISABLE (1 << 25)
8428#define SKL_DFSM_CDCLK_LIMIT_MASK (3 << 23)
8429#define SKL_DFSM_CDCLK_LIMIT_675 (0 << 23)
8430#define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23)
8431#define SKL_DFSM_CDCLK_LIMIT_450 (2 << 23)
8432#define SKL_DFSM_CDCLK_LIMIT_337_5 (3 << 23)
8433#define ICL_DFSM_DMC_DISABLE (1 << 23)
8434#define SKL_DFSM_PIPE_A_DISABLE (1 << 30)
8435#define SKL_DFSM_PIPE_B_DISABLE (1 << 21)
8436#define SKL_DFSM_PIPE_C_DISABLE (1 << 28)
8437#define TGL_DFSM_PIPE_D_DISABLE (1 << 22)
8438#define GLK_DFSM_DISPLAY_DSC_DISABLE (1 << 7)
8439
8440#define SKL_DSSM _MMIO(0x51004)
8441#define ICL_DSSM_CDCLK_PLL_REFCLK_MASK (7 << 29)
8442#define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz (0 << 29)
8443#define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz (1 << 29)
8444#define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz (2 << 29)
8445
8446#define GEN7_FF_SLICE_CS_CHICKEN1 _MMIO(0x20e0)
8447#define GEN9_FFSC_PERCTX_PREEMPT_CTRL (1 << 14)
8448
8449#define FF_SLICE_CS_CHICKEN2 _MMIO(0x20e4)
8450#define GEN9_TSG_BARRIER_ACK_DISABLE (1 << 8)
8451#define GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE (1 << 10)
8452
8453#define GEN9_CS_DEBUG_MODE1 _MMIO(0x20ec)
8454#define FF_DOP_CLOCK_GATE_DISABLE REG_BIT(1)
8455#define GEN9_CTX_PREEMPT_REG _MMIO(0x2248)
8456#define GEN12_DISABLE_POSH_BUSY_FF_DOP_CG REG_BIT(11)
8457
8458#define GEN12_CS_DEBUG_MODE1_CCCSUNIT_BE_COMMON _MMIO(0x20EC)
8459#define GEN12_REPLAY_MODE_GRANULARITY REG_BIT(0)
8460
8461#define GEN8_CS_CHICKEN1 _MMIO(0x2580)
8462#define GEN9_PREEMPT_3D_OBJECT_LEVEL (1 << 0)
8463#define GEN9_PREEMPT_GPGPU_LEVEL(hi, lo) (((hi) << 2) | ((lo) << 1))
8464#define GEN9_PREEMPT_GPGPU_MID_THREAD_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(0, 0)
8465#define GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(0, 1)
8466#define GEN9_PREEMPT_GPGPU_COMMAND_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(1, 0)
8467#define GEN9_PREEMPT_GPGPU_LEVEL_MASK GEN9_PREEMPT_GPGPU_LEVEL(1, 1)
8468
8469
8470#define GEN7_COMMON_SLICE_CHICKEN1 _MMIO(0x7010)
8471 #define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC (1 << 10)
8472 #define GEN9_RHWO_OPTIMIZATION_DISABLE (1 << 14)
8473
8474#define COMMON_SLICE_CHICKEN2 _MMIO(0x7014)
8475 #define GEN9_PBE_COMPRESSED_HASH_SELECTION (1 << 13)
8476 #define GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE (1 << 12)
8477 #define GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION (1 << 8)
8478 #define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1 << 0)
8479
8480#define GEN8_L3CNTLREG _MMIO(0x7034)
8481 #define GEN8_ERRDETBCTRL (1 << 9)
8482
8483#define GEN11_COMMON_SLICE_CHICKEN3 _MMIO(0x7304)
8484#define DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN REG_BIT(12)
8485#define XEHP_DUAL_SIMD8_SEQ_MERGE_DISABLE REG_BIT(12)
8486#define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC REG_BIT(11)
8487#define GEN12_DISABLE_CPS_AWARE_COLOR_PIPE REG_BIT(9)
8488
8489#define HIZ_CHICKEN _MMIO(0x7018)
8490# define CHV_HZ_8X8_MODE_IN_1X REG_BIT(15)
8491# define DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE REG_BIT(14)
8492# define BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE REG_BIT(3)
8493
8494#define GEN9_SLICE_COMMON_ECO_CHICKEN0 _MMIO(0x7308)
8495#define DISABLE_PIXEL_MASK_CAMMING (1 << 14)
8496
8497#define GEN9_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c)
8498#define GEN11_STATE_CACHE_REDIRECT_TO_CS (1 << 11)
8499
8500#define GEN7_SARCHKMD _MMIO(0xB000)
8501#define GEN7_DISABLE_DEMAND_PREFETCH (1 << 31)
8502#define GEN7_DISABLE_SAMPLER_PREFETCH (1 << 30)
8503
8504#define GEN7_L3SQCREG1 _MMIO(0xB010)
8505#define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000
8506
8507#define GEN8_L3SQCREG1 _MMIO(0xB100)
8508
8509
8510
8511
8512
8513
8514#define L3_GENERAL_PRIO_CREDITS(x) (((x) >> 1) << 19)
8515#define L3_HIGH_PRIO_CREDITS(x) (((x) >> 1) << 14)
8516#define L3_PRIO_CREDITS_MASK ((0x1f << 19) | (0x1f << 14))
8517
8518#define GEN7_L3CNTLREG1 _MMIO(0xB01C)
8519#define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C47FF8C
8520#define GEN7_L3AGDIS (1 << 19)
8521#define GEN7_L3CNTLREG2 _MMIO(0xB020)
8522#define GEN7_L3CNTLREG3 _MMIO(0xB024)
8523
8524#define GEN7_L3_CHICKEN_MODE_REGISTER _MMIO(0xB030)
8525#define GEN7_WA_L3_CHICKEN_MODE 0x20000000
8526#define GEN10_L3_CHICKEN_MODE_REGISTER _MMIO(0xB114)
8527#define GEN11_I2M_WRITE_DISABLE (1 << 28)
8528
8529#define GEN7_L3SQCREG4 _MMIO(0xb034)
8530#define L3SQ_URB_READ_CAM_MATCH_DISABLE (1 << 27)
8531
8532#define GEN11_SCRATCH2 _MMIO(0xb140)
8533#define GEN11_COHERENT_PARTIAL_WRITE_MERGE_ENABLE (1 << 19)
8534
8535#define GEN8_L3SQCREG4 _MMIO(0xb118)
8536#define GEN11_LQSC_CLEAN_EVICT_DISABLE (1 << 6)
8537#define GEN8_LQSC_RO_PERF_DIS (1 << 27)
8538#define GEN8_LQSC_FLUSH_COHERENT_LINES (1 << 21)
8539#define GEN8_LQSQ_NONIA_COHERENT_ATOMICS_ENABLE REG_BIT(22)
8540
8541#define GEN11_L3SQCREG5 _MMIO(0xb158)
8542#define L3_PWM_TIMER_INIT_VAL_MASK REG_GENMASK(9, 0)
8543
8544#define XEHP_L3SCQREG7 _MMIO(0xb188)
8545#define BLEND_FILL_CACHING_OPT_DIS REG_BIT(3)
8546
8547
8548#define HDC_CHICKEN0 _MMIO(0x7300)
8549#define ICL_HDC_MODE _MMIO(0xE5F4)
8550#define HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE (1 << 15)
8551#define HDC_FENCE_DEST_SLM_DISABLE (1 << 14)
8552#define HDC_DONOT_FETCH_MEM_WHEN_MASKED (1 << 11)
8553#define HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT (1 << 5)
8554#define HDC_FORCE_NON_COHERENT (1 << 4)
8555#define HDC_BARRIER_PERFORMANCE_DISABLE (1 << 10)
8556
8557#define GEN12_HDC_CHICKEN0 _MMIO(0xE5F0)
8558#define LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK REG_GENMASK(13, 11)
8559
8560#define SARB_CHICKEN1 _MMIO(0xe90c)
8561#define COMP_CKN_IN REG_GENMASK(30, 29)
8562
8563#define GEN8_HDC_CHICKEN1 _MMIO(0x7304)
8564
8565
8566#define SLICE_ECO_CHICKEN0 _MMIO(0x7308)
8567#define PIXEL_MASK_CAMMING_DISABLE (1 << 14)
8568
8569#define GEN9_WM_CHICKEN3 _MMIO(0x5588)
8570#define GEN9_FACTOR_IN_CLR_VAL_HIZ (1 << 9)
8571
8572
8573#define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG _MMIO(0x9030)
8574#define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1 << 11)
8575
8576#define HSW_SCRATCH1 _MMIO(0xb038)
8577#define HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE (1 << 27)
8578
8579#define BDW_SCRATCH1 _MMIO(0xb11c)
8580#define GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE (1 << 2)
8581
8582
8583#define _PIPEA_CHICKEN 0x70038
8584#define _PIPEB_CHICKEN 0x71038
8585#define _PIPEC_CHICKEN 0x72038
8586#define PIPE_CHICKEN(pipe) _MMIO_PIPE(pipe, _PIPEA_CHICKEN,\
8587 _PIPEB_CHICKEN)
8588#define UNDERRUN_RECOVERY_DISABLE_ADLP REG_BIT(30)
8589#define UNDERRUN_RECOVERY_ENABLE_DG2 REG_BIT(30)
8590#define PIXEL_ROUNDING_TRUNC_FB_PASSTHRU REG_BIT(15)
8591#define DG2_RENDER_CCSTAG_4_3_EN REG_BIT(12)
8592#define PER_PIXEL_ALPHA_BYPASS_EN REG_BIT(7)
8593
8594#define VFLSKPD _MMIO(0x62a8)
8595#define DIS_OVER_FETCH_CACHE REG_BIT(1)
8596#define DIS_MULT_MISS_RD_SQUASH REG_BIT(0)
8597
8598#define FF_MODE2 _MMIO(0x6604)
8599#define FF_MODE2_GS_TIMER_MASK REG_GENMASK(31, 24)
8600#define FF_MODE2_GS_TIMER_224 REG_FIELD_PREP(FF_MODE2_GS_TIMER_MASK, 224)
8601#define FF_MODE2_TDS_TIMER_MASK REG_GENMASK(23, 16)
8602#define FF_MODE2_TDS_TIMER_128 REG_FIELD_PREP(FF_MODE2_TDS_TIMER_MASK, 4)
8603
8604
8605
8606#define PCH_DISPLAY_BASE 0xc0000u
8607
8608
8609#define SDE_AUDIO_POWER_D (1 << 27)
8610#define SDE_AUDIO_POWER_C (1 << 26)
8611#define SDE_AUDIO_POWER_B (1 << 25)
8612#define SDE_AUDIO_POWER_SHIFT (25)
8613#define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT)
8614#define SDE_GMBUS (1 << 24)
8615#define SDE_AUDIO_HDCP_TRANSB (1 << 23)
8616#define SDE_AUDIO_HDCP_TRANSA (1 << 22)
8617#define SDE_AUDIO_HDCP_MASK (3 << 22)
8618#define SDE_AUDIO_TRANSB (1 << 21)
8619#define SDE_AUDIO_TRANSA (1 << 20)
8620#define SDE_AUDIO_TRANS_MASK (3 << 20)
8621#define SDE_POISON (1 << 19)
8622
8623#define SDE_FDI_RXB (1 << 17)
8624#define SDE_FDI_RXA (1 << 16)
8625#define SDE_FDI_MASK (3 << 16)
8626#define SDE_AUXD (1 << 15)
8627#define SDE_AUXC (1 << 14)
8628#define SDE_AUXB (1 << 13)
8629#define SDE_AUX_MASK (7 << 13)
8630
8631#define SDE_CRT_HOTPLUG (1 << 11)
8632#define SDE_PORTD_HOTPLUG (1 << 10)
8633#define SDE_PORTC_HOTPLUG (1 << 9)
8634#define SDE_PORTB_HOTPLUG (1 << 8)
8635#define SDE_SDVOB_HOTPLUG (1 << 6)
8636#define SDE_HOTPLUG_MASK (SDE_CRT_HOTPLUG | \
8637 SDE_SDVOB_HOTPLUG | \
8638 SDE_PORTB_HOTPLUG | \
8639 SDE_PORTC_HOTPLUG | \
8640 SDE_PORTD_HOTPLUG)
8641#define SDE_TRANSB_CRC_DONE (1 << 5)
8642#define SDE_TRANSB_CRC_ERR (1 << 4)
8643#define SDE_TRANSB_FIFO_UNDER (1 << 3)
8644#define SDE_TRANSA_CRC_DONE (1 << 2)
8645#define SDE_TRANSA_CRC_ERR (1 << 1)
8646#define SDE_TRANSA_FIFO_UNDER (1 << 0)
8647#define SDE_TRANS_MASK (0x3f)
8648
8649
8650#define SDE_AUDIO_POWER_D_CPT (1 << 31)
8651#define SDE_AUDIO_POWER_C_CPT (1 << 30)
8652#define SDE_AUDIO_POWER_B_CPT (1 << 29)
8653#define SDE_AUDIO_POWER_SHIFT_CPT 29
8654#define SDE_AUDIO_POWER_MASK_CPT (7 << 29)
8655#define SDE_AUXD_CPT (1 << 27)
8656#define SDE_AUXC_CPT (1 << 26)
8657#define SDE_AUXB_CPT (1 << 25)
8658#define SDE_AUX_MASK_CPT (7 << 25)
8659#define SDE_PORTE_HOTPLUG_SPT (1 << 25)
8660#define SDE_PORTA_HOTPLUG_SPT (1 << 24)
8661#define SDE_PORTD_HOTPLUG_CPT (1 << 23)
8662#define SDE_PORTC_HOTPLUG_CPT (1 << 22)
8663#define SDE_PORTB_HOTPLUG_CPT (1 << 21)
8664#define SDE_CRT_HOTPLUG_CPT (1 << 19)
8665#define SDE_SDVOB_HOTPLUG_CPT (1 << 18)
8666#define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \
8667 SDE_SDVOB_HOTPLUG_CPT | \
8668 SDE_PORTD_HOTPLUG_CPT | \
8669 SDE_PORTC_HOTPLUG_CPT | \
8670 SDE_PORTB_HOTPLUG_CPT)
8671#define SDE_HOTPLUG_MASK_SPT (SDE_PORTE_HOTPLUG_SPT | \
8672 SDE_PORTD_HOTPLUG_CPT | \
8673 SDE_PORTC_HOTPLUG_CPT | \
8674 SDE_PORTB_HOTPLUG_CPT | \
8675 SDE_PORTA_HOTPLUG_SPT)
8676#define SDE_GMBUS_CPT (1 << 17)
8677#define SDE_ERROR_CPT (1 << 16)
8678#define SDE_AUDIO_CP_REQ_C_CPT (1 << 10)
8679#define SDE_AUDIO_CP_CHG_C_CPT (1 << 9)
8680#define SDE_FDI_RXC_CPT (1 << 8)
8681#define SDE_AUDIO_CP_REQ_B_CPT (1 << 6)
8682#define SDE_AUDIO_CP_CHG_B_CPT (1 << 5)
8683#define SDE_FDI_RXB_CPT (1 << 4)
8684#define SDE_AUDIO_CP_REQ_A_CPT (1 << 2)
8685#define SDE_AUDIO_CP_CHG_A_CPT (1 << 1)
8686#define SDE_FDI_RXA_CPT (1 << 0)
8687#define SDE_AUDIO_CP_REQ_CPT (SDE_AUDIO_CP_REQ_C_CPT | \
8688 SDE_AUDIO_CP_REQ_B_CPT | \
8689 SDE_AUDIO_CP_REQ_A_CPT)
8690#define SDE_AUDIO_CP_CHG_CPT (SDE_AUDIO_CP_CHG_C_CPT | \
8691 SDE_AUDIO_CP_CHG_B_CPT | \
8692 SDE_AUDIO_CP_CHG_A_CPT)
8693#define SDE_FDI_MASK_CPT (SDE_FDI_RXC_CPT | \
8694 SDE_FDI_RXB_CPT | \
8695 SDE_FDI_RXA_CPT)
8696
8697
8698#define SDE_GMBUS_ICP (1 << 23)
8699#define SDE_TC_HOTPLUG_ICP(hpd_pin) REG_BIT(24 + _HPD_PIN_TC(hpd_pin))
8700#define SDE_DDI_HOTPLUG_ICP(hpd_pin) REG_BIT(16 + _HPD_PIN_DDI(hpd_pin))
8701#define SDE_DDI_HOTPLUG_MASK_ICP (SDE_DDI_HOTPLUG_ICP(HPD_PORT_D) | \
8702 SDE_DDI_HOTPLUG_ICP(HPD_PORT_C) | \
8703 SDE_DDI_HOTPLUG_ICP(HPD_PORT_B) | \
8704 SDE_DDI_HOTPLUG_ICP(HPD_PORT_A))
8705#define SDE_TC_HOTPLUG_MASK_ICP (SDE_TC_HOTPLUG_ICP(HPD_PORT_TC6) | \
8706 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC5) | \
8707 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4) | \
8708 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3) | \
8709 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2) | \
8710 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1))
8711
8712#define SDEISR _MMIO(0xc4000)
8713#define SDEIMR _MMIO(0xc4004)
8714#define SDEIIR _MMIO(0xc4008)
8715#define SDEIER _MMIO(0xc400c)
8716
8717#define SERR_INT _MMIO(0xc4040)
8718#define SERR_INT_POISON (1 << 31)
8719#define SERR_INT_TRANS_FIFO_UNDERRUN(pipe) (1 << ((pipe) * 3))
8720
8721
8722#define PCH_PORT_HOTPLUG _MMIO(0xc4030)
8723#define PORTA_HOTPLUG_ENABLE (1 << 28)
8724#define BXT_DDIA_HPD_INVERT (1 << 27)
8725#define PORTA_HOTPLUG_STATUS_MASK (3 << 24)
8726#define PORTA_HOTPLUG_NO_DETECT (0 << 24)
8727#define PORTA_HOTPLUG_SHORT_DETECT (1 << 24)
8728#define PORTA_HOTPLUG_LONG_DETECT (2 << 24)
8729#define PORTD_HOTPLUG_ENABLE (1 << 20)
8730#define PORTD_PULSE_DURATION_2ms (0 << 18)
8731#define PORTD_PULSE_DURATION_4_5ms (1 << 18)
8732#define PORTD_PULSE_DURATION_6ms (2 << 18)
8733#define PORTD_PULSE_DURATION_100ms (3 << 18)
8734#define PORTD_PULSE_DURATION_MASK (3 << 18)
8735#define PORTD_HOTPLUG_STATUS_MASK (3 << 16)
8736#define PORTD_HOTPLUG_NO_DETECT (0 << 16)
8737#define PORTD_HOTPLUG_SHORT_DETECT (1 << 16)
8738#define PORTD_HOTPLUG_LONG_DETECT (2 << 16)
8739#define PORTC_HOTPLUG_ENABLE (1 << 12)
8740#define BXT_DDIC_HPD_INVERT (1 << 11)
8741#define PORTC_PULSE_DURATION_2ms (0 << 10)
8742#define PORTC_PULSE_DURATION_4_5ms (1 << 10)
8743#define PORTC_PULSE_DURATION_6ms (2 << 10)
8744#define PORTC_PULSE_DURATION_100ms (3 << 10)
8745#define PORTC_PULSE_DURATION_MASK (3 << 10)
8746#define PORTC_HOTPLUG_STATUS_MASK (3 << 8)
8747#define PORTC_HOTPLUG_NO_DETECT (0 << 8)
8748#define PORTC_HOTPLUG_SHORT_DETECT (1 << 8)
8749#define PORTC_HOTPLUG_LONG_DETECT (2 << 8)
8750#define PORTB_HOTPLUG_ENABLE (1 << 4)
8751#define BXT_DDIB_HPD_INVERT (1 << 3)
8752#define PORTB_PULSE_DURATION_2ms (0 << 2)
8753#define PORTB_PULSE_DURATION_4_5ms (1 << 2)
8754#define PORTB_PULSE_DURATION_6ms (2 << 2)
8755#define PORTB_PULSE_DURATION_100ms (3 << 2)
8756#define PORTB_PULSE_DURATION_MASK (3 << 2)
8757#define PORTB_HOTPLUG_STATUS_MASK (3 << 0)
8758#define PORTB_HOTPLUG_NO_DETECT (0 << 0)
8759#define PORTB_HOTPLUG_SHORT_DETECT (1 << 0)
8760#define PORTB_HOTPLUG_LONG_DETECT (2 << 0)
8761#define BXT_DDI_HPD_INVERT_MASK (BXT_DDIA_HPD_INVERT | \
8762 BXT_DDIB_HPD_INVERT | \
8763 BXT_DDIC_HPD_INVERT)
8764
8765#define PCH_PORT_HOTPLUG2 _MMIO(0xc403C)
8766#define PORTE_HOTPLUG_ENABLE (1 << 4)
8767#define PORTE_HOTPLUG_STATUS_MASK (3 << 0)
8768#define PORTE_HOTPLUG_NO_DETECT (0 << 0)
8769#define PORTE_HOTPLUG_SHORT_DETECT (1 << 0)
8770#define PORTE_HOTPLUG_LONG_DETECT (2 << 0)
8771
8772
8773
8774
8775
8776
8777#define SHOTPLUG_CTL_DDI _MMIO(0xc4030)
8778#define SHOTPLUG_CTL_DDI_HPD_ENABLE(hpd_pin) (0x8 << (_HPD_PIN_DDI(hpd_pin) * 4))
8779#define SHOTPLUG_CTL_DDI_HPD_STATUS_MASK(hpd_pin) (0x3 << (_HPD_PIN_DDI(hpd_pin) * 4))
8780#define SHOTPLUG_CTL_DDI_HPD_NO_DETECT(hpd_pin) (0x0 << (_HPD_PIN_DDI(hpd_pin) * 4))
8781#define SHOTPLUG_CTL_DDI_HPD_SHORT_DETECT(hpd_pin) (0x1 << (_HPD_PIN_DDI(hpd_pin) * 4))
8782#define SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(hpd_pin) (0x2 << (_HPD_PIN_DDI(hpd_pin) * 4))
8783#define SHOTPLUG_CTL_DDI_HPD_SHORT_LONG_DETECT(hpd_pin) (0x3 << (_HPD_PIN_DDI(hpd_pin) * 4))
8784
8785#define SHOTPLUG_CTL_TC _MMIO(0xc4034)
8786#define ICP_TC_HPD_ENABLE(hpd_pin) (8 << (_HPD_PIN_TC(hpd_pin) * 4))
8787#define ICP_TC_HPD_LONG_DETECT(hpd_pin) (2 << (_HPD_PIN_TC(hpd_pin) * 4))
8788#define ICP_TC_HPD_SHORT_DETECT(hpd_pin) (1 << (_HPD_PIN_TC(hpd_pin) * 4))
8789
8790#define SHPD_FILTER_CNT _MMIO(0xc4038)
8791#define SHPD_FILTER_CNT_500_ADJ 0x001D9
8792
8793#define _PCH_DPLL_A 0xc6014
8794#define _PCH_DPLL_B 0xc6018
8795#define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
8796
8797#define _PCH_FPA0 0xc6040
8798#define FP_CB_TUNE (0x3 << 22)
8799#define _PCH_FPA1 0xc6044
8800#define _PCH_FPB0 0xc6048
8801#define _PCH_FPB1 0xc604c
8802#define PCH_FP0(pll) _MMIO((pll) == 0 ? _PCH_FPA0 : _PCH_FPB0)
8803#define PCH_FP1(pll) _MMIO((pll) == 0 ? _PCH_FPA1 : _PCH_FPB1)
8804
8805#define PCH_DPLL_TEST _MMIO(0xc606c)
8806
8807#define PCH_DREF_CONTROL _MMIO(0xC6200)
8808#define DREF_CONTROL_MASK 0x7fc3
8809#define DREF_CPU_SOURCE_OUTPUT_DISABLE (0 << 13)
8810#define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2 << 13)
8811#define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3 << 13)
8812#define DREF_CPU_SOURCE_OUTPUT_MASK (3 << 13)
8813#define DREF_SSC_SOURCE_DISABLE (0 << 11)
8814#define DREF_SSC_SOURCE_ENABLE (2 << 11)
8815#define DREF_SSC_SOURCE_MASK (3 << 11)
8816#define DREF_NONSPREAD_SOURCE_DISABLE (0 << 9)
8817#define DREF_NONSPREAD_CK505_ENABLE (1 << 9)
8818#define DREF_NONSPREAD_SOURCE_ENABLE (2 << 9)
8819#define DREF_NONSPREAD_SOURCE_MASK (3 << 9)
8820#define DREF_SUPERSPREAD_SOURCE_DISABLE (0 << 7)
8821#define DREF_SUPERSPREAD_SOURCE_ENABLE (2 << 7)
8822#define DREF_SUPERSPREAD_SOURCE_MASK (3 << 7)
8823#define DREF_SSC4_DOWNSPREAD (0 << 6)
8824#define DREF_SSC4_CENTERSPREAD (1 << 6)
8825#define DREF_SSC1_DISABLE (0 << 1)
8826#define DREF_SSC1_ENABLE (1 << 1)
8827#define DREF_SSC4_DISABLE (0)
8828#define DREF_SSC4_ENABLE (1)
8829
8830#define PCH_RAWCLK_FREQ _MMIO(0xc6204)
8831#define FDL_TP1_TIMER_SHIFT 12
8832#define FDL_TP1_TIMER_MASK (3 << 12)
8833#define FDL_TP2_TIMER_SHIFT 10
8834#define FDL_TP2_TIMER_MASK (3 << 10)
8835#define RAWCLK_FREQ_MASK 0x3ff
8836#define CNP_RAWCLK_DIV_MASK (0x3ff << 16)
8837#define CNP_RAWCLK_DIV(div) ((div) << 16)
8838#define CNP_RAWCLK_FRAC_MASK (0xf << 26)
8839#define CNP_RAWCLK_DEN(den) ((den) << 26)
8840#define ICP_RAWCLK_NUM(num) ((num) << 11)
8841
8842#define PCH_DPLL_TMR_CFG _MMIO(0xc6208)
8843
8844#define PCH_SSC4_PARMS _MMIO(0xc6210)
8845#define PCH_SSC4_AUX_PARMS _MMIO(0xc6214)
8846
8847#define PCH_DPLL_SEL _MMIO(0xc7000)
8848#define TRANS_DPLLB_SEL(pipe) (1 << ((pipe) * 4))
8849#define TRANS_DPLLA_SEL(pipe) 0
8850#define TRANS_DPLL_ENABLE(pipe) (1 << ((pipe) * 4 + 3))
8851
8852
8853
8854#define _PCH_TRANS_HTOTAL_A 0xe0000
8855#define TRANS_HTOTAL_SHIFT 16
8856#define TRANS_HACTIVE_SHIFT 0
8857#define _PCH_TRANS_HBLANK_A 0xe0004
8858#define TRANS_HBLANK_END_SHIFT 16
8859#define TRANS_HBLANK_START_SHIFT 0
8860#define _PCH_TRANS_HSYNC_A 0xe0008
8861#define TRANS_HSYNC_END_SHIFT 16
8862#define TRANS_HSYNC_START_SHIFT 0
8863#define _PCH_TRANS_VTOTAL_A 0xe000c
8864#define TRANS_VTOTAL_SHIFT 16
8865#define TRANS_VACTIVE_SHIFT 0
8866#define _PCH_TRANS_VBLANK_A 0xe0010
8867#define TRANS_VBLANK_END_SHIFT 16
8868#define TRANS_VBLANK_START_SHIFT 0
8869#define _PCH_TRANS_VSYNC_A 0xe0014
8870#define TRANS_VSYNC_END_SHIFT 16
8871#define TRANS_VSYNC_START_SHIFT 0
8872#define _PCH_TRANS_VSYNCSHIFT_A 0xe0028
8873
8874#define _PCH_TRANSA_DATA_M1 0xe0030
8875#define _PCH_TRANSA_DATA_N1 0xe0034
8876#define _PCH_TRANSA_DATA_M2 0xe0038
8877#define _PCH_TRANSA_DATA_N2 0xe003c
8878#define _PCH_TRANSA_LINK_M1 0xe0040
8879#define _PCH_TRANSA_LINK_N1 0xe0044
8880#define _PCH_TRANSA_LINK_M2 0xe0048
8881#define _PCH_TRANSA_LINK_N2 0xe004c
8882
8883
8884#define _VIDEO_DIP_CTL_A 0xe0200
8885#define _VIDEO_DIP_DATA_A 0xe0208
8886#define _VIDEO_DIP_GCP_A 0xe0210
8887#define GCP_COLOR_INDICATION (1 << 2)
8888#define GCP_DEFAULT_PHASE_ENABLE (1 << 1)
8889#define GCP_AV_MUTE (1 << 0)
8890
8891#define _VIDEO_DIP_CTL_B 0xe1200
8892#define _VIDEO_DIP_DATA_B 0xe1208
8893#define _VIDEO_DIP_GCP_B 0xe1210
8894
8895#define TVIDEO_DIP_CTL(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B)
8896#define TVIDEO_DIP_DATA(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
8897#define TVIDEO_DIP_GCP(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
8898
8899
8900#define _VLV_VIDEO_DIP_CTL_A (VLV_DISPLAY_BASE + 0x60200)
8901#define _VLV_VIDEO_DIP_DATA_A (VLV_DISPLAY_BASE + 0x60208)
8902#define _VLV_VIDEO_DIP_GDCP_PAYLOAD_A (VLV_DISPLAY_BASE + 0x60210)
8903
8904#define _VLV_VIDEO_DIP_CTL_B (VLV_DISPLAY_BASE + 0x61170)
8905#define _VLV_VIDEO_DIP_DATA_B (VLV_DISPLAY_BASE + 0x61174)
8906#define _VLV_VIDEO_DIP_GDCP_PAYLOAD_B (VLV_DISPLAY_BASE + 0x61178)
8907
8908#define _CHV_VIDEO_DIP_CTL_C (VLV_DISPLAY_BASE + 0x611f0)
8909#define _CHV_VIDEO_DIP_DATA_C (VLV_DISPLAY_BASE + 0x611f4)
8910#define _CHV_VIDEO_DIP_GDCP_PAYLOAD_C (VLV_DISPLAY_BASE + 0x611f8)
8911
8912#define VLV_TVIDEO_DIP_CTL(pipe) \
8913 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_CTL_A, \
8914 _VLV_VIDEO_DIP_CTL_B, _CHV_VIDEO_DIP_CTL_C)
8915#define VLV_TVIDEO_DIP_DATA(pipe) \
8916 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_DATA_A, \
8917 _VLV_VIDEO_DIP_DATA_B, _CHV_VIDEO_DIP_DATA_C)
8918#define VLV_TVIDEO_DIP_GCP(pipe) \
8919 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_GDCP_PAYLOAD_A, \
8920 _VLV_VIDEO_DIP_GDCP_PAYLOAD_B, _CHV_VIDEO_DIP_GDCP_PAYLOAD_C)
8921
8922
8923
8924#define _HSW_VIDEO_DIP_CTL_A 0x60200
8925#define _HSW_VIDEO_DIP_AVI_DATA_A 0x60220
8926#define _HSW_VIDEO_DIP_VS_DATA_A 0x60260
8927#define _HSW_VIDEO_DIP_SPD_DATA_A 0x602A0
8928#define _HSW_VIDEO_DIP_GMP_DATA_A 0x602E0
8929#define _HSW_VIDEO_DIP_VSC_DATA_A 0x60320
8930#define _GLK_VIDEO_DIP_DRM_DATA_A 0x60440
8931#define _HSW_VIDEO_DIP_AVI_ECC_A 0x60240
8932#define _HSW_VIDEO_DIP_VS_ECC_A 0x60280
8933#define _HSW_VIDEO_DIP_SPD_ECC_A 0x602C0
8934#define _HSW_VIDEO_DIP_GMP_ECC_A 0x60300
8935#define _HSW_VIDEO_DIP_VSC_ECC_A 0x60344
8936#define _HSW_VIDEO_DIP_GCP_A 0x60210
8937
8938#define _HSW_VIDEO_DIP_CTL_B 0x61200
8939#define _HSW_VIDEO_DIP_AVI_DATA_B 0x61220
8940#define _HSW_VIDEO_DIP_VS_DATA_B 0x61260
8941#define _HSW_VIDEO_DIP_SPD_DATA_B 0x612A0
8942#define _HSW_VIDEO_DIP_GMP_DATA_B 0x612E0
8943#define _HSW_VIDEO_DIP_VSC_DATA_B 0x61320
8944#define _GLK_VIDEO_DIP_DRM_DATA_B 0x61440
8945#define _HSW_VIDEO_DIP_BVI_ECC_B 0x61240
8946#define _HSW_VIDEO_DIP_VS_ECC_B 0x61280
8947#define _HSW_VIDEO_DIP_SPD_ECC_B 0x612C0
8948#define _HSW_VIDEO_DIP_GMP_ECC_B 0x61300
8949#define _HSW_VIDEO_DIP_VSC_ECC_B 0x61344
8950#define _HSW_VIDEO_DIP_GCP_B 0x61210
8951
8952
8953
8954
8955
8956
8957
8958#define _ICL_VIDEO_DIP_PPS_DATA_A 0x60350
8959#define _ICL_VIDEO_DIP_PPS_DATA_B 0x61350
8960#define _ICL_VIDEO_DIP_PPS_ECC_A 0x603D4
8961#define _ICL_VIDEO_DIP_PPS_ECC_B 0x613D4
8962
8963#define HSW_TVIDEO_DIP_CTL(trans) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_CTL_A)
8964#define HSW_TVIDEO_DIP_GCP(trans) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GCP_A)
8965#define HSW_TVIDEO_DIP_AVI_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_AVI_DATA_A + (i) * 4)
8966#define HSW_TVIDEO_DIP_VS_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VS_DATA_A + (i) * 4)
8967#define HSW_TVIDEO_DIP_SPD_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4)
8968#define HSW_TVIDEO_DIP_GMP_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GMP_DATA_A + (i) * 4)
8969#define HSW_TVIDEO_DIP_VSC_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4)
8970#define GLK_TVIDEO_DIP_DRM_DATA(trans, i) _MMIO_TRANS2(trans, _GLK_VIDEO_DIP_DRM_DATA_A + (i) * 4)
8971#define ICL_VIDEO_DIP_PPS_DATA(trans, i) _MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_DATA_A + (i) * 4)
8972#define ICL_VIDEO_DIP_PPS_ECC(trans, i) _MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_ECC_A + (i) * 4)
8973
8974#define _HSW_STEREO_3D_CTL_A 0x70020
8975#define S3D_ENABLE (1 << 31)
8976#define _HSW_STEREO_3D_CTL_B 0x71020
8977
8978#define HSW_STEREO_3D_CTL(trans) _MMIO_PIPE2(trans, _HSW_STEREO_3D_CTL_A)
8979
8980#define _PCH_TRANS_HTOTAL_B 0xe1000
8981#define _PCH_TRANS_HBLANK_B 0xe1004
8982#define _PCH_TRANS_HSYNC_B 0xe1008
8983#define _PCH_TRANS_VTOTAL_B 0xe100c
8984#define _PCH_TRANS_VBLANK_B 0xe1010
8985#define _PCH_TRANS_VSYNC_B 0xe1014
8986#define _PCH_TRANS_VSYNCSHIFT_B 0xe1028
8987
8988#define PCH_TRANS_HTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B)
8989#define PCH_TRANS_HBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B)
8990#define PCH_TRANS_HSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B)
8991#define PCH_TRANS_VTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B)
8992#define PCH_TRANS_VBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B)
8993#define PCH_TRANS_VSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B)
8994#define PCH_TRANS_VSYNCSHIFT(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, _PCH_TRANS_VSYNCSHIFT_B)
8995
8996#define _PCH_TRANSB_DATA_M1 0xe1030
8997#define _PCH_TRANSB_DATA_N1 0xe1034
8998#define _PCH_TRANSB_DATA_M2 0xe1038
8999#define _PCH_TRANSB_DATA_N2 0xe103c
9000#define _PCH_TRANSB_LINK_M1 0xe1040
9001#define _PCH_TRANSB_LINK_N1 0xe1044
9002#define _PCH_TRANSB_LINK_M2 0xe1048
9003#define _PCH_TRANSB_LINK_N2 0xe104c
9004
9005#define PCH_TRANS_DATA_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1)
9006#define PCH_TRANS_DATA_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1)
9007#define PCH_TRANS_DATA_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2)
9008#define PCH_TRANS_DATA_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2)
9009#define PCH_TRANS_LINK_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1)
9010#define PCH_TRANS_LINK_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1)
9011#define PCH_TRANS_LINK_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2)
9012#define PCH_TRANS_LINK_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2)
9013
9014#define _PCH_TRANSACONF 0xf0008
9015#define _PCH_TRANSBCONF 0xf1008
9016#define PCH_TRANSCONF(pipe) _MMIO_PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF)
9017#define LPT_TRANSCONF PCH_TRANSCONF(PIPE_A)
9018#define TRANS_DISABLE (0 << 31)
9019#define TRANS_ENABLE (1 << 31)
9020#define TRANS_STATE_MASK (1 << 30)
9021#define TRANS_STATE_DISABLE (0 << 30)
9022#define TRANS_STATE_ENABLE (1 << 30)
9023#define TRANS_FRAME_START_DELAY_MASK (3 << 27)
9024#define TRANS_FRAME_START_DELAY(x) ((x) << 27)
9025#define TRANS_INTERLACE_MASK (7 << 21)
9026#define TRANS_PROGRESSIVE (0 << 21)
9027#define TRANS_INTERLACED (3 << 21)
9028#define TRANS_LEGACY_INTERLACED_ILK (2 << 21)
9029#define TRANS_8BPC (0 << 5)
9030#define TRANS_10BPC (1 << 5)
9031#define TRANS_6BPC (2 << 5)
9032#define TRANS_12BPC (3 << 5)
9033
9034#define _TRANSA_CHICKEN1 0xf0060
9035#define _TRANSB_CHICKEN1 0xf1060
9036#define TRANS_CHICKEN1(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)
9037#define TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE (1 << 10)
9038#define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE (1 << 4)
9039#define _TRANSA_CHICKEN2 0xf0064
9040#define _TRANSB_CHICKEN2 0xf1064
9041#define TRANS_CHICKEN2(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
9042#define TRANS_CHICKEN2_TIMING_OVERRIDE (1 << 31)
9043#define TRANS_CHICKEN2_FDI_POLARITY_REVERSED (1 << 29)
9044#define TRANS_CHICKEN2_FRAME_START_DELAY_MASK (3 << 27)
9045#define TRANS_CHICKEN2_FRAME_START_DELAY(x) ((x) << 27)
9046#define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER (1 << 26)
9047#define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH (1 << 25)
9048
9049#define SOUTH_CHICKEN1 _MMIO(0xc2000)
9050#define FDIA_PHASE_SYNC_SHIFT_OVR 19
9051#define FDIA_PHASE_SYNC_SHIFT_EN 18
9052#define INVERT_DDID_HPD (1 << 18)
9053#define INVERT_DDIC_HPD (1 << 17)
9054#define INVERT_DDIB_HPD (1 << 16)
9055#define INVERT_DDIA_HPD (1 << 15)
9056#define FDI_PHASE_SYNC_OVR(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
9057#define FDI_PHASE_SYNC_EN(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
9058#define FDI_BC_BIFURCATION_SELECT (1 << 12)
9059#define CHASSIS_CLK_REQ_DURATION_MASK (0xf << 8)
9060#define CHASSIS_CLK_REQ_DURATION(x) ((x) << 8)
9061#define SBCLK_RUN_REFCLK_DIS (1 << 7)
9062#define SPT_PWM_GRANULARITY (1 << 0)
9063#define SOUTH_CHICKEN2 _MMIO(0xc2004)
9064#define FDI_MPHY_IOSFSB_RESET_STATUS (1 << 13)
9065#define FDI_MPHY_IOSFSB_RESET_CTL (1 << 12)
9066#define LPT_PWM_GRANULARITY (1 << 5)
9067#define DPLS_EDP_PPS_FIX_DIS (1 << 0)
9068
9069#define _FDI_RXA_CHICKEN 0xc200c
9070#define _FDI_RXB_CHICKEN 0xc2010
9071#define FDI_RX_PHASE_SYNC_POINTER_OVR (1 << 1)
9072#define FDI_RX_PHASE_SYNC_POINTER_EN (1 << 0)
9073#define FDI_RX_CHICKEN(pipe) _MMIO_PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN)
9074
9075#define SOUTH_DSPCLK_GATE_D _MMIO(0xc2020)
9076#define PCH_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 31)
9077#define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1 << 30)
9078#define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1 << 29)
9079#define PCH_DPMGUNIT_CLOCK_GATE_DISABLE (1 << 15)
9080#define PCH_CPUNIT_CLOCK_GATE_DISABLE (1 << 14)
9081#define CNP_PWM_CGE_GATING_DISABLE (1 << 13)
9082#define PCH_LP_PARTITION_LEVEL_DISABLE (1 << 12)
9083
9084
9085#define _FDI_TXA_CTL 0x60100
9086#define _FDI_TXB_CTL 0x61100
9087#define FDI_TX_CTL(pipe) _MMIO_PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL)
9088#define FDI_TX_DISABLE (0 << 31)
9089#define FDI_TX_ENABLE (1 << 31)
9090#define FDI_LINK_TRAIN_PATTERN_1 (0 << 28)
9091#define FDI_LINK_TRAIN_PATTERN_2 (1 << 28)
9092#define FDI_LINK_TRAIN_PATTERN_IDLE (2 << 28)
9093#define FDI_LINK_TRAIN_NONE (3 << 28)
9094#define FDI_LINK_TRAIN_VOLTAGE_0_4V (0 << 25)
9095#define FDI_LINK_TRAIN_VOLTAGE_0_6V (1 << 25)
9096#define FDI_LINK_TRAIN_VOLTAGE_0_8V (2 << 25)
9097#define FDI_LINK_TRAIN_VOLTAGE_1_2V (3 << 25)
9098#define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0 << 22)
9099#define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1 << 22)
9100#define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2 << 22)
9101#define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3 << 22)
9102
9103
9104
9105#define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38 << 22)
9106#define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02 << 22)
9107#define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01 << 22)
9108#define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0 << 22)
9109
9110#define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0 << 22)
9111#define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a << 22)
9112#define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39 << 22)
9113#define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38 << 22)
9114#define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f << 22)
9115#define FDI_DP_PORT_WIDTH_SHIFT 19
9116#define FDI_DP_PORT_WIDTH_MASK (7 << FDI_DP_PORT_WIDTH_SHIFT)
9117#define FDI_DP_PORT_WIDTH(width) (((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT)
9118#define FDI_TX_ENHANCE_FRAME_ENABLE (1 << 18)
9119
9120#define FDI_TX_PLL_ENABLE (1 << 14)
9121
9122
9123#define FDI_LINK_TRAIN_PATTERN_1_IVB (0 << 8)
9124#define FDI_LINK_TRAIN_PATTERN_2_IVB (1 << 8)
9125#define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2 << 8)
9126#define FDI_LINK_TRAIN_NONE_IVB (3 << 8)
9127
9128
9129#define FDI_COMPOSITE_SYNC (1 << 11)
9130#define FDI_LINK_TRAIN_AUTO (1 << 10)
9131#define FDI_SCRAMBLING_ENABLE (0 << 7)
9132#define FDI_SCRAMBLING_DISABLE (1 << 7)
9133
9134
9135#define _FDI_RXA_CTL 0xf000c
9136#define _FDI_RXB_CTL 0xf100c
9137#define FDI_RX_CTL(pipe) _MMIO_PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL)
9138#define FDI_RX_ENABLE (1 << 31)
9139
9140#define FDI_FS_ERRC_ENABLE (1 << 27)
9141#define FDI_FE_ERRC_ENABLE (1 << 26)
9142#define FDI_RX_POLARITY_REVERSED_LPT (1 << 16)
9143#define FDI_8BPC (0 << 16)
9144#define FDI_10BPC (1 << 16)
9145#define FDI_6BPC (2 << 16)
9146#define FDI_12BPC (3 << 16)
9147#define FDI_RX_LINK_REVERSAL_OVERRIDE (1 << 15)
9148#define FDI_DMI_LINK_REVERSE_MASK (1 << 14)
9149#define FDI_RX_PLL_ENABLE (1 << 13)
9150#define FDI_FS_ERR_CORRECT_ENABLE (1 << 11)
9151#define FDI_FE_ERR_CORRECT_ENABLE (1 << 10)
9152#define FDI_FS_ERR_REPORT_ENABLE (1 << 9)
9153#define FDI_FE_ERR_REPORT_ENABLE (1 << 8)
9154#define FDI_RX_ENHANCE_FRAME_ENABLE (1 << 6)
9155#define FDI_PCDCLK (1 << 4)
9156
9157#define FDI_AUTO_TRAINING (1 << 10)
9158#define FDI_LINK_TRAIN_PATTERN_1_CPT (0 << 8)
9159#define FDI_LINK_TRAIN_PATTERN_2_CPT (1 << 8)
9160#define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2 << 8)
9161#define FDI_LINK_TRAIN_NORMAL_CPT (3 << 8)
9162#define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3 << 8)
9163
9164#define _FDI_RXA_MISC 0xf0010
9165#define _FDI_RXB_MISC 0xf1010
9166#define FDI_RX_PWRDN_LANE1_MASK (3 << 26)
9167#define FDI_RX_PWRDN_LANE1_VAL(x) ((x) << 26)
9168#define FDI_RX_PWRDN_LANE0_MASK (3 << 24)
9169#define FDI_RX_PWRDN_LANE0_VAL(x) ((x) << 24)
9170#define FDI_RX_TP1_TO_TP2_48 (2 << 20)
9171#define FDI_RX_TP1_TO_TP2_64 (3 << 20)
9172#define FDI_RX_FDI_DELAY_90 (0x90 << 0)
9173#define FDI_RX_MISC(pipe) _MMIO_PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC)
9174
9175#define _FDI_RXA_TUSIZE1 0xf0030
9176#define _FDI_RXA_TUSIZE2 0xf0038
9177#define _FDI_RXB_TUSIZE1 0xf1030
9178#define _FDI_RXB_TUSIZE2 0xf1038
9179#define FDI_RX_TUSIZE1(pipe) _MMIO_PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1)
9180#define FDI_RX_TUSIZE2(pipe) _MMIO_PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2)
9181
9182
9183#define FDI_RX_INTER_LANE_ALIGN (1 << 10)
9184#define FDI_RX_SYMBOL_LOCK (1 << 9)
9185#define FDI_RX_BIT_LOCK (1 << 8)
9186#define FDI_RX_TRAIN_PATTERN_2_FAIL (1 << 7)
9187#define FDI_RX_FS_CODE_ERR (1 << 6)
9188#define FDI_RX_FE_CODE_ERR (1 << 5)
9189#define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1 << 4)
9190#define FDI_RX_HDCP_LINK_FAIL (1 << 3)
9191#define FDI_RX_PIXEL_FIFO_OVERFLOW (1 << 2)
9192#define FDI_RX_CROSS_CLOCK_OVERFLOW (1 << 1)
9193#define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1 << 0)
9194
9195#define _FDI_RXA_IIR 0xf0014
9196#define _FDI_RXA_IMR 0xf0018
9197#define _FDI_RXB_IIR 0xf1014
9198#define _FDI_RXB_IMR 0xf1018
9199#define FDI_RX_IIR(pipe) _MMIO_PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR)
9200#define FDI_RX_IMR(pipe) _MMIO_PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR)
9201
9202#define FDI_PLL_CTL_1 _MMIO(0xfe000)
9203#define FDI_PLL_CTL_2 _MMIO(0xfe004)
9204
9205#define PCH_LVDS _MMIO(0xe1180)
9206#define LVDS_DETECTED (1 << 1)
9207
9208#define _PCH_DP_B 0xe4100
9209#define PCH_DP_B _MMIO(_PCH_DP_B)
9210#define _PCH_DPB_AUX_CH_CTL 0xe4110
9211#define _PCH_DPB_AUX_CH_DATA1 0xe4114
9212#define _PCH_DPB_AUX_CH_DATA2 0xe4118
9213#define _PCH_DPB_AUX_CH_DATA3 0xe411c
9214#define _PCH_DPB_AUX_CH_DATA4 0xe4120
9215#define _PCH_DPB_AUX_CH_DATA5 0xe4124
9216
9217#define _PCH_DP_C 0xe4200
9218#define PCH_DP_C _MMIO(_PCH_DP_C)
9219#define _PCH_DPC_AUX_CH_CTL 0xe4210
9220#define _PCH_DPC_AUX_CH_DATA1 0xe4214
9221#define _PCH_DPC_AUX_CH_DATA2 0xe4218
9222#define _PCH_DPC_AUX_CH_DATA3 0xe421c
9223#define _PCH_DPC_AUX_CH_DATA4 0xe4220
9224#define _PCH_DPC_AUX_CH_DATA5 0xe4224
9225
9226#define _PCH_DP_D 0xe4300
9227#define PCH_DP_D _MMIO(_PCH_DP_D)
9228#define _PCH_DPD_AUX_CH_CTL 0xe4310
9229#define _PCH_DPD_AUX_CH_DATA1 0xe4314
9230#define _PCH_DPD_AUX_CH_DATA2 0xe4318
9231#define _PCH_DPD_AUX_CH_DATA3 0xe431c
9232#define _PCH_DPD_AUX_CH_DATA4 0xe4320
9233#define _PCH_DPD_AUX_CH_DATA5 0xe4324
9234
9235#define PCH_DP_AUX_CH_CTL(aux_ch) _MMIO_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_CTL, _PCH_DPC_AUX_CH_CTL)
9236#define PCH_DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_DATA1, _PCH_DPC_AUX_CH_DATA1) + (i) * 4)
9237
9238
9239#define _TRANS_DP_CTL_A 0xe0300
9240#define _TRANS_DP_CTL_B 0xe1300
9241#define _TRANS_DP_CTL_C 0xe2300
9242#define TRANS_DP_CTL(pipe) _MMIO_PIPE(pipe, _TRANS_DP_CTL_A, _TRANS_DP_CTL_B)
9243#define TRANS_DP_OUTPUT_ENABLE (1 << 31)
9244#define TRANS_DP_PORT_SEL_MASK (3 << 29)
9245#define TRANS_DP_PORT_SEL_NONE (3 << 29)
9246#define TRANS_DP_PORT_SEL(port) (((port) - PORT_B) << 29)
9247#define TRANS_DP_AUDIO_ONLY (1 << 26)
9248#define TRANS_DP_ENH_FRAMING (1 << 18)
9249#define TRANS_DP_8BPC (0 << 9)
9250#define TRANS_DP_10BPC (1 << 9)
9251#define TRANS_DP_6BPC (2 << 9)
9252#define TRANS_DP_12BPC (3 << 9)
9253#define TRANS_DP_BPC_MASK (3 << 9)
9254#define TRANS_DP_VSYNC_ACTIVE_HIGH (1 << 4)
9255#define TRANS_DP_VSYNC_ACTIVE_LOW 0
9256#define TRANS_DP_HSYNC_ACTIVE_HIGH (1 << 3)
9257#define TRANS_DP_HSYNC_ACTIVE_LOW 0
9258#define TRANS_DP_SYNC_MASK (3 << 3)
9259
9260#define _TRANS_DP2_CTL_A 0x600a0
9261#define _TRANS_DP2_CTL_B 0x610a0
9262#define _TRANS_DP2_CTL_C 0x620a0
9263#define _TRANS_DP2_CTL_D 0x630a0
9264#define TRANS_DP2_CTL(trans) _MMIO_TRANS(trans, _TRANS_DP2_CTL_A, _TRANS_DP2_CTL_B)
9265#define TRANS_DP2_128B132B_CHANNEL_CODING REG_BIT(31)
9266#define TRANS_DP2_PANEL_REPLAY_ENABLE REG_BIT(30)
9267#define TRANS_DP2_DEBUG_ENABLE REG_BIT(23)
9268
9269#define _TRANS_DP2_VFREQHIGH_A 0x600a4
9270#define _TRANS_DP2_VFREQHIGH_B 0x610a4
9271#define _TRANS_DP2_VFREQHIGH_C 0x620a4
9272#define _TRANS_DP2_VFREQHIGH_D 0x630a4
9273#define TRANS_DP2_VFREQHIGH(trans) _MMIO_TRANS(trans, _TRANS_DP2_VFREQHIGH_A, _TRANS_DP2_VFREQHIGH_B)
9274#define TRANS_DP2_VFREQ_PIXEL_CLOCK_MASK REG_GENMASK(31, 8)
9275#define TRANS_DP2_VFREQ_PIXEL_CLOCK(clk_hz) REG_FIELD_PREP(TRANS_DP2_VFREQ_PIXEL_CLOCK_MASK, (clk_hz))
9276
9277#define _TRANS_DP2_VFREQLOW_A 0x600a8
9278#define _TRANS_DP2_VFREQLOW_B 0x610a8
9279#define _TRANS_DP2_VFREQLOW_C 0x620a8
9280#define _TRANS_DP2_VFREQLOW_D 0x630a8
9281#define TRANS_DP2_VFREQLOW(trans) _MMIO_TRANS(trans, _TRANS_DP2_VFREQLOW_A, _TRANS_DP2_VFREQLOW_B)
9282
9283
9284
9285#define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38 << 22)
9286#define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02 << 22)
9287#define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01 << 22)
9288#define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0 << 22)
9289
9290#define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0 << 22)
9291#define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1 << 22)
9292#define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a << 22)
9293#define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39 << 22)
9294#define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38 << 22)
9295#define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f << 22)
9296
9297
9298#define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 << 22)
9299#define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a << 22)
9300#define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f << 22)
9301#define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 << 22)
9302#define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 << 22)
9303#define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 << 22)
9304#define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x3e << 22)
9305
9306
9307#define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 << 22)
9308#define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 << 22)
9309#define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 << 22)
9310#define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 << 22)
9311#define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 << 22)
9312
9313#define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f << 22)
9314
9315#define VLV_PMWGICZ _MMIO(0x1300a4)
9316
9317#define RC6_LOCATION _MMIO(0xD40)
9318#define RC6_CTX_IN_DRAM (1 << 0)
9319#define RC6_CTX_BASE _MMIO(0xD48)
9320#define RC6_CTX_BASE_MASK 0xFFFFFFF0
9321#define PWRCTX_MAXCNT_RCSUNIT _MMIO(0x2054)
9322#define PWRCTX_MAXCNT_VCSUNIT0 _MMIO(0x12054)
9323#define PWRCTX_MAXCNT_BCSUNIT _MMIO(0x22054)
9324#define PWRCTX_MAXCNT_VECSUNIT _MMIO(0x1A054)
9325#define PWRCTX_MAXCNT_VCSUNIT1 _MMIO(0x1C054)
9326#define IDLE_TIME_MASK 0xFFFFF
9327#define FORCEWAKE _MMIO(0xA18C)
9328#define FORCEWAKE_VLV _MMIO(0x1300b0)
9329#define FORCEWAKE_ACK_VLV _MMIO(0x1300b4)
9330#define FORCEWAKE_MEDIA_VLV _MMIO(0x1300b8)
9331#define FORCEWAKE_ACK_MEDIA_VLV _MMIO(0x1300bc)
9332#define FORCEWAKE_ACK_HSW _MMIO(0x130044)
9333#define FORCEWAKE_ACK _MMIO(0x130090)
9334#define VLV_GTLC_WAKE_CTRL _MMIO(0x130090)
9335#define VLV_GTLC_RENDER_CTX_EXISTS (1 << 25)
9336#define VLV_GTLC_MEDIA_CTX_EXISTS (1 << 24)
9337#define VLV_GTLC_ALLOWWAKEREQ (1 << 0)
9338
9339#define VLV_GTLC_PW_STATUS _MMIO(0x130094)
9340#define VLV_GTLC_ALLOWWAKEACK (1 << 0)
9341#define VLV_GTLC_ALLOWWAKEERR (1 << 1)
9342#define VLV_GTLC_PW_MEDIA_STATUS_MASK (1 << 5)
9343#define VLV_GTLC_PW_RENDER_STATUS_MASK (1 << 7)
9344#define FORCEWAKE_MT _MMIO(0xa188)
9345#define FORCEWAKE_MEDIA_GEN9 _MMIO(0xa270)
9346#define FORCEWAKE_MEDIA_VDBOX_GEN11(n) _MMIO(0xa540 + (n) * 4)
9347#define FORCEWAKE_MEDIA_VEBOX_GEN11(n) _MMIO(0xa560 + (n) * 4)
9348#define FORCEWAKE_RENDER_GEN9 _MMIO(0xa278)
9349#define FORCEWAKE_GT_GEN9 _MMIO(0xa188)
9350#define FORCEWAKE_ACK_MEDIA_GEN9 _MMIO(0x0D88)
9351#define FORCEWAKE_ACK_MEDIA_VDBOX_GEN11(n) _MMIO(0x0D50 + (n) * 4)
9352#define FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(n) _MMIO(0x0D70 + (n) * 4)
9353#define FORCEWAKE_ACK_RENDER_GEN9 _MMIO(0x0D84)
9354#define FORCEWAKE_ACK_GT_GEN9 _MMIO(0x130044)
9355#define FORCEWAKE_KERNEL BIT(0)
9356#define FORCEWAKE_USER BIT(1)
9357#define FORCEWAKE_KERNEL_FALLBACK BIT(15)
9358#define FORCEWAKE_MT_ACK _MMIO(0x130040)
9359#define ECOBUS _MMIO(0xa180)
9360#define FORCEWAKE_MT_ENABLE (1 << 5)
9361#define VLV_SPAREG2H _MMIO(0xA194)
9362#define GEN9_PWRGT_DOMAIN_STATUS _MMIO(0xA2A0)
9363#define GEN9_PWRGT_MEDIA_STATUS_MASK (1 << 0)
9364#define GEN9_PWRGT_RENDER_STATUS_MASK (1 << 1)
9365
9366#define GTFIFODBG _MMIO(0x120000)
9367#define GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV (0x1f << 20)
9368#define GT_FIFO_FREE_ENTRIES_CHV (0x7f << 13)
9369#define GT_FIFO_SBDROPERR (1 << 6)
9370#define GT_FIFO_BLOBDROPERR (1 << 5)
9371#define GT_FIFO_SB_READ_ABORTERR (1 << 4)
9372#define GT_FIFO_DROPERR (1 << 3)
9373#define GT_FIFO_OVFERR (1 << 2)
9374#define GT_FIFO_IAWRERR (1 << 1)
9375#define GT_FIFO_IARDERR (1 << 0)
9376
9377#define GTFIFOCTL _MMIO(0x120008)
9378#define GT_FIFO_FREE_ENTRIES_MASK 0x7f
9379#define GT_FIFO_NUM_RESERVED_ENTRIES 20
9380#define GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL (1 << 12)
9381#define GT_FIFO_CTL_RC6_POLICY_STALL (1 << 11)
9382
9383#define HSW_IDICR _MMIO(0x9008)
9384#define IDIHASHMSK(x) (((x) & 0x3f) << 16)
9385#define HSW_EDRAM_CAP _MMIO(0x120010)
9386#define EDRAM_ENABLED 0x1
9387#define EDRAM_NUM_BANKS(cap) (((cap) >> 1) & 0xf)
9388#define EDRAM_WAYS_IDX(cap) (((cap) >> 5) & 0x7)
9389#define EDRAM_SETS_IDX(cap) (((cap) >> 8) & 0x3)
9390
9391#define GEN6_UCGCTL1 _MMIO(0x9400)
9392# define GEN6_GAMUNIT_CLOCK_GATE_DISABLE (1 << 22)
9393# define GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE (1 << 16)
9394# define GEN6_BLBUNIT_CLOCK_GATE_DISABLE (1 << 5)
9395# define GEN6_CSUNIT_CLOCK_GATE_DISABLE (1 << 7)
9396
9397#define GEN6_UCGCTL2 _MMIO(0x9404)
9398# define GEN6_VFUNIT_CLOCK_GATE_DISABLE (1 << 31)
9399# define GEN7_VDSUNIT_CLOCK_GATE_DISABLE (1 << 30)
9400# define GEN7_TDLUNIT_CLOCK_GATE_DISABLE (1 << 22)
9401# define GEN6_RCZUNIT_CLOCK_GATE_DISABLE (1 << 13)
9402# define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE (1 << 12)
9403# define GEN6_RCCUNIT_CLOCK_GATE_DISABLE (1 << 11)
9404
9405#define GEN6_UCGCTL3 _MMIO(0x9408)
9406# define GEN6_OACSUNIT_CLOCK_GATE_DISABLE (1 << 20)
9407
9408#define GEN7_UCGCTL4 _MMIO(0x940c)
9409#define GEN7_L3BANK2X_CLOCK_GATE_DISABLE (1 << 25)
9410#define GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE (1 << 14)
9411
9412#define GEN6_RCGCTL1 _MMIO(0x9410)
9413#define GEN6_RCGCTL2 _MMIO(0x9414)
9414#define GEN6_RSTCTL _MMIO(0x9420)
9415
9416#define GEN8_UCGCTL6 _MMIO(0x9430)
9417#define GEN8_GAPSUNIT_CLOCK_GATE_DISABLE (1 << 24)
9418#define GEN8_SDEUNIT_CLOCK_GATE_DISABLE (1 << 14)
9419#define GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ (1 << 28)
9420
9421#define UNSLCGCTL9430 _MMIO(0x9430)
9422#define MSQDUNIT_CLKGATE_DIS REG_BIT(3)
9423
9424#define GEN6_GFXPAUSE _MMIO(0xA000)
9425#define GEN6_RPNSWREQ _MMIO(0xA008)
9426#define GEN6_TURBO_DISABLE (1 << 31)
9427#define GEN6_FREQUENCY(x) ((x) << 25)
9428#define HSW_FREQUENCY(x) ((x) << 24)
9429#define GEN9_FREQUENCY(x) ((x) << 23)
9430#define GEN6_OFFSET(x) ((x) << 19)
9431#define GEN6_AGGRESSIVE_TURBO (0 << 15)
9432#define GEN9_SW_REQ_UNSLICE_RATIO_SHIFT 23
9433#define GEN9_IGNORE_SLICE_RATIO (0 << 0)
9434
9435#define GEN6_RC_VIDEO_FREQ _MMIO(0xA00C)
9436#define GEN6_RC_CONTROL _MMIO(0xA090)
9437#define GEN6_RC_CTL_RC6pp_ENABLE (1 << 16)
9438#define GEN6_RC_CTL_RC6p_ENABLE (1 << 17)
9439#define GEN6_RC_CTL_RC6_ENABLE (1 << 18)
9440#define GEN6_RC_CTL_RC1e_ENABLE (1 << 20)
9441#define GEN6_RC_CTL_RC7_ENABLE (1 << 22)
9442#define VLV_RC_CTL_CTX_RST_PARALLEL (1 << 24)
9443#define GEN7_RC_CTL_TO_MODE (1 << 28)
9444#define GEN6_RC_CTL_EI_MODE(x) ((x) << 27)
9445#define GEN6_RC_CTL_HW_ENABLE (1 << 31)
9446#define GEN6_RP_DOWN_TIMEOUT _MMIO(0xA010)
9447#define GEN6_RP_INTERRUPT_LIMITS _MMIO(0xA014)
9448#define GEN6_RPSTAT1 _MMIO(0xA01C)
9449#define GEN6_CAGF_SHIFT 8
9450#define HSW_CAGF_SHIFT 7
9451#define GEN9_CAGF_SHIFT 23
9452#define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT)
9453#define HSW_CAGF_MASK (0x7f << HSW_CAGF_SHIFT)
9454#define GEN9_CAGF_MASK (0x1ff << GEN9_CAGF_SHIFT)
9455#define GEN6_RP_CONTROL _MMIO(0xA024)
9456#define GEN6_RP_MEDIA_TURBO (1 << 11)
9457#define GEN6_RP_MEDIA_MODE_MASK (3 << 9)
9458#define GEN6_RP_MEDIA_HW_TURBO_MODE (3 << 9)
9459#define GEN6_RP_MEDIA_HW_NORMAL_MODE (2 << 9)
9460#define GEN6_RP_MEDIA_HW_MODE (1 << 9)
9461#define GEN6_RP_MEDIA_SW_MODE (0 << 9)
9462#define GEN6_RP_MEDIA_IS_GFX (1 << 8)
9463#define GEN6_RP_ENABLE (1 << 7)
9464#define GEN6_RP_UP_IDLE_MIN (0x1 << 3)
9465#define GEN6_RP_UP_BUSY_AVG (0x2 << 3)
9466#define GEN6_RP_UP_BUSY_CONT (0x4 << 3)
9467#define GEN6_RP_DOWN_IDLE_AVG (0x2 << 0)
9468#define GEN6_RP_DOWN_IDLE_CONT (0x1 << 0)
9469#define GEN6_RPSWCTL_SHIFT 9
9470#define GEN9_RPSWCTL_ENABLE (0x2 << GEN6_RPSWCTL_SHIFT)
9471#define GEN9_RPSWCTL_DISABLE (0x0 << GEN6_RPSWCTL_SHIFT)
9472#define GEN6_RP_UP_THRESHOLD _MMIO(0xA02C)
9473#define GEN6_RP_DOWN_THRESHOLD _MMIO(0xA030)
9474#define GEN6_RP_CUR_UP_EI _MMIO(0xA050)
9475#define GEN6_RP_EI_MASK 0xffffff
9476#define GEN6_CURICONT_MASK GEN6_RP_EI_MASK
9477#define GEN6_RP_CUR_UP _MMIO(0xA054)
9478#define GEN6_CURBSYTAVG_MASK GEN6_RP_EI_MASK
9479#define GEN6_RP_PREV_UP _MMIO(0xA058)
9480#define GEN6_RP_CUR_DOWN_EI _MMIO(0xA05C)
9481#define GEN6_CURIAVG_MASK GEN6_RP_EI_MASK
9482#define GEN6_RP_CUR_DOWN _MMIO(0xA060)
9483#define GEN6_RP_PREV_DOWN _MMIO(0xA064)
9484#define GEN6_RP_UP_EI _MMIO(0xA068)
9485#define GEN6_RP_DOWN_EI _MMIO(0xA06C)
9486#define GEN6_RP_IDLE_HYSTERSIS _MMIO(0xA070)
9487#define GEN6_RPDEUHWTC _MMIO(0xA080)
9488#define GEN6_RPDEUC _MMIO(0xA084)
9489#define GEN6_RPDEUCSW _MMIO(0xA088)
9490#define GEN6_RC_STATE _MMIO(0xA094)
9491#define RC_SW_TARGET_STATE_SHIFT 16
9492#define RC_SW_TARGET_STATE_MASK (7 << RC_SW_TARGET_STATE_SHIFT)
9493#define GEN6_RC1_WAKE_RATE_LIMIT _MMIO(0xA098)
9494#define GEN6_RC6_WAKE_RATE_LIMIT _MMIO(0xA09C)
9495#define GEN6_RC6pp_WAKE_RATE_LIMIT _MMIO(0xA0A0)
9496#define GEN10_MEDIA_WAKE_RATE_LIMIT _MMIO(0xA0A0)
9497#define GEN6_RC_EVALUATION_INTERVAL _MMIO(0xA0A8)
9498#define GEN6_RC_IDLE_HYSTERSIS _MMIO(0xA0AC)
9499#define GEN6_RC_SLEEP _MMIO(0xA0B0)
9500#define GEN6_RCUBMABDTMR _MMIO(0xA0B0)
9501#define GEN6_RC1e_THRESHOLD _MMIO(0xA0B4)
9502#define GEN6_RC6_THRESHOLD _MMIO(0xA0B8)
9503#define GEN6_RC6p_THRESHOLD _MMIO(0xA0BC)
9504#define VLV_RCEDATA _MMIO(0xA0BC)
9505#define GEN6_RC6pp_THRESHOLD _MMIO(0xA0C0)
9506#define GEN6_PMINTRMSK _MMIO(0xA168)
9507#define GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC (1 << 31)
9508#define ARAT_EXPIRED_INTRMSK (1 << 9)
9509#define GEN8_MISC_CTRL0 _MMIO(0xA180)
9510#define VLV_PWRDWNUPCTL _MMIO(0xA294)
9511#define GEN9_MEDIA_PG_IDLE_HYSTERESIS _MMIO(0xA0C4)
9512#define GEN9_RENDER_PG_IDLE_HYSTERESIS _MMIO(0xA0C8)
9513#define GEN9_PG_ENABLE _MMIO(0xA210)
9514#define GEN9_RENDER_PG_ENABLE REG_BIT(0)
9515#define GEN9_MEDIA_PG_ENABLE REG_BIT(1)
9516#define GEN11_MEDIA_SAMPLER_PG_ENABLE REG_BIT(2)
9517#define VDN_HCP_POWERGATE_ENABLE(n) REG_BIT(3 + 2 * (n))
9518#define VDN_MFX_POWERGATE_ENABLE(n) REG_BIT(4 + 2 * (n))
9519#define GEN8_PUSHBUS_CONTROL _MMIO(0xA248)
9520#define GEN8_PUSHBUS_ENABLE _MMIO(0xA250)
9521#define GEN8_PUSHBUS_SHIFT _MMIO(0xA25C)
9522
9523#define VLV_CHICKEN_3 _MMIO(VLV_DISPLAY_BASE + 0x7040C)
9524#define PIXEL_OVERLAP_CNT_MASK (3 << 30)
9525#define PIXEL_OVERLAP_CNT_SHIFT 30
9526
9527#define GEN6_PMISR _MMIO(0x44020)
9528#define GEN6_PMIMR _MMIO(0x44024)
9529#define GEN6_PMIIR _MMIO(0x44028)
9530#define GEN6_PMIER _MMIO(0x4402C)
9531#define GEN6_PM_MBOX_EVENT (1 << 25)
9532#define GEN6_PM_THERMAL_EVENT (1 << 24)
9533
9534
9535
9536
9537
9538#define GEN6_PM_RP_DOWN_TIMEOUT (1 << 6)
9539#define GEN6_PM_RP_UP_THRESHOLD (1 << 5)
9540#define GEN6_PM_RP_DOWN_THRESHOLD (1 << 4)
9541#define GEN6_PM_RP_UP_EI_EXPIRED (1 << 2)
9542#define GEN6_PM_RP_DOWN_EI_EXPIRED (1 << 1)
9543#define GEN6_PM_RPS_EVENTS (GEN6_PM_RP_UP_EI_EXPIRED | \
9544 GEN6_PM_RP_UP_THRESHOLD | \
9545 GEN6_PM_RP_DOWN_EI_EXPIRED | \
9546 GEN6_PM_RP_DOWN_THRESHOLD | \
9547 GEN6_PM_RP_DOWN_TIMEOUT)
9548
9549#define GEN7_GT_SCRATCH(i) _MMIO(0x4F100 + (i) * 4)
9550#define GEN7_GT_SCRATCH_REG_NUM 8
9551
9552#define VLV_GTLC_SURVIVABILITY_REG _MMIO(0x130098)
9553#define VLV_GFX_CLK_STATUS_BIT (1 << 3)
9554#define VLV_GFX_CLK_FORCE_ON_BIT (1 << 2)
9555
9556#define GEN6_GT_GFX_RC6_LOCKED _MMIO(0x138104)
9557#define VLV_COUNTER_CONTROL _MMIO(0x138104)
9558#define VLV_COUNT_RANGE_HIGH (1 << 15)
9559#define VLV_MEDIA_RC0_COUNT_EN (1 << 5)
9560#define VLV_RENDER_RC0_COUNT_EN (1 << 4)
9561#define VLV_MEDIA_RC6_COUNT_EN (1 << 1)
9562#define VLV_RENDER_RC6_COUNT_EN (1 << 0)
9563#define GEN6_GT_GFX_RC6 _MMIO(0x138108)
9564#define VLV_GT_RENDER_RC6 _MMIO(0x138108)
9565#define VLV_GT_MEDIA_RC6 _MMIO(0x13810C)
9566
9567#define GEN6_GT_GFX_RC6p _MMIO(0x13810C)
9568#define GEN6_GT_GFX_RC6pp _MMIO(0x138110)
9569#define VLV_RENDER_C0_COUNT _MMIO(0x138118)
9570#define VLV_MEDIA_C0_COUNT _MMIO(0x13811C)
9571
9572#define GEN6_PCODE_MAILBOX _MMIO(0x138124)
9573#define GEN6_PCODE_READY (1 << 31)
9574#define GEN6_PCODE_ERROR_MASK 0xFF
9575#define GEN6_PCODE_SUCCESS 0x0
9576#define GEN6_PCODE_ILLEGAL_CMD 0x1
9577#define GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x2
9578#define GEN6_PCODE_TIMEOUT 0x3
9579#define GEN6_PCODE_UNIMPLEMENTED_CMD 0xFF
9580#define GEN7_PCODE_TIMEOUT 0x2
9581#define GEN7_PCODE_ILLEGAL_DATA 0x3
9582#define GEN11_PCODE_ILLEGAL_SUBCOMMAND 0x4
9583#define GEN11_PCODE_LOCKED 0x6
9584#define GEN11_PCODE_REJECTED 0x11
9585#define GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10
9586#define GEN6_PCODE_WRITE_RC6VIDS 0x4
9587#define GEN6_PCODE_READ_RC6VIDS 0x5
9588#define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5)
9589#define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245)
9590#define BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ 0x18
9591#define GEN9_PCODE_READ_MEM_LATENCY 0x6
9592#define GEN9_MEM_LATENCY_LEVEL_MASK 0xFF
9593#define GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT 8
9594#define GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT 16
9595#define GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT 24
9596#define SKL_PCODE_LOAD_HDCP_KEYS 0x5
9597#define SKL_PCODE_CDCLK_CONTROL 0x7
9598#define SKL_CDCLK_PREPARE_FOR_CHANGE 0x3
9599#define SKL_CDCLK_READY_FOR_CHANGE 0x1
9600#define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8
9601#define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9
9602#define GEN6_READ_OC_PARAMS 0xc
9603#define ICL_PCODE_MEM_SUBSYSYSTEM_INFO 0xd
9604#define ICL_PCODE_MEM_SS_READ_GLOBAL_INFO (0x0 << 8)
9605#define ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point) (((point) << 16) | (0x1 << 8))
9606#define ADL_PCODE_MEM_SS_READ_PSF_GV_INFO ((0) | (0x2 << 8))
9607#define ICL_PCODE_SAGV_DE_MEM_SS_CONFIG 0xe
9608#define ICL_PCODE_POINTS_RESTRICTED 0x0
9609#define ICL_PCODE_POINTS_RESTRICTED_MASK 0xf
9610#define ADLS_PSF_PT_SHIFT 8
9611#define ADLS_QGV_PT_MASK REG_GENMASK(7, 0)
9612#define ADLS_PSF_PT_MASK REG_GENMASK(10, 8)
9613#define GEN6_PCODE_READ_D_COMP 0x10
9614#define GEN6_PCODE_WRITE_D_COMP 0x11
9615#define ICL_PCODE_EXIT_TCCOLD 0x12
9616#define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17
9617#define DISPLAY_IPS_CONTROL 0x19
9618#define TGL_PCODE_TCCOLD 0x26
9619#define TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED REG_BIT(0)
9620#define TGL_PCODE_EXIT_TCCOLD_DATA_L_BLOCK_REQ 0
9621#define TGL_PCODE_EXIT_TCCOLD_DATA_L_UNBLOCK_REQ REG_BIT(0)
9622
9623#define IPS_PCODE_CONTROL (1 << 30)
9624#define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A
9625#define GEN9_PCODE_SAGV_CONTROL 0x21
9626#define GEN9_SAGV_DISABLE 0x0
9627#define GEN9_SAGV_IS_DISABLED 0x1
9628#define GEN9_SAGV_ENABLE 0x3
9629#define DG1_PCODE_STATUS 0x7E
9630#define DG1_UNCORE_GET_INIT_STATUS 0x0
9631#define DG1_UNCORE_INIT_STATUS_COMPLETE 0x1
9632#define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US 0x23
9633#define GEN6_PCODE_DATA _MMIO(0x138128)
9634#define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
9635#define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16
9636#define GEN6_PCODE_DATA1 _MMIO(0x13812C)
9637
9638#define GEN6_GT_CORE_STATUS _MMIO(0x138060)
9639#define GEN6_CORE_CPD_STATE_MASK (7 << 4)
9640#define GEN6_RCn_MASK 7
9641#define GEN6_RC0 0
9642#define GEN6_RC3 2
9643#define GEN6_RC6 3
9644#define GEN6_RC7 4
9645
9646#define GEN8_GT_SLICE_INFO _MMIO(0x138064)
9647#define GEN8_LSLICESTAT_MASK 0x7
9648
9649#define CHV_POWER_SS0_SIG1 _MMIO(0xa720)
9650#define CHV_POWER_SS1_SIG1 _MMIO(0xa728)
9651#define CHV_SS_PG_ENABLE (1 << 1)
9652#define CHV_EU08_PG_ENABLE (1 << 9)
9653#define CHV_EU19_PG_ENABLE (1 << 17)
9654#define CHV_EU210_PG_ENABLE (1 << 25)
9655
9656#define CHV_POWER_SS0_SIG2 _MMIO(0xa724)
9657#define CHV_POWER_SS1_SIG2 _MMIO(0xa72c)
9658#define CHV_EU311_PG_ENABLE (1 << 1)
9659
9660#define GEN9_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + (slice) * 0x4)
9661#define GEN10_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + ((slice) / 3) * 0x34 + \
9662 ((slice) % 3) * 0x4)
9663#define GEN9_PGCTL_SLICE_ACK (1 << 0)
9664#define GEN9_PGCTL_SS_ACK(subslice) (1 << (2 + (subslice) * 2))
9665#define GEN10_PGCTL_VALID_SS_MASK(slice) ((slice) == 0 ? 0x7F : 0x1F)
9666
9667#define GEN9_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + (slice) * 0x8)
9668#define GEN10_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + ((slice) / 3) * 0x30 + \
9669 ((slice) % 3) * 0x8)
9670#define GEN9_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + (slice) * 0x8)
9671#define GEN10_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + ((slice) / 3) * 0x30 + \
9672 ((slice) % 3) * 0x8)
9673#define GEN9_PGCTL_SSA_EU08_ACK (1 << 0)
9674#define GEN9_PGCTL_SSA_EU19_ACK (1 << 2)
9675#define GEN9_PGCTL_SSA_EU210_ACK (1 << 4)
9676#define GEN9_PGCTL_SSA_EU311_ACK (1 << 6)
9677#define GEN9_PGCTL_SSB_EU08_ACK (1 << 8)
9678#define GEN9_PGCTL_SSB_EU19_ACK (1 << 10)
9679#define GEN9_PGCTL_SSB_EU210_ACK (1 << 12)
9680#define GEN9_PGCTL_SSB_EU311_ACK (1 << 14)
9681
9682#define GEN7_MISCCPCTL _MMIO(0x9424)
9683#define GEN7_DOP_CLOCK_GATE_ENABLE (1 << 0)
9684#define GEN8_DOP_CLOCK_GATE_CFCLK_ENABLE (1 << 2)
9685#define GEN8_DOP_CLOCK_GATE_GUC_ENABLE (1 << 4)
9686#define GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE (1 << 6)
9687
9688#define GEN8_GARBCNTL _MMIO(0xB004)
9689#define GEN9_GAPS_TSV_CREDIT_DISABLE (1 << 7)
9690#define GEN11_ARBITRATION_PRIO_ORDER_MASK (0x3f << 22)
9691#define GEN11_HASH_CTRL_EXCL_MASK (0x7f << 0)
9692#define GEN11_HASH_CTRL_EXCL_BIT0 (1 << 0)
9693
9694#define GEN11_GLBLINVL _MMIO(0xB404)
9695#define GEN11_BANK_HASH_ADDR_EXCL_MASK (0x7f << 5)
9696#define GEN11_BANK_HASH_ADDR_EXCL_BIT0 (1 << 5)
9697
9698#define GEN10_DFR_RATIO_EN_AND_CHICKEN _MMIO(0x9550)
9699#define DFR_DISABLE (1 << 9)
9700
9701#define GEN11_GACB_PERF_CTRL _MMIO(0x4B80)
9702#define GEN11_HASH_CTRL_MASK (0x3 << 12 | 0xf << 0)
9703#define GEN11_HASH_CTRL_BIT0 (1 << 0)
9704#define GEN11_HASH_CTRL_BIT4 (1 << 12)
9705
9706#define GEN11_LSN_UNSLCVC _MMIO(0xB43C)
9707#define GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MAXALLOC (1 << 9)
9708#define GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC (1 << 7)
9709
9710#define GEN10_SAMPLER_MODE _MMIO(0xE18C)
9711#define ENABLE_SMALLPL REG_BIT(15)
9712#define GEN11_SAMPLER_ENABLE_HEADLESS_MSG REG_BIT(5)
9713
9714
9715#define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200)
9716#define GEN7_L3CDERRST1_ROW_MASK (0x7ff << 14)
9717#define GEN7_PARITY_ERROR_VALID (1 << 13)
9718#define GEN7_L3CDERRST1_BANK_MASK (3 << 11)
9719#define GEN7_L3CDERRST1_SUBBANK_MASK (7 << 8)
9720#define GEN7_PARITY_ERROR_ROW(reg) \
9721 (((reg) & GEN7_L3CDERRST1_ROW_MASK) >> 14)
9722#define GEN7_PARITY_ERROR_BANK(reg) \
9723 (((reg) & GEN7_L3CDERRST1_BANK_MASK) >> 11)
9724#define GEN7_PARITY_ERROR_SUBBANK(reg) \
9725 (((reg) & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8)
9726#define GEN7_L3CDERRST1_ENABLE (1 << 7)
9727
9728#define GEN7_L3LOG(slice, i) _MMIO(0xB070 + (slice) * 0x200 + (i) * 4)
9729#define GEN7_L3LOG_SIZE 0x80
9730
9731#define GEN7_HALF_SLICE_CHICKEN1 _MMIO(0xe100)
9732#define GEN7_HALF_SLICE_CHICKEN1_GT2 _MMIO(0xf100)
9733#define GEN7_MAX_PS_THREAD_DEP (8 << 12)
9734#define GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE (1 << 10)
9735#define GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE (1 << 4)
9736#define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1 << 3)
9737
9738#define GEN9_HALF_SLICE_CHICKEN5 _MMIO(0xe188)
9739#define GEN9_DG_MIRROR_FIX_ENABLE (1 << 5)
9740#define GEN9_CCS_TLB_PREFETCH_ENABLE (1 << 3)
9741
9742#define GEN8_ROW_CHICKEN _MMIO(0xe4f0)
9743#define FLOW_CONTROL_ENABLE REG_BIT(15)
9744#define UGM_BACKUP_MODE REG_BIT(13)
9745#define MDQ_ARBITRATION_MODE REG_BIT(12)
9746#define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE REG_BIT(8)
9747#define STALL_DOP_GATING_DISABLE REG_BIT(5)
9748#define THROTTLE_12_5 REG_GENMASK(4, 2)
9749#define DISABLE_EARLY_EOT REG_BIT(1)
9750
9751#define GEN7_ROW_CHICKEN2 _MMIO(0xe4f4)
9752#define GEN12_DISABLE_READ_SUPPRESSION REG_BIT(15)
9753#define GEN12_DISABLE_EARLY_READ REG_BIT(14)
9754#define GEN12_ENABLE_LARGE_GRF_MODE REG_BIT(12)
9755#define GEN12_PUSH_CONST_DEREF_HOLD_DIS REG_BIT(8)
9756
9757#define LSC_CHICKEN_BIT_0 _MMIO(0xe7c8)
9758#define FORCE_1_SUB_MESSAGE_PER_FRAGMENT REG_BIT(15)
9759#define LSC_CHICKEN_BIT_0_UDW _MMIO(0xe7c8 + 4)
9760#define DIS_CHAIN_2XSIMD8 REG_BIT(55 - 32)
9761#define FORCE_SLM_FENCE_SCOPE_TO_TILE REG_BIT(42 - 32)
9762#define FORCE_UGM_FENCE_SCOPE_TO_TILE REG_BIT(41 - 32)
9763#define MAXREQS_PER_BANK REG_GENMASK(39 - 32, 37 - 32)
9764#define DISABLE_128B_EVICTION_COMMAND_UDW REG_BIT(36 - 32)
9765
9766#define GEN7_ROW_CHICKEN2_GT2 _MMIO(0xf4f4)
9767#define DOP_CLOCK_GATING_DISABLE (1 << 0)
9768#define PUSH_CONSTANT_DEREF_DISABLE (1 << 8)
9769#define GEN11_TDL_CLOCK_GATING_FIX_DISABLE (1 << 1)
9770
9771#define GEN9_ROW_CHICKEN4 _MMIO(0xe48c)
9772#define GEN12_DISABLE_GRF_CLEAR REG_BIT(13)
9773#define GEN12_DISABLE_TDL_PUSH REG_BIT(9)
9774#define GEN11_DIS_PICK_2ND_EU REG_BIT(7)
9775#define GEN12_DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX REG_BIT(4)
9776
9777#define HSW_ROW_CHICKEN3 _MMIO(0xe49c)
9778#define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6)
9779
9780#define HALF_SLICE_CHICKEN2 _MMIO(0xe180)
9781#define GEN8_ST_PO_DISABLE (1 << 13)
9782
9783#define HALF_SLICE_CHICKEN3 _MMIO(0xe184)
9784#define HSW_SAMPLE_C_PERFORMANCE (1 << 9)
9785#define GEN8_CENTROID_PIXEL_OPT_DIS (1 << 8)
9786#define GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC (1 << 5)
9787#define GEN8_SAMPLER_POWER_BYPASS_DIS (1 << 1)
9788
9789#define GEN9_HALF_SLICE_CHICKEN7 _MMIO(0xe194)
9790#define DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA REG_BIT(15)
9791#define GEN9_SAMPLER_HASH_COMPRESSED_READ_ADDR REG_BIT(8)
9792#define GEN9_ENABLE_YV12_BUGFIX REG_BIT(4)
9793#define GEN9_ENABLE_GPGPU_PREEMPTION REG_BIT(2)
9794
9795
9796#define G4X_AUD_VID_DID _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x62020)
9797#define INTEL_AUDIO_DEVCL 0x808629FB
9798#define INTEL_AUDIO_DEVBLC 0x80862801
9799#define INTEL_AUDIO_DEVCTG 0x80862802
9800
9801#define G4X_AUD_CNTL_ST _MMIO(0x620B4)
9802#define G4X_ELDV_DEVCL_DEVBLC (1 << 13)
9803#define G4X_ELDV_DEVCTG (1 << 14)
9804#define G4X_ELD_ADDR_MASK (0xf << 5)
9805#define G4X_ELD_ACK (1 << 4)
9806#define G4X_HDMIW_HDMIEDID _MMIO(0x6210C)
9807
9808#define _IBX_HDMIW_HDMIEDID_A 0xE2050
9809#define _IBX_HDMIW_HDMIEDID_B 0xE2150
9810#define IBX_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _IBX_HDMIW_HDMIEDID_A, \
9811 _IBX_HDMIW_HDMIEDID_B)
9812#define _IBX_AUD_CNTL_ST_A 0xE20B4
9813#define _IBX_AUD_CNTL_ST_B 0xE21B4
9814#define IBX_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _IBX_AUD_CNTL_ST_A, \
9815 _IBX_AUD_CNTL_ST_B)
9816#define IBX_ELD_BUFFER_SIZE_MASK (0x1f << 10)
9817#define IBX_ELD_ADDRESS_MASK (0x1f << 5)
9818#define IBX_ELD_ACK (1 << 4)
9819#define IBX_AUD_CNTL_ST2 _MMIO(0xE20C0)
9820#define IBX_CP_READY(port) ((1 << 1) << (((port) - 1) * 4))
9821#define IBX_ELD_VALID(port) ((1 << 0) << (((port) - 1) * 4))
9822
9823#define _CPT_HDMIW_HDMIEDID_A 0xE5050
9824#define _CPT_HDMIW_HDMIEDID_B 0xE5150
9825#define CPT_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _CPT_HDMIW_HDMIEDID_A, _CPT_HDMIW_HDMIEDID_B)
9826#define _CPT_AUD_CNTL_ST_A 0xE50B4
9827#define _CPT_AUD_CNTL_ST_B 0xE51B4
9828#define CPT_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _CPT_AUD_CNTL_ST_A, _CPT_AUD_CNTL_ST_B)
9829#define CPT_AUD_CNTRL_ST2 _MMIO(0xE50C0)
9830
9831#define _VLV_HDMIW_HDMIEDID_A (VLV_DISPLAY_BASE + 0x62050)
9832#define _VLV_HDMIW_HDMIEDID_B (VLV_DISPLAY_BASE + 0x62150)
9833#define VLV_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _VLV_HDMIW_HDMIEDID_A, _VLV_HDMIW_HDMIEDID_B)
9834#define _VLV_AUD_CNTL_ST_A (VLV_DISPLAY_BASE + 0x620B4)
9835#define _VLV_AUD_CNTL_ST_B (VLV_DISPLAY_BASE + 0x621B4)
9836#define VLV_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _VLV_AUD_CNTL_ST_A, _VLV_AUD_CNTL_ST_B)
9837#define VLV_AUD_CNTL_ST2 _MMIO(VLV_DISPLAY_BASE + 0x620C0)
9838
9839
9840
9841
9842
9843#define GEN7_SO_WRITE_OFFSET(n) _MMIO(0x5280 + (n) * 4)
9844
9845#define _IBX_AUD_CONFIG_A 0xe2000
9846#define _IBX_AUD_CONFIG_B 0xe2100
9847#define IBX_AUD_CFG(pipe) _MMIO_PIPE(pipe, _IBX_AUD_CONFIG_A, _IBX_AUD_CONFIG_B)
9848#define _CPT_AUD_CONFIG_A 0xe5000
9849#define _CPT_AUD_CONFIG_B 0xe5100
9850#define CPT_AUD_CFG(pipe) _MMIO_PIPE(pipe, _CPT_AUD_CONFIG_A, _CPT_AUD_CONFIG_B)
9851#define _VLV_AUD_CONFIG_A (VLV_DISPLAY_BASE + 0x62000)
9852#define _VLV_AUD_CONFIG_B (VLV_DISPLAY_BASE + 0x62100)
9853#define VLV_AUD_CFG(pipe) _MMIO_PIPE(pipe, _VLV_AUD_CONFIG_A, _VLV_AUD_CONFIG_B)
9854
9855#define AUD_CONFIG_N_VALUE_INDEX (1 << 29)
9856#define AUD_CONFIG_N_PROG_ENABLE (1 << 28)
9857#define AUD_CONFIG_UPPER_N_SHIFT 20
9858#define AUD_CONFIG_UPPER_N_MASK (0xff << 20)
9859#define AUD_CONFIG_LOWER_N_SHIFT 4
9860#define AUD_CONFIG_LOWER_N_MASK (0xfff << 4)
9861#define AUD_CONFIG_N_MASK (AUD_CONFIG_UPPER_N_MASK | AUD_CONFIG_LOWER_N_MASK)
9862#define AUD_CONFIG_N(n) \
9863 (((((n) >> 12) & 0xff) << AUD_CONFIG_UPPER_N_SHIFT) | \
9864 (((n) & 0xfff) << AUD_CONFIG_LOWER_N_SHIFT))
9865#define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16
9866#define AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK (0xf << 16)
9867#define AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 (0 << 16)
9868#define AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 (1 << 16)
9869#define AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 (2 << 16)
9870#define AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 (3 << 16)
9871#define AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 (4 << 16)
9872#define AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 (5 << 16)
9873#define AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 (6 << 16)
9874#define AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 (7 << 16)
9875#define AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 (8 << 16)
9876#define AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 (9 << 16)
9877#define AUD_CONFIG_PIXEL_CLOCK_HDMI_296703 (10 << 16)
9878#define AUD_CONFIG_PIXEL_CLOCK_HDMI_297000 (11 << 16)
9879#define AUD_CONFIG_PIXEL_CLOCK_HDMI_593407 (12 << 16)
9880#define AUD_CONFIG_PIXEL_CLOCK_HDMI_594000 (13 << 16)
9881#define AUD_CONFIG_DISABLE_NCTS (1 << 3)
9882
9883
9884#define _HSW_AUD_CONFIG_A 0x65000
9885#define _HSW_AUD_CONFIG_B 0x65100
9886#define HSW_AUD_CFG(trans) _MMIO_TRANS(trans, _HSW_AUD_CONFIG_A, _HSW_AUD_CONFIG_B)
9887
9888#define _HSW_AUD_MISC_CTRL_A 0x65010
9889#define _HSW_AUD_MISC_CTRL_B 0x65110
9890#define HSW_AUD_MISC_CTRL(trans) _MMIO_TRANS(trans, _HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B)
9891
9892#define _HSW_AUD_M_CTS_ENABLE_A 0x65028
9893#define _HSW_AUD_M_CTS_ENABLE_B 0x65128
9894#define HSW_AUD_M_CTS_ENABLE(trans) _MMIO_TRANS(trans, _HSW_AUD_M_CTS_ENABLE_A, _HSW_AUD_M_CTS_ENABLE_B)
9895#define AUD_M_CTS_M_VALUE_INDEX (1 << 21)
9896#define AUD_M_CTS_M_PROG_ENABLE (1 << 20)
9897#define AUD_CONFIG_M_MASK 0xfffff
9898
9899#define _HSW_AUD_DIP_ELD_CTRL_ST_A 0x650b4
9900#define _HSW_AUD_DIP_ELD_CTRL_ST_B 0x651b4
9901#define HSW_AUD_DIP_ELD_CTRL(trans) _MMIO_TRANS(trans, _HSW_AUD_DIP_ELD_CTRL_ST_A, _HSW_AUD_DIP_ELD_CTRL_ST_B)
9902
9903
9904#define _HSW_AUD_DIG_CNVT_1 0x65080
9905#define _HSW_AUD_DIG_CNVT_2 0x65180
9906#define AUD_DIG_CNVT(trans) _MMIO_TRANS(trans, _HSW_AUD_DIG_CNVT_1, _HSW_AUD_DIG_CNVT_2)
9907#define DIP_PORT_SEL_MASK 0x3
9908
9909#define _HSW_AUD_EDID_DATA_A 0x65050
9910#define _HSW_AUD_EDID_DATA_B 0x65150
9911#define HSW_AUD_EDID_DATA(trans) _MMIO_TRANS(trans, _HSW_AUD_EDID_DATA_A, _HSW_AUD_EDID_DATA_B)
9912
9913#define HSW_AUD_PIPE_CONV_CFG _MMIO(0x6507c)
9914#define HSW_AUD_PIN_ELD_CP_VLD _MMIO(0x650c0)
9915#define AUDIO_INACTIVE(trans) ((1 << 3) << ((trans) * 4))
9916#define AUDIO_OUTPUT_ENABLE(trans) ((1 << 2) << ((trans) * 4))
9917#define AUDIO_CP_READY(trans) ((1 << 1) << ((trans) * 4))
9918#define AUDIO_ELD_VALID(trans) ((1 << 0) << ((trans) * 4))
9919
9920#define _AUD_TCA_DP_2DOT0_CTRL 0x650bc
9921#define _AUD_TCB_DP_2DOT0_CTRL 0x651bc
9922#define AUD_DP_2DOT0_CTRL(trans) _MMIO_TRANS(trans, _AUD_TCA_DP_2DOT0_CTRL, _AUD_TCB_DP_2DOT0_CTRL)
9923#define AUD_ENABLE_SDP_SPLIT REG_BIT(31)
9924
9925#define HSW_AUD_CHICKENBIT _MMIO(0x65f10)
9926#define SKL_AUD_CODEC_WAKE_SIGNAL (1 << 15)
9927
9928#define AUD_FREQ_CNTRL _MMIO(0x65900)
9929#define AUD_PIN_BUF_CTL _MMIO(0x48414)
9930#define AUD_PIN_BUF_ENABLE REG_BIT(31)
9931
9932#define AUD_TS_CDCLK_M _MMIO(0x65ea0)
9933#define AUD_TS_CDCLK_M_EN REG_BIT(31)
9934#define AUD_TS_CDCLK_N _MMIO(0x65ea4)
9935
9936
9937#define AUD_CONFIG_BE _MMIO(0x65ef0)
9938#define HBLANK_EARLY_ENABLE_ICL(pipe) (0x1 << (20 - (pipe)))
9939#define HBLANK_EARLY_ENABLE_TGL(pipe) (0x1 << (24 + (pipe)))
9940#define HBLANK_START_COUNT_MASK(pipe) (0x7 << (3 + ((pipe) * 6)))
9941#define HBLANK_START_COUNT(pipe, val) (((val) & 0x7) << (3 + ((pipe)) * 6))
9942#define NUMBER_SAMPLES_PER_LINE_MASK(pipe) (0x3 << ((pipe) * 6))
9943#define NUMBER_SAMPLES_PER_LINE(pipe, val) (((val) & 0x3) << ((pipe) * 6))
9944
9945#define HBLANK_START_COUNT_8 0
9946#define HBLANK_START_COUNT_16 1
9947#define HBLANK_START_COUNT_32 2
9948#define HBLANK_START_COUNT_64 3
9949#define HBLANK_START_COUNT_96 4
9950#define HBLANK_START_COUNT_128 5
9951
9952
9953
9954
9955
9956
9957
9958
9959
9960
9961
9962
9963
9964
9965
9966
9967#define HSW_PWR_WELL_CTL1 _MMIO(0x45400)
9968#define HSW_PWR_WELL_CTL2 _MMIO(0x45404)
9969#define HSW_PWR_WELL_CTL3 _MMIO(0x45408)
9970#define HSW_PWR_WELL_CTL4 _MMIO(0x4540C)
9971#define HSW_PWR_WELL_CTL_REQ(pw_idx) (0x2 << ((pw_idx) * 2))
9972#define HSW_PWR_WELL_CTL_STATE(pw_idx) (0x1 << ((pw_idx) * 2))
9973
9974
9975#define HSW_PW_CTL_IDX_GLOBAL 15
9976
9977
9978#define SKL_PW_CTL_IDX_PW_2 15
9979#define SKL_PW_CTL_IDX_PW_1 14
9980#define GLK_PW_CTL_IDX_AUX_C 10
9981#define GLK_PW_CTL_IDX_AUX_B 9
9982#define GLK_PW_CTL_IDX_AUX_A 8
9983#define SKL_PW_CTL_IDX_DDI_D 4
9984#define SKL_PW_CTL_IDX_DDI_C 3
9985#define SKL_PW_CTL_IDX_DDI_B 2
9986#define SKL_PW_CTL_IDX_DDI_A_E 1
9987#define GLK_PW_CTL_IDX_DDI_A 1
9988#define SKL_PW_CTL_IDX_MISC_IO 0
9989
9990
9991#define TGL_PW_CTL_IDX_PW_5 4
9992#define ICL_PW_CTL_IDX_PW_4 3
9993#define ICL_PW_CTL_IDX_PW_3 2
9994#define ICL_PW_CTL_IDX_PW_2 1
9995#define ICL_PW_CTL_IDX_PW_1 0
9996
9997
9998#define XELPD_PW_CTL_IDX_PW_D 8
9999#define XELPD_PW_CTL_IDX_PW_C 7
10000#define XELPD_PW_CTL_IDX_PW_B 6
10001#define XELPD_PW_CTL_IDX_PW_A 5
10002
10003#define ICL_PWR_WELL_CTL_AUX1 _MMIO(0x45440)
10004#define ICL_PWR_WELL_CTL_AUX2 _MMIO(0x45444)
10005#define ICL_PWR_WELL_CTL_AUX4 _MMIO(0x4544C)
10006#define TGL_PW_CTL_IDX_AUX_TBT6 14
10007#define TGL_PW_CTL_IDX_AUX_TBT5 13
10008#define TGL_PW_CTL_IDX_AUX_TBT4 12
10009#define ICL_PW_CTL_IDX_AUX_TBT4 11
10010#define TGL_PW_CTL_IDX_AUX_TBT3 11
10011#define ICL_PW_CTL_IDX_AUX_TBT3 10
10012#define TGL_PW_CTL_IDX_AUX_TBT2 10
10013#define ICL_PW_CTL_IDX_AUX_TBT2 9
10014#define TGL_PW_CTL_IDX_AUX_TBT1 9
10015#define ICL_PW_CTL_IDX_AUX_TBT1 8
10016#define TGL_PW_CTL_IDX_AUX_TC6 8
10017#define XELPD_PW_CTL_IDX_AUX_E 8
10018#define TGL_PW_CTL_IDX_AUX_TC5 7
10019#define XELPD_PW_CTL_IDX_AUX_D 7
10020#define TGL_PW_CTL_IDX_AUX_TC4 6
10021#define ICL_PW_CTL_IDX_AUX_F 5
10022#define TGL_PW_CTL_IDX_AUX_TC3 5
10023#define ICL_PW_CTL_IDX_AUX_E 4
10024#define TGL_PW_CTL_IDX_AUX_TC2 4
10025#define ICL_PW_CTL_IDX_AUX_D 3
10026#define TGL_PW_CTL_IDX_AUX_TC1 3
10027#define ICL_PW_CTL_IDX_AUX_C 2
10028#define ICL_PW_CTL_IDX_AUX_B 1
10029#define ICL_PW_CTL_IDX_AUX_A 0
10030
10031#define ICL_PWR_WELL_CTL_DDI1 _MMIO(0x45450)
10032#define ICL_PWR_WELL_CTL_DDI2 _MMIO(0x45454)
10033#define ICL_PWR_WELL_CTL_DDI4 _MMIO(0x4545C)
10034#define XELPD_PW_CTL_IDX_DDI_E 8
10035#define TGL_PW_CTL_IDX_DDI_TC6 8
10036#define XELPD_PW_CTL_IDX_DDI_D 7
10037#define TGL_PW_CTL_IDX_DDI_TC5 7
10038#define TGL_PW_CTL_IDX_DDI_TC4 6
10039#define ICL_PW_CTL_IDX_DDI_F 5
10040#define TGL_PW_CTL_IDX_DDI_TC3 5
10041#define ICL_PW_CTL_IDX_DDI_E 4
10042#define TGL_PW_CTL_IDX_DDI_TC2 4
10043#define ICL_PW_CTL_IDX_DDI_D 3
10044#define TGL_PW_CTL_IDX_DDI_TC1 3
10045#define ICL_PW_CTL_IDX_DDI_C 2
10046#define ICL_PW_CTL_IDX_DDI_B 1
10047#define ICL_PW_CTL_IDX_DDI_A 0
10048
10049
10050#define HSW_PWR_WELL_CTL5 _MMIO(0x45410)
10051#define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1 << 31)
10052#define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1 << 20)
10053#define HSW_PWR_WELL_FORCE_ON (1 << 19)
10054#define HSW_PWR_WELL_CTL6 _MMIO(0x45414)
10055
10056
10057enum skl_power_gate {
10058 SKL_PG0,
10059 SKL_PG1,
10060 SKL_PG2,
10061 ICL_PG3,
10062 ICL_PG4,
10063};
10064
10065#define SKL_FUSE_STATUS _MMIO(0x42000)
10066#define SKL_FUSE_DOWNLOAD_STATUS (1 << 31)
10067
10068
10069
10070
10071#define SKL_PW_CTL_IDX_TO_PG(pw_idx) \
10072 ((pw_idx) - SKL_PW_CTL_IDX_PW_1 + SKL_PG1)
10073
10074
10075
10076
10077#define ICL_PW_CTL_IDX_TO_PG(pw_idx) \
10078 ((pw_idx) - ICL_PW_CTL_IDX_PW_1 + SKL_PG1)
10079#define SKL_FUSE_PG_DIST_STATUS(pg) (1 << (27 - (pg)))
10080
10081#define _ICL_AUX_REG_IDX(pw_idx) ((pw_idx) - ICL_PW_CTL_IDX_AUX_A)
10082#define _ICL_AUX_ANAOVRD1_A 0x162398
10083#define _ICL_AUX_ANAOVRD1_B 0x6C398
10084#define ICL_AUX_ANAOVRD1(pw_idx) _MMIO(_PICK(_ICL_AUX_REG_IDX(pw_idx), \
10085 _ICL_AUX_ANAOVRD1_A, \
10086 _ICL_AUX_ANAOVRD1_B))
10087#define ICL_AUX_ANAOVRD1_LDO_BYPASS (1 << 7)
10088#define ICL_AUX_ANAOVRD1_ENABLE (1 << 0)
10089
10090
10091#define HDCP_KEY_CONF _MMIO(0x66c00)
10092#define HDCP_AKSV_SEND_TRIGGER BIT(31)
10093#define HDCP_CLEAR_KEYS_TRIGGER BIT(30)
10094#define HDCP_KEY_LOAD_TRIGGER BIT(8)
10095#define HDCP_KEY_STATUS _MMIO(0x66c04)
10096#define HDCP_FUSE_IN_PROGRESS BIT(7)
10097#define HDCP_FUSE_ERROR BIT(6)
10098#define HDCP_FUSE_DONE BIT(5)
10099#define HDCP_KEY_LOAD_STATUS BIT(1)
10100#define HDCP_KEY_LOAD_DONE BIT(0)
10101#define HDCP_AKSV_LO _MMIO(0x66c10)
10102#define HDCP_AKSV_HI _MMIO(0x66c14)
10103
10104
10105#define HDCP_REP_CTL _MMIO(0x66d00)
10106#define HDCP_TRANSA_REP_PRESENT BIT(31)
10107#define HDCP_TRANSB_REP_PRESENT BIT(30)
10108#define HDCP_TRANSC_REP_PRESENT BIT(29)
10109#define HDCP_TRANSD_REP_PRESENT BIT(28)
10110#define HDCP_DDIB_REP_PRESENT BIT(30)
10111#define HDCP_DDIA_REP_PRESENT BIT(29)
10112#define HDCP_DDIC_REP_PRESENT BIT(28)
10113#define HDCP_DDID_REP_PRESENT BIT(27)
10114#define HDCP_DDIF_REP_PRESENT BIT(26)
10115#define HDCP_DDIE_REP_PRESENT BIT(25)
10116#define HDCP_TRANSA_SHA1_M0 (1 << 20)
10117#define HDCP_TRANSB_SHA1_M0 (2 << 20)
10118#define HDCP_TRANSC_SHA1_M0 (3 << 20)
10119#define HDCP_TRANSD_SHA1_M0 (4 << 20)
10120#define HDCP_DDIB_SHA1_M0 (1 << 20)
10121#define HDCP_DDIA_SHA1_M0 (2 << 20)
10122#define HDCP_DDIC_SHA1_M0 (3 << 20)
10123#define HDCP_DDID_SHA1_M0 (4 << 20)
10124#define HDCP_DDIF_SHA1_M0 (5 << 20)
10125#define HDCP_DDIE_SHA1_M0 (6 << 20)
10126#define HDCP_SHA1_BUSY BIT(16)
10127#define HDCP_SHA1_READY BIT(17)
10128#define HDCP_SHA1_COMPLETE BIT(18)
10129#define HDCP_SHA1_V_MATCH BIT(19)
10130#define HDCP_SHA1_TEXT_32 (1 << 1)
10131#define HDCP_SHA1_COMPLETE_HASH (2 << 1)
10132#define HDCP_SHA1_TEXT_24 (4 << 1)
10133#define HDCP_SHA1_TEXT_16 (5 << 1)
10134#define HDCP_SHA1_TEXT_8 (6 << 1)
10135#define HDCP_SHA1_TEXT_0 (7 << 1)
10136#define HDCP_SHA_V_PRIME_H0 _MMIO(0x66d04)
10137#define HDCP_SHA_V_PRIME_H1 _MMIO(0x66d08)
10138#define HDCP_SHA_V_PRIME_H2 _MMIO(0x66d0C)
10139#define HDCP_SHA_V_PRIME_H3 _MMIO(0x66d10)
10140#define HDCP_SHA_V_PRIME_H4 _MMIO(0x66d14)
10141#define HDCP_SHA_V_PRIME(h) _MMIO((0x66d04 + (h) * 4))
10142#define HDCP_SHA_TEXT _MMIO(0x66d18)
10143
10144
10145#define _PORTA_HDCP_AUTHENC 0x66800
10146#define _PORTB_HDCP_AUTHENC 0x66500
10147#define _PORTC_HDCP_AUTHENC 0x66600
10148#define _PORTD_HDCP_AUTHENC 0x66700
10149#define _PORTE_HDCP_AUTHENC 0x66A00
10150#define _PORTF_HDCP_AUTHENC 0x66900
10151#define _PORT_HDCP_AUTHENC(port, x) _MMIO(_PICK(port, \
10152 _PORTA_HDCP_AUTHENC, \
10153 _PORTB_HDCP_AUTHENC, \
10154 _PORTC_HDCP_AUTHENC, \
10155 _PORTD_HDCP_AUTHENC, \
10156 _PORTE_HDCP_AUTHENC, \
10157 _PORTF_HDCP_AUTHENC) + (x))
10158#define PORT_HDCP_CONF(port) _PORT_HDCP_AUTHENC(port, 0x0)
10159#define _TRANSA_HDCP_CONF 0x66400
10160#define _TRANSB_HDCP_CONF 0x66500
10161#define TRANS_HDCP_CONF(trans) _MMIO_TRANS(trans, _TRANSA_HDCP_CONF, \
10162 _TRANSB_HDCP_CONF)
10163#define HDCP_CONF(dev_priv, trans, port) \
10164 (GRAPHICS_VER(dev_priv) >= 12 ? \
10165 TRANS_HDCP_CONF(trans) : \
10166 PORT_HDCP_CONF(port))
10167
10168#define HDCP_CONF_CAPTURE_AN BIT(0)
10169#define HDCP_CONF_AUTH_AND_ENC (BIT(1) | BIT(0))
10170#define PORT_HDCP_ANINIT(port) _PORT_HDCP_AUTHENC(port, 0x4)
10171#define _TRANSA_HDCP_ANINIT 0x66404
10172#define _TRANSB_HDCP_ANINIT 0x66504
10173#define TRANS_HDCP_ANINIT(trans) _MMIO_TRANS(trans, \
10174 _TRANSA_HDCP_ANINIT, \
10175 _TRANSB_HDCP_ANINIT)
10176#define HDCP_ANINIT(dev_priv, trans, port) \
10177 (GRAPHICS_VER(dev_priv) >= 12 ? \
10178 TRANS_HDCP_ANINIT(trans) : \
10179 PORT_HDCP_ANINIT(port))
10180
10181#define PORT_HDCP_ANLO(port) _PORT_HDCP_AUTHENC(port, 0x8)
10182#define _TRANSA_HDCP_ANLO 0x66408
10183#define _TRANSB_HDCP_ANLO 0x66508
10184#define TRANS_HDCP_ANLO(trans) _MMIO_TRANS(trans, _TRANSA_HDCP_ANLO, \
10185 _TRANSB_HDCP_ANLO)
10186#define HDCP_ANLO(dev_priv, trans, port) \
10187 (GRAPHICS_VER(dev_priv) >= 12 ? \
10188 TRANS_HDCP_ANLO(trans) : \
10189 PORT_HDCP_ANLO(port))
10190
10191#define PORT_HDCP_ANHI(port) _PORT_HDCP_AUTHENC(port, 0xC)
10192#define _TRANSA_HDCP_ANHI 0x6640C
10193#define _TRANSB_HDCP_ANHI 0x6650C
10194#define TRANS_HDCP_ANHI(trans) _MMIO_TRANS(trans, _TRANSA_HDCP_ANHI, \
10195 _TRANSB_HDCP_ANHI)
10196#define HDCP_ANHI(dev_priv, trans, port) \
10197 (GRAPHICS_VER(dev_priv) >= 12 ? \
10198 TRANS_HDCP_ANHI(trans) : \
10199 PORT_HDCP_ANHI(port))
10200
10201#define PORT_HDCP_BKSVLO(port) _PORT_HDCP_AUTHENC(port, 0x10)
10202#define _TRANSA_HDCP_BKSVLO 0x66410
10203#define _TRANSB_HDCP_BKSVLO 0x66510
10204#define TRANS_HDCP_BKSVLO(trans) _MMIO_TRANS(trans, \
10205 _TRANSA_HDCP_BKSVLO, \
10206 _TRANSB_HDCP_BKSVLO)
10207#define HDCP_BKSVLO(dev_priv, trans, port) \
10208 (GRAPHICS_VER(dev_priv) >= 12 ? \
10209 TRANS_HDCP_BKSVLO(trans) : \
10210 PORT_HDCP_BKSVLO(port))
10211
10212#define PORT_HDCP_BKSVHI(port) _PORT_HDCP_AUTHENC(port, 0x14)
10213#define _TRANSA_HDCP_BKSVHI 0x66414
10214#define _TRANSB_HDCP_BKSVHI 0x66514
10215#define TRANS_HDCP_BKSVHI(trans) _MMIO_TRANS(trans, \
10216 _TRANSA_HDCP_BKSVHI, \
10217 _TRANSB_HDCP_BKSVHI)
10218#define HDCP_BKSVHI(dev_priv, trans, port) \
10219 (GRAPHICS_VER(dev_priv) >= 12 ? \
10220 TRANS_HDCP_BKSVHI(trans) : \
10221 PORT_HDCP_BKSVHI(port))
10222
10223#define PORT_HDCP_RPRIME(port) _PORT_HDCP_AUTHENC(port, 0x18)
10224#define _TRANSA_HDCP_RPRIME 0x66418
10225#define _TRANSB_HDCP_RPRIME 0x66518
10226#define TRANS_HDCP_RPRIME(trans) _MMIO_TRANS(trans, \
10227 _TRANSA_HDCP_RPRIME, \
10228 _TRANSB_HDCP_RPRIME)
10229#define HDCP_RPRIME(dev_priv, trans, port) \
10230 (GRAPHICS_VER(dev_priv) >= 12 ? \
10231 TRANS_HDCP_RPRIME(trans) : \
10232 PORT_HDCP_RPRIME(port))
10233
10234#define PORT_HDCP_STATUS(port) _PORT_HDCP_AUTHENC(port, 0x1C)
10235#define _TRANSA_HDCP_STATUS 0x6641C
10236#define _TRANSB_HDCP_STATUS 0x6651C
10237#define TRANS_HDCP_STATUS(trans) _MMIO_TRANS(trans, \
10238 _TRANSA_HDCP_STATUS, \
10239 _TRANSB_HDCP_STATUS)
10240#define HDCP_STATUS(dev_priv, trans, port) \
10241 (GRAPHICS_VER(dev_priv) >= 12 ? \
10242 TRANS_HDCP_STATUS(trans) : \
10243 PORT_HDCP_STATUS(port))
10244
10245#define HDCP_STATUS_STREAM_A_ENC BIT(31)
10246#define HDCP_STATUS_STREAM_B_ENC BIT(30)
10247#define HDCP_STATUS_STREAM_C_ENC BIT(29)
10248#define HDCP_STATUS_STREAM_D_ENC BIT(28)
10249#define HDCP_STATUS_AUTH BIT(21)
10250#define HDCP_STATUS_ENC BIT(20)
10251#define HDCP_STATUS_RI_MATCH BIT(19)
10252#define HDCP_STATUS_R0_READY BIT(18)
10253#define HDCP_STATUS_AN_READY BIT(17)
10254#define HDCP_STATUS_CIPHER BIT(16)
10255#define HDCP_STATUS_FRAME_CNT(x) (((x) >> 8) & 0xff)
10256
10257
10258#define _PORTA_HDCP2_BASE 0x66800
10259#define _PORTB_HDCP2_BASE 0x66500
10260#define _PORTC_HDCP2_BASE 0x66600
10261#define _PORTD_HDCP2_BASE 0x66700
10262#define _PORTE_HDCP2_BASE 0x66A00
10263#define _PORTF_HDCP2_BASE 0x66900
10264#define _PORT_HDCP2_BASE(port, x) _MMIO(_PICK((port), \
10265 _PORTA_HDCP2_BASE, \
10266 _PORTB_HDCP2_BASE, \
10267 _PORTC_HDCP2_BASE, \
10268 _PORTD_HDCP2_BASE, \
10269 _PORTE_HDCP2_BASE, \
10270 _PORTF_HDCP2_BASE) + (x))
10271
10272#define PORT_HDCP2_AUTH(port) _PORT_HDCP2_BASE(port, 0x98)
10273#define _TRANSA_HDCP2_AUTH 0x66498
10274#define _TRANSB_HDCP2_AUTH 0x66598
10275#define TRANS_HDCP2_AUTH(trans) _MMIO_TRANS(trans, _TRANSA_HDCP2_AUTH, \
10276 _TRANSB_HDCP2_AUTH)
10277#define AUTH_LINK_AUTHENTICATED BIT(31)
10278#define AUTH_LINK_TYPE BIT(30)
10279#define AUTH_FORCE_CLR_INPUTCTR BIT(19)
10280#define AUTH_CLR_KEYS BIT(18)
10281#define HDCP2_AUTH(dev_priv, trans, port) \
10282 (GRAPHICS_VER(dev_priv) >= 12 ? \
10283 TRANS_HDCP2_AUTH(trans) : \
10284 PORT_HDCP2_AUTH(port))
10285
10286#define PORT_HDCP2_CTL(port) _PORT_HDCP2_BASE(port, 0xB0)
10287#define _TRANSA_HDCP2_CTL 0x664B0
10288#define _TRANSB_HDCP2_CTL 0x665B0
10289#define TRANS_HDCP2_CTL(trans) _MMIO_TRANS(trans, _TRANSA_HDCP2_CTL, \
10290 _TRANSB_HDCP2_CTL)
10291#define CTL_LINK_ENCRYPTION_REQ BIT(31)
10292#define HDCP2_CTL(dev_priv, trans, port) \
10293 (GRAPHICS_VER(dev_priv) >= 12 ? \
10294 TRANS_HDCP2_CTL(trans) : \
10295 PORT_HDCP2_CTL(port))
10296
10297#define PORT_HDCP2_STATUS(port) _PORT_HDCP2_BASE(port, 0xB4)
10298#define _TRANSA_HDCP2_STATUS 0x664B4
10299#define _TRANSB_HDCP2_STATUS 0x665B4
10300#define TRANS_HDCP2_STATUS(trans) _MMIO_TRANS(trans, \
10301 _TRANSA_HDCP2_STATUS, \
10302 _TRANSB_HDCP2_STATUS)
10303#define LINK_TYPE_STATUS BIT(22)
10304#define LINK_AUTH_STATUS BIT(21)
10305#define LINK_ENCRYPTION_STATUS BIT(20)
10306#define HDCP2_STATUS(dev_priv, trans, port) \
10307 (GRAPHICS_VER(dev_priv) >= 12 ? \
10308 TRANS_HDCP2_STATUS(trans) : \
10309 PORT_HDCP2_STATUS(port))
10310
10311#define _PIPEA_HDCP2_STREAM_STATUS 0x668C0
10312#define _PIPEB_HDCP2_STREAM_STATUS 0x665C0
10313#define _PIPEC_HDCP2_STREAM_STATUS 0x666C0
10314#define _PIPED_HDCP2_STREAM_STATUS 0x667C0
10315#define PIPE_HDCP2_STREAM_STATUS(pipe) _MMIO(_PICK((pipe), \
10316 _PIPEA_HDCP2_STREAM_STATUS, \
10317 _PIPEB_HDCP2_STREAM_STATUS, \
10318 _PIPEC_HDCP2_STREAM_STATUS, \
10319 _PIPED_HDCP2_STREAM_STATUS))
10320
10321#define _TRANSA_HDCP2_STREAM_STATUS 0x664C0
10322#define _TRANSB_HDCP2_STREAM_STATUS 0x665C0
10323#define TRANS_HDCP2_STREAM_STATUS(trans) _MMIO_TRANS(trans, \
10324 _TRANSA_HDCP2_STREAM_STATUS, \
10325 _TRANSB_HDCP2_STREAM_STATUS)
10326#define STREAM_ENCRYPTION_STATUS BIT(31)
10327#define STREAM_TYPE_STATUS BIT(30)
10328#define HDCP2_STREAM_STATUS(dev_priv, trans, port) \
10329 (GRAPHICS_VER(dev_priv) >= 12 ? \
10330 TRANS_HDCP2_STREAM_STATUS(trans) : \
10331 PIPE_HDCP2_STREAM_STATUS(pipe))
10332
10333#define _PORTA_HDCP2_AUTH_STREAM 0x66F00
10334#define _PORTB_HDCP2_AUTH_STREAM 0x66F04
10335#define PORT_HDCP2_AUTH_STREAM(port) _MMIO_PORT(port, \
10336 _PORTA_HDCP2_AUTH_STREAM, \
10337 _PORTB_HDCP2_AUTH_STREAM)
10338#define _TRANSA_HDCP2_AUTH_STREAM 0x66F00
10339#define _TRANSB_HDCP2_AUTH_STREAM 0x66F04
10340#define TRANS_HDCP2_AUTH_STREAM(trans) _MMIO_TRANS(trans, \
10341 _TRANSA_HDCP2_AUTH_STREAM, \
10342 _TRANSB_HDCP2_AUTH_STREAM)
10343#define AUTH_STREAM_TYPE BIT(31)
10344#define HDCP2_AUTH_STREAM(dev_priv, trans, port) \
10345 (GRAPHICS_VER(dev_priv) >= 12 ? \
10346 TRANS_HDCP2_AUTH_STREAM(trans) : \
10347 PORT_HDCP2_AUTH_STREAM(port))
10348
10349
10350#define _TRANS_DDI_FUNC_CTL_A 0x60400
10351#define _TRANS_DDI_FUNC_CTL_B 0x61400
10352#define _TRANS_DDI_FUNC_CTL_C 0x62400
10353#define _TRANS_DDI_FUNC_CTL_D 0x63400
10354#define _TRANS_DDI_FUNC_CTL_EDP 0x6F400
10355#define _TRANS_DDI_FUNC_CTL_DSI0 0x6b400
10356#define _TRANS_DDI_FUNC_CTL_DSI1 0x6bc00
10357#define TRANS_DDI_FUNC_CTL(tran) _MMIO_TRANS2(tran, _TRANS_DDI_FUNC_CTL_A)
10358
10359#define TRANS_DDI_FUNC_ENABLE (1 << 31)
10360
10361#define TRANS_DDI_PORT_SHIFT 28
10362#define TGL_TRANS_DDI_PORT_SHIFT 27
10363#define TRANS_DDI_PORT_MASK (7 << TRANS_DDI_PORT_SHIFT)
10364#define TGL_TRANS_DDI_PORT_MASK (0xf << TGL_TRANS_DDI_PORT_SHIFT)
10365#define TRANS_DDI_SELECT_PORT(x) ((x) << TRANS_DDI_PORT_SHIFT)
10366#define TGL_TRANS_DDI_SELECT_PORT(x) (((x) + 1) << TGL_TRANS_DDI_PORT_SHIFT)
10367#define TRANS_DDI_MODE_SELECT_MASK (7 << 24)
10368#define TRANS_DDI_MODE_SELECT_HDMI (0 << 24)
10369#define TRANS_DDI_MODE_SELECT_DVI (1 << 24)
10370#define TRANS_DDI_MODE_SELECT_DP_SST (2 << 24)
10371#define TRANS_DDI_MODE_SELECT_DP_MST (3 << 24)
10372#define TRANS_DDI_MODE_SELECT_FDI_OR_128B132B (4 << 24)
10373#define TRANS_DDI_BPC_MASK (7 << 20)
10374#define TRANS_DDI_BPC_8 (0 << 20)
10375#define TRANS_DDI_BPC_10 (1 << 20)
10376#define TRANS_DDI_BPC_6 (2 << 20)
10377#define TRANS_DDI_BPC_12 (3 << 20)
10378#define TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK REG_GENMASK(19, 18)
10379#define TRANS_DDI_PORT_SYNC_MASTER_SELECT(x) REG_FIELD_PREP(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, (x))
10380#define TRANS_DDI_PVSYNC (1 << 17)
10381#define TRANS_DDI_PHSYNC (1 << 16)
10382#define TRANS_DDI_PORT_SYNC_ENABLE REG_BIT(15)
10383#define TRANS_DDI_EDP_INPUT_MASK (7 << 12)
10384#define TRANS_DDI_EDP_INPUT_A_ON (0 << 12)
10385#define TRANS_DDI_EDP_INPUT_A_ONOFF (4 << 12)
10386#define TRANS_DDI_EDP_INPUT_B_ONOFF (5 << 12)
10387#define TRANS_DDI_EDP_INPUT_C_ONOFF (6 << 12)
10388#define TRANS_DDI_EDP_INPUT_D_ONOFF (7 << 12)
10389#define TRANS_DDI_MST_TRANSPORT_SELECT_MASK REG_GENMASK(11, 10)
10390#define TRANS_DDI_MST_TRANSPORT_SELECT(trans) \
10391 REG_FIELD_PREP(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, trans)
10392#define TRANS_DDI_HDCP_SIGNALLING (1 << 9)
10393#define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1 << 8)
10394#define TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE (1 << 7)
10395#define TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ (1 << 6)
10396#define TRANS_DDI_HDCP_SELECT REG_BIT(5)
10397#define TRANS_DDI_BFI_ENABLE (1 << 4)
10398#define TRANS_DDI_HIGH_TMDS_CHAR_RATE (1 << 4)
10399#define TRANS_DDI_HDMI_SCRAMBLING (1 << 0)
10400#define TRANS_DDI_HDMI_SCRAMBLING_MASK (TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE \
10401 | TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ \
10402 | TRANS_DDI_HDMI_SCRAMBLING)
10403
10404#define _TRANS_DDI_FUNC_CTL2_A 0x60404
10405#define _TRANS_DDI_FUNC_CTL2_B 0x61404
10406#define _TRANS_DDI_FUNC_CTL2_C 0x62404
10407#define _TRANS_DDI_FUNC_CTL2_EDP 0x6f404
10408#define _TRANS_DDI_FUNC_CTL2_DSI0 0x6b404
10409#define _TRANS_DDI_FUNC_CTL2_DSI1 0x6bc04
10410#define TRANS_DDI_FUNC_CTL2(tran) _MMIO_TRANS2(tran, _TRANS_DDI_FUNC_CTL2_A)
10411#define PORT_SYNC_MODE_ENABLE REG_BIT(4)
10412#define PORT_SYNC_MODE_MASTER_SELECT_MASK REG_GENMASK(2, 0)
10413#define PORT_SYNC_MODE_MASTER_SELECT(x) REG_FIELD_PREP(PORT_SYNC_MODE_MASTER_SELECT_MASK, (x))
10414
10415#define TRANS_CMTG_CHICKEN _MMIO(0x6fa90)
10416#define DISABLE_DPT_CLK_GATING REG_BIT(1)
10417
10418
10419#define _DP_TP_CTL_A 0x64040
10420#define _DP_TP_CTL_B 0x64140
10421#define _TGL_DP_TP_CTL_A 0x60540
10422#define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B)
10423#define TGL_DP_TP_CTL(tran) _MMIO_TRANS2((tran), _TGL_DP_TP_CTL_A)
10424#define DP_TP_CTL_ENABLE (1 << 31)
10425#define DP_TP_CTL_FEC_ENABLE (1 << 30)
10426#define DP_TP_CTL_MODE_SST (0 << 27)
10427#define DP_TP_CTL_MODE_MST (1 << 27)
10428#define DP_TP_CTL_FORCE_ACT (1 << 25)
10429#define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1 << 18)
10430#define DP_TP_CTL_FDI_AUTOTRAIN (1 << 15)
10431#define DP_TP_CTL_LINK_TRAIN_MASK (7 << 8)
10432#define DP_TP_CTL_LINK_TRAIN_PAT1 (0 << 8)
10433#define DP_TP_CTL_LINK_TRAIN_PAT2 (1 << 8)
10434#define DP_TP_CTL_LINK_TRAIN_PAT3 (4 << 8)
10435#define DP_TP_CTL_LINK_TRAIN_PAT4 (5 << 8)
10436#define DP_TP_CTL_LINK_TRAIN_IDLE (2 << 8)
10437#define DP_TP_CTL_LINK_TRAIN_NORMAL (3 << 8)
10438#define DP_TP_CTL_SCRAMBLE_DISABLE (1 << 7)
10439
10440
10441#define _DP_TP_STATUS_A 0x64044
10442#define _DP_TP_STATUS_B 0x64144
10443#define _TGL_DP_TP_STATUS_A 0x60544
10444#define DP_TP_STATUS(port) _MMIO_PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B)
10445#define TGL_DP_TP_STATUS(tran) _MMIO_TRANS2((tran), _TGL_DP_TP_STATUS_A)
10446#define DP_TP_STATUS_FEC_ENABLE_LIVE (1 << 28)
10447#define DP_TP_STATUS_IDLE_DONE (1 << 25)
10448#define DP_TP_STATUS_ACT_SENT (1 << 24)
10449#define DP_TP_STATUS_MODE_STATUS_MST (1 << 23)
10450#define DP_TP_STATUS_AUTOTRAIN_DONE (1 << 12)
10451#define DP_TP_STATUS_PAYLOAD_MAPPING_VC2 (3 << 8)
10452#define DP_TP_STATUS_PAYLOAD_MAPPING_VC1 (3 << 4)
10453#define DP_TP_STATUS_PAYLOAD_MAPPING_VC0 (3 << 0)
10454
10455
10456#define _DDI_BUF_CTL_A 0x64000
10457#define _DDI_BUF_CTL_B 0x64100
10458#define DDI_BUF_CTL(port) _MMIO_PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B)
10459#define DDI_BUF_CTL_ENABLE (1 << 31)
10460#define DDI_BUF_TRANS_SELECT(n) ((n) << 24)
10461#define DDI_BUF_EMP_MASK (0xf << 24)
10462#define DDI_BUF_PHY_LINK_RATE(r) ((r) << 20)
10463#define DDI_BUF_PORT_REVERSAL (1 << 16)
10464#define DDI_BUF_IS_IDLE (1 << 7)
10465#define DDI_BUF_CTL_TC_PHY_OWNERSHIP REG_BIT(6)
10466#define DDI_A_4_LANES (1 << 4)
10467#define DDI_PORT_WIDTH(width) (((width) - 1) << 1)
10468#define DDI_PORT_WIDTH_MASK (7 << 1)
10469#define DDI_PORT_WIDTH_SHIFT 1
10470#define DDI_INIT_DISPLAY_DETECTED (1 << 0)
10471
10472
10473#define _DDI_BUF_TRANS_A 0x64E00
10474#define _DDI_BUF_TRANS_B 0x64E60
10475#define DDI_BUF_TRANS_LO(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8)
10476#define DDI_BUF_BALANCE_LEG_ENABLE (1 << 31)
10477#define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4)
10478
10479
10480#define _DDI_DP_COMP_CTL_A 0x605F0
10481#define _DDI_DP_COMP_CTL_B 0x615F0
10482#define DDI_DP_COMP_CTL(pipe) _MMIO_PIPE(pipe, _DDI_DP_COMP_CTL_A, _DDI_DP_COMP_CTL_B)
10483#define DDI_DP_COMP_CTL_ENABLE (1 << 31)
10484#define DDI_DP_COMP_CTL_D10_2 (0 << 28)
10485#define DDI_DP_COMP_CTL_SCRAMBLED_0 (1 << 28)
10486#define DDI_DP_COMP_CTL_PRBS7 (2 << 28)
10487#define DDI_DP_COMP_CTL_CUSTOM80 (3 << 28)
10488#define DDI_DP_COMP_CTL_HBR2 (4 << 28)
10489#define DDI_DP_COMP_CTL_SCRAMBLED_1 (5 << 28)
10490#define DDI_DP_COMP_CTL_HBR2_RESET (0xFC << 0)
10491
10492
10493#define _DDI_DP_COMP_PAT_A 0x605F4
10494#define _DDI_DP_COMP_PAT_B 0x615F4
10495#define DDI_DP_COMP_PAT(pipe, i) _MMIO(_PIPE(pipe, _DDI_DP_COMP_PAT_A, _DDI_DP_COMP_PAT_B) + (i) * 4)
10496
10497
10498
10499
10500#define SBI_ADDR _MMIO(0xC6000)
10501#define SBI_DATA _MMIO(0xC6004)
10502#define SBI_CTL_STAT _MMIO(0xC6008)
10503#define SBI_CTL_DEST_ICLK (0x0 << 16)
10504#define SBI_CTL_DEST_MPHY (0x1 << 16)
10505#define SBI_CTL_OP_IORD (0x2 << 8)
10506#define SBI_CTL_OP_IOWR (0x3 << 8)
10507#define SBI_CTL_OP_CRRD (0x6 << 8)
10508#define SBI_CTL_OP_CRWR (0x7 << 8)
10509#define SBI_RESPONSE_FAIL (0x1 << 1)
10510#define SBI_RESPONSE_SUCCESS (0x0 << 1)
10511#define SBI_BUSY (0x1 << 0)
10512#define SBI_READY (0x0 << 0)
10513
10514
10515#define SBI_SSCDIVINTPHASE 0x0200
10516#define SBI_SSCDIVINTPHASE6 0x0600
10517#define SBI_SSCDIVINTPHASE_DIVSEL_SHIFT 1
10518#define SBI_SSCDIVINTPHASE_DIVSEL_MASK (0x7f << 1)
10519#define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x) << 1)
10520#define SBI_SSCDIVINTPHASE_INCVAL_SHIFT 8
10521#define SBI_SSCDIVINTPHASE_INCVAL_MASK (0x7f << 8)
10522#define SBI_SSCDIVINTPHASE_INCVAL(x) ((x) << 8)
10523#define SBI_SSCDIVINTPHASE_DIR(x) ((x) << 15)
10524#define SBI_SSCDIVINTPHASE_PROPAGATE (1 << 0)
10525#define SBI_SSCDITHPHASE 0x0204
10526#define SBI_SSCCTL 0x020c
10527#define SBI_SSCCTL6 0x060C
10528#define SBI_SSCCTL_PATHALT (1 << 3)
10529#define SBI_SSCCTL_DISABLE (1 << 0)
10530#define SBI_SSCAUXDIV6 0x0610
10531#define SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT 4
10532#define SBI_SSCAUXDIV_FINALDIV2SEL_MASK (1 << 4)
10533#define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x) << 4)
10534#define SBI_DBUFF0 0x2a00
10535#define SBI_GEN0 0x1f00
10536#define SBI_GEN0_CFG_BUFFENABLE_DISABLE (1 << 0)
10537
10538
10539#define PIXCLK_GATE _MMIO(0xC6020)
10540#define PIXCLK_GATE_UNGATE (1 << 0)
10541#define PIXCLK_GATE_GATE (0 << 0)
10542
10543
10544#define SPLL_CTL _MMIO(0x46020)
10545#define SPLL_PLL_ENABLE (1 << 31)
10546#define SPLL_REF_BCLK (0 << 28)
10547#define SPLL_REF_MUXED_SSC (1 << 28)
10548#define SPLL_REF_NON_SSC_HSW (2 << 28)
10549#define SPLL_REF_PCH_SSC_BDW (2 << 28)
10550#define SPLL_REF_LCPLL (3 << 28)
10551#define SPLL_REF_MASK (3 << 28)
10552#define SPLL_FREQ_810MHz (0 << 26)
10553#define SPLL_FREQ_1350MHz (1 << 26)
10554#define SPLL_FREQ_2700MHz (2 << 26)
10555#define SPLL_FREQ_MASK (3 << 26)
10556
10557
10558#define _WRPLL_CTL1 0x46040
10559#define _WRPLL_CTL2 0x46060
10560#define WRPLL_CTL(pll) _MMIO_PIPE(pll, _WRPLL_CTL1, _WRPLL_CTL2)
10561#define WRPLL_PLL_ENABLE (1 << 31)
10562#define WRPLL_REF_BCLK (0 << 28)
10563#define WRPLL_REF_PCH_SSC (1 << 28)
10564#define WRPLL_REF_MUXED_SSC_BDW (2 << 28)
10565#define WRPLL_REF_SPECIAL_HSW (2 << 28)
10566#define WRPLL_REF_LCPLL (3 << 28)
10567#define WRPLL_REF_MASK (3 << 28)
10568
10569#define WRPLL_DIVIDER_REFERENCE(x) ((x) << 0)
10570#define WRPLL_DIVIDER_REF_MASK (0xff)
10571#define WRPLL_DIVIDER_POST(x) ((x) << 8)
10572#define WRPLL_DIVIDER_POST_MASK (0x3f << 8)
10573#define WRPLL_DIVIDER_POST_SHIFT 8
10574#define WRPLL_DIVIDER_FEEDBACK(x) ((x) << 16)
10575#define WRPLL_DIVIDER_FB_SHIFT 16
10576#define WRPLL_DIVIDER_FB_MASK (0xff << 16)
10577
10578
10579#define _PORT_CLK_SEL_A 0x46100
10580#define _PORT_CLK_SEL_B 0x46104
10581#define PORT_CLK_SEL(port) _MMIO_PORT(port, _PORT_CLK_SEL_A, _PORT_CLK_SEL_B)
10582#define PORT_CLK_SEL_LCPLL_2700 (0 << 29)
10583#define PORT_CLK_SEL_LCPLL_1350 (1 << 29)
10584#define PORT_CLK_SEL_LCPLL_810 (2 << 29)
10585#define PORT_CLK_SEL_SPLL (3 << 29)
10586#define PORT_CLK_SEL_WRPLL(pll) (((pll) + 4) << 29)
10587#define PORT_CLK_SEL_WRPLL1 (4 << 29)
10588#define PORT_CLK_SEL_WRPLL2 (5 << 29)
10589#define PORT_CLK_SEL_NONE (7 << 29)
10590#define PORT_CLK_SEL_MASK (7 << 29)
10591
10592
10593#define DDI_CLK_SEL(port) PORT_CLK_SEL(port)
10594#define DDI_CLK_SEL_NONE (0x0 << 28)
10595#define DDI_CLK_SEL_MG (0x8 << 28)
10596#define DDI_CLK_SEL_TBT_162 (0xC << 28)
10597#define DDI_CLK_SEL_TBT_270 (0xD << 28)
10598#define DDI_CLK_SEL_TBT_540 (0xE << 28)
10599#define DDI_CLK_SEL_TBT_810 (0xF << 28)
10600#define DDI_CLK_SEL_MASK (0xF << 28)
10601
10602
10603#define _TRANS_CLK_SEL_A 0x46140
10604#define _TRANS_CLK_SEL_B 0x46144
10605#define TRANS_CLK_SEL(tran) _MMIO_TRANS(tran, _TRANS_CLK_SEL_A, _TRANS_CLK_SEL_B)
10606
10607#define TRANS_CLK_SEL_DISABLED (0x0 << 29)
10608#define TRANS_CLK_SEL_PORT(x) (((x) + 1) << 29)
10609#define TGL_TRANS_CLK_SEL_DISABLED (0x0 << 28)
10610#define TGL_TRANS_CLK_SEL_PORT(x) (((x) + 1) << 28)
10611
10612
10613#define CDCLK_FREQ _MMIO(0x46200)
10614
10615#define _TRANSA_MSA_MISC 0x60410
10616#define _TRANSB_MSA_MISC 0x61410
10617#define _TRANSC_MSA_MISC 0x62410
10618#define _TRANS_EDP_MSA_MISC 0x6f410
10619#define TRANS_MSA_MISC(tran) _MMIO_TRANS2(tran, _TRANSA_MSA_MISC)
10620
10621
10622#define _TRANS_A_SET_CONTEXT_LATENCY 0x6007C
10623#define _TRANS_B_SET_CONTEXT_LATENCY 0x6107C
10624#define _TRANS_C_SET_CONTEXT_LATENCY 0x6207C
10625#define _TRANS_D_SET_CONTEXT_LATENCY 0x6307C
10626#define TRANS_SET_CONTEXT_LATENCY(tran) _MMIO_TRANS2(tran, _TRANS_A_SET_CONTEXT_LATENCY)
10627#define TRANS_SET_CONTEXT_LATENCY_MASK REG_GENMASK(15, 0)
10628#define TRANS_SET_CONTEXT_LATENCY_VALUE(x) REG_FIELD_PREP(TRANS_SET_CONTEXT_LATENCY_MASK, (x))
10629
10630
10631#define LCPLL_CTL _MMIO(0x130040)
10632#define LCPLL_PLL_DISABLE (1 << 31)
10633#define LCPLL_PLL_LOCK (1 << 30)
10634#define LCPLL_REF_NON_SSC (0 << 28)
10635#define LCPLL_REF_BCLK (2 << 28)
10636#define LCPLL_REF_PCH_SSC (3 << 28)
10637#define LCPLL_REF_MASK (3 << 28)
10638#define LCPLL_CLK_FREQ_MASK (3 << 26)
10639#define LCPLL_CLK_FREQ_450 (0 << 26)
10640#define LCPLL_CLK_FREQ_54O_BDW (1 << 26)
10641#define LCPLL_CLK_FREQ_337_5_BDW (2 << 26)
10642#define LCPLL_CLK_FREQ_675_BDW (3 << 26)
10643#define LCPLL_CD_CLOCK_DISABLE (1 << 25)
10644#define LCPLL_ROOT_CD_CLOCK_DISABLE (1 << 24)
10645#define LCPLL_CD2X_CLOCK_DISABLE (1 << 23)
10646#define LCPLL_POWER_DOWN_ALLOW (1 << 22)
10647#define LCPLL_CD_SOURCE_FCLK (1 << 21)
10648#define LCPLL_CD_SOURCE_FCLK_DONE (1 << 19)
10649
10650
10651
10652
10653
10654
10655#define CDCLK_CTL _MMIO(0x46000)
10656#define CDCLK_FREQ_SEL_MASK (3 << 26)
10657#define CDCLK_FREQ_450_432 (0 << 26)
10658#define CDCLK_FREQ_540 (1 << 26)
10659#define CDCLK_FREQ_337_308 (2 << 26)
10660#define CDCLK_FREQ_675_617 (3 << 26)
10661#define BXT_CDCLK_CD2X_DIV_SEL_MASK (3 << 22)
10662#define BXT_CDCLK_CD2X_DIV_SEL_1 (0 << 22)
10663#define BXT_CDCLK_CD2X_DIV_SEL_1_5 (1 << 22)
10664#define BXT_CDCLK_CD2X_DIV_SEL_2 (2 << 22)
10665#define BXT_CDCLK_CD2X_DIV_SEL_4 (3 << 22)
10666#define BXT_CDCLK_CD2X_PIPE(pipe) ((pipe) << 20)
10667#define CDCLK_DIVMUX_CD_OVERRIDE (1 << 19)
10668#define BXT_CDCLK_CD2X_PIPE_NONE BXT_CDCLK_CD2X_PIPE(3)
10669#define ICL_CDCLK_CD2X_PIPE(pipe) (_PICK(pipe, 0, 2, 6) << 19)
10670#define ICL_CDCLK_CD2X_PIPE_NONE (7 << 19)
10671#define TGL_CDCLK_CD2X_PIPE(pipe) BXT_CDCLK_CD2X_PIPE(pipe)
10672#define TGL_CDCLK_CD2X_PIPE_NONE ICL_CDCLK_CD2X_PIPE_NONE
10673#define BXT_CDCLK_SSA_PRECHARGE_ENABLE (1 << 16)
10674#define CDCLK_FREQ_DECIMAL_MASK (0x7ff)
10675
10676
10677#define CDCLK_SQUASH_CTL _MMIO(0x46008)
10678#define CDCLK_SQUASH_ENABLE REG_BIT(31)
10679#define CDCLK_SQUASH_WINDOW_SIZE_MASK REG_GENMASK(27, 24)
10680#define CDCLK_SQUASH_WINDOW_SIZE(x) REG_FIELD_PREP(CDCLK_SQUASH_WINDOW_SIZE_MASK, (x))
10681#define CDCLK_SQUASH_WAVEFORM_MASK REG_GENMASK(15, 0)
10682#define CDCLK_SQUASH_WAVEFORM(x) REG_FIELD_PREP(CDCLK_SQUASH_WAVEFORM_MASK, (x))
10683
10684
10685#define LCPLL1_CTL _MMIO(0x46010)
10686#define LCPLL2_CTL _MMIO(0x46014)
10687#define LCPLL_PLL_ENABLE (1 << 31)
10688
10689
10690#define DPLL_CTRL1 _MMIO(0x6C058)
10691#define DPLL_CTRL1_HDMI_MODE(id) (1 << ((id) * 6 + 5))
10692#define DPLL_CTRL1_SSC(id) (1 << ((id) * 6 + 4))
10693#define DPLL_CTRL1_LINK_RATE_MASK(id) (7 << ((id) * 6 + 1))
10694#define DPLL_CTRL1_LINK_RATE_SHIFT(id) ((id) * 6 + 1)
10695#define DPLL_CTRL1_LINK_RATE(linkrate, id) ((linkrate) << ((id) * 6 + 1))
10696#define DPLL_CTRL1_OVERRIDE(id) (1 << ((id) * 6))
10697#define DPLL_CTRL1_LINK_RATE_2700 0
10698#define DPLL_CTRL1_LINK_RATE_1350 1
10699#define DPLL_CTRL1_LINK_RATE_810 2
10700#define DPLL_CTRL1_LINK_RATE_1620 3
10701#define DPLL_CTRL1_LINK_RATE_1080 4
10702#define DPLL_CTRL1_LINK_RATE_2160 5
10703
10704
10705#define DPLL_CTRL2 _MMIO(0x6C05C)
10706#define DPLL_CTRL2_DDI_CLK_OFF(port) (1 << ((port) + 15))
10707#define DPLL_CTRL2_DDI_CLK_SEL_MASK(port) (3 << ((port) * 3 + 1))
10708#define DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port) ((port) * 3 + 1)
10709#define DPLL_CTRL2_DDI_CLK_SEL(clk, port) ((clk) << ((port) * 3 + 1))
10710#define DPLL_CTRL2_DDI_SEL_OVERRIDE(port) (1 << ((port) * 3))
10711
10712
10713#define DPLL_STATUS _MMIO(0x6C060)
10714#define DPLL_LOCK(id) (1 << ((id) * 8))
10715
10716
10717#define _DPLL1_CFGCR1 0x6C040
10718#define _DPLL2_CFGCR1 0x6C048
10719#define _DPLL3_CFGCR1 0x6C050
10720#define DPLL_CFGCR1_FREQ_ENABLE (1 << 31)
10721#define DPLL_CFGCR1_DCO_FRACTION_MASK (0x7fff << 9)
10722#define DPLL_CFGCR1_DCO_FRACTION(x) ((x) << 9)
10723#define DPLL_CFGCR1_DCO_INTEGER_MASK (0x1ff)
10724
10725#define _DPLL1_CFGCR2 0x6C044
10726#define _DPLL2_CFGCR2 0x6C04C
10727#define _DPLL3_CFGCR2 0x6C054
10728#define DPLL_CFGCR2_QDIV_RATIO_MASK (0xff << 8)
10729#define DPLL_CFGCR2_QDIV_RATIO(x) ((x) << 8)
10730#define DPLL_CFGCR2_QDIV_MODE(x) ((x) << 7)
10731#define DPLL_CFGCR2_KDIV_MASK (3 << 5)
10732#define DPLL_CFGCR2_KDIV(x) ((x) << 5)
10733#define DPLL_CFGCR2_KDIV_5 (0 << 5)
10734#define DPLL_CFGCR2_KDIV_2 (1 << 5)
10735#define DPLL_CFGCR2_KDIV_3 (2 << 5)
10736#define DPLL_CFGCR2_KDIV_1 (3 << 5)
10737#define DPLL_CFGCR2_PDIV_MASK (7 << 2)
10738#define DPLL_CFGCR2_PDIV(x) ((x) << 2)
10739#define DPLL_CFGCR2_PDIV_1 (0 << 2)
10740#define DPLL_CFGCR2_PDIV_2 (1 << 2)
10741#define DPLL_CFGCR2_PDIV_3 (2 << 2)
10742#define DPLL_CFGCR2_PDIV_7 (4 << 2)
10743#define DPLL_CFGCR2_PDIV_7_INVALID (5 << 2)
10744#define DPLL_CFGCR2_CENTRAL_FREQ_MASK (3)
10745
10746#define DPLL_CFGCR1(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1, _DPLL2_CFGCR1)
10747#define DPLL_CFGCR2(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR2, _DPLL2_CFGCR2)
10748
10749
10750#define ICL_DPCLKA_CFGCR0 _MMIO(0x164280)
10751#define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) (1 << _PICK(phy, 10, 11, 24, 4, 5))
10752#define RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT((phy) + 10)
10753#define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) < TC_PORT_4 ? \
10754 (tc_port) + 12 : \
10755 (tc_port) - TC_PORT_4 + 21))
10756#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) ((phy) * 2)
10757#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (3 << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
10758#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) ((pll) << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
10759#define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) _PICK(phy, 0, 2, 4, 27)
10760#define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) \
10761 (3 << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
10762#define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) \
10763 ((pll) << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
10764
10765
10766
10767
10768
10769
10770
10771#define _DG1_DPCLKA_CFGCR0 0x164280
10772#define _DG1_DPCLKA1_CFGCR0 0x16C280
10773#define _DG1_DPCLKA_PHY_IDX(phy) ((phy) % 2)
10774#define _DG1_DPCLKA_PLL_IDX(pll) ((pll) % 2)
10775#define DG1_DPCLKA_CFGCR0(phy) _MMIO_PHY((phy) / 2, \
10776 _DG1_DPCLKA_CFGCR0, \
10777 _DG1_DPCLKA1_CFGCR0)
10778#define DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT(_DG1_DPCLKA_PHY_IDX(phy) + 10)
10779#define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) (_DG1_DPCLKA_PHY_IDX(phy) * 2)
10780#define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) (_DG1_DPCLKA_PLL_IDX(pll) << DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
10781#define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (0x3 << DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
10782
10783
10784#define _ADLS_DPCLKA_CFGCR0 0x164280
10785#define _ADLS_DPCLKA_CFGCR1 0x1642BC
10786#define ADLS_DPCLKA_CFGCR(phy) _MMIO_PHY((phy) / 3, \
10787 _ADLS_DPCLKA_CFGCR0, \
10788 _ADLS_DPCLKA_CFGCR1)
10789#define ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy) (((phy) % 3) * 2)
10790
10791#define ADLS_DPCLKA_DDII_SEL_MASK REG_GENMASK(5, 4)
10792#define ADLS_DPCLKA_DDIB_SEL_MASK REG_GENMASK(3, 2)
10793#define ADLS_DPCLKA_DDIA_SEL_MASK REG_GENMASK(1, 0)
10794
10795#define ADLS_DPCLKA_DDIK_SEL_MASK REG_GENMASK(3, 2)
10796#define ADLS_DPCLKA_DDIJ_SEL_MASK REG_GENMASK(1, 0)
10797#define ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy) _PICK((phy), \
10798 ADLS_DPCLKA_DDIA_SEL_MASK, \
10799 ADLS_DPCLKA_DDIB_SEL_MASK, \
10800 ADLS_DPCLKA_DDII_SEL_MASK, \
10801 ADLS_DPCLKA_DDIJ_SEL_MASK, \
10802 ADLS_DPCLKA_DDIK_SEL_MASK)
10803
10804
10805#define DPLL0_ENABLE 0x46010
10806#define DPLL1_ENABLE 0x46014
10807#define _ADLS_DPLL2_ENABLE 0x46018
10808#define _ADLS_DPLL3_ENABLE 0x46030
10809#define PLL_ENABLE (1 << 31)
10810#define PLL_LOCK (1 << 30)
10811#define PLL_POWER_ENABLE (1 << 27)
10812#define PLL_POWER_STATE (1 << 26)
10813#define ICL_DPLL_ENABLE(pll) _MMIO_PLL3(pll, DPLL0_ENABLE, DPLL1_ENABLE, \
10814 _ADLS_DPLL2_ENABLE, _ADLS_DPLL3_ENABLE)
10815
10816#define _DG2_PLL3_ENABLE 0x4601C
10817
10818#define DG2_PLL_ENABLE(pll) _MMIO_PLL3(pll, DPLL0_ENABLE, DPLL1_ENABLE, \
10819 _ADLS_DPLL2_ENABLE, _DG2_PLL3_ENABLE)
10820
10821#define TBT_PLL_ENABLE _MMIO(0x46020)
10822
10823#define _MG_PLL1_ENABLE 0x46030
10824#define _MG_PLL2_ENABLE 0x46034
10825#define _MG_PLL3_ENABLE 0x46038
10826#define _MG_PLL4_ENABLE 0x4603C
10827
10828#define MG_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port), _MG_PLL1_ENABLE, \
10829 _MG_PLL2_ENABLE)
10830
10831
10832#define DG1_DPLL_ENABLE(pll) _MMIO_PLL3(pll, DPLL0_ENABLE, DPLL1_ENABLE, \
10833 _MG_PLL1_ENABLE, _MG_PLL2_ENABLE)
10834
10835
10836#define PORTTC1_PLL_ENABLE 0x46038
10837#define PORTTC2_PLL_ENABLE 0x46040
10838
10839#define ADLP_PORTTC_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port), \
10840 PORTTC1_PLL_ENABLE, \
10841 PORTTC2_PLL_ENABLE)
10842
10843#define _MG_REFCLKIN_CTL_PORT1 0x16892C
10844#define _MG_REFCLKIN_CTL_PORT2 0x16992C
10845#define _MG_REFCLKIN_CTL_PORT3 0x16A92C
10846#define _MG_REFCLKIN_CTL_PORT4 0x16B92C
10847#define MG_REFCLKIN_CTL_OD_2_MUX(x) ((x) << 8)
10848#define MG_REFCLKIN_CTL_OD_2_MUX_MASK (0x7 << 8)
10849#define MG_REFCLKIN_CTL(tc_port) _MMIO_PORT((tc_port), \
10850 _MG_REFCLKIN_CTL_PORT1, \
10851 _MG_REFCLKIN_CTL_PORT2)
10852
10853#define _MG_CLKTOP2_CORECLKCTL1_PORT1 0x1688D8
10854#define _MG_CLKTOP2_CORECLKCTL1_PORT2 0x1698D8
10855#define _MG_CLKTOP2_CORECLKCTL1_PORT3 0x16A8D8
10856#define _MG_CLKTOP2_CORECLKCTL1_PORT4 0x16B8D8
10857#define MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO(x) ((x) << 16)
10858#define MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO_MASK (0xff << 16)
10859#define MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO(x) ((x) << 8)
10860#define MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK (0xff << 8)
10861#define MG_CLKTOP2_CORECLKCTL1(tc_port) _MMIO_PORT((tc_port), \
10862 _MG_CLKTOP2_CORECLKCTL1_PORT1, \
10863 _MG_CLKTOP2_CORECLKCTL1_PORT2)
10864
10865#define _MG_CLKTOP2_HSCLKCTL_PORT1 0x1688D4
10866#define _MG_CLKTOP2_HSCLKCTL_PORT2 0x1698D4
10867#define _MG_CLKTOP2_HSCLKCTL_PORT3 0x16A8D4
10868#define _MG_CLKTOP2_HSCLKCTL_PORT4 0x16B8D4
10869#define MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL(x) ((x) << 16)
10870#define MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK (0x1 << 16)
10871#define MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL(x) ((x) << 14)
10872#define MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK (0x3 << 14)
10873#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK (0x3 << 12)
10874#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2 (0 << 12)
10875#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3 (1 << 12)
10876#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5 (2 << 12)
10877#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7 (3 << 12)
10878#define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO(x) ((x) << 8)
10879#define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT 8
10880#define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK (0xf << 8)
10881#define MG_CLKTOP2_HSCLKCTL(tc_port) _MMIO_PORT((tc_port), \
10882 _MG_CLKTOP2_HSCLKCTL_PORT1, \
10883 _MG_CLKTOP2_HSCLKCTL_PORT2)
10884
10885#define _MG_PLL_DIV0_PORT1 0x168A00
10886#define _MG_PLL_DIV0_PORT2 0x169A00
10887#define _MG_PLL_DIV0_PORT3 0x16AA00
10888#define _MG_PLL_DIV0_PORT4 0x16BA00
10889#define MG_PLL_DIV0_FRACNEN_H (1 << 30)
10890#define MG_PLL_DIV0_FBDIV_FRAC_MASK (0x3fffff << 8)
10891#define MG_PLL_DIV0_FBDIV_FRAC_SHIFT 8
10892#define MG_PLL_DIV0_FBDIV_FRAC(x) ((x) << 8)
10893#define MG_PLL_DIV0_FBDIV_INT_MASK (0xff << 0)
10894#define MG_PLL_DIV0_FBDIV_INT(x) ((x) << 0)
10895#define MG_PLL_DIV0(tc_port) _MMIO_PORT((tc_port), _MG_PLL_DIV0_PORT1, \
10896 _MG_PLL_DIV0_PORT2)
10897
10898#define _MG_PLL_DIV1_PORT1 0x168A04
10899#define _MG_PLL_DIV1_PORT2 0x169A04
10900#define _MG_PLL_DIV1_PORT3 0x16AA04
10901#define _MG_PLL_DIV1_PORT4 0x16BA04
10902#define MG_PLL_DIV1_IREF_NDIVRATIO(x) ((x) << 16)
10903#define MG_PLL_DIV1_DITHER_DIV_1 (0 << 12)
10904#define MG_PLL_DIV1_DITHER_DIV_2 (1 << 12)
10905#define MG_PLL_DIV1_DITHER_DIV_4 (2 << 12)
10906#define MG_PLL_DIV1_DITHER_DIV_8 (3 << 12)
10907#define MG_PLL_DIV1_NDIVRATIO(x) ((x) << 4)
10908#define MG_PLL_DIV1_FBPREDIV_MASK (0xf << 0)
10909#define MG_PLL_DIV1_FBPREDIV(x) ((x) << 0)
10910#define MG_PLL_DIV1(tc_port) _MMIO_PORT((tc_port), _MG_PLL_DIV1_PORT1, \
10911 _MG_PLL_DIV1_PORT2)
10912
10913#define _MG_PLL_LF_PORT1 0x168A08
10914#define _MG_PLL_LF_PORT2 0x169A08
10915#define _MG_PLL_LF_PORT3 0x16AA08
10916#define _MG_PLL_LF_PORT4 0x16BA08
10917#define MG_PLL_LF_TDCTARGETCNT(x) ((x) << 24)
10918#define MG_PLL_LF_AFCCNTSEL_256 (0 << 20)
10919#define MG_PLL_LF_AFCCNTSEL_512 (1 << 20)
10920#define MG_PLL_LF_GAINCTRL(x) ((x) << 16)
10921#define MG_PLL_LF_INT_COEFF(x) ((x) << 8)
10922#define MG_PLL_LF_PROP_COEFF(x) ((x) << 0)
10923#define MG_PLL_LF(tc_port) _MMIO_PORT((tc_port), _MG_PLL_LF_PORT1, \
10924 _MG_PLL_LF_PORT2)
10925
10926#define _MG_PLL_FRAC_LOCK_PORT1 0x168A0C
10927#define _MG_PLL_FRAC_LOCK_PORT2 0x169A0C
10928#define _MG_PLL_FRAC_LOCK_PORT3 0x16AA0C
10929#define _MG_PLL_FRAC_LOCK_PORT4 0x16BA0C
10930#define MG_PLL_FRAC_LOCK_TRUELOCK_CRIT_32 (1 << 18)
10931#define MG_PLL_FRAC_LOCK_EARLYLOCK_CRIT_32 (1 << 16)
10932#define MG_PLL_FRAC_LOCK_LOCKTHRESH(x) ((x) << 11)
10933#define MG_PLL_FRAC_LOCK_DCODITHEREN (1 << 10)
10934#define MG_PLL_FRAC_LOCK_FEEDFWRDCAL_EN (1 << 8)
10935#define MG_PLL_FRAC_LOCK_FEEDFWRDGAIN(x) ((x) << 0)
10936#define MG_PLL_FRAC_LOCK(tc_port) _MMIO_PORT((tc_port), \
10937 _MG_PLL_FRAC_LOCK_PORT1, \
10938 _MG_PLL_FRAC_LOCK_PORT2)
10939
10940#define _MG_PLL_SSC_PORT1 0x168A10
10941#define _MG_PLL_SSC_PORT2 0x169A10
10942#define _MG_PLL_SSC_PORT3 0x16AA10
10943#define _MG_PLL_SSC_PORT4 0x16BA10
10944#define MG_PLL_SSC_EN (1 << 28)
10945#define MG_PLL_SSC_TYPE(x) ((x) << 26)
10946#define MG_PLL_SSC_STEPLENGTH(x) ((x) << 16)
10947#define MG_PLL_SSC_STEPNUM(x) ((x) << 10)
10948#define MG_PLL_SSC_FLLEN (1 << 9)
10949#define MG_PLL_SSC_STEPSIZE(x) ((x) << 0)
10950#define MG_PLL_SSC(tc_port) _MMIO_PORT((tc_port), _MG_PLL_SSC_PORT1, \
10951 _MG_PLL_SSC_PORT2)
10952
10953#define _MG_PLL_BIAS_PORT1 0x168A14
10954#define _MG_PLL_BIAS_PORT2 0x169A14
10955#define _MG_PLL_BIAS_PORT3 0x16AA14
10956#define _MG_PLL_BIAS_PORT4 0x16BA14
10957#define MG_PLL_BIAS_BIAS_GB_SEL(x) ((x) << 30)
10958#define MG_PLL_BIAS_BIAS_GB_SEL_MASK (0x3 << 30)
10959#define MG_PLL_BIAS_INIT_DCOAMP(x) ((x) << 24)
10960#define MG_PLL_BIAS_INIT_DCOAMP_MASK (0x3f << 24)
10961#define MG_PLL_BIAS_BIAS_BONUS(x) ((x) << 16)
10962#define MG_PLL_BIAS_BIAS_BONUS_MASK (0xff << 16)
10963#define MG_PLL_BIAS_BIASCAL_EN (1 << 15)
10964#define MG_PLL_BIAS_CTRIM(x) ((x) << 8)
10965#define MG_PLL_BIAS_CTRIM_MASK (0x1f << 8)
10966#define MG_PLL_BIAS_VREF_RDAC(x) ((x) << 5)
10967#define MG_PLL_BIAS_VREF_RDAC_MASK (0x7 << 5)
10968#define MG_PLL_BIAS_IREFTRIM(x) ((x) << 0)
10969#define MG_PLL_BIAS_IREFTRIM_MASK (0x1f << 0)
10970#define MG_PLL_BIAS(tc_port) _MMIO_PORT((tc_port), _MG_PLL_BIAS_PORT1, \
10971 _MG_PLL_BIAS_PORT2)
10972
10973#define _MG_PLL_TDC_COLDST_BIAS_PORT1 0x168A18
10974#define _MG_PLL_TDC_COLDST_BIAS_PORT2 0x169A18
10975#define _MG_PLL_TDC_COLDST_BIAS_PORT3 0x16AA18
10976#define _MG_PLL_TDC_COLDST_BIAS_PORT4 0x16BA18
10977#define MG_PLL_TDC_COLDST_IREFINT_EN (1 << 27)
10978#define MG_PLL_TDC_COLDST_REFBIAS_START_PULSE_W(x) ((x) << 17)
10979#define MG_PLL_TDC_COLDST_COLDSTART (1 << 16)
10980#define MG_PLL_TDC_TDCOVCCORR_EN (1 << 2)
10981#define MG_PLL_TDC_TDCSEL(x) ((x) << 0)
10982#define MG_PLL_TDC_COLDST_BIAS(tc_port) _MMIO_PORT((tc_port), \
10983 _MG_PLL_TDC_COLDST_BIAS_PORT1, \
10984 _MG_PLL_TDC_COLDST_BIAS_PORT2)
10985
10986#define _ICL_DPLL0_CFGCR0 0x164000
10987#define _ICL_DPLL1_CFGCR0 0x164080
10988#define ICL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR0, \
10989 _ICL_DPLL1_CFGCR0)
10990#define DPLL_CFGCR0_HDMI_MODE (1 << 30)
10991#define DPLL_CFGCR0_SSC_ENABLE (1 << 29)
10992#define DPLL_CFGCR0_SSC_ENABLE_ICL (1 << 25)
10993#define DPLL_CFGCR0_LINK_RATE_MASK (0xf << 25)
10994#define DPLL_CFGCR0_LINK_RATE_2700 (0 << 25)
10995#define DPLL_CFGCR0_LINK_RATE_1350 (1 << 25)
10996#define DPLL_CFGCR0_LINK_RATE_810 (2 << 25)
10997#define DPLL_CFGCR0_LINK_RATE_1620 (3 << 25)
10998#define DPLL_CFGCR0_LINK_RATE_1080 (4 << 25)
10999#define DPLL_CFGCR0_LINK_RATE_2160 (5 << 25)
11000#define DPLL_CFGCR0_LINK_RATE_3240 (6 << 25)
11001#define DPLL_CFGCR0_LINK_RATE_4050 (7 << 25)
11002#define DPLL_CFGCR0_DCO_FRACTION_MASK (0x7fff << 10)
11003#define DPLL_CFGCR0_DCO_FRACTION_SHIFT (10)
11004#define DPLL_CFGCR0_DCO_FRACTION(x) ((x) << 10)
11005#define DPLL_CFGCR0_DCO_INTEGER_MASK (0x3ff)
11006
11007#define _ICL_DPLL0_CFGCR1 0x164004
11008#define _ICL_DPLL1_CFGCR1 0x164084
11009#define ICL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR1, \
11010 _ICL_DPLL1_CFGCR1)
11011#define DPLL_CFGCR1_QDIV_RATIO_MASK (0xff << 10)
11012#define DPLL_CFGCR1_QDIV_RATIO_SHIFT (10)
11013#define DPLL_CFGCR1_QDIV_RATIO(x) ((x) << 10)
11014#define DPLL_CFGCR1_QDIV_MODE_SHIFT (9)
11015#define DPLL_CFGCR1_QDIV_MODE(x) ((x) << 9)
11016#define DPLL_CFGCR1_KDIV_MASK (7 << 6)
11017#define DPLL_CFGCR1_KDIV_SHIFT (6)
11018#define DPLL_CFGCR1_KDIV(x) ((x) << 6)
11019#define DPLL_CFGCR1_KDIV_1 (1 << 6)
11020#define DPLL_CFGCR1_KDIV_2 (2 << 6)
11021#define DPLL_CFGCR1_KDIV_3 (4 << 6)
11022#define DPLL_CFGCR1_PDIV_MASK (0xf << 2)
11023#define DPLL_CFGCR1_PDIV_SHIFT (2)
11024#define DPLL_CFGCR1_PDIV(x) ((x) << 2)
11025#define DPLL_CFGCR1_PDIV_2 (1 << 2)
11026#define DPLL_CFGCR1_PDIV_3 (2 << 2)
11027#define DPLL_CFGCR1_PDIV_5 (4 << 2)
11028#define DPLL_CFGCR1_PDIV_7 (8 << 2)
11029#define DPLL_CFGCR1_CENTRAL_FREQ (3 << 0)
11030#define DPLL_CFGCR1_CENTRAL_FREQ_8400 (3 << 0)
11031#define TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL (0 << 0)
11032
11033#define _TGL_DPLL0_CFGCR0 0x164284
11034#define _TGL_DPLL1_CFGCR0 0x16428C
11035#define _TGL_TBTPLL_CFGCR0 0x16429C
11036#define TGL_DPLL_CFGCR0(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \
11037 _TGL_DPLL1_CFGCR0, \
11038 _TGL_TBTPLL_CFGCR0)
11039#define RKL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR0, \
11040 _TGL_DPLL1_CFGCR0)
11041
11042#define _TGL_DPLL0_CFGCR1 0x164288
11043#define _TGL_DPLL1_CFGCR1 0x164290
11044#define _TGL_TBTPLL_CFGCR1 0x1642A0
11045#define TGL_DPLL_CFGCR1(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \
11046 _TGL_DPLL1_CFGCR1, \
11047 _TGL_TBTPLL_CFGCR1)
11048#define RKL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR1, \
11049 _TGL_DPLL1_CFGCR1)
11050
11051#define _DG1_DPLL2_CFGCR0 0x16C284
11052#define _DG1_DPLL3_CFGCR0 0x16C28C
11053#define DG1_DPLL_CFGCR0(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \
11054 _TGL_DPLL1_CFGCR0, \
11055 _DG1_DPLL2_CFGCR0, \
11056 _DG1_DPLL3_CFGCR0)
11057
11058#define _DG1_DPLL2_CFGCR1 0x16C288
11059#define _DG1_DPLL3_CFGCR1 0x16C290
11060#define DG1_DPLL_CFGCR1(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \
11061 _TGL_DPLL1_CFGCR1, \
11062 _DG1_DPLL2_CFGCR1, \
11063 _DG1_DPLL3_CFGCR1)
11064
11065
11066#define _ADLS_DPLL3_CFGCR0 0x1642C0
11067#define _ADLS_DPLL4_CFGCR0 0x164294
11068#define ADLS_DPLL_CFGCR0(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \
11069 _TGL_DPLL1_CFGCR0, \
11070 _ADLS_DPLL4_CFGCR0, \
11071 _ADLS_DPLL3_CFGCR0)
11072
11073#define _ADLS_DPLL3_CFGCR1 0x1642C4
11074#define _ADLS_DPLL4_CFGCR1 0x164298
11075#define ADLS_DPLL_CFGCR1(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \
11076 _TGL_DPLL1_CFGCR1, \
11077 _ADLS_DPLL4_CFGCR1, \
11078 _ADLS_DPLL3_CFGCR1)
11079
11080#define _DKL_PHY1_BASE 0x168000
11081#define _DKL_PHY2_BASE 0x169000
11082#define _DKL_PHY3_BASE 0x16A000
11083#define _DKL_PHY4_BASE 0x16B000
11084#define _DKL_PHY5_BASE 0x16C000
11085#define _DKL_PHY6_BASE 0x16D000
11086
11087
11088#define _DKL_PLL_DIV0 0x200
11089#define DKL_PLL_DIV0_INTEG_COEFF(x) ((x) << 16)
11090#define DKL_PLL_DIV0_INTEG_COEFF_MASK (0x1F << 16)
11091#define DKL_PLL_DIV0_PROP_COEFF(x) ((x) << 12)
11092#define DKL_PLL_DIV0_PROP_COEFF_MASK (0xF << 12)
11093#define DKL_PLL_DIV0_FBPREDIV_SHIFT (8)
11094#define DKL_PLL_DIV0_FBPREDIV(x) ((x) << DKL_PLL_DIV0_FBPREDIV_SHIFT)
11095#define DKL_PLL_DIV0_FBPREDIV_MASK (0xF << DKL_PLL_DIV0_FBPREDIV_SHIFT)
11096#define DKL_PLL_DIV0_FBDIV_INT(x) ((x) << 0)
11097#define DKL_PLL_DIV0_FBDIV_INT_MASK (0xFF << 0)
11098#define DKL_PLL_DIV0(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \
11099 _DKL_PHY2_BASE) + \
11100 _DKL_PLL_DIV0)
11101
11102#define _DKL_PLL_DIV1 0x204
11103#define DKL_PLL_DIV1_IREF_TRIM(x) ((x) << 16)
11104#define DKL_PLL_DIV1_IREF_TRIM_MASK (0x1F << 16)
11105#define DKL_PLL_DIV1_TDC_TARGET_CNT(x) ((x) << 0)
11106#define DKL_PLL_DIV1_TDC_TARGET_CNT_MASK (0xFF << 0)
11107#define DKL_PLL_DIV1(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \
11108 _DKL_PHY2_BASE) + \
11109 _DKL_PLL_DIV1)
11110
11111#define _DKL_PLL_SSC 0x210
11112#define DKL_PLL_SSC_IREF_NDIV_RATIO(x) ((x) << 29)
11113#define DKL_PLL_SSC_IREF_NDIV_RATIO_MASK (0x7 << 29)
11114#define DKL_PLL_SSC_STEP_LEN(x) ((x) << 16)
11115#define DKL_PLL_SSC_STEP_LEN_MASK (0xFF << 16)
11116#define DKL_PLL_SSC_STEP_NUM(x) ((x) << 11)
11117#define DKL_PLL_SSC_STEP_NUM_MASK (0x7 << 11)
11118#define DKL_PLL_SSC_EN (1 << 9)
11119#define DKL_PLL_SSC(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \
11120 _DKL_PHY2_BASE) + \
11121 _DKL_PLL_SSC)
11122
11123#define _DKL_PLL_BIAS 0x214
11124#define DKL_PLL_BIAS_FRAC_EN_H (1 << 30)
11125#define DKL_PLL_BIAS_FBDIV_SHIFT (8)
11126#define DKL_PLL_BIAS_FBDIV_FRAC(x) ((x) << DKL_PLL_BIAS_FBDIV_SHIFT)
11127#define DKL_PLL_BIAS_FBDIV_FRAC_MASK (0x3FFFFF << DKL_PLL_BIAS_FBDIV_SHIFT)
11128#define DKL_PLL_BIAS(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \
11129 _DKL_PHY2_BASE) + \
11130 _DKL_PLL_BIAS)
11131
11132#define _DKL_PLL_TDC_COLDST_BIAS 0x218
11133#define DKL_PLL_TDC_SSC_STEP_SIZE(x) ((x) << 8)
11134#define DKL_PLL_TDC_SSC_STEP_SIZE_MASK (0xFF << 8)
11135#define DKL_PLL_TDC_FEED_FWD_GAIN(x) ((x) << 0)
11136#define DKL_PLL_TDC_FEED_FWD_GAIN_MASK (0xFF << 0)
11137#define DKL_PLL_TDC_COLDST_BIAS(tc_port) _MMIO(_PORT(tc_port, \
11138 _DKL_PHY1_BASE, \
11139 _DKL_PHY2_BASE) + \
11140 _DKL_PLL_TDC_COLDST_BIAS)
11141
11142#define _DKL_REFCLKIN_CTL 0x12C
11143
11144#define DKL_REFCLKIN_CTL(tc_port) _MMIO(_PORT(tc_port, \
11145 _DKL_PHY1_BASE, \
11146 _DKL_PHY2_BASE) + \
11147 _DKL_REFCLKIN_CTL)
11148
11149#define _DKL_CLKTOP2_HSCLKCTL 0xD4
11150
11151#define DKL_CLKTOP2_HSCLKCTL(tc_port) _MMIO(_PORT(tc_port, \
11152 _DKL_PHY1_BASE, \
11153 _DKL_PHY2_BASE) + \
11154 _DKL_CLKTOP2_HSCLKCTL)
11155
11156#define _DKL_CLKTOP2_CORECLKCTL1 0xD8
11157
11158#define DKL_CLKTOP2_CORECLKCTL1(tc_port) _MMIO(_PORT(tc_port, \
11159 _DKL_PHY1_BASE, \
11160 _DKL_PHY2_BASE) + \
11161 _DKL_CLKTOP2_CORECLKCTL1)
11162
11163#define _DKL_TX_DPCNTL0 0x2C0
11164#define DKL_TX_PRESHOOT_COEFF(x) ((x) << 13)
11165#define DKL_TX_PRESHOOT_COEFF_MASK (0x1f << 13)
11166#define DKL_TX_DE_EMPHASIS_COEFF(x) ((x) << 8)
11167#define DKL_TX_DE_EMPAHSIS_COEFF_MASK (0x1f << 8)
11168#define DKL_TX_VSWING_CONTROL(x) ((x) << 0)
11169#define DKL_TX_VSWING_CONTROL_MASK (0x7 << 0)
11170#define DKL_TX_DPCNTL0(tc_port) _MMIO(_PORT(tc_port, \
11171 _DKL_PHY1_BASE, \
11172 _DKL_PHY2_BASE) + \
11173 _DKL_TX_DPCNTL0)
11174
11175#define _DKL_TX_DPCNTL1 0x2C4
11176
11177#define DKL_TX_DPCNTL1(tc_port) _MMIO(_PORT(tc_port, \
11178 _DKL_PHY1_BASE, \
11179 _DKL_PHY2_BASE) + \
11180 _DKL_TX_DPCNTL1)
11181
11182#define _DKL_TX_DPCNTL2 0x2C8
11183#define DKL_TX_DP20BITMODE REG_BIT(2)
11184#define DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK REG_GENMASK(4, 3)
11185#define DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(val) REG_FIELD_PREP(DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK, (val))
11186#define DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK REG_GENMASK(6, 5)
11187#define DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(val) REG_FIELD_PREP(DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK, (val))
11188#define DKL_TX_DPCNTL2(tc_port) _MMIO(_PORT(tc_port, \
11189 _DKL_PHY1_BASE, \
11190 _DKL_PHY2_BASE) + \
11191 _DKL_TX_DPCNTL2)
11192
11193#define _DKL_TX_FW_CALIB 0x2F8
11194#define DKL_TX_CFG_DISABLE_WAIT_INIT (1 << 7)
11195#define DKL_TX_FW_CALIB(tc_port) _MMIO(_PORT(tc_port, \
11196 _DKL_PHY1_BASE, \
11197 _DKL_PHY2_BASE) + \
11198 _DKL_TX_FW_CALIB)
11199
11200#define _DKL_TX_PMD_LANE_SUS 0xD00
11201#define DKL_TX_PMD_LANE_SUS(tc_port) _MMIO(_PORT(tc_port, \
11202 _DKL_PHY1_BASE, \
11203 _DKL_PHY2_BASE) + \
11204 _DKL_TX_PMD_LANE_SUS)
11205
11206#define _DKL_TX_DW17 0xDC4
11207#define DKL_TX_DW17(tc_port) _MMIO(_PORT(tc_port, \
11208 _DKL_PHY1_BASE, \
11209 _DKL_PHY2_BASE) + \
11210 _DKL_TX_DW17)
11211
11212#define _DKL_TX_DW18 0xDC8
11213#define DKL_TX_DW18(tc_port) _MMIO(_PORT(tc_port, \
11214 _DKL_PHY1_BASE, \
11215 _DKL_PHY2_BASE) + \
11216 _DKL_TX_DW18)
11217
11218#define _DKL_DP_MODE 0xA0
11219#define DKL_DP_MODE(tc_port) _MMIO(_PORT(tc_port, \
11220 _DKL_PHY1_BASE, \
11221 _DKL_PHY2_BASE) + \
11222 _DKL_DP_MODE)
11223
11224#define _DKL_CMN_UC_DW27 0x36C
11225#define DKL_CMN_UC_DW27_UC_HEALTH (0x1 << 15)
11226#define DKL_CMN_UC_DW_27(tc_port) _MMIO(_PORT(tc_port, \
11227 _DKL_PHY1_BASE, \
11228 _DKL_PHY2_BASE) + \
11229 _DKL_CMN_UC_DW27)
11230
11231
11232
11233
11234
11235
11236
11237#define _HIP_INDEX_REG0 0x1010A0
11238#define _HIP_INDEX_REG1 0x1010A4
11239#define HIP_INDEX_REG(tc_port) _MMIO((tc_port) < 4 ? _HIP_INDEX_REG0 \
11240 : _HIP_INDEX_REG1)
11241#define _HIP_INDEX_SHIFT(tc_port) (8 * ((tc_port) % 4))
11242#define HIP_INDEX_VAL(tc_port, val) ((val) << _HIP_INDEX_SHIFT(tc_port))
11243
11244
11245#define BXT_DE_PLL_CTL _MMIO(0x6d000)
11246#define BXT_DE_PLL_RATIO(x) (x)
11247#define BXT_DE_PLL_RATIO_MASK 0xff
11248
11249#define BXT_DE_PLL_ENABLE _MMIO(0x46070)
11250#define BXT_DE_PLL_PLL_ENABLE (1 << 31)
11251#define BXT_DE_PLL_LOCK (1 << 30)
11252#define BXT_DE_PLL_FREQ_REQ (1 << 23)
11253#define BXT_DE_PLL_FREQ_REQ_ACK (1 << 22)
11254#define ICL_CDCLK_PLL_RATIO(x) (x)
11255#define ICL_CDCLK_PLL_RATIO_MASK 0xff
11256
11257
11258#define DC_STATE_EN _MMIO(0x45504)
11259#define DC_STATE_DISABLE 0
11260#define DC_STATE_EN_DC3CO REG_BIT(30)
11261#define DC_STATE_DC3CO_STATUS REG_BIT(29)
11262#define DC_STATE_EN_UPTO_DC5 (1 << 0)
11263#define DC_STATE_EN_DC9 (1 << 3)
11264#define DC_STATE_EN_UPTO_DC6 (2 << 0)
11265#define DC_STATE_EN_UPTO_DC5_DC6_MASK 0x3
11266
11267#define DC_STATE_DEBUG _MMIO(0x45520)
11268#define DC_STATE_DEBUG_MASK_CORES (1 << 0)
11269#define DC_STATE_DEBUG_MASK_MEMORY_UP (1 << 1)
11270
11271#define BXT_D_CR_DRP0_DUNIT8 0x1000
11272#define BXT_D_CR_DRP0_DUNIT9 0x1200
11273#define BXT_D_CR_DRP0_DUNIT_START 8
11274#define BXT_D_CR_DRP0_DUNIT_END 11
11275#define BXT_D_CR_DRP0_DUNIT(x) _MMIO(MCHBAR_MIRROR_BASE_SNB + \
11276 _PICK_EVEN((x) - 8, BXT_D_CR_DRP0_DUNIT8,\
11277 BXT_D_CR_DRP0_DUNIT9))
11278#define BXT_DRAM_RANK_MASK 0x3
11279#define BXT_DRAM_RANK_SINGLE 0x1
11280#define BXT_DRAM_RANK_DUAL 0x3
11281#define BXT_DRAM_WIDTH_MASK (0x3 << 4)
11282#define BXT_DRAM_WIDTH_SHIFT 4
11283#define BXT_DRAM_WIDTH_X8 (0x0 << 4)
11284#define BXT_DRAM_WIDTH_X16 (0x1 << 4)
11285#define BXT_DRAM_WIDTH_X32 (0x2 << 4)
11286#define BXT_DRAM_WIDTH_X64 (0x3 << 4)
11287#define BXT_DRAM_SIZE_MASK (0x7 << 6)
11288#define BXT_DRAM_SIZE_SHIFT 6
11289#define BXT_DRAM_SIZE_4GBIT (0x0 << 6)
11290#define BXT_DRAM_SIZE_6GBIT (0x1 << 6)
11291#define BXT_DRAM_SIZE_8GBIT (0x2 << 6)
11292#define BXT_DRAM_SIZE_12GBIT (0x3 << 6)
11293#define BXT_DRAM_SIZE_16GBIT (0x4 << 6)
11294#define BXT_DRAM_TYPE_MASK (0x7 << 22)
11295#define BXT_DRAM_TYPE_SHIFT 22
11296#define BXT_DRAM_TYPE_DDR3 (0x0 << 22)
11297#define BXT_DRAM_TYPE_LPDDR3 (0x1 << 22)
11298#define BXT_DRAM_TYPE_LPDDR4 (0x2 << 22)
11299#define BXT_DRAM_TYPE_DDR4 (0x4 << 22)
11300
11301#define SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5E04)
11302#define DG1_GEAR_TYPE REG_BIT(16)
11303
11304#define SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5000)
11305#define SKL_DRAM_DDR_TYPE_MASK (0x3 << 0)
11306#define SKL_DRAM_DDR_TYPE_DDR4 (0 << 0)
11307#define SKL_DRAM_DDR_TYPE_DDR3 (1 << 0)
11308#define SKL_DRAM_DDR_TYPE_LPDDR3 (2 << 0)
11309#define SKL_DRAM_DDR_TYPE_LPDDR4 (3 << 0)
11310
11311#define SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C)
11312#define SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5010)
11313#define SKL_DRAM_S_SHIFT 16
11314#define SKL_DRAM_SIZE_MASK 0x3F
11315#define SKL_DRAM_WIDTH_MASK (0x3 << 8)
11316#define SKL_DRAM_WIDTH_SHIFT 8
11317#define SKL_DRAM_WIDTH_X8 (0x0 << 8)
11318#define SKL_DRAM_WIDTH_X16 (0x1 << 8)
11319#define SKL_DRAM_WIDTH_X32 (0x2 << 8)
11320#define SKL_DRAM_RANK_MASK (0x1 << 10)
11321#define SKL_DRAM_RANK_SHIFT 10
11322#define SKL_DRAM_RANK_1 (0x0 << 10)
11323#define SKL_DRAM_RANK_2 (0x1 << 10)
11324#define SKL_DRAM_RANK_MASK (0x1 << 10)
11325#define ICL_DRAM_SIZE_MASK 0x7F
11326#define ICL_DRAM_WIDTH_MASK (0x3 << 7)
11327#define ICL_DRAM_WIDTH_SHIFT 7
11328#define ICL_DRAM_WIDTH_X8 (0x0 << 7)
11329#define ICL_DRAM_WIDTH_X16 (0x1 << 7)
11330#define ICL_DRAM_WIDTH_X32 (0x2 << 7)
11331#define ICL_DRAM_RANK_MASK (0x3 << 9)
11332#define ICL_DRAM_RANK_SHIFT 9
11333#define ICL_DRAM_RANK_1 (0x0 << 9)
11334#define ICL_DRAM_RANK_2 (0x1 << 9)
11335#define ICL_DRAM_RANK_3 (0x2 << 9)
11336#define ICL_DRAM_RANK_4 (0x3 << 9)
11337
11338#define SA_PERF_STATUS_0_0_0_MCHBAR_PC _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5918)
11339#define DG1_QCLK_RATIO_MASK REG_GENMASK(9, 2)
11340#define DG1_QCLK_REFERENCE REG_BIT(10)
11341
11342#define MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x4000)
11343#define DG1_DRAM_T_RDPRE_MASK REG_GENMASK(16, 11)
11344#define DG1_DRAM_T_RP_MASK REG_GENMASK(6, 0)
11345#define MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR_HIGH _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x4004)
11346#define DG1_DRAM_T_RCD_MASK REG_GENMASK(15, 9)
11347#define DG1_DRAM_T_RAS_MASK REG_GENMASK(8, 1)
11348
11349
11350
11351
11352
11353#define D_COMP_HSW _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5F0C)
11354#define D_COMP_BDW _MMIO(0x138144)
11355#define D_COMP_RCOMP_IN_PROGRESS (1 << 9)
11356#define D_COMP_COMP_FORCE (1 << 8)
11357#define D_COMP_COMP_DISABLE (1 << 0)
11358
11359
11360#define _WM_LINETIME_A 0x45270
11361#define _WM_LINETIME_B 0x45274
11362#define WM_LINETIME(pipe) _MMIO_PIPE(pipe, _WM_LINETIME_A, _WM_LINETIME_B)
11363#define HSW_LINETIME_MASK REG_GENMASK(8, 0)
11364#define HSW_LINETIME(x) REG_FIELD_PREP(HSW_LINETIME_MASK, (x))
11365#define HSW_IPS_LINETIME_MASK REG_GENMASK(24, 16)
11366#define HSW_IPS_LINETIME(x) REG_FIELD_PREP(HSW_IPS_LINETIME_MASK, (x))
11367
11368
11369#define SFUSE_STRAP _MMIO(0xc2014)
11370#define SFUSE_STRAP_FUSE_LOCK (1 << 13)
11371#define SFUSE_STRAP_RAW_FREQUENCY (1 << 8)
11372#define SFUSE_STRAP_DISPLAY_DISABLED (1 << 7)
11373#define SFUSE_STRAP_CRT_DISABLED (1 << 6)
11374#define SFUSE_STRAP_DDIF_DETECTED (1 << 3)
11375#define SFUSE_STRAP_DDIB_DETECTED (1 << 2)
11376#define SFUSE_STRAP_DDIC_DETECTED (1 << 1)
11377#define SFUSE_STRAP_DDID_DETECTED (1 << 0)
11378
11379#define WM_MISC _MMIO(0x45260)
11380#define WM_MISC_DATA_PARTITION_5_6 (1 << 0)
11381
11382#define WM_DBG _MMIO(0x45280)
11383#define WM_DBG_DISALLOW_MULTIPLE_LP (1 << 0)
11384#define WM_DBG_DISALLOW_MAXFIFO (1 << 1)
11385#define WM_DBG_DISALLOW_SPRITE (1 << 2)
11386
11387
11388#define _PIPE_A_CSC_COEFF_RY_GY 0x49010
11389#define _PIPE_A_CSC_COEFF_BY 0x49014
11390#define _PIPE_A_CSC_COEFF_RU_GU 0x49018
11391#define _PIPE_A_CSC_COEFF_BU 0x4901c
11392#define _PIPE_A_CSC_COEFF_RV_GV 0x49020
11393#define _PIPE_A_CSC_COEFF_BV 0x49024
11394
11395#define _PIPE_A_CSC_MODE 0x49028
11396#define ICL_CSC_ENABLE (1 << 31)
11397#define ICL_OUTPUT_CSC_ENABLE (1 << 30)
11398#define CSC_BLACK_SCREEN_OFFSET (1 << 2)
11399#define CSC_POSITION_BEFORE_GAMMA (1 << 1)
11400#define CSC_MODE_YUV_TO_RGB (1 << 0)
11401
11402#define _PIPE_A_CSC_PREOFF_HI 0x49030
11403#define _PIPE_A_CSC_PREOFF_ME 0x49034
11404#define _PIPE_A_CSC_PREOFF_LO 0x49038
11405#define _PIPE_A_CSC_POSTOFF_HI 0x49040
11406#define _PIPE_A_CSC_POSTOFF_ME 0x49044
11407#define _PIPE_A_CSC_POSTOFF_LO 0x49048
11408
11409#define _PIPE_B_CSC_COEFF_RY_GY 0x49110
11410#define _PIPE_B_CSC_COEFF_BY 0x49114
11411#define _PIPE_B_CSC_COEFF_RU_GU 0x49118
11412#define _PIPE_B_CSC_COEFF_BU 0x4911c
11413#define _PIPE_B_CSC_COEFF_RV_GV 0x49120
11414#define _PIPE_B_CSC_COEFF_BV 0x49124
11415#define _PIPE_B_CSC_MODE 0x49128
11416#define _PIPE_B_CSC_PREOFF_HI 0x49130
11417#define _PIPE_B_CSC_PREOFF_ME 0x49134
11418#define _PIPE_B_CSC_PREOFF_LO 0x49138
11419#define _PIPE_B_CSC_POSTOFF_HI 0x49140
11420#define _PIPE_B_CSC_POSTOFF_ME 0x49144
11421#define _PIPE_B_CSC_POSTOFF_LO 0x49148
11422
11423#define PIPE_CSC_COEFF_RY_GY(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY)
11424#define PIPE_CSC_COEFF_BY(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY)
11425#define PIPE_CSC_COEFF_RU_GU(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU)
11426#define PIPE_CSC_COEFF_BU(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU)
11427#define PIPE_CSC_COEFF_RV_GV(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV)
11428#define PIPE_CSC_COEFF_BV(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV)
11429#define PIPE_CSC_MODE(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_MODE, _PIPE_B_CSC_MODE)
11430#define PIPE_CSC_PREOFF_HI(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI)
11431#define PIPE_CSC_PREOFF_ME(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME)
11432#define PIPE_CSC_PREOFF_LO(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO)
11433#define PIPE_CSC_POSTOFF_HI(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI)
11434#define PIPE_CSC_POSTOFF_ME(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME)
11435#define PIPE_CSC_POSTOFF_LO(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO)
11436
11437
11438#define _PIPE_A_OUTPUT_CSC_COEFF_RY_GY 0x49050
11439#define _PIPE_A_OUTPUT_CSC_COEFF_BY 0x49054
11440#define _PIPE_A_OUTPUT_CSC_COEFF_RU_GU 0x49058
11441#define _PIPE_A_OUTPUT_CSC_COEFF_BU 0x4905c
11442#define _PIPE_A_OUTPUT_CSC_COEFF_RV_GV 0x49060
11443#define _PIPE_A_OUTPUT_CSC_COEFF_BV 0x49064
11444#define _PIPE_A_OUTPUT_CSC_PREOFF_HI 0x49068
11445#define _PIPE_A_OUTPUT_CSC_PREOFF_ME 0x4906c
11446#define _PIPE_A_OUTPUT_CSC_PREOFF_LO 0x49070
11447#define _PIPE_A_OUTPUT_CSC_POSTOFF_HI 0x49074
11448#define _PIPE_A_OUTPUT_CSC_POSTOFF_ME 0x49078
11449#define _PIPE_A_OUTPUT_CSC_POSTOFF_LO 0x4907c
11450
11451#define _PIPE_B_OUTPUT_CSC_COEFF_RY_GY 0x49150
11452#define _PIPE_B_OUTPUT_CSC_COEFF_BY 0x49154
11453#define _PIPE_B_OUTPUT_CSC_COEFF_RU_GU 0x49158
11454#define _PIPE_B_OUTPUT_CSC_COEFF_BU 0x4915c
11455#define _PIPE_B_OUTPUT_CSC_COEFF_RV_GV 0x49160
11456#define _PIPE_B_OUTPUT_CSC_COEFF_BV 0x49164
11457#define _PIPE_B_OUTPUT_CSC_PREOFF_HI 0x49168
11458#define _PIPE_B_OUTPUT_CSC_PREOFF_ME 0x4916c
11459#define _PIPE_B_OUTPUT_CSC_PREOFF_LO 0x49170
11460#define _PIPE_B_OUTPUT_CSC_POSTOFF_HI 0x49174
11461#define _PIPE_B_OUTPUT_CSC_POSTOFF_ME 0x49178
11462#define _PIPE_B_OUTPUT_CSC_POSTOFF_LO 0x4917c
11463
11464#define PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe) _MMIO_PIPE(pipe,\
11465 _PIPE_A_OUTPUT_CSC_COEFF_RY_GY,\
11466 _PIPE_B_OUTPUT_CSC_COEFF_RY_GY)
11467#define PIPE_CSC_OUTPUT_COEFF_BY(pipe) _MMIO_PIPE(pipe, \
11468 _PIPE_A_OUTPUT_CSC_COEFF_BY, \
11469 _PIPE_B_OUTPUT_CSC_COEFF_BY)
11470#define PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe) _MMIO_PIPE(pipe, \
11471 _PIPE_A_OUTPUT_CSC_COEFF_RU_GU, \
11472 _PIPE_B_OUTPUT_CSC_COEFF_RU_GU)
11473#define PIPE_CSC_OUTPUT_COEFF_BU(pipe) _MMIO_PIPE(pipe, \
11474 _PIPE_A_OUTPUT_CSC_COEFF_BU, \
11475 _PIPE_B_OUTPUT_CSC_COEFF_BU)
11476#define PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe) _MMIO_PIPE(pipe, \
11477 _PIPE_A_OUTPUT_CSC_COEFF_RV_GV, \
11478 _PIPE_B_OUTPUT_CSC_COEFF_RV_GV)
11479#define PIPE_CSC_OUTPUT_COEFF_BV(pipe) _MMIO_PIPE(pipe, \
11480 _PIPE_A_OUTPUT_CSC_COEFF_BV, \
11481 _PIPE_B_OUTPUT_CSC_COEFF_BV)
11482#define PIPE_CSC_OUTPUT_PREOFF_HI(pipe) _MMIO_PIPE(pipe, \
11483 _PIPE_A_OUTPUT_CSC_PREOFF_HI, \
11484 _PIPE_B_OUTPUT_CSC_PREOFF_HI)
11485#define PIPE_CSC_OUTPUT_PREOFF_ME(pipe) _MMIO_PIPE(pipe, \
11486 _PIPE_A_OUTPUT_CSC_PREOFF_ME, \
11487 _PIPE_B_OUTPUT_CSC_PREOFF_ME)
11488#define PIPE_CSC_OUTPUT_PREOFF_LO(pipe) _MMIO_PIPE(pipe, \
11489 _PIPE_A_OUTPUT_CSC_PREOFF_LO, \
11490 _PIPE_B_OUTPUT_CSC_PREOFF_LO)
11491#define PIPE_CSC_OUTPUT_POSTOFF_HI(pipe) _MMIO_PIPE(pipe, \
11492 _PIPE_A_OUTPUT_CSC_POSTOFF_HI, \
11493 _PIPE_B_OUTPUT_CSC_POSTOFF_HI)
11494#define PIPE_CSC_OUTPUT_POSTOFF_ME(pipe) _MMIO_PIPE(pipe, \
11495 _PIPE_A_OUTPUT_CSC_POSTOFF_ME, \
11496 _PIPE_B_OUTPUT_CSC_POSTOFF_ME)
11497#define PIPE_CSC_OUTPUT_POSTOFF_LO(pipe) _MMIO_PIPE(pipe, \
11498 _PIPE_A_OUTPUT_CSC_POSTOFF_LO, \
11499 _PIPE_B_OUTPUT_CSC_POSTOFF_LO)
11500
11501
11502#define _PAL_PREC_INDEX_A 0x4A400
11503#define _PAL_PREC_INDEX_B 0x4AC00
11504#define _PAL_PREC_INDEX_C 0x4B400
11505#define PAL_PREC_10_12_BIT (0 << 31)
11506#define PAL_PREC_SPLIT_MODE (1 << 31)
11507#define PAL_PREC_AUTO_INCREMENT (1 << 15)
11508#define PAL_PREC_INDEX_VALUE_MASK (0x3ff << 0)
11509#define PAL_PREC_INDEX_VALUE(x) ((x) << 0)
11510#define _PAL_PREC_DATA_A 0x4A404
11511#define _PAL_PREC_DATA_B 0x4AC04
11512#define _PAL_PREC_DATA_C 0x4B404
11513#define _PAL_PREC_GC_MAX_A 0x4A410
11514#define _PAL_PREC_GC_MAX_B 0x4AC10
11515#define _PAL_PREC_GC_MAX_C 0x4B410
11516#define PREC_PAL_DATA_RED_MASK REG_GENMASK(29, 20)
11517#define PREC_PAL_DATA_GREEN_MASK REG_GENMASK(19, 10)
11518#define PREC_PAL_DATA_BLUE_MASK REG_GENMASK(9, 0)
11519#define _PAL_PREC_EXT_GC_MAX_A 0x4A420
11520#define _PAL_PREC_EXT_GC_MAX_B 0x4AC20
11521#define _PAL_PREC_EXT_GC_MAX_C 0x4B420
11522#define _PAL_PREC_EXT2_GC_MAX_A 0x4A430
11523#define _PAL_PREC_EXT2_GC_MAX_B 0x4AC30
11524#define _PAL_PREC_EXT2_GC_MAX_C 0x4B430
11525
11526#define PREC_PAL_INDEX(pipe) _MMIO_PIPE(pipe, _PAL_PREC_INDEX_A, _PAL_PREC_INDEX_B)
11527#define PREC_PAL_DATA(pipe) _MMIO_PIPE(pipe, _PAL_PREC_DATA_A, _PAL_PREC_DATA_B)
11528#define PREC_PAL_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_GC_MAX_A, _PAL_PREC_GC_MAX_B) + (i) * 4)
11529#define PREC_PAL_EXT_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT_GC_MAX_A, _PAL_PREC_EXT_GC_MAX_B) + (i) * 4)
11530#define PREC_PAL_EXT2_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT2_GC_MAX_A, _PAL_PREC_EXT2_GC_MAX_B) + (i) * 4)
11531
11532#define _PRE_CSC_GAMC_INDEX_A 0x4A484
11533#define _PRE_CSC_GAMC_INDEX_B 0x4AC84
11534#define _PRE_CSC_GAMC_INDEX_C 0x4B484
11535#define PRE_CSC_GAMC_AUTO_INCREMENT (1 << 10)
11536#define _PRE_CSC_GAMC_DATA_A 0x4A488
11537#define _PRE_CSC_GAMC_DATA_B 0x4AC88
11538#define _PRE_CSC_GAMC_DATA_C 0x4B488
11539
11540#define PRE_CSC_GAMC_INDEX(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_INDEX_A, _PRE_CSC_GAMC_INDEX_B)
11541#define PRE_CSC_GAMC_DATA(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_DATA_A, _PRE_CSC_GAMC_DATA_B)
11542
11543
11544#define _PAL_PREC_MULTI_SEG_INDEX_A 0x4A408
11545#define _PAL_PREC_MULTI_SEG_INDEX_B 0x4AC08
11546#define PAL_PREC_MULTI_SEGMENT_AUTO_INCREMENT REG_BIT(15)
11547#define PAL_PREC_MULTI_SEGMENT_INDEX_VALUE_MASK REG_GENMASK(4, 0)
11548
11549#define _PAL_PREC_MULTI_SEG_DATA_A 0x4A40C
11550#define _PAL_PREC_MULTI_SEG_DATA_B 0x4AC0C
11551#define PAL_PREC_MULTI_SEG_RED_LDW_MASK REG_GENMASK(29, 24)
11552#define PAL_PREC_MULTI_SEG_RED_UDW_MASK REG_GENMASK(29, 20)
11553#define PAL_PREC_MULTI_SEG_GREEN_LDW_MASK REG_GENMASK(19, 14)
11554#define PAL_PREC_MULTI_SEG_GREEN_UDW_MASK REG_GENMASK(19, 10)
11555#define PAL_PREC_MULTI_SEG_BLUE_LDW_MASK REG_GENMASK(9, 4)
11556#define PAL_PREC_MULTI_SEG_BLUE_UDW_MASK REG_GENMASK(9, 0)
11557
11558#define PREC_PAL_MULTI_SEG_INDEX(pipe) _MMIO_PIPE(pipe, \
11559 _PAL_PREC_MULTI_SEG_INDEX_A, \
11560 _PAL_PREC_MULTI_SEG_INDEX_B)
11561#define PREC_PAL_MULTI_SEG_DATA(pipe) _MMIO_PIPE(pipe, \
11562 _PAL_PREC_MULTI_SEG_DATA_A, \
11563 _PAL_PREC_MULTI_SEG_DATA_B)
11564
11565#define _MMIO_PLANE_GAMC(plane, i, a, b) _MMIO(_PIPE(plane, a, b) + (i) * 4)
11566
11567
11568#define _PLANE_CSC_RY_GY_1_A 0x70210
11569#define _PLANE_CSC_RY_GY_2_A 0x70310
11570
11571#define _PLANE_CSC_RY_GY_1_B 0x71210
11572#define _PLANE_CSC_RY_GY_2_B 0x71310
11573
11574#define _PLANE_CSC_RY_GY_1(pipe) _PIPE(pipe, _PLANE_CSC_RY_GY_1_A, \
11575 _PLANE_CSC_RY_GY_1_B)
11576#define _PLANE_CSC_RY_GY_2(pipe) _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_2_A, \
11577 _PLANE_INPUT_CSC_RY_GY_2_B)
11578#define PLANE_CSC_COEFF(pipe, plane, index) _MMIO_PLANE(plane, \
11579 _PLANE_CSC_RY_GY_1(pipe) + (index) * 4, \
11580 _PLANE_CSC_RY_GY_2(pipe) + (index) * 4)
11581
11582#define _PLANE_CSC_PREOFF_HI_1_A 0x70228
11583#define _PLANE_CSC_PREOFF_HI_2_A 0x70328
11584
11585#define _PLANE_CSC_PREOFF_HI_1_B 0x71228
11586#define _PLANE_CSC_PREOFF_HI_2_B 0x71328
11587
11588#define _PLANE_CSC_PREOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_1_A, \
11589 _PLANE_CSC_PREOFF_HI_1_B)
11590#define _PLANE_CSC_PREOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_2_A, \
11591 _PLANE_CSC_PREOFF_HI_2_B)
11592#define PLANE_CSC_PREOFF(pipe, plane, index) _MMIO_PLANE(plane, _PLANE_CSC_PREOFF_HI_1(pipe) + \
11593 (index) * 4, _PLANE_CSC_PREOFF_HI_2(pipe) + \
11594 (index) * 4)
11595
11596#define _PLANE_CSC_POSTOFF_HI_1_A 0x70234
11597#define _PLANE_CSC_POSTOFF_HI_2_A 0x70334
11598
11599#define _PLANE_CSC_POSTOFF_HI_1_B 0x71234
11600#define _PLANE_CSC_POSTOFF_HI_2_B 0x71334
11601
11602#define _PLANE_CSC_POSTOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_1_A, \
11603 _PLANE_CSC_POSTOFF_HI_1_B)
11604#define _PLANE_CSC_POSTOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_2_A, \
11605 _PLANE_CSC_POSTOFF_HI_2_B)
11606#define PLANE_CSC_POSTOFF(pipe, plane, index) _MMIO_PLANE(plane, _PLANE_CSC_POSTOFF_HI_1(pipe) + \
11607 (index) * 4, _PLANE_CSC_POSTOFF_HI_2(pipe) + \
11608 (index) * 4)
11609
11610
11611#define _CGM_PIPE_A_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x67900)
11612#define _CGM_PIPE_A_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x67904)
11613#define _CGM_PIPE_A_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x67908)
11614#define _CGM_PIPE_A_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6790C)
11615#define _CGM_PIPE_A_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x67910)
11616#define _CGM_PIPE_A_DEGAMMA (VLV_DISPLAY_BASE + 0x66000)
11617#define CGM_PIPE_DEGAMMA_RED_MASK REG_GENMASK(13, 0)
11618#define CGM_PIPE_DEGAMMA_GREEN_MASK REG_GENMASK(29, 16)
11619#define CGM_PIPE_DEGAMMA_BLUE_MASK REG_GENMASK(13, 0)
11620#define _CGM_PIPE_A_GAMMA (VLV_DISPLAY_BASE + 0x67000)
11621#define CGM_PIPE_GAMMA_RED_MASK REG_GENMASK(9, 0)
11622#define CGM_PIPE_GAMMA_GREEN_MASK REG_GENMASK(25, 16)
11623#define CGM_PIPE_GAMMA_BLUE_MASK REG_GENMASK(9, 0)
11624#define _CGM_PIPE_A_MODE (VLV_DISPLAY_BASE + 0x67A00)
11625#define CGM_PIPE_MODE_GAMMA (1 << 2)
11626#define CGM_PIPE_MODE_CSC (1 << 1)
11627#define CGM_PIPE_MODE_DEGAMMA (1 << 0)
11628
11629#define _CGM_PIPE_B_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x69900)
11630#define _CGM_PIPE_B_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x69904)
11631#define _CGM_PIPE_B_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x69908)
11632#define _CGM_PIPE_B_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6990C)
11633#define _CGM_PIPE_B_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x69910)
11634#define _CGM_PIPE_B_DEGAMMA (VLV_DISPLAY_BASE + 0x68000)
11635#define _CGM_PIPE_B_GAMMA (VLV_DISPLAY_BASE + 0x69000)
11636#define _CGM_PIPE_B_MODE (VLV_DISPLAY_BASE + 0x69A00)
11637
11638#define CGM_PIPE_CSC_COEFF01(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF01, _CGM_PIPE_B_CSC_COEFF01)
11639#define CGM_PIPE_CSC_COEFF23(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF23, _CGM_PIPE_B_CSC_COEFF23)
11640#define CGM_PIPE_CSC_COEFF45(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF45, _CGM_PIPE_B_CSC_COEFF45)
11641#define CGM_PIPE_CSC_COEFF67(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF67, _CGM_PIPE_B_CSC_COEFF67)
11642#define CGM_PIPE_CSC_COEFF8(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF8, _CGM_PIPE_B_CSC_COEFF8)
11643#define CGM_PIPE_DEGAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_DEGAMMA, _CGM_PIPE_B_DEGAMMA) + (i) * 8 + (w) * 4)
11644#define CGM_PIPE_GAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_GAMMA, _CGM_PIPE_B_GAMMA) + (i) * 8 + (w) * 4)
11645#define CGM_PIPE_MODE(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_MODE, _CGM_PIPE_B_MODE)
11646
11647
11648
11649#define _MIPI_PORT(port, a, c) (((port) == PORT_A) ? a : c)
11650#define _MMIO_MIPI(port, a, c) _MMIO(_MIPI_PORT(port, a, c))
11651
11652
11653#define _MMIO_DSI(tc, dsi0, dsi1) _MMIO_TRANS((tc) - TRANSCODER_DSI_0, \
11654 dsi0, dsi1)
11655
11656#define MIPIO_TXESC_CLK_DIV1 _MMIO(0x160004)
11657#define GLK_TX_ESC_CLK_DIV1_MASK 0x3FF
11658#define MIPIO_TXESC_CLK_DIV2 _MMIO(0x160008)
11659#define GLK_TX_ESC_CLK_DIV2_MASK 0x3FF
11660
11661#define _ICL_DSI_ESC_CLK_DIV0 0x6b090
11662#define _ICL_DSI_ESC_CLK_DIV1 0x6b890
11663#define ICL_DSI_ESC_CLK_DIV(port) _MMIO_PORT((port), \
11664 _ICL_DSI_ESC_CLK_DIV0, \
11665 _ICL_DSI_ESC_CLK_DIV1)
11666#define _ICL_DPHY_ESC_CLK_DIV0 0x162190
11667#define _ICL_DPHY_ESC_CLK_DIV1 0x6C190
11668#define ICL_DPHY_ESC_CLK_DIV(port) _MMIO_PORT((port), \
11669 _ICL_DPHY_ESC_CLK_DIV0, \
11670 _ICL_DPHY_ESC_CLK_DIV1)
11671#define ICL_BYTE_CLK_PER_ESC_CLK_MASK (0x1f << 16)
11672#define ICL_BYTE_CLK_PER_ESC_CLK_SHIFT 16
11673#define ICL_ESC_CLK_DIV_MASK 0x1ff
11674#define ICL_ESC_CLK_DIV_SHIFT 0
11675#define DSI_MAX_ESC_CLK 20000
11676
11677#define _ADL_MIPIO_REG 0x180
11678#define ADL_MIPIO_DW(port, dw) _MMIO(_ICL_COMBOPHY(port) + _ADL_MIPIO_REG + 4 * (dw))
11679#define TX_ESC_CLK_DIV_PHY_SEL REGBIT(16)
11680#define TX_ESC_CLK_DIV_PHY_MASK REG_GENMASK(23, 16)
11681#define TX_ESC_CLK_DIV_PHY REG_FIELD_PREP(TX_ESC_CLK_DIV_PHY_MASK, 0x7f)
11682
11683#define _DSI_CMD_FRMCTL_0 0x6b034
11684#define _DSI_CMD_FRMCTL_1 0x6b834
11685#define DSI_CMD_FRMCTL(port) _MMIO_PORT(port, \
11686 _DSI_CMD_FRMCTL_0,\
11687 _DSI_CMD_FRMCTL_1)
11688#define DSI_FRAME_UPDATE_REQUEST (1 << 31)
11689#define DSI_PERIODIC_FRAME_UPDATE_ENABLE (1 << 29)
11690#define DSI_NULL_PACKET_ENABLE (1 << 28)
11691#define DSI_FRAME_IN_PROGRESS (1 << 0)
11692
11693#define _DSI_INTR_MASK_REG_0 0x6b070
11694#define _DSI_INTR_MASK_REG_1 0x6b870
11695#define DSI_INTR_MASK_REG(port) _MMIO_PORT(port, \
11696 _DSI_INTR_MASK_REG_0,\
11697 _DSI_INTR_MASK_REG_1)
11698
11699#define _DSI_INTR_IDENT_REG_0 0x6b074
11700#define _DSI_INTR_IDENT_REG_1 0x6b874
11701#define DSI_INTR_IDENT_REG(port) _MMIO_PORT(port, \
11702 _DSI_INTR_IDENT_REG_0,\
11703 _DSI_INTR_IDENT_REG_1)
11704#define DSI_TE_EVENT (1 << 31)
11705#define DSI_RX_DATA_OR_BTA_TERMINATED (1 << 30)
11706#define DSI_TX_DATA (1 << 29)
11707#define DSI_ULPS_ENTRY_DONE (1 << 28)
11708#define DSI_NON_TE_TRIGGER_RECEIVED (1 << 27)
11709#define DSI_HOST_CHKSUM_ERROR (1 << 26)
11710#define DSI_HOST_MULTI_ECC_ERROR (1 << 25)
11711#define DSI_HOST_SINGL_ECC_ERROR (1 << 24)
11712#define DSI_HOST_CONTENTION_DETECTED (1 << 23)
11713#define DSI_HOST_FALSE_CONTROL_ERROR (1 << 22)
11714#define DSI_HOST_TIMEOUT_ERROR (1 << 21)
11715#define DSI_HOST_LOW_POWER_TX_SYNC_ERROR (1 << 20)
11716#define DSI_HOST_ESCAPE_MODE_ENTRY_ERROR (1 << 19)
11717#define DSI_FRAME_UPDATE_DONE (1 << 16)
11718#define DSI_PROTOCOL_VIOLATION_REPORTED (1 << 15)
11719#define DSI_INVALID_TX_LENGTH (1 << 13)
11720#define DSI_INVALID_VC (1 << 12)
11721#define DSI_INVALID_DATA_TYPE (1 << 11)
11722#define DSI_PERIPHERAL_CHKSUM_ERROR (1 << 10)
11723#define DSI_PERIPHERAL_MULTI_ECC_ERROR (1 << 9)
11724#define DSI_PERIPHERAL_SINGLE_ECC_ERROR (1 << 8)
11725#define DSI_PERIPHERAL_CONTENTION_DETECTED (1 << 7)
11726#define DSI_PERIPHERAL_FALSE_CTRL_ERROR (1 << 6)
11727#define DSI_PERIPHERAL_TIMEOUT_ERROR (1 << 5)
11728#define DSI_PERIPHERAL_LP_TX_SYNC_ERROR (1 << 4)
11729#define DSI_PERIPHERAL_ESC_MODE_ENTRY_CMD_ERR (1 << 3)
11730#define DSI_EOT_SYNC_ERROR (1 << 2)
11731#define DSI_SOT_SYNC_ERROR (1 << 1)
11732#define DSI_SOT_ERROR (1 << 0)
11733
11734
11735#define GEN4_TIMESTAMP _MMIO(0x2358)
11736#define ILK_TIMESTAMP_HI _MMIO(0x70070)
11737#define IVB_TIMESTAMP_CTR _MMIO(0x44070)
11738
11739#define GEN9_TIMESTAMP_OVERRIDE _MMIO(0x44074)
11740#define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT 0
11741#define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK 0x3ff
11742#define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT 12
11743#define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK (0xf << 12)
11744
11745#define _PIPE_FRMTMSTMP_A 0x70048
11746#define PIPE_FRMTMSTMP(pipe) \
11747 _MMIO_PIPE2(pipe, _PIPE_FRMTMSTMP_A)
11748
11749
11750#define BXT_MAX_VAR_OUTPUT_KHZ 39500
11751
11752#define BXT_MIPI_CLOCK_CTL _MMIO(0x46090)
11753#define BXT_MIPI1_DIV_SHIFT 26
11754#define BXT_MIPI2_DIV_SHIFT 10
11755#define BXT_MIPI_DIV_SHIFT(port) \
11756 _MIPI_PORT(port, BXT_MIPI1_DIV_SHIFT, \
11757 BXT_MIPI2_DIV_SHIFT)
11758
11759
11760#define BXT_MIPI1_TX_ESCLK_SHIFT 26
11761#define BXT_MIPI2_TX_ESCLK_SHIFT 10
11762#define BXT_MIPI_TX_ESCLK_SHIFT(port) \
11763 _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_SHIFT, \
11764 BXT_MIPI2_TX_ESCLK_SHIFT)
11765#define BXT_MIPI1_TX_ESCLK_FIXDIV_MASK (0x3F << 26)
11766#define BXT_MIPI2_TX_ESCLK_FIXDIV_MASK (0x3F << 10)
11767#define BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port) \
11768 _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_FIXDIV_MASK, \
11769 BXT_MIPI2_TX_ESCLK_FIXDIV_MASK)
11770#define BXT_MIPI_TX_ESCLK_DIVIDER(port, val) \
11771 (((val) & 0x3F) << BXT_MIPI_TX_ESCLK_SHIFT(port))
11772
11773#define BXT_MIPI1_RX_ESCLK_UPPER_SHIFT 21
11774#define BXT_MIPI2_RX_ESCLK_UPPER_SHIFT 5
11775#define BXT_MIPI_RX_ESCLK_UPPER_SHIFT(port) \
11776 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_UPPER_SHIFT, \
11777 BXT_MIPI2_RX_ESCLK_UPPER_SHIFT)
11778#define BXT_MIPI1_RX_ESCLK_UPPER_FIXDIV_MASK (3 << 21)
11779#define BXT_MIPI2_RX_ESCLK_UPPER_FIXDIV_MASK (3 << 5)
11780#define BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port) \
11781 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_UPPER_FIXDIV_MASK, \
11782 BXT_MIPI2_RX_ESCLK_UPPER_FIXDIV_MASK)
11783#define BXT_MIPI_RX_ESCLK_UPPER_DIVIDER(port, val) \
11784 (((val) & 3) << BXT_MIPI_RX_ESCLK_UPPER_SHIFT(port))
11785
11786#define BXT_MIPI1_8X_BY3_SHIFT 19
11787#define BXT_MIPI2_8X_BY3_SHIFT 3
11788#define BXT_MIPI_8X_BY3_SHIFT(port) \
11789 _MIPI_PORT(port, BXT_MIPI1_8X_BY3_SHIFT, \
11790 BXT_MIPI2_8X_BY3_SHIFT)
11791#define BXT_MIPI1_8X_BY3_DIVIDER_MASK (3 << 19)
11792#define BXT_MIPI2_8X_BY3_DIVIDER_MASK (3 << 3)
11793#define BXT_MIPI_8X_BY3_DIVIDER_MASK(port) \
11794 _MIPI_PORT(port, BXT_MIPI1_8X_BY3_DIVIDER_MASK, \
11795 BXT_MIPI2_8X_BY3_DIVIDER_MASK)
11796#define BXT_MIPI_8X_BY3_DIVIDER(port, val) \
11797 (((val) & 3) << BXT_MIPI_8X_BY3_SHIFT(port))
11798
11799#define BXT_MIPI1_RX_ESCLK_LOWER_SHIFT 16
11800#define BXT_MIPI2_RX_ESCLK_LOWER_SHIFT 0
11801#define BXT_MIPI_RX_ESCLK_LOWER_SHIFT(port) \
11802 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_LOWER_SHIFT, \
11803 BXT_MIPI2_RX_ESCLK_LOWER_SHIFT)
11804#define BXT_MIPI1_RX_ESCLK_LOWER_FIXDIV_MASK (3 << 16)
11805#define BXT_MIPI2_RX_ESCLK_LOWER_FIXDIV_MASK (3 << 0)
11806#define BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port) \
11807 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_LOWER_FIXDIV_MASK, \
11808 BXT_MIPI2_RX_ESCLK_LOWER_FIXDIV_MASK)
11809#define BXT_MIPI_RX_ESCLK_LOWER_DIVIDER(port, val) \
11810 (((val) & 3) << BXT_MIPI_RX_ESCLK_LOWER_SHIFT(port))
11811
11812#define RX_DIVIDER_BIT_1_2 0x3
11813#define RX_DIVIDER_BIT_3_4 0xC
11814
11815
11816#define _BXT_MIPIA_TRANS_HACTIVE 0x6B0F8
11817#define _BXT_MIPIC_TRANS_HACTIVE 0x6B8F8
11818#define BXT_MIPI_TRANS_HACTIVE(tc) _MMIO_MIPI(tc, \
11819 _BXT_MIPIA_TRANS_HACTIVE, _BXT_MIPIC_TRANS_HACTIVE)
11820
11821#define _BXT_MIPIA_TRANS_VACTIVE 0x6B0FC
11822#define _BXT_MIPIC_TRANS_VACTIVE 0x6B8FC
11823#define BXT_MIPI_TRANS_VACTIVE(tc) _MMIO_MIPI(tc, \
11824 _BXT_MIPIA_TRANS_VACTIVE, _BXT_MIPIC_TRANS_VACTIVE)
11825
11826#define _BXT_MIPIA_TRANS_VTOTAL 0x6B100
11827#define _BXT_MIPIC_TRANS_VTOTAL 0x6B900
11828#define BXT_MIPI_TRANS_VTOTAL(tc) _MMIO_MIPI(tc, \
11829 _BXT_MIPIA_TRANS_VTOTAL, _BXT_MIPIC_TRANS_VTOTAL)
11830
11831#define BXT_DSI_PLL_CTL _MMIO(0x161000)
11832#define BXT_DSI_PLL_PVD_RATIO_SHIFT 16
11833#define BXT_DSI_PLL_PVD_RATIO_MASK (3 << BXT_DSI_PLL_PVD_RATIO_SHIFT)
11834#define BXT_DSI_PLL_PVD_RATIO_1 (1 << BXT_DSI_PLL_PVD_RATIO_SHIFT)
11835#define BXT_DSIC_16X_BY1 (0 << 10)
11836#define BXT_DSIC_16X_BY2 (1 << 10)
11837#define BXT_DSIC_16X_BY3 (2 << 10)
11838#define BXT_DSIC_16X_BY4 (3 << 10)
11839#define BXT_DSIC_16X_MASK (3 << 10)
11840#define BXT_DSIA_16X_BY1 (0 << 8)
11841#define BXT_DSIA_16X_BY2 (1 << 8)
11842#define BXT_DSIA_16X_BY3 (2 << 8)
11843#define BXT_DSIA_16X_BY4 (3 << 8)
11844#define BXT_DSIA_16X_MASK (3 << 8)
11845#define BXT_DSI_FREQ_SEL_SHIFT 8
11846#define BXT_DSI_FREQ_SEL_MASK (0xF << BXT_DSI_FREQ_SEL_SHIFT)
11847
11848#define BXT_DSI_PLL_RATIO_MAX 0x7D
11849#define BXT_DSI_PLL_RATIO_MIN 0x22
11850#define GLK_DSI_PLL_RATIO_MAX 0x6F
11851#define GLK_DSI_PLL_RATIO_MIN 0x22
11852#define BXT_DSI_PLL_RATIO_MASK 0xFF
11853#define BXT_REF_CLOCK_KHZ 19200
11854
11855#define BXT_DSI_PLL_ENABLE _MMIO(0x46080)
11856#define BXT_DSI_PLL_DO_ENABLE (1 << 31)
11857#define BXT_DSI_PLL_LOCKED (1 << 30)
11858
11859#define _MIPIA_PORT_CTRL (VLV_DISPLAY_BASE + 0x61190)
11860#define _MIPIC_PORT_CTRL (VLV_DISPLAY_BASE + 0x61700)
11861#define MIPI_PORT_CTRL(port) _MMIO_MIPI(port, _MIPIA_PORT_CTRL, _MIPIC_PORT_CTRL)
11862
11863
11864#define _BXT_MIPIA_PORT_CTRL 0x6B0C0
11865#define _BXT_MIPIC_PORT_CTRL 0x6B8C0
11866#define BXT_MIPI_PORT_CTRL(tc) _MMIO_MIPI(tc, _BXT_MIPIA_PORT_CTRL, _BXT_MIPIC_PORT_CTRL)
11867
11868
11869#define _ICL_DSI_IO_MODECTL_0 0x6B094
11870#define _ICL_DSI_IO_MODECTL_1 0x6B894
11871#define ICL_DSI_IO_MODECTL(port) _MMIO_PORT(port, \
11872 _ICL_DSI_IO_MODECTL_0, \
11873 _ICL_DSI_IO_MODECTL_1)
11874#define COMBO_PHY_MODE_DSI (1 << 0)
11875
11876
11877#define _TGL_DSI_CHKN_REG_0 0x6B0C0
11878#define _TGL_DSI_CHKN_REG_1 0x6B8C0
11879#define TGL_DSI_CHKN_REG(port) _MMIO_PORT(port, \
11880 _TGL_DSI_CHKN_REG_0, \
11881 _TGL_DSI_CHKN_REG_1)
11882#define TGL_DSI_CHKN_LSHS_GB_MASK REG_GENMASK(15, 12)
11883#define TGL_DSI_CHKN_LSHS_GB(byte_clocks) REG_FIELD_PREP(TGL_DSI_CHKN_LSHS_GB_MASK, \
11884 (byte_clocks))
11885
11886
11887#define DSS_CTL1 _MMIO(0x67400)
11888#define SPLITTER_ENABLE (1 << 31)
11889#define JOINER_ENABLE (1 << 30)
11890#define DUAL_LINK_MODE_INTERLEAVE (1 << 24)
11891#define DUAL_LINK_MODE_FRONTBACK (0 << 24)
11892#define OVERLAP_PIXELS_MASK (0xf << 16)
11893#define OVERLAP_PIXELS(pixels) ((pixels) << 16)
11894#define LEFT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0)
11895#define LEFT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0)
11896#define MAX_DL_BUFFER_TARGET_DEPTH 0x5a0
11897
11898#define DSS_CTL2 _MMIO(0x67404)
11899#define LEFT_BRANCH_VDSC_ENABLE (1 << 31)
11900#define RIGHT_BRANCH_VDSC_ENABLE (1 << 15)
11901#define RIGHT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0)
11902#define RIGHT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0)
11903
11904#define _ICL_PIPE_DSS_CTL1_PB 0x78200
11905#define _ICL_PIPE_DSS_CTL1_PC 0x78400
11906#define ICL_PIPE_DSS_CTL1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11907 _ICL_PIPE_DSS_CTL1_PB, \
11908 _ICL_PIPE_DSS_CTL1_PC)
11909#define BIG_JOINER_ENABLE (1 << 29)
11910#define MASTER_BIG_JOINER_ENABLE (1 << 28)
11911#define VGA_CENTERING_ENABLE (1 << 27)
11912#define SPLITTER_CONFIGURATION_MASK REG_GENMASK(26, 25)
11913#define SPLITTER_CONFIGURATION_2_SEGMENT REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 0)
11914#define SPLITTER_CONFIGURATION_4_SEGMENT REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 1)
11915#define UNCOMPRESSED_JOINER_MASTER (1 << 21)
11916#define UNCOMPRESSED_JOINER_SLAVE (1 << 20)
11917
11918#define _ICL_PIPE_DSS_CTL2_PB 0x78204
11919#define _ICL_PIPE_DSS_CTL2_PC 0x78404
11920#define ICL_PIPE_DSS_CTL2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11921 _ICL_PIPE_DSS_CTL2_PB, \
11922 _ICL_PIPE_DSS_CTL2_PC)
11923
11924#define BXT_P_DSI_REGULATOR_CFG _MMIO(0x160020)
11925#define STAP_SELECT (1 << 0)
11926
11927#define BXT_P_DSI_REGULATOR_TX_CTRL _MMIO(0x160054)
11928#define HS_IO_CTRL_SELECT (1 << 0)
11929
11930#define DPI_ENABLE (1 << 31)
11931#define MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT 27
11932#define MIPIA_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 27)
11933#define DUAL_LINK_MODE_SHIFT 26
11934#define DUAL_LINK_MODE_MASK (1 << 26)
11935#define DUAL_LINK_MODE_FRONT_BACK (0 << 26)
11936#define DUAL_LINK_MODE_PIXEL_ALTERNATIVE (1 << 26)
11937#define DITHERING_ENABLE (1 << 25)
11938#define FLOPPED_HSTX (1 << 23)
11939#define DE_INVERT (1 << 19)
11940#define MIPIA_FLISDSI_DELAY_COUNT_SHIFT 18
11941#define MIPIA_FLISDSI_DELAY_COUNT_MASK (0xf << 18)
11942#define AFE_LATCHOUT (1 << 17)
11943#define LP_OUTPUT_HOLD (1 << 16)
11944#define MIPIC_FLISDSI_DELAY_COUNT_HIGH_SHIFT 15
11945#define MIPIC_FLISDSI_DELAY_COUNT_HIGH_MASK (1 << 15)
11946#define MIPIC_MIPI4DPHY_DELAY_COUNT_SHIFT 11
11947#define MIPIC_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 11)
11948#define CSB_SHIFT 9
11949#define CSB_MASK (3 << 9)
11950#define CSB_20MHZ (0 << 9)
11951#define CSB_10MHZ (1 << 9)
11952#define CSB_40MHZ (2 << 9)
11953#define BANDGAP_MASK (1 << 8)
11954#define BANDGAP_PNW_CIRCUIT (0 << 8)
11955#define BANDGAP_LNC_CIRCUIT (1 << 8)
11956#define MIPIC_FLISDSI_DELAY_COUNT_LOW_SHIFT 5
11957#define MIPIC_FLISDSI_DELAY_COUNT_LOW_MASK (7 << 5)
11958#define TEARING_EFFECT_DELAY (1 << 4)
11959#define TEARING_EFFECT_SHIFT 2
11960#define TEARING_EFFECT_MASK (3 << 2)
11961#define TEARING_EFFECT_OFF (0 << 2)
11962#define TEARING_EFFECT_DSI (1 << 2)
11963#define TEARING_EFFECT_GPIO (2 << 2)
11964#define LANE_CONFIGURATION_SHIFT 0
11965#define LANE_CONFIGURATION_MASK (3 << 0)
11966#define LANE_CONFIGURATION_4LANE (0 << 0)
11967#define LANE_CONFIGURATION_DUAL_LINK_A (1 << 0)
11968#define LANE_CONFIGURATION_DUAL_LINK_B (2 << 0)
11969
11970#define _MIPIA_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61194)
11971#define _MIPIC_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61704)
11972#define MIPI_TEARING_CTRL(port) _MMIO_MIPI(port, _MIPIA_TEARING_CTRL, _MIPIC_TEARING_CTRL)
11973#define TEARING_EFFECT_DELAY_SHIFT 0
11974#define TEARING_EFFECT_DELAY_MASK (0xffff << 0)
11975
11976
11977#define _MIPIA_AUTOPWG (VLV_DISPLAY_BASE + 0x611a0)
11978
11979
11980
11981#define _MIPIA_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb000)
11982#define _MIPIC_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb800)
11983#define MIPI_DEVICE_READY(port) _MMIO_MIPI(port, _MIPIA_DEVICE_READY, _MIPIC_DEVICE_READY)
11984#define BUS_POSSESSION (1 << 3)
11985#define ULPS_STATE_MASK (3 << 1)
11986#define ULPS_STATE_ENTER (2 << 1)
11987#define ULPS_STATE_EXIT (1 << 1)
11988#define ULPS_STATE_NORMAL_OPERATION (0 << 1)
11989#define DEVICE_READY (1 << 0)
11990
11991#define _MIPIA_INTR_STAT (dev_priv->mipi_mmio_base + 0xb004)
11992#define _MIPIC_INTR_STAT (dev_priv->mipi_mmio_base + 0xb804)
11993#define MIPI_INTR_STAT(port) _MMIO_MIPI(port, _MIPIA_INTR_STAT, _MIPIC_INTR_STAT)
11994#define _MIPIA_INTR_EN (dev_priv->mipi_mmio_base + 0xb008)
11995#define _MIPIC_INTR_EN (dev_priv->mipi_mmio_base + 0xb808)
11996#define MIPI_INTR_EN(port) _MMIO_MIPI(port, _MIPIA_INTR_EN, _MIPIC_INTR_EN)
11997#define TEARING_EFFECT (1 << 31)
11998#define SPL_PKT_SENT_INTERRUPT (1 << 30)
11999#define GEN_READ_DATA_AVAIL (1 << 29)
12000#define LP_GENERIC_WR_FIFO_FULL (1 << 28)
12001#define HS_GENERIC_WR_FIFO_FULL (1 << 27)
12002#define RX_PROT_VIOLATION (1 << 26)
12003#define RX_INVALID_TX_LENGTH (1 << 25)
12004#define ACK_WITH_NO_ERROR (1 << 24)
12005#define TURN_AROUND_ACK_TIMEOUT (1 << 23)
12006#define LP_RX_TIMEOUT (1 << 22)
12007#define HS_TX_TIMEOUT (1 << 21)
12008#define DPI_FIFO_UNDERRUN (1 << 20)
12009#define LOW_CONTENTION (1 << 19)
12010#define HIGH_CONTENTION (1 << 18)
12011#define TXDSI_VC_ID_INVALID (1 << 17)
12012#define TXDSI_DATA_TYPE_NOT_RECOGNISED (1 << 16)
12013#define TXCHECKSUM_ERROR (1 << 15)
12014#define TXECC_MULTIBIT_ERROR (1 << 14)
12015#define TXECC_SINGLE_BIT_ERROR (1 << 13)
12016#define TXFALSE_CONTROL_ERROR (1 << 12)
12017#define RXDSI_VC_ID_INVALID (1 << 11)
12018#define RXDSI_DATA_TYPE_NOT_REGOGNISED (1 << 10)
12019#define RXCHECKSUM_ERROR (1 << 9)
12020#define RXECC_MULTIBIT_ERROR (1 << 8)
12021#define RXECC_SINGLE_BIT_ERROR (1 << 7)
12022#define RXFALSE_CONTROL_ERROR (1 << 6)
12023#define RXHS_RECEIVE_TIMEOUT_ERROR (1 << 5)
12024#define RX_LP_TX_SYNC_ERROR (1 << 4)
12025#define RXEXCAPE_MODE_ENTRY_ERROR (1 << 3)
12026#define RXEOT_SYNC_ERROR (1 << 2)
12027#define RXSOT_SYNC_ERROR (1 << 1)
12028#define RXSOT_ERROR (1 << 0)
12029
12030#define _MIPIA_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb00c)
12031#define _MIPIC_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb80c)
12032#define MIPI_DSI_FUNC_PRG(port) _MMIO_MIPI(port, _MIPIA_DSI_FUNC_PRG, _MIPIC_DSI_FUNC_PRG)
12033#define CMD_MODE_DATA_WIDTH_MASK (7 << 13)
12034#define CMD_MODE_NOT_SUPPORTED (0 << 13)
12035#define CMD_MODE_DATA_WIDTH_16_BIT (1 << 13)
12036#define CMD_MODE_DATA_WIDTH_9_BIT (2 << 13)
12037#define CMD_MODE_DATA_WIDTH_8_BIT (3 << 13)
12038#define CMD_MODE_DATA_WIDTH_OPTION1 (4 << 13)
12039#define CMD_MODE_DATA_WIDTH_OPTION2 (5 << 13)
12040#define VID_MODE_FORMAT_MASK (0xf << 7)
12041#define VID_MODE_NOT_SUPPORTED (0 << 7)
12042#define VID_MODE_FORMAT_RGB565 (1 << 7)
12043#define VID_MODE_FORMAT_RGB666_PACKED (2 << 7)
12044#define VID_MODE_FORMAT_RGB666 (3 << 7)
12045#define VID_MODE_FORMAT_RGB888 (4 << 7)
12046#define CMD_MODE_CHANNEL_NUMBER_SHIFT 5
12047#define CMD_MODE_CHANNEL_NUMBER_MASK (3 << 5)
12048#define VID_MODE_CHANNEL_NUMBER_SHIFT 3
12049#define VID_MODE_CHANNEL_NUMBER_MASK (3 << 3)
12050#define DATA_LANES_PRG_REG_SHIFT 0
12051#define DATA_LANES_PRG_REG_MASK (7 << 0)
12052
12053#define _MIPIA_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb010)
12054#define _MIPIC_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb810)
12055#define MIPI_HS_TX_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_HS_TX_TIMEOUT, _MIPIC_HS_TX_TIMEOUT)
12056#define HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK 0xffffff
12057
12058#define _MIPIA_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb014)
12059#define _MIPIC_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb814)
12060#define MIPI_LP_RX_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_LP_RX_TIMEOUT, _MIPIC_LP_RX_TIMEOUT)
12061#define LOW_POWER_RX_TIMEOUT_COUNTER_MASK 0xffffff
12062
12063#define _MIPIA_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb018)
12064#define _MIPIC_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb818)
12065#define MIPI_TURN_AROUND_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_TURN_AROUND_TIMEOUT, _MIPIC_TURN_AROUND_TIMEOUT)
12066#define TURN_AROUND_TIMEOUT_MASK 0x3f
12067
12068#define _MIPIA_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb01c)
12069#define _MIPIC_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb81c)
12070#define MIPI_DEVICE_RESET_TIMER(port) _MMIO_MIPI(port, _MIPIA_DEVICE_RESET_TIMER, _MIPIC_DEVICE_RESET_TIMER)
12071#define DEVICE_RESET_TIMER_MASK 0xffff
12072
12073#define _MIPIA_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb020)
12074#define _MIPIC_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb820)
12075#define MIPI_DPI_RESOLUTION(port) _MMIO_MIPI(port, _MIPIA_DPI_RESOLUTION, _MIPIC_DPI_RESOLUTION)
12076#define VERTICAL_ADDRESS_SHIFT 16
12077#define VERTICAL_ADDRESS_MASK (0xffff << 16)
12078#define HORIZONTAL_ADDRESS_SHIFT 0
12079#define HORIZONTAL_ADDRESS_MASK 0xffff
12080
12081#define _MIPIA_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb024)
12082#define _MIPIC_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb824)
12083#define MIPI_DBI_FIFO_THROTTLE(port) _MMIO_MIPI(port, _MIPIA_DBI_FIFO_THROTTLE, _MIPIC_DBI_FIFO_THROTTLE)
12084#define DBI_FIFO_EMPTY_HALF (0 << 0)
12085#define DBI_FIFO_EMPTY_QUARTER (1 << 0)
12086#define DBI_FIFO_EMPTY_7_LOCATIONS (2 << 0)
12087
12088
12089#define _MIPIA_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb028)
12090#define _MIPIC_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb828)
12091#define MIPI_HSYNC_PADDING_COUNT(port) _MMIO_MIPI(port, _MIPIA_HSYNC_PADDING_COUNT, _MIPIC_HSYNC_PADDING_COUNT)
12092
12093#define _MIPIA_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb02c)
12094#define _MIPIC_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb82c)
12095#define MIPI_HBP_COUNT(port) _MMIO_MIPI(port, _MIPIA_HBP_COUNT, _MIPIC_HBP_COUNT)
12096
12097#define _MIPIA_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb030)
12098#define _MIPIC_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb830)
12099#define MIPI_HFP_COUNT(port) _MMIO_MIPI(port, _MIPIA_HFP_COUNT, _MIPIC_HFP_COUNT)
12100
12101#define _MIPIA_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb034)
12102#define _MIPIC_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb834)
12103#define MIPI_HACTIVE_AREA_COUNT(port) _MMIO_MIPI(port, _MIPIA_HACTIVE_AREA_COUNT, _MIPIC_HACTIVE_AREA_COUNT)
12104
12105#define _MIPIA_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb038)
12106#define _MIPIC_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb838)
12107#define MIPI_VSYNC_PADDING_COUNT(port) _MMIO_MIPI(port, _MIPIA_VSYNC_PADDING_COUNT, _MIPIC_VSYNC_PADDING_COUNT)
12108
12109#define _MIPIA_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb03c)
12110#define _MIPIC_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb83c)
12111#define MIPI_VBP_COUNT(port) _MMIO_MIPI(port, _MIPIA_VBP_COUNT, _MIPIC_VBP_COUNT)
12112
12113#define _MIPIA_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb040)
12114#define _MIPIC_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb840)
12115#define MIPI_VFP_COUNT(port) _MMIO_MIPI(port, _MIPIA_VFP_COUNT, _MIPIC_VFP_COUNT)
12116
12117#define _MIPIA_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb044)
12118#define _MIPIC_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb844)
12119#define MIPI_HIGH_LOW_SWITCH_COUNT(port) _MMIO_MIPI(port, _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIC_HIGH_LOW_SWITCH_COUNT)
12120
12121
12122
12123#define _MIPIA_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb048)
12124#define _MIPIC_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb848)
12125#define MIPI_DPI_CONTROL(port) _MMIO_MIPI(port, _MIPIA_DPI_CONTROL, _MIPIC_DPI_CONTROL)
12126#define DPI_LP_MODE (1 << 6)
12127#define BACKLIGHT_OFF (1 << 5)
12128#define BACKLIGHT_ON (1 << 4)
12129#define COLOR_MODE_OFF (1 << 3)
12130#define COLOR_MODE_ON (1 << 2)
12131#define TURN_ON (1 << 1)
12132#define SHUTDOWN (1 << 0)
12133
12134#define _MIPIA_DPI_DATA (dev_priv->mipi_mmio_base + 0xb04c)
12135#define _MIPIC_DPI_DATA (dev_priv->mipi_mmio_base + 0xb84c)
12136#define MIPI_DPI_DATA(port) _MMIO_MIPI(port, _MIPIA_DPI_DATA, _MIPIC_DPI_DATA)
12137#define COMMAND_BYTE_SHIFT 0
12138#define COMMAND_BYTE_MASK (0x3f << 0)
12139
12140#define _MIPIA_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb050)
12141#define _MIPIC_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb850)
12142#define MIPI_INIT_COUNT(port) _MMIO_MIPI(port, _MIPIA_INIT_COUNT, _MIPIC_INIT_COUNT)
12143#define MASTER_INIT_TIMER_SHIFT 0
12144#define MASTER_INIT_TIMER_MASK (0xffff << 0)
12145
12146#define _MIPIA_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb054)
12147#define _MIPIC_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb854)
12148#define MIPI_MAX_RETURN_PKT_SIZE(port) _MMIO_MIPI(port, \
12149 _MIPIA_MAX_RETURN_PKT_SIZE, _MIPIC_MAX_RETURN_PKT_SIZE)
12150#define MAX_RETURN_PKT_SIZE_SHIFT 0
12151#define MAX_RETURN_PKT_SIZE_MASK (0x3ff << 0)
12152
12153#define _MIPIA_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb058)
12154#define _MIPIC_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb858)
12155#define MIPI_VIDEO_MODE_FORMAT(port) _MMIO_MIPI(port, _MIPIA_VIDEO_MODE_FORMAT, _MIPIC_VIDEO_MODE_FORMAT)
12156#define RANDOM_DPI_DISPLAY_RESOLUTION (1 << 4)
12157#define DISABLE_VIDEO_BTA (1 << 3)
12158#define IP_TG_CONFIG (1 << 2)
12159#define VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE (1 << 0)
12160#define VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS (2 << 0)
12161#define VIDEO_MODE_BURST (3 << 0)
12162
12163#define _MIPIA_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb05c)
12164#define _MIPIC_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb85c)
12165#define MIPI_EOT_DISABLE(port) _MMIO_MIPI(port, _MIPIA_EOT_DISABLE, _MIPIC_EOT_DISABLE)
12166#define BXT_DEFEATURE_DPI_FIFO_CTR (1 << 9)
12167#define BXT_DPHY_DEFEATURE_EN (1 << 8)
12168#define LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 7)
12169#define HS_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 6)
12170#define LOW_CONTENTION_RECOVERY_DISABLE (1 << 5)
12171#define HIGH_CONTENTION_RECOVERY_DISABLE (1 << 4)
12172#define TXDSI_TYPE_NOT_RECOGNISED_ERROR_RECOVERY_DISABLE (1 << 3)
12173#define TXECC_MULTIBIT_ERROR_RECOVERY_DISABLE (1 << 2)
12174#define CLOCKSTOP (1 << 1)
12175#define EOT_DISABLE (1 << 0)
12176
12177#define _MIPIA_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb060)
12178#define _MIPIC_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb860)
12179#define MIPI_LP_BYTECLK(port) _MMIO_MIPI(port, _MIPIA_LP_BYTECLK, _MIPIC_LP_BYTECLK)
12180#define LP_BYTECLK_SHIFT 0
12181#define LP_BYTECLK_MASK (0xffff << 0)
12182
12183#define _MIPIA_TLPX_TIME_COUNT (dev_priv->mipi_mmio_base + 0xb0a4)
12184#define _MIPIC_TLPX_TIME_COUNT (dev_priv->mipi_mmio_base + 0xb8a4)
12185#define MIPI_TLPX_TIME_COUNT(port) _MMIO_MIPI(port, _MIPIA_TLPX_TIME_COUNT, _MIPIC_TLPX_TIME_COUNT)
12186
12187#define _MIPIA_CLK_LANE_TIMING (dev_priv->mipi_mmio_base + 0xb098)
12188#define _MIPIC_CLK_LANE_TIMING (dev_priv->mipi_mmio_base + 0xb898)
12189#define MIPI_CLK_LANE_TIMING(port) _MMIO_MIPI(port, _MIPIA_CLK_LANE_TIMING, _MIPIC_CLK_LANE_TIMING)
12190
12191
12192#define _MIPIA_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb064)
12193#define _MIPIC_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb864)
12194#define MIPI_LP_GEN_DATA(port) _MMIO_MIPI(port, _MIPIA_LP_GEN_DATA, _MIPIC_LP_GEN_DATA)
12195
12196
12197#define _MIPIA_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb068)
12198#define _MIPIC_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb868)
12199#define MIPI_HS_GEN_DATA(port) _MMIO_MIPI(port, _MIPIA_HS_GEN_DATA, _MIPIC_HS_GEN_DATA)
12200
12201#define _MIPIA_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb06c)
12202#define _MIPIC_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb86c)
12203#define MIPI_LP_GEN_CTRL(port) _MMIO_MIPI(port, _MIPIA_LP_GEN_CTRL, _MIPIC_LP_GEN_CTRL)
12204#define _MIPIA_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb070)
12205#define _MIPIC_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb870)
12206#define MIPI_HS_GEN_CTRL(port) _MMIO_MIPI(port, _MIPIA_HS_GEN_CTRL, _MIPIC_HS_GEN_CTRL)
12207#define LONG_PACKET_WORD_COUNT_SHIFT 8
12208#define LONG_PACKET_WORD_COUNT_MASK (0xffff << 8)
12209#define SHORT_PACKET_PARAM_SHIFT 8
12210#define SHORT_PACKET_PARAM_MASK (0xffff << 8)
12211#define VIRTUAL_CHANNEL_SHIFT 6
12212#define VIRTUAL_CHANNEL_MASK (3 << 6)
12213#define DATA_TYPE_SHIFT 0
12214#define DATA_TYPE_MASK (0x3f << 0)
12215
12216
12217#define _MIPIA_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb074)
12218#define _MIPIC_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb874)
12219#define MIPI_GEN_FIFO_STAT(port) _MMIO_MIPI(port, _MIPIA_GEN_FIFO_STAT, _MIPIC_GEN_FIFO_STAT)
12220#define DPI_FIFO_EMPTY (1 << 28)
12221#define DBI_FIFO_EMPTY (1 << 27)
12222#define LP_CTRL_FIFO_EMPTY (1 << 26)
12223#define LP_CTRL_FIFO_HALF_EMPTY (1 << 25)
12224#define LP_CTRL_FIFO_FULL (1 << 24)
12225#define HS_CTRL_FIFO_EMPTY (1 << 18)
12226#define HS_CTRL_FIFO_HALF_EMPTY (1 << 17)
12227#define HS_CTRL_FIFO_FULL (1 << 16)
12228#define LP_DATA_FIFO_EMPTY (1 << 10)
12229#define LP_DATA_FIFO_HALF_EMPTY (1 << 9)
12230#define LP_DATA_FIFO_FULL (1 << 8)
12231#define HS_DATA_FIFO_EMPTY (1 << 2)
12232#define HS_DATA_FIFO_HALF_EMPTY (1 << 1)
12233#define HS_DATA_FIFO_FULL (1 << 0)
12234
12235#define _MIPIA_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb078)
12236#define _MIPIC_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb878)
12237#define MIPI_HS_LP_DBI_ENABLE(port) _MMIO_MIPI(port, _MIPIA_HS_LS_DBI_ENABLE, _MIPIC_HS_LS_DBI_ENABLE)
12238#define DBI_HS_LP_MODE_MASK (1 << 0)
12239#define DBI_LP_MODE (1 << 0)
12240#define DBI_HS_MODE (0 << 0)
12241
12242#define _MIPIA_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb080)
12243#define _MIPIC_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb880)
12244#define MIPI_DPHY_PARAM(port) _MMIO_MIPI(port, _MIPIA_DPHY_PARAM, _MIPIC_DPHY_PARAM)
12245#define EXIT_ZERO_COUNT_SHIFT 24
12246#define EXIT_ZERO_COUNT_MASK (0x3f << 24)
12247#define TRAIL_COUNT_SHIFT 16
12248#define TRAIL_COUNT_MASK (0x1f << 16)
12249#define CLK_ZERO_COUNT_SHIFT 8
12250#define CLK_ZERO_COUNT_MASK (0xff << 8)
12251#define PREPARE_COUNT_SHIFT 0
12252#define PREPARE_COUNT_MASK (0x3f << 0)
12253
12254#define _ICL_DSI_T_INIT_MASTER_0 0x6b088
12255#define _ICL_DSI_T_INIT_MASTER_1 0x6b888
12256#define ICL_DSI_T_INIT_MASTER(port) _MMIO_PORT(port, \
12257 _ICL_DSI_T_INIT_MASTER_0,\
12258 _ICL_DSI_T_INIT_MASTER_1)
12259
12260#define _DPHY_CLK_TIMING_PARAM_0 0x162180
12261#define _DPHY_CLK_TIMING_PARAM_1 0x6c180
12262#define DPHY_CLK_TIMING_PARAM(port) _MMIO_PORT(port, \
12263 _DPHY_CLK_TIMING_PARAM_0,\
12264 _DPHY_CLK_TIMING_PARAM_1)
12265#define _DSI_CLK_TIMING_PARAM_0 0x6b080
12266#define _DSI_CLK_TIMING_PARAM_1 0x6b880
12267#define DSI_CLK_TIMING_PARAM(port) _MMIO_PORT(port, \
12268 _DSI_CLK_TIMING_PARAM_0,\
12269 _DSI_CLK_TIMING_PARAM_1)
12270#define CLK_PREPARE_OVERRIDE (1 << 31)
12271#define CLK_PREPARE(x) ((x) << 28)
12272#define CLK_PREPARE_MASK (0x7 << 28)
12273#define CLK_PREPARE_SHIFT 28
12274#define CLK_ZERO_OVERRIDE (1 << 27)
12275#define CLK_ZERO(x) ((x) << 20)
12276#define CLK_ZERO_MASK (0xf << 20)
12277#define CLK_ZERO_SHIFT 20
12278#define CLK_PRE_OVERRIDE (1 << 19)
12279#define CLK_PRE(x) ((x) << 16)
12280#define CLK_PRE_MASK (0x3 << 16)
12281#define CLK_PRE_SHIFT 16
12282#define CLK_POST_OVERRIDE (1 << 15)
12283#define CLK_POST(x) ((x) << 8)
12284#define CLK_POST_MASK (0x7 << 8)
12285#define CLK_POST_SHIFT 8
12286#define CLK_TRAIL_OVERRIDE (1 << 7)
12287#define CLK_TRAIL(x) ((x) << 0)
12288#define CLK_TRAIL_MASK (0xf << 0)
12289#define CLK_TRAIL_SHIFT 0
12290
12291#define _DPHY_DATA_TIMING_PARAM_0 0x162184
12292#define _DPHY_DATA_TIMING_PARAM_1 0x6c184
12293#define DPHY_DATA_TIMING_PARAM(port) _MMIO_PORT(port, \
12294 _DPHY_DATA_TIMING_PARAM_0,\
12295 _DPHY_DATA_TIMING_PARAM_1)
12296#define _DSI_DATA_TIMING_PARAM_0 0x6B084
12297#define _DSI_DATA_TIMING_PARAM_1 0x6B884
12298#define DSI_DATA_TIMING_PARAM(port) _MMIO_PORT(port, \
12299 _DSI_DATA_TIMING_PARAM_0,\
12300 _DSI_DATA_TIMING_PARAM_1)
12301#define HS_PREPARE_OVERRIDE (1 << 31)
12302#define HS_PREPARE(x) ((x) << 24)
12303#define HS_PREPARE_MASK (0x7 << 24)
12304#define HS_PREPARE_SHIFT 24
12305#define HS_ZERO_OVERRIDE (1 << 23)
12306#define HS_ZERO(x) ((x) << 16)
12307#define HS_ZERO_MASK (0xf << 16)
12308#define HS_ZERO_SHIFT 16
12309#define HS_TRAIL_OVERRIDE (1 << 15)
12310#define HS_TRAIL(x) ((x) << 8)
12311#define HS_TRAIL_MASK (0x7 << 8)
12312#define HS_TRAIL_SHIFT 8
12313#define HS_EXIT_OVERRIDE (1 << 7)
12314#define HS_EXIT(x) ((x) << 0)
12315#define HS_EXIT_MASK (0x7 << 0)
12316#define HS_EXIT_SHIFT 0
12317
12318#define _DPHY_TA_TIMING_PARAM_0 0x162188
12319#define _DPHY_TA_TIMING_PARAM_1 0x6c188
12320#define DPHY_TA_TIMING_PARAM(port) _MMIO_PORT(port, \
12321 _DPHY_TA_TIMING_PARAM_0,\
12322 _DPHY_TA_TIMING_PARAM_1)
12323#define _DSI_TA_TIMING_PARAM_0 0x6b098
12324#define _DSI_TA_TIMING_PARAM_1 0x6b898
12325#define DSI_TA_TIMING_PARAM(port) _MMIO_PORT(port, \
12326 _DSI_TA_TIMING_PARAM_0,\
12327 _DSI_TA_TIMING_PARAM_1)
12328#define TA_SURE_OVERRIDE (1 << 31)
12329#define TA_SURE(x) ((x) << 16)
12330#define TA_SURE_MASK (0x1f << 16)
12331#define TA_SURE_SHIFT 16
12332#define TA_GO_OVERRIDE (1 << 15)
12333#define TA_GO(x) ((x) << 8)
12334#define TA_GO_MASK (0xf << 8)
12335#define TA_GO_SHIFT 8
12336#define TA_GET_OVERRIDE (1 << 7)
12337#define TA_GET(x) ((x) << 0)
12338#define TA_GET_MASK (0xf << 0)
12339#define TA_GET_SHIFT 0
12340
12341
12342#define _DSI_TRANS_FUNC_CONF_0 0x6b030
12343#define _DSI_TRANS_FUNC_CONF_1 0x6b830
12344#define DSI_TRANS_FUNC_CONF(tc) _MMIO_DSI(tc, \
12345 _DSI_TRANS_FUNC_CONF_0,\
12346 _DSI_TRANS_FUNC_CONF_1)
12347#define OP_MODE_MASK (0x3 << 28)
12348#define OP_MODE_SHIFT 28
12349#define CMD_MODE_NO_GATE (0x0 << 28)
12350#define CMD_MODE_TE_GATE (0x1 << 28)
12351#define VIDEO_MODE_SYNC_EVENT (0x2 << 28)
12352#define VIDEO_MODE_SYNC_PULSE (0x3 << 28)
12353#define TE_SOURCE_GPIO (1 << 27)
12354#define LINK_READY (1 << 20)
12355#define PIX_FMT_MASK (0x3 << 16)
12356#define PIX_FMT_SHIFT 16
12357#define PIX_FMT_RGB565 (0x0 << 16)
12358#define PIX_FMT_RGB666_PACKED (0x1 << 16)
12359#define PIX_FMT_RGB666_LOOSE (0x2 << 16)
12360#define PIX_FMT_RGB888 (0x3 << 16)
12361#define PIX_FMT_RGB101010 (0x4 << 16)
12362#define PIX_FMT_RGB121212 (0x5 << 16)
12363#define PIX_FMT_COMPRESSED (0x6 << 16)
12364#define BGR_TRANSMISSION (1 << 15)
12365#define PIX_VIRT_CHAN(x) ((x) << 12)
12366#define PIX_VIRT_CHAN_MASK (0x3 << 12)
12367#define PIX_VIRT_CHAN_SHIFT 12
12368#define PIX_BUF_THRESHOLD_MASK (0x3 << 10)
12369#define PIX_BUF_THRESHOLD_SHIFT 10
12370#define PIX_BUF_THRESHOLD_1_4 (0x0 << 10)
12371#define PIX_BUF_THRESHOLD_1_2 (0x1 << 10)
12372#define PIX_BUF_THRESHOLD_3_4 (0x2 << 10)
12373#define PIX_BUF_THRESHOLD_FULL (0x3 << 10)
12374#define CONTINUOUS_CLK_MASK (0x3 << 8)
12375#define CONTINUOUS_CLK_SHIFT 8
12376#define CLK_ENTER_LP_AFTER_DATA (0x0 << 8)
12377#define CLK_HS_OR_LP (0x2 << 8)
12378#define CLK_HS_CONTINUOUS (0x3 << 8)
12379#define LINK_CALIBRATION_MASK (0x3 << 4)
12380#define LINK_CALIBRATION_SHIFT 4
12381#define CALIBRATION_DISABLED (0x0 << 4)
12382#define CALIBRATION_ENABLED_INITIAL_ONLY (0x2 << 4)
12383#define CALIBRATION_ENABLED_INITIAL_PERIODIC (0x3 << 4)
12384#define BLANKING_PACKET_ENABLE (1 << 2)
12385#define S3D_ORIENTATION_LANDSCAPE (1 << 1)
12386#define EOTP_DISABLED (1 << 0)
12387
12388#define _DSI_CMD_RXCTL_0 0x6b0d4
12389#define _DSI_CMD_RXCTL_1 0x6b8d4
12390#define DSI_CMD_RXCTL(tc) _MMIO_DSI(tc, \
12391 _DSI_CMD_RXCTL_0,\
12392 _DSI_CMD_RXCTL_1)
12393#define READ_UNLOADS_DW (1 << 16)
12394#define RECEIVED_UNASSIGNED_TRIGGER (1 << 15)
12395#define RECEIVED_ACKNOWLEDGE_TRIGGER (1 << 14)
12396#define RECEIVED_TEAR_EFFECT_TRIGGER (1 << 13)
12397#define RECEIVED_RESET_TRIGGER (1 << 12)
12398#define RECEIVED_PAYLOAD_WAS_LOST (1 << 11)
12399#define RECEIVED_CRC_WAS_LOST (1 << 10)
12400#define NUMBER_RX_PLOAD_DW_MASK (0xff << 0)
12401#define NUMBER_RX_PLOAD_DW_SHIFT 0
12402
12403#define _DSI_CMD_TXCTL_0 0x6b0d0
12404#define _DSI_CMD_TXCTL_1 0x6b8d0
12405#define DSI_CMD_TXCTL(tc) _MMIO_DSI(tc, \
12406 _DSI_CMD_TXCTL_0,\
12407 _DSI_CMD_TXCTL_1)
12408#define KEEP_LINK_IN_HS (1 << 24)
12409#define FREE_HEADER_CREDIT_MASK (0x1f << 8)
12410#define FREE_HEADER_CREDIT_SHIFT 0x8
12411#define FREE_PLOAD_CREDIT_MASK (0xff << 0)
12412#define FREE_PLOAD_CREDIT_SHIFT 0
12413#define MAX_HEADER_CREDIT 0x10
12414#define MAX_PLOAD_CREDIT 0x40
12415
12416#define _DSI_CMD_TXHDR_0 0x6b100
12417#define _DSI_CMD_TXHDR_1 0x6b900
12418#define DSI_CMD_TXHDR(tc) _MMIO_DSI(tc, \
12419 _DSI_CMD_TXHDR_0,\
12420 _DSI_CMD_TXHDR_1)
12421#define PAYLOAD_PRESENT (1 << 31)
12422#define LP_DATA_TRANSFER (1 << 30)
12423#define VBLANK_FENCE (1 << 29)
12424#define PARAM_WC_MASK (0xffff << 8)
12425#define PARAM_WC_LOWER_SHIFT 8
12426#define PARAM_WC_UPPER_SHIFT 16
12427#define VC_MASK (0x3 << 6)
12428#define VC_SHIFT 6
12429#define DT_MASK (0x3f << 0)
12430#define DT_SHIFT 0
12431
12432#define _DSI_CMD_TXPYLD_0 0x6b104
12433#define _DSI_CMD_TXPYLD_1 0x6b904
12434#define DSI_CMD_TXPYLD(tc) _MMIO_DSI(tc, \
12435 _DSI_CMD_TXPYLD_0,\
12436 _DSI_CMD_TXPYLD_1)
12437
12438#define _DSI_LP_MSG_0 0x6b0d8
12439#define _DSI_LP_MSG_1 0x6b8d8
12440#define DSI_LP_MSG(tc) _MMIO_DSI(tc, \
12441 _DSI_LP_MSG_0,\
12442 _DSI_LP_MSG_1)
12443#define LPTX_IN_PROGRESS (1 << 17)
12444#define LINK_IN_ULPS (1 << 16)
12445#define LINK_ULPS_TYPE_LP11 (1 << 8)
12446#define LINK_ENTER_ULPS (1 << 0)
12447
12448
12449#define _DSI_HSTX_TO_0 0x6b044
12450#define _DSI_HSTX_TO_1 0x6b844
12451#define DSI_HSTX_TO(tc) _MMIO_DSI(tc, \
12452 _DSI_HSTX_TO_0,\
12453 _DSI_HSTX_TO_1)
12454#define HSTX_TIMEOUT_VALUE_MASK (0xffff << 16)
12455#define HSTX_TIMEOUT_VALUE_SHIFT 16
12456#define HSTX_TIMEOUT_VALUE(x) ((x) << 16)
12457#define HSTX_TIMED_OUT (1 << 0)
12458
12459#define _DSI_LPRX_HOST_TO_0 0x6b048
12460#define _DSI_LPRX_HOST_TO_1 0x6b848
12461#define DSI_LPRX_HOST_TO(tc) _MMIO_DSI(tc, \
12462 _DSI_LPRX_HOST_TO_0,\
12463 _DSI_LPRX_HOST_TO_1)
12464#define LPRX_TIMED_OUT (1 << 16)
12465#define LPRX_TIMEOUT_VALUE_MASK (0xffff << 0)
12466#define LPRX_TIMEOUT_VALUE_SHIFT 0
12467#define LPRX_TIMEOUT_VALUE(x) ((x) << 0)
12468
12469#define _DSI_PWAIT_TO_0 0x6b040
12470#define _DSI_PWAIT_TO_1 0x6b840
12471#define DSI_PWAIT_TO(tc) _MMIO_DSI(tc, \
12472 _DSI_PWAIT_TO_0,\
12473 _DSI_PWAIT_TO_1)
12474#define PRESET_TIMEOUT_VALUE_MASK (0xffff << 16)
12475#define PRESET_TIMEOUT_VALUE_SHIFT 16
12476#define PRESET_TIMEOUT_VALUE(x) ((x) << 16)
12477#define PRESPONSE_TIMEOUT_VALUE_MASK (0xffff << 0)
12478#define PRESPONSE_TIMEOUT_VALUE_SHIFT 0
12479#define PRESPONSE_TIMEOUT_VALUE(x) ((x) << 0)
12480
12481#define _DSI_TA_TO_0 0x6b04c
12482#define _DSI_TA_TO_1 0x6b84c
12483#define DSI_TA_TO(tc) _MMIO_DSI(tc, \
12484 _DSI_TA_TO_0,\
12485 _DSI_TA_TO_1)
12486#define TA_TIMED_OUT (1 << 16)
12487#define TA_TIMEOUT_VALUE_MASK (0xffff << 0)
12488#define TA_TIMEOUT_VALUE_SHIFT 0
12489#define TA_TIMEOUT_VALUE(x) ((x) << 0)
12490
12491
12492#define _MIPIA_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb084)
12493#define _MIPIC_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb884)
12494#define MIPI_DBI_BW_CTRL(port) _MMIO_MIPI(port, _MIPIA_DBI_BW_CTRL, _MIPIC_DBI_BW_CTRL)
12495
12496#define _MIPIA_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base + 0xb088)
12497#define _MIPIC_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base + 0xb888)
12498#define MIPI_CLK_LANE_SWITCH_TIME_CNT(port) _MMIO_MIPI(port, _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIC_CLK_LANE_SWITCH_TIME_CNT)
12499#define LP_HS_SSW_CNT_SHIFT 16
12500#define LP_HS_SSW_CNT_MASK (0xffff << 16)
12501#define HS_LP_PWR_SW_CNT_SHIFT 0
12502#define HS_LP_PWR_SW_CNT_MASK (0xffff << 0)
12503
12504#define _MIPIA_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb08c)
12505#define _MIPIC_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb88c)
12506#define MIPI_STOP_STATE_STALL(port) _MMIO_MIPI(port, _MIPIA_STOP_STATE_STALL, _MIPIC_STOP_STATE_STALL)
12507#define STOP_STATE_STALL_COUNTER_SHIFT 0
12508#define STOP_STATE_STALL_COUNTER_MASK (0xff << 0)
12509
12510#define _MIPIA_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb090)
12511#define _MIPIC_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb890)
12512#define MIPI_INTR_STAT_REG_1(port) _MMIO_MIPI(port, _MIPIA_INTR_STAT_REG_1, _MIPIC_INTR_STAT_REG_1)
12513#define _MIPIA_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb094)
12514#define _MIPIC_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb894)
12515#define MIPI_INTR_EN_REG_1(port) _MMIO_MIPI(port, _MIPIA_INTR_EN_REG_1, _MIPIC_INTR_EN_REG_1)
12516#define RX_CONTENTION_DETECTED (1 << 0)
12517
12518
12519#define MIPIA_DBI_TYPEC_CTRL (dev_priv->mipi_mmio_base + 0xb100)
12520#define DBI_TYPEC_ENABLE (1 << 31)
12521#define DBI_TYPEC_WIP (1 << 30)
12522#define DBI_TYPEC_OPTION_SHIFT 28
12523#define DBI_TYPEC_OPTION_MASK (3 << 28)
12524#define DBI_TYPEC_FREQ_SHIFT 24
12525#define DBI_TYPEC_FREQ_MASK (0xf << 24)
12526#define DBI_TYPEC_OVERRIDE (1 << 8)
12527#define DBI_TYPEC_OVERRIDE_COUNTER_SHIFT 0
12528#define DBI_TYPEC_OVERRIDE_COUNTER_MASK (0xff << 0)
12529
12530
12531
12532
12533#define _MIPIA_CTRL (dev_priv->mipi_mmio_base + 0xb104)
12534#define _MIPIC_CTRL (dev_priv->mipi_mmio_base + 0xb904)
12535#define MIPI_CTRL(port) _MMIO_MIPI(port, _MIPIA_CTRL, _MIPIC_CTRL)
12536#define ESCAPE_CLOCK_DIVIDER_SHIFT 5
12537#define ESCAPE_CLOCK_DIVIDER_MASK (3 << 5)
12538#define ESCAPE_CLOCK_DIVIDER_1 (0 << 5)
12539#define ESCAPE_CLOCK_DIVIDER_2 (1 << 5)
12540#define ESCAPE_CLOCK_DIVIDER_4 (2 << 5)
12541#define READ_REQUEST_PRIORITY_SHIFT 3
12542#define READ_REQUEST_PRIORITY_MASK (3 << 3)
12543#define READ_REQUEST_PRIORITY_LOW (0 << 3)
12544#define READ_REQUEST_PRIORITY_HIGH (3 << 3)
12545#define RGB_FLIP_TO_BGR (1 << 2)
12546
12547#define BXT_PIPE_SELECT_SHIFT 7
12548#define BXT_PIPE_SELECT_MASK (7 << 7)
12549#define BXT_PIPE_SELECT(pipe) ((pipe) << 7)
12550#define GLK_PHY_STATUS_PORT_READY (1 << 31)
12551#define GLK_ULPS_NOT_ACTIVE (1 << 30)
12552#define GLK_MIPIIO_RESET_RELEASED (1 << 28)
12553#define GLK_CLOCK_LANE_STOP_STATE (1 << 27)
12554#define GLK_DATA_LANE_STOP_STATE (1 << 26)
12555#define GLK_LP_WAKE (1 << 22)
12556#define GLK_LP11_LOW_PWR_MODE (1 << 21)
12557#define GLK_LP00_LOW_PWR_MODE (1 << 20)
12558#define GLK_FIREWALL_ENABLE (1 << 16)
12559#define BXT_PIXEL_OVERLAP_CNT_MASK (0xf << 10)
12560#define BXT_PIXEL_OVERLAP_CNT_SHIFT 10
12561#define BXT_DSC_ENABLE (1 << 3)
12562#define BXT_RGB_FLIP (1 << 2)
12563#define GLK_MIPIIO_PORT_POWERED (1 << 1)
12564#define GLK_MIPIIO_ENABLE (1 << 0)
12565
12566#define _MIPIA_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb108)
12567#define _MIPIC_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb908)
12568#define MIPI_DATA_ADDRESS(port) _MMIO_MIPI(port, _MIPIA_DATA_ADDRESS, _MIPIC_DATA_ADDRESS)
12569#define DATA_MEM_ADDRESS_SHIFT 5
12570#define DATA_MEM_ADDRESS_MASK (0x7ffffff << 5)
12571#define DATA_VALID (1 << 0)
12572
12573#define _MIPIA_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb10c)
12574#define _MIPIC_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb90c)
12575#define MIPI_DATA_LENGTH(port) _MMIO_MIPI(port, _MIPIA_DATA_LENGTH, _MIPIC_DATA_LENGTH)
12576#define DATA_LENGTH_SHIFT 0
12577#define DATA_LENGTH_MASK (0xfffff << 0)
12578
12579#define _MIPIA_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb110)
12580#define _MIPIC_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb910)
12581#define MIPI_COMMAND_ADDRESS(port) _MMIO_MIPI(port, _MIPIA_COMMAND_ADDRESS, _MIPIC_COMMAND_ADDRESS)
12582#define COMMAND_MEM_ADDRESS_SHIFT 5
12583#define COMMAND_MEM_ADDRESS_MASK (0x7ffffff << 5)
12584#define AUTO_PWG_ENABLE (1 << 2)
12585#define MEMORY_WRITE_DATA_FROM_PIPE_RENDERING (1 << 1)
12586#define COMMAND_VALID (1 << 0)
12587
12588#define _MIPIA_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb114)
12589#define _MIPIC_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb914)
12590#define MIPI_COMMAND_LENGTH(port) _MMIO_MIPI(port, _MIPIA_COMMAND_LENGTH, _MIPIC_COMMAND_LENGTH)
12591#define COMMAND_LENGTH_SHIFT(n) (8 * (n))
12592#define COMMAND_LENGTH_MASK(n) (0xff << (8 * (n)))
12593
12594#define _MIPIA_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb118)
12595#define _MIPIC_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb918)
12596#define MIPI_READ_DATA_RETURN(port, n) _MMIO(_MIPI(port, _MIPIA_READ_DATA_RETURN0, _MIPIC_READ_DATA_RETURN0) + 4 * (n))
12597
12598#define _MIPIA_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb138)
12599#define _MIPIC_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb938)
12600#define MIPI_READ_DATA_VALID(port) _MMIO_MIPI(port, _MIPIA_READ_DATA_VALID, _MIPIC_READ_DATA_VALID)
12601#define READ_DATA_VALID(n) (1 << (n))
12602
12603
12604#define GEN9_LNCFCMOCS(i) _MMIO(0xb020 + (i) * 4)
12605#define GEN9_LNCFCMOCS_REG_COUNT 32
12606
12607#define __GEN9_RCS0_MOCS0 0xc800
12608#define GEN9_GFX_MOCS(i) _MMIO(__GEN9_RCS0_MOCS0 + (i) * 4)
12609#define __GEN9_VCS0_MOCS0 0xc900
12610#define GEN9_MFX0_MOCS(i) _MMIO(__GEN9_VCS0_MOCS0 + (i) * 4)
12611#define __GEN9_VCS1_MOCS0 0xca00
12612#define GEN9_MFX1_MOCS(i) _MMIO(__GEN9_VCS1_MOCS0 + (i) * 4)
12613#define __GEN9_VECS0_MOCS0 0xcb00
12614#define GEN9_VEBOX_MOCS(i) _MMIO(__GEN9_VECS0_MOCS0 + (i) * 4)
12615#define __GEN9_BCS0_MOCS0 0xcc00
12616#define GEN9_BLT_MOCS(i) _MMIO(__GEN9_BCS0_MOCS0 + (i) * 4)
12617#define __GEN11_VCS2_MOCS0 0x10000
12618#define GEN11_MFX2_MOCS(i) _MMIO(__GEN11_VCS2_MOCS0 + (i) * 4)
12619
12620#define GEN9_SCRATCH_LNCF1 _MMIO(0xb008)
12621#define GEN9_LNCF_NONIA_COHERENT_ATOMICS_ENABLE REG_BIT(0)
12622
12623#define GEN9_SCRATCH1 _MMIO(0xb11c)
12624#define EVICTION_PERF_FIX_ENABLE REG_BIT(8)
12625
12626#define GEN10_SCRATCH_LNCF2 _MMIO(0xb0a0)
12627#define PMFLUSHDONE_LNICRSDROP (1 << 20)
12628#define PMFLUSH_GAPL3UNBLOCK (1 << 21)
12629#define PMFLUSHDONE_LNEBLK (1 << 22)
12630
12631#define XEHP_L3NODEARBCFG _MMIO(0xb0b4)
12632#define XEHP_LNESPARE REG_BIT(19)
12633
12634#define GEN12_GLOBAL_MOCS(i) _MMIO(0x4000 + (i) * 4)
12635
12636#define GEN12_GSMBASE _MMIO(0x108100)
12637#define GEN12_DSMBASE _MMIO(0x1080C0)
12638
12639#define XEHP_CLOCK_GATE_DIS _MMIO(0x101014)
12640#define SGSI_SIDECLK_DIS REG_BIT(17)
12641#define SGGI_DIS REG_BIT(15)
12642#define SGR_DIS REG_BIT(13)
12643
12644
12645#define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4)
12646#define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW 0x67F1427F
12647#define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV 0x5FF101FF
12648#define GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL 0x67F1427F
12649#define GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT 0x5FF101FF
12650
12651#define MMCD_MISC_CTRL _MMIO(0x4ddc)
12652#define MMCD_PCLA (1 << 31)
12653#define MMCD_HOTSPOT_EN (1 << 27)
12654
12655#define _ICL_PHY_MISC_A 0x64C00
12656#define _ICL_PHY_MISC_B 0x64C04
12657#define ICL_PHY_MISC(port) _MMIO_PORT(port, _ICL_PHY_MISC_A, \
12658 _ICL_PHY_MISC_B)
12659#define ICL_PHY_MISC_MUX_DDID (1 << 28)
12660#define ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN (1 << 23)
12661#define DG2_PHY_DP_TX_ACK_MASK REG_GENMASK(23, 20)
12662
12663
12664#define DSCA_PICTURE_PARAMETER_SET_0 _MMIO(0x6B200)
12665#define DSCC_PICTURE_PARAMETER_SET_0 _MMIO(0x6BA00)
12666#define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB 0x78270
12667#define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB 0x78370
12668#define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC 0x78470
12669#define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC 0x78570
12670#define ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12671 _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB, \
12672 _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC)
12673#define ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12674 _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \
12675 _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC)
12676#define DSC_VBR_ENABLE (1 << 19)
12677#define DSC_422_ENABLE (1 << 18)
12678#define DSC_COLOR_SPACE_CONVERSION (1 << 17)
12679#define DSC_BLOCK_PREDICTION (1 << 16)
12680#define DSC_LINE_BUF_DEPTH_SHIFT 12
12681#define DSC_BPC_SHIFT 8
12682#define DSC_VER_MIN_SHIFT 4
12683#define DSC_VER_MAJ (0x1 << 0)
12684
12685#define DSCA_PICTURE_PARAMETER_SET_1 _MMIO(0x6B204)
12686#define DSCC_PICTURE_PARAMETER_SET_1 _MMIO(0x6BA04)
12687#define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB 0x78274
12688#define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB 0x78374
12689#define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC 0x78474
12690#define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC 0x78574
12691#define ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12692 _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB, \
12693 _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC)
12694#define ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12695 _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB, \
12696 _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC)
12697#define DSC_BPP(bpp) ((bpp) << 0)
12698
12699#define DSCA_PICTURE_PARAMETER_SET_2 _MMIO(0x6B208)
12700#define DSCC_PICTURE_PARAMETER_SET_2 _MMIO(0x6BA08)
12701#define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB 0x78278
12702#define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB 0x78378
12703#define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC 0x78478
12704#define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PC 0x78578
12705#define ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12706 _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB, \
12707 _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC)
12708#define ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12709 _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB, \
12710 _ICL_DSC1_PICTURE_PARAMETER_SET_2_PC)
12711#define DSC_PIC_WIDTH(pic_width) ((pic_width) << 16)
12712#define DSC_PIC_HEIGHT(pic_height) ((pic_height) << 0)
12713
12714#define DSCA_PICTURE_PARAMETER_SET_3 _MMIO(0x6B20C)
12715#define DSCC_PICTURE_PARAMETER_SET_3 _MMIO(0x6BA0C)
12716#define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB 0x7827C
12717#define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB 0x7837C
12718#define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC 0x7847C
12719#define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PC 0x7857C
12720#define ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12721 _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB, \
12722 _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC)
12723#define ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12724 _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB, \
12725 _ICL_DSC1_PICTURE_PARAMETER_SET_3_PC)
12726#define DSC_SLICE_WIDTH(slice_width) ((slice_width) << 16)
12727#define DSC_SLICE_HEIGHT(slice_height) ((slice_height) << 0)
12728
12729#define DSCA_PICTURE_PARAMETER_SET_4 _MMIO(0x6B210)
12730#define DSCC_PICTURE_PARAMETER_SET_4 _MMIO(0x6BA10)
12731#define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB 0x78280
12732#define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB 0x78380
12733#define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC 0x78480
12734#define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC 0x78580
12735#define ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12736 _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB, \
12737 _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC)
12738#define ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12739 _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB, \
12740 _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC)
12741#define DSC_INITIAL_DEC_DELAY(dec_delay) ((dec_delay) << 16)
12742#define DSC_INITIAL_XMIT_DELAY(xmit_delay) ((xmit_delay) << 0)
12743
12744#define DSCA_PICTURE_PARAMETER_SET_5 _MMIO(0x6B214)
12745#define DSCC_PICTURE_PARAMETER_SET_5 _MMIO(0x6BA14)
12746#define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB 0x78284
12747#define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB 0x78384
12748#define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC 0x78484
12749#define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC 0x78584
12750#define ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12751 _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB, \
12752 _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC)
12753#define ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12754 _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB, \
12755 _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC)
12756#define DSC_SCALE_DEC_INT(scale_dec) ((scale_dec) << 16)
12757#define DSC_SCALE_INC_INT(scale_inc) ((scale_inc) << 0)
12758
12759#define DSCA_PICTURE_PARAMETER_SET_6 _MMIO(0x6B218)
12760#define DSCC_PICTURE_PARAMETER_SET_6 _MMIO(0x6BA18)
12761#define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB 0x78288
12762#define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB 0x78388
12763#define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC 0x78488
12764#define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC 0x78588
12765#define ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12766 _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB, \
12767 _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC)
12768#define ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12769 _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB, \
12770 _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC)
12771#define DSC_FLATNESS_MAX_QP(max_qp) ((max_qp) << 24)
12772#define DSC_FLATNESS_MIN_QP(min_qp) ((min_qp) << 16)
12773#define DSC_FIRST_LINE_BPG_OFFSET(offset) ((offset) << 8)
12774#define DSC_INITIAL_SCALE_VALUE(value) ((value) << 0)
12775
12776#define DSCA_PICTURE_PARAMETER_SET_7 _MMIO(0x6B21C)
12777#define DSCC_PICTURE_PARAMETER_SET_7 _MMIO(0x6BA1C)
12778#define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB 0x7828C
12779#define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB 0x7838C
12780#define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC 0x7848C
12781#define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PC 0x7858C
12782#define ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12783 _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB, \
12784 _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC)
12785#define ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12786 _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB, \
12787 _ICL_DSC1_PICTURE_PARAMETER_SET_7_PC)
12788#define DSC_NFL_BPG_OFFSET(bpg_offset) ((bpg_offset) << 16)
12789#define DSC_SLICE_BPG_OFFSET(bpg_offset) ((bpg_offset) << 0)
12790
12791#define DSCA_PICTURE_PARAMETER_SET_8 _MMIO(0x6B220)
12792#define DSCC_PICTURE_PARAMETER_SET_8 _MMIO(0x6BA20)
12793#define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB 0x78290
12794#define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB 0x78390
12795#define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC 0x78490
12796#define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PC 0x78590
12797#define ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12798 _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB, \
12799 _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC)
12800#define ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12801 _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB, \
12802 _ICL_DSC1_PICTURE_PARAMETER_SET_8_PC)
12803#define DSC_INITIAL_OFFSET(initial_offset) ((initial_offset) << 16)
12804#define DSC_FINAL_OFFSET(final_offset) ((final_offset) << 0)
12805
12806#define DSCA_PICTURE_PARAMETER_SET_9 _MMIO(0x6B224)
12807#define DSCC_PICTURE_PARAMETER_SET_9 _MMIO(0x6BA24)
12808#define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB 0x78294
12809#define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB 0x78394
12810#define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC 0x78494
12811#define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PC 0x78594
12812#define ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12813 _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB, \
12814 _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC)
12815#define ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12816 _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB, \
12817 _ICL_DSC1_PICTURE_PARAMETER_SET_9_PC)
12818#define DSC_RC_EDGE_FACTOR(rc_edge_fact) ((rc_edge_fact) << 16)
12819#define DSC_RC_MODEL_SIZE(rc_model_size) ((rc_model_size) << 0)
12820
12821#define DSCA_PICTURE_PARAMETER_SET_10 _MMIO(0x6B228)
12822#define DSCC_PICTURE_PARAMETER_SET_10 _MMIO(0x6BA28)
12823#define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB 0x78298
12824#define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB 0x78398
12825#define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC 0x78498
12826#define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PC 0x78598
12827#define ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12828 _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB, \
12829 _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC)
12830#define ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12831 _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB, \
12832 _ICL_DSC1_PICTURE_PARAMETER_SET_10_PC)
12833#define DSC_RC_TARGET_OFF_LOW(rc_tgt_off_low) ((rc_tgt_off_low) << 20)
12834#define DSC_RC_TARGET_OFF_HIGH(rc_tgt_off_high) ((rc_tgt_off_high) << 16)
12835#define DSC_RC_QUANT_INC_LIMIT1(lim) ((lim) << 8)
12836#define DSC_RC_QUANT_INC_LIMIT0(lim) ((lim) << 0)
12837
12838#define DSCA_PICTURE_PARAMETER_SET_11 _MMIO(0x6B22C)
12839#define DSCC_PICTURE_PARAMETER_SET_11 _MMIO(0x6BA2C)
12840#define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB 0x7829C
12841#define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB 0x7839C
12842#define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC 0x7849C
12843#define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC 0x7859C
12844#define ICL_DSC0_PICTURE_PARAMETER_SET_11(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12845 _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB, \
12846 _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC)
12847#define ICL_DSC1_PICTURE_PARAMETER_SET_11(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12848 _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB, \
12849 _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC)
12850
12851#define DSCA_PICTURE_PARAMETER_SET_12 _MMIO(0x6B260)
12852#define DSCC_PICTURE_PARAMETER_SET_12 _MMIO(0x6BA60)
12853#define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB 0x782A0
12854#define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB 0x783A0
12855#define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC 0x784A0
12856#define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC 0x785A0
12857#define ICL_DSC0_PICTURE_PARAMETER_SET_12(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12858 _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB, \
12859 _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC)
12860#define ICL_DSC1_PICTURE_PARAMETER_SET_12(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12861 _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB, \
12862 _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC)
12863
12864#define DSCA_PICTURE_PARAMETER_SET_13 _MMIO(0x6B264)
12865#define DSCC_PICTURE_PARAMETER_SET_13 _MMIO(0x6BA64)
12866#define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB 0x782A4
12867#define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB 0x783A4
12868#define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC 0x784A4
12869#define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC 0x785A4
12870#define ICL_DSC0_PICTURE_PARAMETER_SET_13(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12871 _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB, \
12872 _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC)
12873#define ICL_DSC1_PICTURE_PARAMETER_SET_13(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12874 _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB, \
12875 _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC)
12876
12877#define DSCA_PICTURE_PARAMETER_SET_14 _MMIO(0x6B268)
12878#define DSCC_PICTURE_PARAMETER_SET_14 _MMIO(0x6BA68)
12879#define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB 0x782A8
12880#define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB 0x783A8
12881#define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC 0x784A8
12882#define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC 0x785A8
12883#define ICL_DSC0_PICTURE_PARAMETER_SET_14(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12884 _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB, \
12885 _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC)
12886#define ICL_DSC1_PICTURE_PARAMETER_SET_14(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12887 _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB, \
12888 _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC)
12889
12890#define DSCA_PICTURE_PARAMETER_SET_15 _MMIO(0x6B26C)
12891#define DSCC_PICTURE_PARAMETER_SET_15 _MMIO(0x6BA6C)
12892#define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB 0x782AC
12893#define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB 0x783AC
12894#define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC 0x784AC
12895#define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC 0x785AC
12896#define ICL_DSC0_PICTURE_PARAMETER_SET_15(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12897 _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB, \
12898 _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC)
12899#define ICL_DSC1_PICTURE_PARAMETER_SET_15(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12900 _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB, \
12901 _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC)
12902
12903#define DSCA_PICTURE_PARAMETER_SET_16 _MMIO(0x6B270)
12904#define DSCC_PICTURE_PARAMETER_SET_16 _MMIO(0x6BA70)
12905#define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB 0x782B0
12906#define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB 0x783B0
12907#define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC 0x784B0
12908#define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC 0x785B0
12909#define ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12910 _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB, \
12911 _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC)
12912#define ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12913 _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB, \
12914 _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC)
12915#define DSC_SLICE_ROW_PER_FRAME(slice_row_per_frame) ((slice_row_per_frame) << 20)
12916#define DSC_SLICE_PER_LINE(slice_per_line) ((slice_per_line) << 16)
12917#define DSC_SLICE_CHUNK_SIZE(slice_chunk_size) ((slice_chunk_size) << 0)
12918
12919
12920#define DSCA_RC_BUF_THRESH_0 _MMIO(0x6B230)
12921#define DSCA_RC_BUF_THRESH_0_UDW _MMIO(0x6B230 + 4)
12922#define DSCC_RC_BUF_THRESH_0 _MMIO(0x6BA30)
12923#define DSCC_RC_BUF_THRESH_0_UDW _MMIO(0x6BA30 + 4)
12924#define _ICL_DSC0_RC_BUF_THRESH_0_PB (0x78254)
12925#define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PB (0x78254 + 4)
12926#define _ICL_DSC1_RC_BUF_THRESH_0_PB (0x78354)
12927#define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PB (0x78354 + 4)
12928#define _ICL_DSC0_RC_BUF_THRESH_0_PC (0x78454)
12929#define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PC (0x78454 + 4)
12930#define _ICL_DSC1_RC_BUF_THRESH_0_PC (0x78554)
12931#define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PC (0x78554 + 4)
12932#define ICL_DSC0_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12933 _ICL_DSC0_RC_BUF_THRESH_0_PB, \
12934 _ICL_DSC0_RC_BUF_THRESH_0_PC)
12935#define ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12936 _ICL_DSC0_RC_BUF_THRESH_0_UDW_PB, \
12937 _ICL_DSC0_RC_BUF_THRESH_0_UDW_PC)
12938#define ICL_DSC1_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12939 _ICL_DSC1_RC_BUF_THRESH_0_PB, \
12940 _ICL_DSC1_RC_BUF_THRESH_0_PC)
12941#define ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12942 _ICL_DSC1_RC_BUF_THRESH_0_UDW_PB, \
12943 _ICL_DSC1_RC_BUF_THRESH_0_UDW_PC)
12944
12945#define DSCA_RC_BUF_THRESH_1 _MMIO(0x6B238)
12946#define DSCA_RC_BUF_THRESH_1_UDW _MMIO(0x6B238 + 4)
12947#define DSCC_RC_BUF_THRESH_1 _MMIO(0x6BA38)
12948#define DSCC_RC_BUF_THRESH_1_UDW _MMIO(0x6BA38 + 4)
12949#define _ICL_DSC0_RC_BUF_THRESH_1_PB (0x7825C)
12950#define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PB (0x7825C + 4)
12951#define _ICL_DSC1_RC_BUF_THRESH_1_PB (0x7835C)
12952#define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB (0x7835C + 4)
12953#define _ICL_DSC0_RC_BUF_THRESH_1_PC (0x7845C)
12954#define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PC (0x7845C + 4)
12955#define _ICL_DSC1_RC_BUF_THRESH_1_PC (0x7855C)
12956#define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC (0x7855C + 4)
12957#define ICL_DSC0_RC_BUF_THRESH_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12958 _ICL_DSC0_RC_BUF_THRESH_1_PB, \
12959 _ICL_DSC0_RC_BUF_THRESH_1_PC)
12960#define ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12961 _ICL_DSC0_RC_BUF_THRESH_1_UDW_PB, \
12962 _ICL_DSC0_RC_BUF_THRESH_1_UDW_PC)
12963#define ICL_DSC1_RC_BUF_THRESH_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12964 _ICL_DSC1_RC_BUF_THRESH_1_PB, \
12965 _ICL_DSC1_RC_BUF_THRESH_1_PC)
12966#define ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12967 _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB, \
12968 _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC)
12969
12970#define PORT_TX_DFLEXDPSP(fia) _MMIO_FIA((fia), 0x008A0)
12971#define MODULAR_FIA_MASK (1 << 4)
12972#define TC_LIVE_STATE_TBT(idx) (1 << ((idx) * 8 + 6))
12973#define TC_LIVE_STATE_TC(idx) (1 << ((idx) * 8 + 5))
12974#define DP_LANE_ASSIGNMENT_SHIFT(idx) ((idx) * 8)
12975#define DP_LANE_ASSIGNMENT_MASK(idx) (0xf << ((idx) * 8))
12976#define DP_LANE_ASSIGNMENT(idx, x) ((x) << ((idx) * 8))
12977
12978#define PORT_TX_DFLEXDPPMS(fia) _MMIO_FIA((fia), 0x00890)
12979#define DP_PHY_MODE_STATUS_COMPLETED(idx) (1 << (idx))
12980
12981#define PORT_TX_DFLEXDPCSSS(fia) _MMIO_FIA((fia), 0x00894)
12982#define DP_PHY_MODE_STATUS_NOT_SAFE(idx) (1 << (idx))
12983
12984#define PORT_TX_DFLEXPA1(fia) _MMIO_FIA((fia), 0x00880)
12985#define DP_PIN_ASSIGNMENT_SHIFT(idx) ((idx) * 4)
12986#define DP_PIN_ASSIGNMENT_MASK(idx) (0xf << ((idx) * 4))
12987#define DP_PIN_ASSIGNMENT(idx, x) ((x) << ((idx) * 4))
12988
12989#define _TCSS_DDI_STATUS_1 0x161500
12990#define _TCSS_DDI_STATUS_2 0x161504
12991#define TCSS_DDI_STATUS(tc) _MMIO(_PICK_EVEN(tc, \
12992 _TCSS_DDI_STATUS_1, \
12993 _TCSS_DDI_STATUS_2))
12994#define TCSS_DDI_STATUS_READY REG_BIT(2)
12995#define TCSS_DDI_STATUS_HPD_LIVE_STATUS_TBT REG_BIT(1)
12996#define TCSS_DDI_STATUS_HPD_LIVE_STATUS_ALT REG_BIT(0)
12997
12998
12999#define _DSBSL_INSTANCE_BASE 0x70B00
13000#define DSBSL_INSTANCE(pipe, id) (_DSBSL_INSTANCE_BASE + \
13001 (pipe) * 0x1000 + (id) * 0x100)
13002#define DSB_HEAD(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x0)
13003#define DSB_TAIL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x4)
13004#define DSB_CTRL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x8)
13005#define DSB_ENABLE (1 << 31)
13006#define DSB_STATUS (1 << 0)
13007
13008#define TGL_ROOT_DEVICE_ID 0x9A00
13009#define TGL_ROOT_DEVICE_MASK 0xFF00
13010#define TGL_ROOT_DEVICE_SKU_MASK 0xF
13011#define TGL_ROOT_DEVICE_SKU_ULX 0x2
13012#define TGL_ROOT_DEVICE_SKU_ULT 0x4
13013
13014#define CLKREQ_POLICY _MMIO(0x101038)
13015#define CLKREQ_POLICY_MEM_UP_OVRD REG_BIT(1)
13016
13017#define CLKGATE_DIS_MISC _MMIO(0x46534)
13018#define CLKGATE_DIS_MISC_DMASC_GATING_DIS REG_BIT(21)
13019
13020#define SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731C)
13021#define MSC_MSAA_REODER_BUF_BYPASS_DISABLE REG_BIT(14)
13022
13023#endif
13024