LXR linux/drivers/gpu/drm/msm/disp/mdp5/mdp5

   1/* SPDX-License-Identifier: GPL-2.0-only */
   2/*
   3 * Copyright (c) 2014 The Linux Foundation. All rights reserved.
   4 */
   5
   6#ifndef __MDP5_CFG_H__
   7#define __MDP5_CFG_H__
   8
   9#include "msm_drv.h"
  10
  11/*
  12 * mdp5_cfg
  13 *
  14 * This module configures the dynamic offsets used by mdp5.xml.h
  15 * (initialized in mdp5_cfg.c)
  16 */
  17extern const struct mdp5_cfg_hw *mdp5_cfg;
  18
  19#define MAX_CTL                 8
  20#define MAX_BASES               8
  21#define MAX_SMP_BLOCKS          44
  22#define MAX_CLIENTS             32
  23
  24typedef DECLARE_BITMAP(mdp5_smp_state_t, MAX_SMP_BLOCKS);
  25
  26#define MDP5_SUB_BLOCK_DEFINITION \
  27        unsigned int count; \
  28        uint32_t base[MAX_BASES]
  29
  30struct mdp5_sub_block {
  31        MDP5_SUB_BLOCK_DEFINITION;
  32};
  33
  34struct mdp5_lm_instance {
  35        int id;
  36        int pp;
  37        int dspp;
  38        uint32_t caps;
  39};
  40
  41struct mdp5_lm_block {
  42        MDP5_SUB_BLOCK_DEFINITION;
  43        struct mdp5_lm_instance instances[MAX_BASES];
  44        uint32_t nb_stages;             /* number of stages per blender */
  45        uint32_t max_width;             /* Maximum output resolution */
  46        uint32_t max_height;
  47};
  48
  49struct mdp5_pipe_block {
  50        MDP5_SUB_BLOCK_DEFINITION;
  51        uint32_t caps;                  /* pipe capabilities */
  52};
  53
  54struct mdp5_ctl_block {
  55        MDP5_SUB_BLOCK_DEFINITION;
  56        uint32_t flush_hw_mask;         /* FLUSH register's hardware mask */
  57};
  58
  59struct mdp5_smp_block {
  60        int mmb_count;                  /* number of SMP MMBs */
  61        int mmb_size;                   /* MMB: size in bytes */
  62        uint32_t clients[MAX_CLIENTS];  /* SMP port allocation /pipe */
  63        mdp5_smp_state_t reserved_state;/* SMP MMBs statically allocated */
  64        uint8_t reserved[MAX_CLIENTS];  /* # of MMBs allocated per client */
  65};
  66
  67struct mdp5_mdp_block {
  68        MDP5_SUB_BLOCK_DEFINITION;
  69        uint32_t caps;                  /* MDP capabilities: MDP_CAP_xxx bits */
  70};
  71
  72#define MDP5_INTF_NUM_MAX       5
  73
  74struct mdp5_intf_block {
  75        uint32_t base[MAX_BASES];
  76        u32 connect[MDP5_INTF_NUM_MAX]; /* array of enum mdp5_intf_type */
  77};
  78
  79struct mdp5_perf_block {
  80        u32 ab_inefficiency;
  81        u32 ib_inefficiency;
  82        u32 clk_inefficiency;
  83};
  84
  85struct mdp5_cfg_hw {
  86        char  *name;
  87
  88        struct mdp5_mdp_block mdp;
  89        struct mdp5_smp_block smp;
  90        struct mdp5_ctl_block ctl;
  91        struct mdp5_pipe_block pipe_vig;
  92        struct mdp5_pipe_block pipe_rgb;
  93        struct mdp5_pipe_block pipe_dma;
  94        struct mdp5_pipe_block pipe_cursor;
  95        struct mdp5_lm_block  lm;
  96        struct mdp5_sub_block dspp;
  97        struct mdp5_sub_block ad;
  98        struct mdp5_sub_block pp;
  99        struct mdp5_sub_block dsc;
 100        struct mdp5_sub_block cdm;
 101        struct mdp5_intf_block intf;
 102        struct mdp5_perf_block perf;
 103
 104        uint32_t max_clk;
 105};
 106
 107/* platform config data (ie. from DT, or pdata) */
 108struct mdp5_cfg_platform {
 109        struct iommu_domain *iommu;
 110};
 111
 112struct mdp5_cfg {
 113        const struct mdp5_cfg_hw *hw;
 114        struct mdp5_cfg_platform platform;
 115};
 116
 117struct mdp5_kms;
 118struct mdp5_cfg_handler;
 119
 120const struct mdp5_cfg_hw *mdp5_cfg_get_hw_config(struct mdp5_cfg_handler *cfg_hnd);
 121struct mdp5_cfg *mdp5_cfg_get_config(struct mdp5_cfg_handler *cfg_hnd);
 122int mdp5_cfg_get_hw_rev(struct mdp5_cfg_handler *cfg_hnd);
 123
 124#define mdp5_cfg_intf_is_virtual(intf_type) ({  \
 125        typeof(intf_type) __val = (intf_type);  \
 126        (__val) >= INTF_VIRTUAL ? true : false; })
 127
 128struct mdp5_cfg_handler *mdp5_cfg_init(struct mdp5_kms *mdp5_kms,
 129                uint32_t major, uint32_t minor);
 130void mdp5_cfg_destroy(struct mdp5_cfg_handler *cfg_hnd);
 131
 132#endif /* __MDP5_CFG_H__ */
 133