LXR linux/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv10.c

   1/*
   2 * Copyright 2012 Red Hat Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 * Authors: Ben Skeggs
  23 */
  24#include "nv04.h"
  25#include "channv04.h"
  26#include "regsnv04.h"
  27
  28static const struct nv04_fifo_ramfc
  29nv10_fifo_ramfc[] = {
  30        { 32,  0, 0x00,  0, NV04_PFIFO_CACHE1_DMA_PUT },
  31        { 32,  0, 0x04,  0, NV04_PFIFO_CACHE1_DMA_GET },
  32        { 32,  0, 0x08,  0, NV10_PFIFO_CACHE1_REF_CNT },
  33        { 16,  0, 0x0c,  0, NV04_PFIFO_CACHE1_DMA_INSTANCE },
  34        { 16, 16, 0x0c,  0, NV04_PFIFO_CACHE1_DMA_DCOUNT },
  35        { 32,  0, 0x10,  0, NV04_PFIFO_CACHE1_DMA_STATE },
  36        { 32,  0, 0x14,  0, NV04_PFIFO_CACHE1_DMA_FETCH },
  37        { 32,  0, 0x18,  0, NV04_PFIFO_CACHE1_ENGINE },
  38        { 32,  0, 0x1c,  0, NV04_PFIFO_CACHE1_PULL1 },
  39        {}
  40};
  41
  42static const struct nvkm_fifo_func
  43nv10_fifo = {
  44        .init = nv04_fifo_init,
  45        .intr = nv04_fifo_intr,
  46        .engine_id = nv04_fifo_engine_id,
  47        .id_engine = nv04_fifo_id_engine,
  48        .pause = nv04_fifo_pause,
  49        .start = nv04_fifo_start,
  50        .chan = {
  51                &nv10_fifo_dma_oclass,
  52                NULL
  53        },
  54};
  55
  56int
  57nv10_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
  58              struct nvkm_fifo **pfifo)
  59{
  60        return nv04_fifo_new_(&nv10_fifo, device, type, inst, 32, nv10_fifo_ramfc, pfifo);
  61}
  62