linux/drivers/gpu/drm/rockchip/inno_hdmi.c
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   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
   4 *    Zheng Yang <zhengyang@rock-chips.com>
   5 *    Yakir Yang <ykk@rock-chips.com>
   6 */
   7
   8#include <linux/irq.h>
   9#include <linux/clk.h>
  10#include <linux/delay.h>
  11#include <linux/err.h>
  12#include <linux/hdmi.h>
  13#include <linux/mfd/syscon.h>
  14#include <linux/module.h>
  15#include <linux/mutex.h>
  16#include <linux/of_device.h>
  17
  18#include <drm/drm_atomic_helper.h>
  19#include <drm/drm_edid.h>
  20#include <drm/drm_of.h>
  21#include <drm/drm_probe_helper.h>
  22#include <drm/drm_simple_kms_helper.h>
  23
  24#include "rockchip_drm_drv.h"
  25#include "rockchip_drm_vop.h"
  26
  27#include "inno_hdmi.h"
  28
  29#define to_inno_hdmi(x) container_of(x, struct inno_hdmi, x)
  30
  31struct hdmi_data_info {
  32        int vic;
  33        bool sink_is_hdmi;
  34        bool sink_has_audio;
  35        unsigned int enc_in_format;
  36        unsigned int enc_out_format;
  37        unsigned int colorimetry;
  38};
  39
  40struct inno_hdmi_i2c {
  41        struct i2c_adapter adap;
  42
  43        u8 ddc_addr;
  44        u8 segment_addr;
  45
  46        struct mutex lock;
  47        struct completion cmp;
  48};
  49
  50struct inno_hdmi {
  51        struct device *dev;
  52        struct drm_device *drm_dev;
  53
  54        int irq;
  55        struct clk *pclk;
  56        void __iomem *regs;
  57
  58        struct drm_connector    connector;
  59        struct drm_encoder      encoder;
  60
  61        struct inno_hdmi_i2c *i2c;
  62        struct i2c_adapter *ddc;
  63
  64        unsigned int tmds_rate;
  65
  66        struct hdmi_data_info   hdmi_data;
  67        struct drm_display_mode previous_mode;
  68};
  69
  70enum {
  71        CSC_ITU601_16_235_TO_RGB_0_255_8BIT,
  72        CSC_ITU601_0_255_TO_RGB_0_255_8BIT,
  73        CSC_ITU709_16_235_TO_RGB_0_255_8BIT,
  74        CSC_RGB_0_255_TO_ITU601_16_235_8BIT,
  75        CSC_RGB_0_255_TO_ITU709_16_235_8BIT,
  76        CSC_RGB_0_255_TO_RGB_16_235_8BIT,
  77};
  78
  79static const char coeff_csc[][24] = {
  80        /*
  81         * YUV2RGB:601 SD mode(Y[16:235], UV[16:240], RGB[0:255]):
  82         *   R = 1.164*Y + 1.596*V - 204
  83         *   G = 1.164*Y - 0.391*U - 0.813*V + 154
  84         *   B = 1.164*Y + 2.018*U - 258
  85         */
  86        {
  87                0x04, 0xa7, 0x00, 0x00, 0x06, 0x62, 0x02, 0xcc,
  88                0x04, 0xa7, 0x11, 0x90, 0x13, 0x40, 0x00, 0x9a,
  89                0x04, 0xa7, 0x08, 0x12, 0x00, 0x00, 0x03, 0x02
  90        },
  91        /*
  92         * YUV2RGB:601 SD mode(YUV[0:255],RGB[0:255]):
  93         *   R = Y + 1.402*V - 248
  94         *   G = Y - 0.344*U - 0.714*V + 135
  95         *   B = Y + 1.772*U - 227
  96         */
  97        {
  98                0x04, 0x00, 0x00, 0x00, 0x05, 0x9b, 0x02, 0xf8,
  99                0x04, 0x00, 0x11, 0x60, 0x12, 0xdb, 0x00, 0x87,
 100                0x04, 0x00, 0x07, 0x16, 0x00, 0x00, 0x02, 0xe3
 101        },
 102        /*
 103         * YUV2RGB:709 HD mode(Y[16:235],UV[16:240],RGB[0:255]):
 104         *   R = 1.164*Y + 1.793*V - 248
 105         *   G = 1.164*Y - 0.213*U - 0.534*V + 77
 106         *   B = 1.164*Y + 2.115*U - 289
 107         */
 108        {
 109                0x04, 0xa7, 0x00, 0x00, 0x07, 0x2c, 0x02, 0xf8,
 110                0x04, 0xa7, 0x10, 0xda, 0x12, 0x22, 0x00, 0x4d,
 111                0x04, 0xa7, 0x08, 0x74, 0x00, 0x00, 0x03, 0x21
 112        },
 113
 114        /*
 115         * RGB2YUV:601 SD mode:
 116         *   Cb = -0.291G - 0.148R + 0.439B + 128
 117         *   Y  = 0.504G  + 0.257R + 0.098B + 16
 118         *   Cr = -0.368G + 0.439R - 0.071B + 128
 119         */
 120        {
 121                0x11, 0x5f, 0x01, 0x82, 0x10, 0x23, 0x00, 0x80,
 122                0x02, 0x1c, 0x00, 0xa1, 0x00, 0x36, 0x00, 0x1e,
 123                0x11, 0x29, 0x10, 0x59, 0x01, 0x82, 0x00, 0x80
 124        },
 125        /*
 126         * RGB2YUV:709 HD mode:
 127         *   Cb = - 0.338G - 0.101R + 0.439B + 128
 128         *   Y  = 0.614G   + 0.183R + 0.062B + 16
 129         *   Cr = - 0.399G + 0.439R - 0.040B + 128
 130         */
 131        {
 132                0x11, 0x98, 0x01, 0xc1, 0x10, 0x28, 0x00, 0x80,
 133                0x02, 0x74, 0x00, 0xbb, 0x00, 0x3f, 0x00, 0x10,
 134                0x11, 0x5a, 0x10, 0x67, 0x01, 0xc1, 0x00, 0x80
 135        },
 136        /*
 137         * RGB[0:255]2RGB[16:235]:
 138         *   R' = R x (235-16)/255 + 16;
 139         *   G' = G x (235-16)/255 + 16;
 140         *   B' = B x (235-16)/255 + 16;
 141         */
 142        {
 143                0x00, 0x00, 0x03, 0x6F, 0x00, 0x00, 0x00, 0x10,
 144                0x03, 0x6F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
 145                0x00, 0x00, 0x00, 0x00, 0x03, 0x6F, 0x00, 0x10
 146        },
 147};
 148
 149static inline u8 hdmi_readb(struct inno_hdmi *hdmi, u16 offset)
 150{
 151        return readl_relaxed(hdmi->regs + (offset) * 0x04);
 152}
 153
 154static inline void hdmi_writeb(struct inno_hdmi *hdmi, u16 offset, u32 val)
 155{
 156        writel_relaxed(val, hdmi->regs + (offset) * 0x04);
 157}
 158
 159static inline void hdmi_modb(struct inno_hdmi *hdmi, u16 offset,
 160                             u32 msk, u32 val)
 161{
 162        u8 temp = hdmi_readb(hdmi, offset) & ~msk;
 163
 164        temp |= val & msk;
 165        hdmi_writeb(hdmi, offset, temp);
 166}
 167
 168static void inno_hdmi_i2c_init(struct inno_hdmi *hdmi)
 169{
 170        int ddc_bus_freq;
 171
 172        ddc_bus_freq = (hdmi->tmds_rate >> 2) / HDMI_SCL_RATE;
 173
 174        hdmi_writeb(hdmi, DDC_BUS_FREQ_L, ddc_bus_freq & 0xFF);
 175        hdmi_writeb(hdmi, DDC_BUS_FREQ_H, (ddc_bus_freq >> 8) & 0xFF);
 176
 177        /* Clear the EDID interrupt flag and mute the interrupt */
 178        hdmi_writeb(hdmi, HDMI_INTERRUPT_MASK1, 0);
 179        hdmi_writeb(hdmi, HDMI_INTERRUPT_STATUS1, m_INT_EDID_READY);
 180}
 181
 182static void inno_hdmi_sys_power(struct inno_hdmi *hdmi, bool enable)
 183{
 184        if (enable)
 185                hdmi_modb(hdmi, HDMI_SYS_CTRL, m_POWER, v_PWR_ON);
 186        else
 187                hdmi_modb(hdmi, HDMI_SYS_CTRL, m_POWER, v_PWR_OFF);
 188}
 189
 190static void inno_hdmi_set_pwr_mode(struct inno_hdmi *hdmi, int mode)
 191{
 192        switch (mode) {
 193        case NORMAL:
 194                inno_hdmi_sys_power(hdmi, false);
 195
 196                hdmi_writeb(hdmi, HDMI_PHY_PRE_EMPHASIS, 0x6f);
 197                hdmi_writeb(hdmi, HDMI_PHY_DRIVER, 0xbb);
 198
 199                hdmi_writeb(hdmi, HDMI_PHY_SYS_CTL, 0x15);
 200                hdmi_writeb(hdmi, HDMI_PHY_SYS_CTL, 0x14);
 201                hdmi_writeb(hdmi, HDMI_PHY_SYS_CTL, 0x10);
 202                hdmi_writeb(hdmi, HDMI_PHY_CHG_PWR, 0x0f);
 203                hdmi_writeb(hdmi, HDMI_PHY_SYNC, 0x00);
 204                hdmi_writeb(hdmi, HDMI_PHY_SYNC, 0x01);
 205
 206                inno_hdmi_sys_power(hdmi, true);
 207                break;
 208
 209        case LOWER_PWR:
 210                inno_hdmi_sys_power(hdmi, false);
 211                hdmi_writeb(hdmi, HDMI_PHY_DRIVER, 0x00);
 212                hdmi_writeb(hdmi, HDMI_PHY_PRE_EMPHASIS, 0x00);
 213                hdmi_writeb(hdmi, HDMI_PHY_CHG_PWR, 0x00);
 214                hdmi_writeb(hdmi, HDMI_PHY_SYS_CTL, 0x15);
 215
 216                break;
 217
 218        default:
 219                DRM_DEV_ERROR(hdmi->dev, "Unknown power mode %d\n", mode);
 220        }
 221}
 222
 223static void inno_hdmi_reset(struct inno_hdmi *hdmi)
 224{
 225        u32 val;
 226        u32 msk;
 227
 228        hdmi_modb(hdmi, HDMI_SYS_CTRL, m_RST_DIGITAL, v_NOT_RST_DIGITAL);
 229        udelay(100);
 230
 231        hdmi_modb(hdmi, HDMI_SYS_CTRL, m_RST_ANALOG, v_NOT_RST_ANALOG);
 232        udelay(100);
 233
 234        msk = m_REG_CLK_INV | m_REG_CLK_SOURCE | m_POWER | m_INT_POL;
 235        val = v_REG_CLK_INV | v_REG_CLK_SOURCE_SYS | v_PWR_ON | v_INT_POL_HIGH;
 236        hdmi_modb(hdmi, HDMI_SYS_CTRL, msk, val);
 237
 238        inno_hdmi_set_pwr_mode(hdmi, NORMAL);
 239}
 240
 241static int inno_hdmi_upload_frame(struct inno_hdmi *hdmi, int setup_rc,
 242                                  union hdmi_infoframe *frame, u32 frame_index,
 243                                  u32 mask, u32 disable, u32 enable)
 244{
 245        if (mask)
 246                hdmi_modb(hdmi, HDMI_PACKET_SEND_AUTO, mask, disable);
 247
 248        hdmi_writeb(hdmi, HDMI_CONTROL_PACKET_BUF_INDEX, frame_index);
 249
 250        if (setup_rc >= 0) {
 251                u8 packed_frame[HDMI_MAXIMUM_INFO_FRAME_SIZE];
 252                ssize_t rc, i;
 253
 254                rc = hdmi_infoframe_pack(frame, packed_frame,
 255                                         sizeof(packed_frame));
 256                if (rc < 0)
 257                        return rc;
 258
 259                for (i = 0; i < rc; i++)
 260                        hdmi_writeb(hdmi, HDMI_CONTROL_PACKET_ADDR + i,
 261                                    packed_frame[i]);
 262
 263                if (mask)
 264                        hdmi_modb(hdmi, HDMI_PACKET_SEND_AUTO, mask, enable);
 265        }
 266
 267        return setup_rc;
 268}
 269
 270static int inno_hdmi_config_video_vsi(struct inno_hdmi *hdmi,
 271                                      struct drm_display_mode *mode)
 272{
 273        union hdmi_infoframe frame;
 274        int rc;
 275
 276        rc = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi,
 277                                                         &hdmi->connector,
 278                                                         mode);
 279
 280        return inno_hdmi_upload_frame(hdmi, rc, &frame, INFOFRAME_VSI,
 281                m_PACKET_VSI_EN, v_PACKET_VSI_EN(0), v_PACKET_VSI_EN(1));
 282}
 283
 284static int inno_hdmi_config_video_avi(struct inno_hdmi *hdmi,
 285                                      struct drm_display_mode *mode)
 286{
 287        union hdmi_infoframe frame;
 288        int rc;
 289
 290        rc = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
 291                                                      &hdmi->connector,
 292                                                      mode);
 293
 294        if (hdmi->hdmi_data.enc_out_format == HDMI_COLORSPACE_YUV444)
 295                frame.avi.colorspace = HDMI_COLORSPACE_YUV444;
 296        else if (hdmi->hdmi_data.enc_out_format == HDMI_COLORSPACE_YUV422)
 297                frame.avi.colorspace = HDMI_COLORSPACE_YUV422;
 298        else
 299                frame.avi.colorspace = HDMI_COLORSPACE_RGB;
 300
 301        return inno_hdmi_upload_frame(hdmi, rc, &frame, INFOFRAME_AVI, 0, 0, 0);
 302}
 303
 304static int inno_hdmi_config_video_csc(struct inno_hdmi *hdmi)
 305{
 306        struct hdmi_data_info *data = &hdmi->hdmi_data;
 307        int c0_c2_change = 0;
 308        int csc_enable = 0;
 309        int csc_mode = 0;
 310        int auto_csc = 0;
 311        int value;
 312        int i;
 313
 314        /* Input video mode is SDR RGB24bit, data enable signal from external */
 315        hdmi_writeb(hdmi, HDMI_VIDEO_CONTRL1, v_DE_EXTERNAL |
 316                    v_VIDEO_INPUT_FORMAT(VIDEO_INPUT_SDR_RGB444));
 317
 318        /* Input color hardcode to RGB, and output color hardcode to RGB888 */
 319        value = v_VIDEO_INPUT_BITS(VIDEO_INPUT_8BITS) |
 320                v_VIDEO_OUTPUT_COLOR(0) |
 321                v_VIDEO_INPUT_CSP(0);
 322        hdmi_writeb(hdmi, HDMI_VIDEO_CONTRL2, value);
 323
 324        if (data->enc_in_format == data->enc_out_format) {
 325                if ((data->enc_in_format == HDMI_COLORSPACE_RGB) ||
 326                    (data->enc_in_format >= HDMI_COLORSPACE_YUV444)) {
 327                        value = v_SOF_DISABLE | v_COLOR_DEPTH_NOT_INDICATED(1);
 328                        hdmi_writeb(hdmi, HDMI_VIDEO_CONTRL3, value);
 329
 330                        hdmi_modb(hdmi, HDMI_VIDEO_CONTRL,
 331                                  m_VIDEO_AUTO_CSC | m_VIDEO_C0_C2_SWAP,
 332                                  v_VIDEO_AUTO_CSC(AUTO_CSC_DISABLE) |
 333                                  v_VIDEO_C0_C2_SWAP(C0_C2_CHANGE_DISABLE));
 334                        return 0;
 335                }
 336        }
 337
 338        if (data->colorimetry == HDMI_COLORIMETRY_ITU_601) {
 339                if ((data->enc_in_format == HDMI_COLORSPACE_RGB) &&
 340                    (data->enc_out_format == HDMI_COLORSPACE_YUV444)) {
 341                        csc_mode = CSC_RGB_0_255_TO_ITU601_16_235_8BIT;
 342                        auto_csc = AUTO_CSC_DISABLE;
 343                        c0_c2_change = C0_C2_CHANGE_DISABLE;
 344                        csc_enable = v_CSC_ENABLE;
 345                } else if ((data->enc_in_format == HDMI_COLORSPACE_YUV444) &&
 346                           (data->enc_out_format == HDMI_COLORSPACE_RGB)) {
 347                        csc_mode = CSC_ITU601_16_235_TO_RGB_0_255_8BIT;
 348                        auto_csc = AUTO_CSC_ENABLE;
 349                        c0_c2_change = C0_C2_CHANGE_DISABLE;
 350                        csc_enable = v_CSC_DISABLE;
 351                }
 352        } else {
 353                if ((data->enc_in_format == HDMI_COLORSPACE_RGB) &&
 354                    (data->enc_out_format == HDMI_COLORSPACE_YUV444)) {
 355                        csc_mode = CSC_RGB_0_255_TO_ITU709_16_235_8BIT;
 356                        auto_csc = AUTO_CSC_DISABLE;
 357                        c0_c2_change = C0_C2_CHANGE_DISABLE;
 358                        csc_enable = v_CSC_ENABLE;
 359                } else if ((data->enc_in_format == HDMI_COLORSPACE_YUV444) &&
 360                           (data->enc_out_format == HDMI_COLORSPACE_RGB)) {
 361                        csc_mode = CSC_ITU709_16_235_TO_RGB_0_255_8BIT;
 362                        auto_csc = AUTO_CSC_ENABLE;
 363                        c0_c2_change = C0_C2_CHANGE_DISABLE;
 364                        csc_enable = v_CSC_DISABLE;
 365                }
 366        }
 367
 368        for (i = 0; i < 24; i++)
 369                hdmi_writeb(hdmi, HDMI_VIDEO_CSC_COEF + i,
 370                            coeff_csc[csc_mode][i]);
 371
 372        value = v_SOF_DISABLE | csc_enable | v_COLOR_DEPTH_NOT_INDICATED(1);
 373        hdmi_writeb(hdmi, HDMI_VIDEO_CONTRL3, value);
 374        hdmi_modb(hdmi, HDMI_VIDEO_CONTRL, m_VIDEO_AUTO_CSC |
 375                  m_VIDEO_C0_C2_SWAP, v_VIDEO_AUTO_CSC(auto_csc) |
 376                  v_VIDEO_C0_C2_SWAP(c0_c2_change));
 377
 378        return 0;
 379}
 380
 381static int inno_hdmi_config_video_timing(struct inno_hdmi *hdmi,
 382                                         struct drm_display_mode *mode)
 383{
 384        int value;
 385
 386        /* Set detail external video timing polarity and interlace mode */
 387        value = v_EXTERANL_VIDEO(1);
 388        value |= mode->flags & DRM_MODE_FLAG_PHSYNC ?
 389                 v_HSYNC_POLARITY(1) : v_HSYNC_POLARITY(0);
 390        value |= mode->flags & DRM_MODE_FLAG_PVSYNC ?
 391                 v_VSYNC_POLARITY(1) : v_VSYNC_POLARITY(0);
 392        value |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
 393                 v_INETLACE(1) : v_INETLACE(0);
 394        hdmi_writeb(hdmi, HDMI_VIDEO_TIMING_CTL, value);
 395
 396        /* Set detail external video timing */
 397        value = mode->htotal;
 398        hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HTOTAL_L, value & 0xFF);
 399        hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HTOTAL_H, (value >> 8) & 0xFF);
 400
 401        value = mode->htotal - mode->hdisplay;
 402        hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HBLANK_L, value & 0xFF);
 403        hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HBLANK_H, (value >> 8) & 0xFF);
 404
 405        value = mode->hsync_start - mode->hdisplay;
 406        hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HDELAY_L, value & 0xFF);
 407        hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HDELAY_H, (value >> 8) & 0xFF);
 408
 409        value = mode->hsync_end - mode->hsync_start;
 410        hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HDURATION_L, value & 0xFF);
 411        hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HDURATION_H, (value >> 8) & 0xFF);
 412
 413        value = mode->vtotal;
 414        hdmi_writeb(hdmi, HDMI_VIDEO_EXT_VTOTAL_L, value & 0xFF);
 415        hdmi_writeb(hdmi, HDMI_VIDEO_EXT_VTOTAL_H, (value >> 8) & 0xFF);
 416
 417        value = mode->vtotal - mode->vdisplay;
 418        hdmi_writeb(hdmi, HDMI_VIDEO_EXT_VBLANK, value & 0xFF);
 419
 420        value = mode->vsync_start - mode->vdisplay;
 421        hdmi_writeb(hdmi, HDMI_VIDEO_EXT_VDELAY, value & 0xFF);
 422
 423        value = mode->vsync_end - mode->vsync_start;
 424        hdmi_writeb(hdmi, HDMI_VIDEO_EXT_VDURATION, value & 0xFF);
 425
 426        hdmi_writeb(hdmi, HDMI_PHY_PRE_DIV_RATIO, 0x1e);
 427        hdmi_writeb(hdmi, HDMI_PHY_FEEDBACK_DIV_RATIO_LOW, 0x2c);
 428        hdmi_writeb(hdmi, HDMI_PHY_FEEDBACK_DIV_RATIO_HIGH, 0x01);
 429
 430        return 0;
 431}
 432
 433static int inno_hdmi_setup(struct inno_hdmi *hdmi,
 434                           struct drm_display_mode *mode)
 435{
 436        hdmi->hdmi_data.vic = drm_match_cea_mode(mode);
 437
 438        hdmi->hdmi_data.enc_in_format = HDMI_COLORSPACE_RGB;
 439        hdmi->hdmi_data.enc_out_format = HDMI_COLORSPACE_RGB;
 440
 441        if ((hdmi->hdmi_data.vic == 6) || (hdmi->hdmi_data.vic == 7) ||
 442            (hdmi->hdmi_data.vic == 21) || (hdmi->hdmi_data.vic == 22) ||
 443            (hdmi->hdmi_data.vic == 2) || (hdmi->hdmi_data.vic == 3) ||
 444            (hdmi->hdmi_data.vic == 17) || (hdmi->hdmi_data.vic == 18))
 445                hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_601;
 446        else
 447                hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_709;
 448
 449        /* Mute video and audio output */
 450        hdmi_modb(hdmi, HDMI_AV_MUTE, m_AUDIO_MUTE | m_VIDEO_BLACK,
 451                  v_AUDIO_MUTE(1) | v_VIDEO_MUTE(1));
 452
 453        /* Set HDMI Mode */
 454        hdmi_writeb(hdmi, HDMI_HDCP_CTRL,
 455                    v_HDMI_DVI(hdmi->hdmi_data.sink_is_hdmi));
 456
 457        inno_hdmi_config_video_timing(hdmi, mode);
 458
 459        inno_hdmi_config_video_csc(hdmi);
 460
 461        if (hdmi->hdmi_data.sink_is_hdmi) {
 462                inno_hdmi_config_video_avi(hdmi, mode);
 463                inno_hdmi_config_video_vsi(hdmi, mode);
 464        }
 465
 466        /*
 467         * When IP controller have configured to an accurate video
 468         * timing, then the TMDS clock source would be switched to
 469         * DCLK_LCDC, so we need to init the TMDS rate to mode pixel
 470         * clock rate, and reconfigure the DDC clock.
 471         */
 472        hdmi->tmds_rate = mode->clock * 1000;
 473        inno_hdmi_i2c_init(hdmi);
 474
 475        /* Unmute video and audio output */
 476        hdmi_modb(hdmi, HDMI_AV_MUTE, m_AUDIO_MUTE | m_VIDEO_BLACK,
 477                  v_AUDIO_MUTE(0) | v_VIDEO_MUTE(0));
 478
 479        return 0;
 480}
 481
 482static void inno_hdmi_encoder_mode_set(struct drm_encoder *encoder,
 483                                       struct drm_display_mode *mode,
 484                                       struct drm_display_mode *adj_mode)
 485{
 486        struct inno_hdmi *hdmi = to_inno_hdmi(encoder);
 487
 488        inno_hdmi_setup(hdmi, adj_mode);
 489
 490        /* Store the display mode for plugin/DPMS poweron events */
 491        memcpy(&hdmi->previous_mode, adj_mode, sizeof(hdmi->previous_mode));
 492}
 493
 494static void inno_hdmi_encoder_enable(struct drm_encoder *encoder)
 495{
 496        struct inno_hdmi *hdmi = to_inno_hdmi(encoder);
 497
 498        inno_hdmi_set_pwr_mode(hdmi, NORMAL);
 499}
 500
 501static void inno_hdmi_encoder_disable(struct drm_encoder *encoder)
 502{
 503        struct inno_hdmi *hdmi = to_inno_hdmi(encoder);
 504
 505        inno_hdmi_set_pwr_mode(hdmi, LOWER_PWR);
 506}
 507
 508static bool inno_hdmi_encoder_mode_fixup(struct drm_encoder *encoder,
 509                                         const struct drm_display_mode *mode,
 510                                         struct drm_display_mode *adj_mode)
 511{
 512        return true;
 513}
 514
 515static int
 516inno_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
 517                               struct drm_crtc_state *crtc_state,
 518                               struct drm_connector_state *conn_state)
 519{
 520        struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
 521
 522        s->output_mode = ROCKCHIP_OUT_MODE_P888;
 523        s->output_type = DRM_MODE_CONNECTOR_HDMIA;
 524
 525        return 0;
 526}
 527
 528static struct drm_encoder_helper_funcs inno_hdmi_encoder_helper_funcs = {
 529        .enable     = inno_hdmi_encoder_enable,
 530        .disable    = inno_hdmi_encoder_disable,
 531        .mode_fixup = inno_hdmi_encoder_mode_fixup,
 532        .mode_set   = inno_hdmi_encoder_mode_set,
 533        .atomic_check = inno_hdmi_encoder_atomic_check,
 534};
 535
 536static enum drm_connector_status
 537inno_hdmi_connector_detect(struct drm_connector *connector, bool force)
 538{
 539        struct inno_hdmi *hdmi = to_inno_hdmi(connector);
 540
 541        return (hdmi_readb(hdmi, HDMI_STATUS) & m_HOTPLUG) ?
 542                connector_status_connected : connector_status_disconnected;
 543}
 544
 545static int inno_hdmi_connector_get_modes(struct drm_connector *connector)
 546{
 547        struct inno_hdmi *hdmi = to_inno_hdmi(connector);
 548        struct edid *edid;
 549        int ret = 0;
 550
 551        if (!hdmi->ddc)
 552                return 0;
 553
 554        edid = drm_get_edid(connector, hdmi->ddc);
 555        if (edid) {
 556                hdmi->hdmi_data.sink_is_hdmi = drm_detect_hdmi_monitor(edid);
 557                hdmi->hdmi_data.sink_has_audio = drm_detect_monitor_audio(edid);
 558                drm_connector_update_edid_property(connector, edid);
 559                ret = drm_add_edid_modes(connector, edid);
 560                kfree(edid);
 561        }
 562
 563        return ret;
 564}
 565
 566static enum drm_mode_status
 567inno_hdmi_connector_mode_valid(struct drm_connector *connector,
 568                               struct drm_display_mode *mode)
 569{
 570        return MODE_OK;
 571}
 572
 573static int
 574inno_hdmi_probe_single_connector_modes(struct drm_connector *connector,
 575                                       uint32_t maxX, uint32_t maxY)
 576{
 577        return drm_helper_probe_single_connector_modes(connector, 1920, 1080);
 578}
 579
 580static void inno_hdmi_connector_destroy(struct drm_connector *connector)
 581{
 582        drm_connector_unregister(connector);
 583        drm_connector_cleanup(connector);
 584}
 585
 586static const struct drm_connector_funcs inno_hdmi_connector_funcs = {
 587        .fill_modes = inno_hdmi_probe_single_connector_modes,
 588        .detect = inno_hdmi_connector_detect,
 589        .destroy = inno_hdmi_connector_destroy,
 590        .reset = drm_atomic_helper_connector_reset,
 591        .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
 592        .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 593};
 594
 595static struct drm_connector_helper_funcs inno_hdmi_connector_helper_funcs = {
 596        .get_modes = inno_hdmi_connector_get_modes,
 597        .mode_valid = inno_hdmi_connector_mode_valid,
 598};
 599
 600static int inno_hdmi_register(struct drm_device *drm, struct inno_hdmi *hdmi)
 601{
 602        struct drm_encoder *encoder = &hdmi->encoder;
 603        struct device *dev = hdmi->dev;
 604
 605        encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
 606
 607        /*
 608         * If we failed to find the CRTC(s) which this encoder is
 609         * supposed to be connected to, it's because the CRTC has
 610         * not been registered yet.  Defer probing, and hope that
 611         * the required CRTC is added later.
 612         */
 613        if (encoder->possible_crtcs == 0)
 614                return -EPROBE_DEFER;
 615
 616        drm_encoder_helper_add(encoder, &inno_hdmi_encoder_helper_funcs);
 617        drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS);
 618
 619        hdmi->connector.polled = DRM_CONNECTOR_POLL_HPD;
 620
 621        drm_connector_helper_add(&hdmi->connector,
 622                                 &inno_hdmi_connector_helper_funcs);
 623        drm_connector_init_with_ddc(drm, &hdmi->connector,
 624                                    &inno_hdmi_connector_funcs,
 625                                    DRM_MODE_CONNECTOR_HDMIA,
 626                                    hdmi->ddc);
 627
 628        drm_connector_attach_encoder(&hdmi->connector, encoder);
 629
 630        return 0;
 631}
 632
 633static irqreturn_t inno_hdmi_i2c_irq(struct inno_hdmi *hdmi)
 634{
 635        struct inno_hdmi_i2c *i2c = hdmi->i2c;
 636        u8 stat;
 637
 638        stat = hdmi_readb(hdmi, HDMI_INTERRUPT_STATUS1);
 639        if (!(stat & m_INT_EDID_READY))
 640                return IRQ_NONE;
 641
 642        /* Clear HDMI EDID interrupt flag */
 643        hdmi_writeb(hdmi, HDMI_INTERRUPT_STATUS1, m_INT_EDID_READY);
 644
 645        complete(&i2c->cmp);
 646
 647        return IRQ_HANDLED;
 648}
 649
 650static irqreturn_t inno_hdmi_hardirq(int irq, void *dev_id)
 651{
 652        struct inno_hdmi *hdmi = dev_id;
 653        irqreturn_t ret = IRQ_NONE;
 654        u8 interrupt;
 655
 656        if (hdmi->i2c)
 657                ret = inno_hdmi_i2c_irq(hdmi);
 658
 659        interrupt = hdmi_readb(hdmi, HDMI_STATUS);
 660        if (interrupt & m_INT_HOTPLUG) {
 661                hdmi_modb(hdmi, HDMI_STATUS, m_INT_HOTPLUG, m_INT_HOTPLUG);
 662                ret = IRQ_WAKE_THREAD;
 663        }
 664
 665        return ret;
 666}
 667
 668static irqreturn_t inno_hdmi_irq(int irq, void *dev_id)
 669{
 670        struct inno_hdmi *hdmi = dev_id;
 671
 672        drm_helper_hpd_irq_event(hdmi->connector.dev);
 673
 674        return IRQ_HANDLED;
 675}
 676
 677static int inno_hdmi_i2c_read(struct inno_hdmi *hdmi, struct i2c_msg *msgs)
 678{
 679        int length = msgs->len;
 680        u8 *buf = msgs->buf;
 681        int ret;
 682
 683        ret = wait_for_completion_timeout(&hdmi->i2c->cmp, HZ / 10);
 684        if (!ret)
 685                return -EAGAIN;
 686
 687        while (length--)
 688                *buf++ = hdmi_readb(hdmi, HDMI_EDID_FIFO_ADDR);
 689
 690        return 0;
 691}
 692
 693static int inno_hdmi_i2c_write(struct inno_hdmi *hdmi, struct i2c_msg *msgs)
 694{
 695        /*
 696         * The DDC module only support read EDID message, so
 697         * we assume that each word write to this i2c adapter
 698         * should be the offset of EDID word address.
 699         */
 700        if ((msgs->len != 1) ||
 701            ((msgs->addr != DDC_ADDR) && (msgs->addr != DDC_SEGMENT_ADDR)))
 702                return -EINVAL;
 703
 704        reinit_completion(&hdmi->i2c->cmp);
 705
 706        if (msgs->addr == DDC_SEGMENT_ADDR)
 707                hdmi->i2c->segment_addr = msgs->buf[0];
 708        if (msgs->addr == DDC_ADDR)
 709                hdmi->i2c->ddc_addr = msgs->buf[0];
 710
 711        /* Set edid fifo first addr */
 712        hdmi_writeb(hdmi, HDMI_EDID_FIFO_OFFSET, 0x00);
 713
 714        /* Set edid word address 0x00/0x80 */
 715        hdmi_writeb(hdmi, HDMI_EDID_WORD_ADDR, hdmi->i2c->ddc_addr);
 716
 717        /* Set edid segment pointer */
 718        hdmi_writeb(hdmi, HDMI_EDID_SEGMENT_POINTER, hdmi->i2c->segment_addr);
 719
 720        return 0;
 721}
 722
 723static int inno_hdmi_i2c_xfer(struct i2c_adapter *adap,
 724                              struct i2c_msg *msgs, int num)
 725{
 726        struct inno_hdmi *hdmi = i2c_get_adapdata(adap);
 727        struct inno_hdmi_i2c *i2c = hdmi->i2c;
 728        int i, ret = 0;
 729
 730        mutex_lock(&i2c->lock);
 731
 732        /* Clear the EDID interrupt flag and unmute the interrupt */
 733        hdmi_writeb(hdmi, HDMI_INTERRUPT_MASK1, m_INT_EDID_READY);
 734        hdmi_writeb(hdmi, HDMI_INTERRUPT_STATUS1, m_INT_EDID_READY);
 735
 736        for (i = 0; i < num; i++) {
 737                DRM_DEV_DEBUG(hdmi->dev,
 738                              "xfer: num: %d/%d, len: %d, flags: %#x\n",
 739                              i + 1, num, msgs[i].len, msgs[i].flags);
 740
 741                if (msgs[i].flags & I2C_M_RD)
 742                        ret = inno_hdmi_i2c_read(hdmi, &msgs[i]);
 743                else
 744                        ret = inno_hdmi_i2c_write(hdmi, &msgs[i]);
 745
 746                if (ret < 0)
 747                        break;
 748        }
 749
 750        if (!ret)
 751                ret = num;
 752
 753        /* Mute HDMI EDID interrupt */
 754        hdmi_writeb(hdmi, HDMI_INTERRUPT_MASK1, 0);
 755
 756        mutex_unlock(&i2c->lock);
 757
 758        return ret;
 759}
 760
 761static u32 inno_hdmi_i2c_func(struct i2c_adapter *adapter)
 762{
 763        return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 764}
 765
 766static const struct i2c_algorithm inno_hdmi_algorithm = {
 767        .master_xfer    = inno_hdmi_i2c_xfer,
 768        .functionality  = inno_hdmi_i2c_func,
 769};
 770
 771static struct i2c_adapter *inno_hdmi_i2c_adapter(struct inno_hdmi *hdmi)
 772{
 773        struct i2c_adapter *adap;
 774        struct inno_hdmi_i2c *i2c;
 775        int ret;
 776
 777        i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL);
 778        if (!i2c)
 779                return ERR_PTR(-ENOMEM);
 780
 781        mutex_init(&i2c->lock);
 782        init_completion(&i2c->cmp);
 783
 784        adap = &i2c->adap;
 785        adap->class = I2C_CLASS_DDC;
 786        adap->owner = THIS_MODULE;
 787        adap->dev.parent = hdmi->dev;
 788        adap->dev.of_node = hdmi->dev->of_node;
 789        adap->algo = &inno_hdmi_algorithm;
 790        strlcpy(adap->name, "Inno HDMI", sizeof(adap->name));
 791        i2c_set_adapdata(adap, hdmi);
 792
 793        ret = i2c_add_adapter(adap);
 794        if (ret) {
 795                dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name);
 796                devm_kfree(hdmi->dev, i2c);
 797                return ERR_PTR(ret);
 798        }
 799
 800        hdmi->i2c = i2c;
 801
 802        DRM_DEV_INFO(hdmi->dev, "registered %s I2C bus driver\n", adap->name);
 803
 804        return adap;
 805}
 806
 807static int inno_hdmi_bind(struct device *dev, struct device *master,
 808                                 void *data)
 809{
 810        struct platform_device *pdev = to_platform_device(dev);
 811        struct drm_device *drm = data;
 812        struct inno_hdmi *hdmi;
 813        int irq;
 814        int ret;
 815
 816        hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
 817        if (!hdmi)
 818                return -ENOMEM;
 819
 820        hdmi->dev = dev;
 821        hdmi->drm_dev = drm;
 822
 823        hdmi->regs = devm_platform_ioremap_resource(pdev, 0);
 824        if (IS_ERR(hdmi->regs))
 825                return PTR_ERR(hdmi->regs);
 826
 827        hdmi->pclk = devm_clk_get(hdmi->dev, "pclk");
 828        if (IS_ERR(hdmi->pclk)) {
 829                DRM_DEV_ERROR(hdmi->dev, "Unable to get HDMI pclk clk\n");
 830                return PTR_ERR(hdmi->pclk);
 831        }
 832
 833        ret = clk_prepare_enable(hdmi->pclk);
 834        if (ret) {
 835                DRM_DEV_ERROR(hdmi->dev,
 836                              "Cannot enable HDMI pclk clock: %d\n", ret);
 837                return ret;
 838        }
 839
 840        irq = platform_get_irq(pdev, 0);
 841        if (irq < 0) {
 842                ret = irq;
 843                goto err_disable_clk;
 844        }
 845
 846        inno_hdmi_reset(hdmi);
 847
 848        hdmi->ddc = inno_hdmi_i2c_adapter(hdmi);
 849        if (IS_ERR(hdmi->ddc)) {
 850                ret = PTR_ERR(hdmi->ddc);
 851                hdmi->ddc = NULL;
 852                goto err_disable_clk;
 853        }
 854
 855        /*
 856         * When IP controller haven't configured to an accurate video
 857         * timing, then the TMDS clock source would be switched to
 858         * PCLK_HDMI, so we need to init the TMDS rate to PCLK rate,
 859         * and reconfigure the DDC clock.
 860         */
 861        hdmi->tmds_rate = clk_get_rate(hdmi->pclk);
 862        inno_hdmi_i2c_init(hdmi);
 863
 864        ret = inno_hdmi_register(drm, hdmi);
 865        if (ret)
 866                goto err_put_adapter;
 867
 868        dev_set_drvdata(dev, hdmi);
 869
 870        /* Unmute hotplug interrupt */
 871        hdmi_modb(hdmi, HDMI_STATUS, m_MASK_INT_HOTPLUG, v_MASK_INT_HOTPLUG(1));
 872
 873        ret = devm_request_threaded_irq(dev, irq, inno_hdmi_hardirq,
 874                                        inno_hdmi_irq, IRQF_SHARED,
 875                                        dev_name(dev), hdmi);
 876        if (ret < 0)
 877                goto err_cleanup_hdmi;
 878
 879        return 0;
 880err_cleanup_hdmi:
 881        hdmi->connector.funcs->destroy(&hdmi->connector);
 882        hdmi->encoder.funcs->destroy(&hdmi->encoder);
 883err_put_adapter:
 884        i2c_put_adapter(hdmi->ddc);
 885err_disable_clk:
 886        clk_disable_unprepare(hdmi->pclk);
 887        return ret;
 888}
 889
 890static void inno_hdmi_unbind(struct device *dev, struct device *master,
 891                             void *data)
 892{
 893        struct inno_hdmi *hdmi = dev_get_drvdata(dev);
 894
 895        hdmi->connector.funcs->destroy(&hdmi->connector);
 896        hdmi->encoder.funcs->destroy(&hdmi->encoder);
 897
 898        i2c_put_adapter(hdmi->ddc);
 899        clk_disable_unprepare(hdmi->pclk);
 900}
 901
 902static const struct component_ops inno_hdmi_ops = {
 903        .bind   = inno_hdmi_bind,
 904        .unbind = inno_hdmi_unbind,
 905};
 906
 907static int inno_hdmi_probe(struct platform_device *pdev)
 908{
 909        return component_add(&pdev->dev, &inno_hdmi_ops);
 910}
 911
 912static int inno_hdmi_remove(struct platform_device *pdev)
 913{
 914        component_del(&pdev->dev, &inno_hdmi_ops);
 915
 916        return 0;
 917}
 918
 919static const struct of_device_id inno_hdmi_dt_ids[] = {
 920        { .compatible = "rockchip,rk3036-inno-hdmi",
 921        },
 922        {},
 923};
 924MODULE_DEVICE_TABLE(of, inno_hdmi_dt_ids);
 925
 926struct platform_driver inno_hdmi_driver = {
 927        .probe  = inno_hdmi_probe,
 928        .remove = inno_hdmi_remove,
 929        .driver = {
 930                .name = "innohdmi-rockchip",
 931                .of_match_table = inno_hdmi_dt_ids,
 932        },
 933};
 934