LXR linux/drivers/hid/intel-ish-hid/ipc/hw-ish.h

   1/* SPDX-License-Identifier: GPL-2.0-only */
   2/*
   3 * H/W layer of ISHTP provider device (ISH)
   4 *
   5 * Copyright (c) 2014-2016, Intel Corporation.
   6 */
   7
   8#ifndef _ISHTP_HW_ISH_H_
   9#define _ISHTP_HW_ISH_H_
  10
  11#include <linux/pci.h>
  12#include <linux/interrupt.h>
  13#include "hw-ish-regs.h"
  14#include "ishtp-dev.h"
  15
  16#define CHV_DEVICE_ID           0x22D8
  17#define BXT_Ax_DEVICE_ID        0x0AA2
  18#define BXT_Bx_DEVICE_ID        0x1AA2
  19#define APL_Ax_DEVICE_ID        0x5AA2
  20#define SPT_Ax_DEVICE_ID        0x9D35
  21#define CNL_Ax_DEVICE_ID        0x9DFC
  22#define GLK_Ax_DEVICE_ID        0x31A2
  23#define CNL_H_DEVICE_ID         0xA37C
  24#define ICL_MOBILE_DEVICE_ID    0x34FC
  25#define SPT_H_DEVICE_ID         0xA135
  26#define CML_LP_DEVICE_ID        0x02FC
  27#define CMP_H_DEVICE_ID         0x06FC
  28#define EHL_Ax_DEVICE_ID        0x4BB3
  29#define TGL_LP_DEVICE_ID        0xA0FC
  30#define TGL_H_DEVICE_ID         0x43FC
  31#define ADL_S_DEVICE_ID         0x7AF8
  32#define ADL_P_DEVICE_ID         0x51FC
  33
  34#define REVISION_ID_CHT_A0      0x6
  35#define REVISION_ID_CHT_Ax_SI   0x0
  36#define REVISION_ID_CHT_Bx_SI   0x10
  37#define REVISION_ID_CHT_Kx_SI   0x20
  38#define REVISION_ID_CHT_Dx_SI   0x30
  39#define REVISION_ID_CHT_B0      0xB0
  40#define REVISION_ID_SI_MASK     0x70
  41
  42struct ipc_rst_payload_type {
  43        uint16_t        reset_id;
  44        uint16_t        reserved;
  45};
  46
  47struct time_sync_format {
  48        uint8_t ts1_source;
  49        uint8_t ts2_source;
  50        uint16_t reserved;
  51} __packed;
  52
  53struct ipc_time_update_msg {
  54        uint64_t primary_host_time;
  55        struct time_sync_format sync_info;
  56        uint64_t secondary_host_time;
  57} __packed;
  58
  59enum {
  60        HOST_UTC_TIME_USEC = 0,
  61        HOST_SYSTEM_TIME_USEC = 1
  62};
  63
  64struct ish_hw {
  65        void __iomem *mem_addr;
  66};
  67
  68/*
  69 * ISH FW status type
  70 */
  71enum {
  72        FWSTS_AFTER_RESET               = 0,
  73        FWSTS_WAIT_FOR_HOST             = 4,
  74        FWSTS_START_KERNEL_DMA          = 5,
  75        FWSTS_FW_IS_RUNNING             = 7,
  76        FWSTS_SENSOR_APP_LOADED         = 8,
  77        FWSTS_SENSOR_APP_RUNNING        = 15
  78};
  79
  80#define to_ish_hw(dev) (struct ish_hw *)((dev)->hw)
  81
  82irqreturn_t ish_irq_handler(int irq, void *dev_id);
  83struct ishtp_device *ish_dev_init(struct pci_dev *pdev);
  84int ish_hw_start(struct ishtp_device *dev);
  85void ish_device_disable(struct ishtp_device *dev);
  86int ish_disable_dma(struct ishtp_device *dev);
  87void ish_set_host_ready(struct ishtp_device *dev);
  88
  89#endif /* _ISHTP_HW_ISH_H_ */
  90