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7#include <linux/device.h>
8#include <linux/interconnect.h>
9#include <linux/interconnect-provider.h>
10#include <linux/module.h>
11#include <linux/of_platform.h>
12#include <dt-bindings/interconnect/qcom,sm8250.h>
13
14#include "bcm-voter.h"
15#include "icc-rpmh.h"
16#include "sm8250.h"
17
18DEFINE_QNODE(qhm_a1noc_cfg, SM8250_MASTER_A1NOC_CFG, 1, 4, SM8250_SLAVE_SERVICE_A1NOC);
19DEFINE_QNODE(qhm_qspi, SM8250_MASTER_QSPI_0, 1, 4, SM8250_A1NOC_SNOC_SLV);
20DEFINE_QNODE(qhm_qup1, SM8250_MASTER_QUP_1, 1, 4, SM8250_A1NOC_SNOC_SLV);
21DEFINE_QNODE(qhm_qup2, SM8250_MASTER_QUP_2, 1, 4, SM8250_A1NOC_SNOC_SLV);
22DEFINE_QNODE(qhm_tsif, SM8250_MASTER_TSIF, 1, 4, SM8250_A1NOC_SNOC_SLV);
23DEFINE_QNODE(xm_pcie3_modem, SM8250_MASTER_PCIE_2, 1, 8, SM8250_SLAVE_ANOC_PCIE_GEM_NOC_1);
24DEFINE_QNODE(xm_sdc4, SM8250_MASTER_SDCC_4, 1, 8, SM8250_A1NOC_SNOC_SLV);
25DEFINE_QNODE(xm_ufs_mem, SM8250_MASTER_UFS_MEM, 1, 8, SM8250_A1NOC_SNOC_SLV);
26DEFINE_QNODE(xm_usb3_0, SM8250_MASTER_USB3, 1, 8, SM8250_A1NOC_SNOC_SLV);
27DEFINE_QNODE(xm_usb3_1, SM8250_MASTER_USB3_1, 1, 8, SM8250_A1NOC_SNOC_SLV);
28DEFINE_QNODE(qhm_a2noc_cfg, SM8250_MASTER_A2NOC_CFG, 1, 4, SM8250_SLAVE_SERVICE_A2NOC);
29DEFINE_QNODE(qhm_qdss_bam, SM8250_MASTER_QDSS_BAM, 1, 4, SM8250_A2NOC_SNOC_SLV);
30DEFINE_QNODE(qhm_qup0, SM8250_MASTER_QUP_0, 1, 4, SM8250_A2NOC_SNOC_SLV);
31DEFINE_QNODE(qnm_cnoc, SM8250_MASTER_CNOC_A2NOC, 1, 8, SM8250_A2NOC_SNOC_SLV);
32DEFINE_QNODE(qxm_crypto, SM8250_MASTER_CRYPTO_CORE_0, 1, 8, SM8250_A2NOC_SNOC_SLV);
33DEFINE_QNODE(qxm_ipa, SM8250_MASTER_IPA, 1, 8, SM8250_A2NOC_SNOC_SLV);
34DEFINE_QNODE(xm_pcie3_0, SM8250_MASTER_PCIE, 1, 8, SM8250_SLAVE_ANOC_PCIE_GEM_NOC);
35DEFINE_QNODE(xm_pcie3_1, SM8250_MASTER_PCIE_1, 1, 8, SM8250_SLAVE_ANOC_PCIE_GEM_NOC);
36DEFINE_QNODE(xm_qdss_etr, SM8250_MASTER_QDSS_ETR, 1, 8, SM8250_A2NOC_SNOC_SLV);
37DEFINE_QNODE(xm_sdc2, SM8250_MASTER_SDCC_2, 1, 8, SM8250_A2NOC_SNOC_SLV);
38DEFINE_QNODE(xm_ufs_card, SM8250_MASTER_UFS_CARD, 1, 8, SM8250_A2NOC_SNOC_SLV);
39DEFINE_QNODE(qnm_npu, SM8250_MASTER_NPU, 2, 32, SM8250_SLAVE_CDSP_MEM_NOC);
40DEFINE_QNODE(qnm_snoc, SM8250_SNOC_CNOC_MAS, 1, 8, SM8250_SLAVE_CDSP_CFG, SM8250_SLAVE_CAMERA_CFG, SM8250_SLAVE_TLMM_SOUTH, SM8250_SLAVE_TLMM_NORTH, SM8250_SLAVE_SDCC_4, SM8250_SLAVE_TLMM_WEST, SM8250_SLAVE_SDCC_2, SM8250_SLAVE_CNOC_MNOC_CFG, SM8250_SLAVE_UFS_MEM_CFG, SM8250_SLAVE_SNOC_CFG, SM8250_SLAVE_PDM, SM8250_SLAVE_CX_RDPM, SM8250_SLAVE_PCIE_1_CFG, SM8250_SLAVE_A2NOC_CFG, SM8250_SLAVE_QDSS_CFG, SM8250_SLAVE_DISPLAY_CFG, SM8250_SLAVE_PCIE_2_CFG, SM8250_SLAVE_TCSR, SM8250_SLAVE_DCC_CFG, SM8250_SLAVE_CNOC_DDRSS, SM8250_SLAVE_IPC_ROUTER_CFG, SM8250_SLAVE_PCIE_0_CFG, SM8250_SLAVE_RBCPR_MMCX_CFG, SM8250_SLAVE_NPU_CFG, SM8250_SLAVE_AHB2PHY_SOUTH, SM8250_SLAVE_AHB2PHY_NORTH, SM8250_SLAVE_GRAPHICS_3D_CFG, SM8250_SLAVE_VENUS_CFG, SM8250_SLAVE_TSIF, SM8250_SLAVE_IPA_CFG, SM8250_SLAVE_IMEM_CFG, SM8250_SLAVE_USB3, SM8250_SLAVE_SERVICE_CNOC, SM8250_SLAVE_UFS_CARD_CFG, SM8250_SLAVE_USB3_1, SM8250_SLAVE_LPASS, SM8250_SLAVE_RBCPR_CX_CFG, SM8250_SLAVE_A1NOC_CFG, SM8250_SLAVE_AOSS, SM8250_SLAVE_PRNG, SM8250_SLAVE_VSENSE_CTRL_CFG, SM8250_SLAVE_QSPI_0, SM8250_SLAVE_CRYPTO_0_CFG, SM8250_SLAVE_PIMEM_CFG, SM8250_SLAVE_RBCPR_MX_CFG, SM8250_SLAVE_QUP_0, SM8250_SLAVE_QUP_1, SM8250_SLAVE_QUP_2, SM8250_SLAVE_CLK_CTL);
41DEFINE_QNODE(xm_qdss_dap, SM8250_MASTER_QDSS_DAP, 1, 8, SM8250_SLAVE_CDSP_CFG, SM8250_SLAVE_CAMERA_CFG, SM8250_SLAVE_TLMM_SOUTH, SM8250_SLAVE_TLMM_NORTH, SM8250_SLAVE_SDCC_4, SM8250_SLAVE_TLMM_WEST, SM8250_SLAVE_SDCC_2, SM8250_SLAVE_CNOC_MNOC_CFG, SM8250_SLAVE_UFS_MEM_CFG, SM8250_SLAVE_SNOC_CFG, SM8250_SLAVE_PDM, SM8250_SLAVE_CX_RDPM, SM8250_SLAVE_PCIE_1_CFG, SM8250_SLAVE_A2NOC_CFG, SM8250_SLAVE_QDSS_CFG, SM8250_SLAVE_DISPLAY_CFG, SM8250_SLAVE_PCIE_2_CFG, SM8250_SLAVE_TCSR, SM8250_SLAVE_DCC_CFG, SM8250_SLAVE_CNOC_DDRSS, SM8250_SLAVE_IPC_ROUTER_CFG, SM8250_SLAVE_CNOC_A2NOC, SM8250_SLAVE_PCIE_0_CFG, SM8250_SLAVE_RBCPR_MMCX_CFG, SM8250_SLAVE_NPU_CFG, SM8250_SLAVE_AHB2PHY_SOUTH, SM8250_SLAVE_AHB2PHY_NORTH, SM8250_SLAVE_GRAPHICS_3D_CFG, SM8250_SLAVE_VENUS_CFG, SM8250_SLAVE_TSIF, SM8250_SLAVE_IPA_CFG, SM8250_SLAVE_IMEM_CFG, SM8250_SLAVE_USB3, SM8250_SLAVE_SERVICE_CNOC, SM8250_SLAVE_UFS_CARD_CFG, SM8250_SLAVE_USB3_1, SM8250_SLAVE_LPASS, SM8250_SLAVE_RBCPR_CX_CFG, SM8250_SLAVE_A1NOC_CFG, SM8250_SLAVE_AOSS, SM8250_SLAVE_PRNG, SM8250_SLAVE_VSENSE_CTRL_CFG, SM8250_SLAVE_QSPI_0, SM8250_SLAVE_CRYPTO_0_CFG, SM8250_SLAVE_PIMEM_CFG, SM8250_SLAVE_RBCPR_MX_CFG, SM8250_SLAVE_QUP_0, SM8250_SLAVE_QUP_1, SM8250_SLAVE_QUP_2, SM8250_SLAVE_CLK_CTL);
42DEFINE_QNODE(qhm_cnoc_dc_noc, SM8250_MASTER_CNOC_DC_NOC, 1, 4, SM8250_SLAVE_GEM_NOC_CFG, SM8250_SLAVE_LLCC_CFG);
43DEFINE_QNODE(alm_gpu_tcu, SM8250_MASTER_GPU_TCU, 1, 8, SM8250_SLAVE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC);
44DEFINE_QNODE(alm_sys_tcu, SM8250_MASTER_SYS_TCU, 1, 8, SM8250_SLAVE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC);
45DEFINE_QNODE(chm_apps, SM8250_MASTER_AMPSS_M0, 2, 32, SM8250_SLAVE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC, SM8250_SLAVE_MEM_NOC_PCIE_SNOC);
46DEFINE_QNODE(qhm_gemnoc_cfg, SM8250_MASTER_GEM_NOC_CFG, 1, 4, SM8250_SLAVE_SERVICE_GEM_NOC_2, SM8250_SLAVE_SERVICE_GEM_NOC_1, SM8250_SLAVE_SERVICE_GEM_NOC);
47DEFINE_QNODE(qnm_cmpnoc, SM8250_MASTER_COMPUTE_NOC, 2, 32, SM8250_SLAVE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC);
48DEFINE_QNODE(qnm_gpu, SM8250_MASTER_GRAPHICS_3D, 2, 32, SM8250_SLAVE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC);
49DEFINE_QNODE(qnm_mnoc_hf, SM8250_MASTER_MNOC_HF_MEM_NOC, 2, 32, SM8250_SLAVE_LLCC);
50DEFINE_QNODE(qnm_mnoc_sf, SM8250_MASTER_MNOC_SF_MEM_NOC, 2, 32, SM8250_SLAVE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC);
51DEFINE_QNODE(qnm_pcie, SM8250_MASTER_ANOC_PCIE_GEM_NOC, 1, 16, SM8250_SLAVE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC);
52DEFINE_QNODE(qnm_snoc_gc, SM8250_MASTER_SNOC_GC_MEM_NOC, 1, 8, SM8250_SLAVE_LLCC);
53DEFINE_QNODE(qnm_snoc_sf, SM8250_MASTER_SNOC_SF_MEM_NOC, 1, 16, SM8250_SLAVE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC, SM8250_SLAVE_MEM_NOC_PCIE_SNOC);
54DEFINE_QNODE(ipa_core_master, SM8250_MASTER_IPA_CORE, 1, 8, SM8250_SLAVE_IPA_CORE);
55DEFINE_QNODE(llcc_mc, SM8250_MASTER_LLCC, 4, 4, SM8250_SLAVE_EBI_CH0);
56DEFINE_QNODE(qhm_mnoc_cfg, SM8250_MASTER_CNOC_MNOC_CFG, 1, 4, SM8250_SLAVE_SERVICE_MNOC);
57DEFINE_QNODE(qnm_camnoc_hf, SM8250_MASTER_CAMNOC_HF, 2, 32, SM8250_SLAVE_MNOC_HF_MEM_NOC);
58DEFINE_QNODE(qnm_camnoc_icp, SM8250_MASTER_CAMNOC_ICP, 1, 8, SM8250_SLAVE_MNOC_SF_MEM_NOC);
59DEFINE_QNODE(qnm_camnoc_sf, SM8250_MASTER_CAMNOC_SF, 2, 32, SM8250_SLAVE_MNOC_SF_MEM_NOC);
60DEFINE_QNODE(qnm_video0, SM8250_MASTER_VIDEO_P0, 1, 32, SM8250_SLAVE_MNOC_SF_MEM_NOC);
61DEFINE_QNODE(qnm_video1, SM8250_MASTER_VIDEO_P1, 1, 32, SM8250_SLAVE_MNOC_SF_MEM_NOC);
62DEFINE_QNODE(qnm_video_cvp, SM8250_MASTER_VIDEO_PROC, 1, 32, SM8250_SLAVE_MNOC_SF_MEM_NOC);
63DEFINE_QNODE(qxm_mdp0, SM8250_MASTER_MDP_PORT0, 1, 32, SM8250_SLAVE_MNOC_HF_MEM_NOC);
64DEFINE_QNODE(qxm_mdp1, SM8250_MASTER_MDP_PORT1, 1, 32, SM8250_SLAVE_MNOC_HF_MEM_NOC);
65DEFINE_QNODE(qxm_rot, SM8250_MASTER_ROTATOR, 1, 32, SM8250_SLAVE_MNOC_SF_MEM_NOC);
66DEFINE_QNODE(amm_npu_sys, SM8250_MASTER_NPU_SYS, 4, 32, SM8250_SLAVE_NPU_COMPUTE_NOC);
67DEFINE_QNODE(amm_npu_sys_cdp_w, SM8250_MASTER_NPU_CDP, 2, 16, SM8250_SLAVE_NPU_COMPUTE_NOC);
68DEFINE_QNODE(qhm_cfg, SM8250_MASTER_NPU_NOC_CFG, 1, 4, SM8250_SLAVE_SERVICE_NPU_NOC, SM8250_SLAVE_ISENSE_CFG, SM8250_SLAVE_NPU_LLM_CFG, SM8250_SLAVE_NPU_INT_DMA_BWMON_CFG, SM8250_SLAVE_NPU_CP, SM8250_SLAVE_NPU_TCM, SM8250_SLAVE_NPU_CAL_DP0, SM8250_SLAVE_NPU_CAL_DP1, SM8250_SLAVE_NPU_DPM);
69DEFINE_QNODE(qhm_snoc_cfg, SM8250_MASTER_SNOC_CFG, 1, 4, SM8250_SLAVE_SERVICE_SNOC);
70DEFINE_QNODE(qnm_aggre1_noc, SM8250_A1NOC_SNOC_MAS, 1, 16, SM8250_SLAVE_SNOC_GEM_NOC_SF);
71DEFINE_QNODE(qnm_aggre2_noc, SM8250_A2NOC_SNOC_MAS, 1, 16, SM8250_SLAVE_SNOC_GEM_NOC_SF);
72DEFINE_QNODE(qnm_gemnoc, SM8250_MASTER_GEM_NOC_SNOC, 1, 16, SM8250_SLAVE_PIMEM, SM8250_SLAVE_OCIMEM, SM8250_SLAVE_APPSS, SM8250_SNOC_CNOC_SLV, SM8250_SLAVE_TCU, SM8250_SLAVE_QDSS_STM);
73DEFINE_QNODE(qnm_gemnoc_pcie, SM8250_MASTER_GEM_NOC_PCIE_SNOC, 1, 8, SM8250_SLAVE_PCIE_2, SM8250_SLAVE_PCIE_0, SM8250_SLAVE_PCIE_1);
74DEFINE_QNODE(qxm_pimem, SM8250_MASTER_PIMEM, 1, 8, SM8250_SLAVE_SNOC_GEM_NOC_GC);
75DEFINE_QNODE(xm_gic, SM8250_MASTER_GIC, 1, 8, SM8250_SLAVE_SNOC_GEM_NOC_GC);
76DEFINE_QNODE(qns_a1noc_snoc, SM8250_A1NOC_SNOC_SLV, 1, 16, SM8250_A1NOC_SNOC_MAS);
77DEFINE_QNODE(qns_pcie_modem_mem_noc, SM8250_SLAVE_ANOC_PCIE_GEM_NOC_1, 1, 16, SM8250_MASTER_ANOC_PCIE_GEM_NOC);
78DEFINE_QNODE(srvc_aggre1_noc, SM8250_SLAVE_SERVICE_A1NOC, 1, 4);
79DEFINE_QNODE(qns_a2noc_snoc, SM8250_A2NOC_SNOC_SLV, 1, 16, SM8250_A2NOC_SNOC_MAS);
80DEFINE_QNODE(qns_pcie_mem_noc, SM8250_SLAVE_ANOC_PCIE_GEM_NOC, 1, 16, SM8250_MASTER_ANOC_PCIE_GEM_NOC);
81DEFINE_QNODE(srvc_aggre2_noc, SM8250_SLAVE_SERVICE_A2NOC, 1, 4);
82DEFINE_QNODE(qns_cdsp_mem_noc, SM8250_SLAVE_CDSP_MEM_NOC, 2, 32, SM8250_MASTER_COMPUTE_NOC);
83DEFINE_QNODE(qhs_a1_noc_cfg, SM8250_SLAVE_A1NOC_CFG, 1, 4, SM8250_MASTER_A1NOC_CFG);
84DEFINE_QNODE(qhs_a2_noc_cfg, SM8250_SLAVE_A2NOC_CFG, 1, 4, SM8250_MASTER_A2NOC_CFG);
85DEFINE_QNODE(qhs_ahb2phy0, SM8250_SLAVE_AHB2PHY_SOUTH, 1, 4);
86DEFINE_QNODE(qhs_ahb2phy1, SM8250_SLAVE_AHB2PHY_NORTH, 1, 4);
87DEFINE_QNODE(qhs_aoss, SM8250_SLAVE_AOSS, 1, 4);
88DEFINE_QNODE(qhs_camera_cfg, SM8250_SLAVE_CAMERA_CFG, 1, 4);
89DEFINE_QNODE(qhs_clk_ctl, SM8250_SLAVE_CLK_CTL, 1, 4);
90DEFINE_QNODE(qhs_compute_dsp, SM8250_SLAVE_CDSP_CFG, 1, 4);
91DEFINE_QNODE(qhs_cpr_cx, SM8250_SLAVE_RBCPR_CX_CFG, 1, 4);
92DEFINE_QNODE(qhs_cpr_mmcx, SM8250_SLAVE_RBCPR_MMCX_CFG, 1, 4);
93DEFINE_QNODE(qhs_cpr_mx, SM8250_SLAVE_RBCPR_MX_CFG, 1, 4);
94DEFINE_QNODE(qhs_crypto0_cfg, SM8250_SLAVE_CRYPTO_0_CFG, 1, 4);
95DEFINE_QNODE(qhs_cx_rdpm, SM8250_SLAVE_CX_RDPM, 1, 4);
96DEFINE_QNODE(qhs_dcc_cfg, SM8250_SLAVE_DCC_CFG, 1, 4);
97DEFINE_QNODE(qhs_ddrss_cfg, SM8250_SLAVE_CNOC_DDRSS, 1, 4, SM8250_MASTER_CNOC_DC_NOC);
98DEFINE_QNODE(qhs_display_cfg, SM8250_SLAVE_DISPLAY_CFG, 1, 4);
99DEFINE_QNODE(qhs_gpuss_cfg, SM8250_SLAVE_GRAPHICS_3D_CFG, 1, 8);
100DEFINE_QNODE(qhs_imem_cfg, SM8250_SLAVE_IMEM_CFG, 1, 4);
101DEFINE_QNODE(qhs_ipa, SM8250_SLAVE_IPA_CFG, 1, 4);
102DEFINE_QNODE(qhs_ipc_router, SM8250_SLAVE_IPC_ROUTER_CFG, 1, 4);
103DEFINE_QNODE(qhs_lpass_cfg, SM8250_SLAVE_LPASS, 1, 4);
104DEFINE_QNODE(qhs_mnoc_cfg, SM8250_SLAVE_CNOC_MNOC_CFG, 1, 4, SM8250_MASTER_CNOC_MNOC_CFG);
105DEFINE_QNODE(qhs_npu_cfg, SM8250_SLAVE_NPU_CFG, 1, 4, SM8250_MASTER_NPU_NOC_CFG);
106DEFINE_QNODE(qhs_pcie0_cfg, SM8250_SLAVE_PCIE_0_CFG, 1, 4);
107DEFINE_QNODE(qhs_pcie1_cfg, SM8250_SLAVE_PCIE_1_CFG, 1, 4);
108DEFINE_QNODE(qhs_pcie_modem_cfg, SM8250_SLAVE_PCIE_2_CFG, 1, 4);
109DEFINE_QNODE(qhs_pdm, SM8250_SLAVE_PDM, 1, 4);
110DEFINE_QNODE(qhs_pimem_cfg, SM8250_SLAVE_PIMEM_CFG, 1, 4);
111DEFINE_QNODE(qhs_prng, SM8250_SLAVE_PRNG, 1, 4);
112DEFINE_QNODE(qhs_qdss_cfg, SM8250_SLAVE_QDSS_CFG, 1, 4);
113DEFINE_QNODE(qhs_qspi, SM8250_SLAVE_QSPI_0, 1, 4);
114DEFINE_QNODE(qhs_qup0, SM8250_SLAVE_QUP_0, 1, 4);
115DEFINE_QNODE(qhs_qup1, SM8250_SLAVE_QUP_1, 1, 4);
116DEFINE_QNODE(qhs_qup2, SM8250_SLAVE_QUP_2, 1, 4);
117DEFINE_QNODE(qhs_sdc2, SM8250_SLAVE_SDCC_2, 1, 4);
118DEFINE_QNODE(qhs_sdc4, SM8250_SLAVE_SDCC_4, 1, 4);
119DEFINE_QNODE(qhs_snoc_cfg, SM8250_SLAVE_SNOC_CFG, 1, 4, SM8250_MASTER_SNOC_CFG);
120DEFINE_QNODE(qhs_tcsr, SM8250_SLAVE_TCSR, 1, 4);
121DEFINE_QNODE(qhs_tlmm0, SM8250_SLAVE_TLMM_NORTH, 1, 4);
122DEFINE_QNODE(qhs_tlmm1, SM8250_SLAVE_TLMM_SOUTH, 1, 4);
123DEFINE_QNODE(qhs_tlmm2, SM8250_SLAVE_TLMM_WEST, 1, 4);
124DEFINE_QNODE(qhs_tsif, SM8250_SLAVE_TSIF, 1, 4);
125DEFINE_QNODE(qhs_ufs_card_cfg, SM8250_SLAVE_UFS_CARD_CFG, 1, 4);
126DEFINE_QNODE(qhs_ufs_mem_cfg, SM8250_SLAVE_UFS_MEM_CFG, 1, 4);
127DEFINE_QNODE(qhs_usb3_0, SM8250_SLAVE_USB3, 1, 4);
128DEFINE_QNODE(qhs_usb3_1, SM8250_SLAVE_USB3_1, 1, 4);
129DEFINE_QNODE(qhs_venus_cfg, SM8250_SLAVE_VENUS_CFG, 1, 4);
130DEFINE_QNODE(qhs_vsense_ctrl_cfg, SM8250_SLAVE_VSENSE_CTRL_CFG, 1, 4);
131DEFINE_QNODE(qns_cnoc_a2noc, SM8250_SLAVE_CNOC_A2NOC, 1, 8, SM8250_MASTER_CNOC_A2NOC);
132DEFINE_QNODE(srvc_cnoc, SM8250_SLAVE_SERVICE_CNOC, 1, 4);
133DEFINE_QNODE(qhs_llcc, SM8250_SLAVE_LLCC_CFG, 1, 4);
134DEFINE_QNODE(qhs_memnoc, SM8250_SLAVE_GEM_NOC_CFG, 1, 4, SM8250_MASTER_GEM_NOC_CFG);
135DEFINE_QNODE(qns_gem_noc_snoc, SM8250_SLAVE_GEM_NOC_SNOC, 1, 16, SM8250_MASTER_GEM_NOC_SNOC);
136DEFINE_QNODE(qns_llcc, SM8250_SLAVE_LLCC, 4, 16, SM8250_MASTER_LLCC);
137DEFINE_QNODE(qns_sys_pcie, SM8250_SLAVE_MEM_NOC_PCIE_SNOC, 1, 8, SM8250_MASTER_GEM_NOC_PCIE_SNOC);
138DEFINE_QNODE(srvc_even_gemnoc, SM8250_SLAVE_SERVICE_GEM_NOC_1, 1, 4);
139DEFINE_QNODE(srvc_odd_gemnoc, SM8250_SLAVE_SERVICE_GEM_NOC_2, 1, 4);
140DEFINE_QNODE(srvc_sys_gemnoc, SM8250_SLAVE_SERVICE_GEM_NOC, 1, 4);
141DEFINE_QNODE(ipa_core_slave, SM8250_SLAVE_IPA_CORE, 1, 8);
142DEFINE_QNODE(ebi, SM8250_SLAVE_EBI_CH0, 4, 4);
143DEFINE_QNODE(qns_mem_noc_hf, SM8250_SLAVE_MNOC_HF_MEM_NOC, 2, 32, SM8250_MASTER_MNOC_HF_MEM_NOC);
144DEFINE_QNODE(qns_mem_noc_sf, SM8250_SLAVE_MNOC_SF_MEM_NOC, 2, 32, SM8250_MASTER_MNOC_SF_MEM_NOC);
145DEFINE_QNODE(srvc_mnoc, SM8250_SLAVE_SERVICE_MNOC, 1, 4);
146DEFINE_QNODE(qhs_cal_dp0, SM8250_SLAVE_NPU_CAL_DP0, 1, 4);
147DEFINE_QNODE(qhs_cal_dp1, SM8250_SLAVE_NPU_CAL_DP1, 1, 4);
148DEFINE_QNODE(qhs_cp, SM8250_SLAVE_NPU_CP, 1, 4);
149DEFINE_QNODE(qhs_dma_bwmon, SM8250_SLAVE_NPU_INT_DMA_BWMON_CFG, 1, 4);
150DEFINE_QNODE(qhs_dpm, SM8250_SLAVE_NPU_DPM, 1, 4);
151DEFINE_QNODE(qhs_isense, SM8250_SLAVE_ISENSE_CFG, 1, 4);
152DEFINE_QNODE(qhs_llm, SM8250_SLAVE_NPU_LLM_CFG, 1, 4);
153DEFINE_QNODE(qhs_tcm, SM8250_SLAVE_NPU_TCM, 1, 4);
154DEFINE_QNODE(qns_npu_sys, SM8250_SLAVE_NPU_COMPUTE_NOC, 2, 32);
155DEFINE_QNODE(srvc_noc, SM8250_SLAVE_SERVICE_NPU_NOC, 1, 4);
156DEFINE_QNODE(qhs_apss, SM8250_SLAVE_APPSS, 1, 8);
157DEFINE_QNODE(qns_cnoc, SM8250_SNOC_CNOC_SLV, 1, 8, SM8250_SNOC_CNOC_MAS);
158DEFINE_QNODE(qns_gemnoc_gc, SM8250_SLAVE_SNOC_GEM_NOC_GC, 1, 8, SM8250_MASTER_SNOC_GC_MEM_NOC);
159DEFINE_QNODE(qns_gemnoc_sf, SM8250_SLAVE_SNOC_GEM_NOC_SF, 1, 16, SM8250_MASTER_SNOC_SF_MEM_NOC);
160DEFINE_QNODE(qxs_imem, SM8250_SLAVE_OCIMEM, 1, 8);
161DEFINE_QNODE(qxs_pimem, SM8250_SLAVE_PIMEM, 1, 8);
162DEFINE_QNODE(srvc_snoc, SM8250_SLAVE_SERVICE_SNOC, 1, 4);
163DEFINE_QNODE(xs_pcie_0, SM8250_SLAVE_PCIE_0, 1, 8);
164DEFINE_QNODE(xs_pcie_1, SM8250_SLAVE_PCIE_1, 1, 8);
165DEFINE_QNODE(xs_pcie_modem, SM8250_SLAVE_PCIE_2, 1, 8);
166DEFINE_QNODE(xs_qdss_stm, SM8250_SLAVE_QDSS_STM, 1, 4);
167DEFINE_QNODE(xs_sys_tcu_cfg, SM8250_SLAVE_TCU, 1, 8);
168
169DEFINE_QBCM(bcm_acv, "ACV", false, &ebi);
170DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi);
171DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc);
172DEFINE_QBCM(bcm_mm0, "MM0", true, &qns_mem_noc_hf);
173DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto);
174DEFINE_QBCM(bcm_ip0, "IP0", false, &ipa_core_slave);
175DEFINE_QBCM(bcm_mm1, "MM1", false, &qnm_camnoc_hf, &qxm_mdp0, &qxm_mdp1);
176DEFINE_QBCM(bcm_sh2, "SH2", false, &alm_gpu_tcu, &alm_sys_tcu);
177DEFINE_QBCM(bcm_mm2, "MM2", false, &qns_mem_noc_sf);
178DEFINE_QBCM(bcm_qup0, "QUP0", false, &qhm_qup1, &qhm_qup2, &qhm_qup0);
179DEFINE_QBCM(bcm_sh3, "SH3", false, &qnm_cmpnoc);
180DEFINE_QBCM(bcm_mm3, "MM3", false, &qnm_camnoc_icp, &qnm_camnoc_sf, &qnm_video0, &qnm_video1, &qnm_video_cvp);
181DEFINE_QBCM(bcm_sh4, "SH4", false, &chm_apps);
182DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_gemnoc_sf);
183DEFINE_QBCM(bcm_co0, "CO0", false, &qns_cdsp_mem_noc);
184DEFINE_QBCM(bcm_cn0, "CN0", true, &qnm_snoc, &xm_qdss_dap, &qhs_a1_noc_cfg, &qhs_a2_noc_cfg, &qhs_ahb2phy0, &qhs_ahb2phy1, &qhs_aoss, &qhs_camera_cfg, &qhs_clk_ctl, &qhs_compute_dsp, &qhs_cpr_cx, &qhs_cpr_mmcx, &qhs_cpr_mx, &qhs_crypto0_cfg, &qhs_cx_rdpm, &qhs_dcc_cfg, &qhs_ddrss_cfg, &qhs_display_cfg, &qhs_gpuss_cfg, &qhs_imem_cfg, &qhs_ipa, &qhs_ipc_router, &qhs_lpass_cfg, &qhs_mnoc_cfg, &qhs_npu_cfg, &qhs_pcie0_cfg, &qhs_pcie1_cfg, &qhs_pcie_modem_cfg, &qhs_pdm, &qhs_pimem_cfg, &qhs_prng, &qhs_qdss_cfg, &qhs_qspi, &qhs_qup0, &qhs_qup1, &qhs_qup2, &qhs_sdc2, &qhs_sdc4, &qhs_snoc_cfg, &qhs_tcsr, &qhs_tlmm0, &qhs_tlmm1, &qhs_tlmm2, &qhs_tsif, &qhs_ufs_card_cfg, &qhs_ufs_mem_cfg, &qhs_usb3_0, &qhs_usb3_1, &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, &qns_cnoc_a2noc, &srvc_cnoc);
185DEFINE_QBCM(bcm_sn1, "SN1", false, &qxs_imem);
186DEFINE_QBCM(bcm_sn2, "SN2", false, &qns_gemnoc_gc);
187DEFINE_QBCM(bcm_co2, "CO2", false, &qnm_npu);
188DEFINE_QBCM(bcm_sn3, "SN3", false, &qxs_pimem);
189DEFINE_QBCM(bcm_sn4, "SN4", false, &xs_qdss_stm);
190DEFINE_QBCM(bcm_sn5, "SN5", false, &xs_pcie_modem);
191DEFINE_QBCM(bcm_sn6, "SN6", false, &xs_pcie_0, &xs_pcie_1);
192DEFINE_QBCM(bcm_sn7, "SN7", false, &qnm_aggre1_noc);
193DEFINE_QBCM(bcm_sn8, "SN8", false, &qnm_aggre2_noc);
194DEFINE_QBCM(bcm_sn9, "SN9", false, &qnm_gemnoc_pcie);
195DEFINE_QBCM(bcm_sn11, "SN11", false, &qnm_gemnoc);
196DEFINE_QBCM(bcm_sn12, "SN12", false, &qns_pcie_modem_mem_noc, &qns_pcie_mem_noc);
197
198static struct qcom_icc_bcm *aggre1_noc_bcms[] = {
199 &bcm_qup0,
200 &bcm_sn12,
201};
202
203static struct qcom_icc_node *aggre1_noc_nodes[] = {
204 [MASTER_A1NOC_CFG] = &qhm_a1noc_cfg,
205 [MASTER_QSPI_0] = &qhm_qspi,
206 [MASTER_QUP_1] = &qhm_qup1,
207 [MASTER_QUP_2] = &qhm_qup2,
208 [MASTER_TSIF] = &qhm_tsif,
209 [MASTER_PCIE_2] = &xm_pcie3_modem,
210 [MASTER_SDCC_4] = &xm_sdc4,
211 [MASTER_UFS_MEM] = &xm_ufs_mem,
212 [MASTER_USB3] = &xm_usb3_0,
213 [MASTER_USB3_1] = &xm_usb3_1,
214 [A1NOC_SNOC_SLV] = &qns_a1noc_snoc,
215 [SLAVE_ANOC_PCIE_GEM_NOC_1] = &qns_pcie_modem_mem_noc,
216 [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc,
217};
218
219static struct qcom_icc_desc sm8250_aggre1_noc = {
220 .nodes = aggre1_noc_nodes,
221 .num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
222 .bcms = aggre1_noc_bcms,
223 .num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
224};
225
226static struct qcom_icc_bcm *aggre2_noc_bcms[] = {
227 &bcm_ce0,
228 &bcm_qup0,
229 &bcm_sn12,
230};
231
232static struct qcom_icc_node *aggre2_noc_nodes[] = {
233 [MASTER_A2NOC_CFG] = &qhm_a2noc_cfg,
234 [MASTER_QDSS_BAM] = &qhm_qdss_bam,
235 [MASTER_QUP_0] = &qhm_qup0,
236 [MASTER_CNOC_A2NOC] = &qnm_cnoc,
237 [MASTER_CRYPTO_CORE_0] = &qxm_crypto,
238 [MASTER_IPA] = &qxm_ipa,
239 [MASTER_PCIE] = &xm_pcie3_0,
240 [MASTER_PCIE_1] = &xm_pcie3_1,
241 [MASTER_QDSS_ETR] = &xm_qdss_etr,
242 [MASTER_SDCC_2] = &xm_sdc2,
243 [MASTER_UFS_CARD] = &xm_ufs_card,
244 [A2NOC_SNOC_SLV] = &qns_a2noc_snoc,
245 [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc,
246 [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc,
247};
248
249static struct qcom_icc_desc sm8250_aggre2_noc = {
250 .nodes = aggre2_noc_nodes,
251 .num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
252 .bcms = aggre2_noc_bcms,
253 .num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
254};
255
256static struct qcom_icc_bcm *compute_noc_bcms[] = {
257 &bcm_co0,
258 &bcm_co2,
259};
260
261static struct qcom_icc_node *compute_noc_nodes[] = {
262 [MASTER_NPU] = &qnm_npu,
263 [SLAVE_CDSP_MEM_NOC] = &qns_cdsp_mem_noc,
264};
265
266static struct qcom_icc_desc sm8250_compute_noc = {
267 .nodes = compute_noc_nodes,
268 .num_nodes = ARRAY_SIZE(compute_noc_nodes),
269 .bcms = compute_noc_bcms,
270 .num_bcms = ARRAY_SIZE(compute_noc_bcms),
271};
272
273static struct qcom_icc_bcm *config_noc_bcms[] = {
274 &bcm_cn0,
275};
276
277static struct qcom_icc_node *config_noc_nodes[] = {
278 [SNOC_CNOC_MAS] = &qnm_snoc,
279 [MASTER_QDSS_DAP] = &xm_qdss_dap,
280 [SLAVE_A1NOC_CFG] = &qhs_a1_noc_cfg,
281 [SLAVE_A2NOC_CFG] = &qhs_a2_noc_cfg,
282 [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0,
283 [SLAVE_AHB2PHY_NORTH] = &qhs_ahb2phy1,
284 [SLAVE_AOSS] = &qhs_aoss,
285 [SLAVE_CAMERA_CFG] = &qhs_camera_cfg,
286 [SLAVE_CLK_CTL] = &qhs_clk_ctl,
287 [SLAVE_CDSP_CFG] = &qhs_compute_dsp,
288 [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx,
289 [SLAVE_RBCPR_MMCX_CFG] = &qhs_cpr_mmcx,
290 [SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx,
291 [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg,
292 [SLAVE_CX_RDPM] = &qhs_cx_rdpm,
293 [SLAVE_DCC_CFG] = &qhs_dcc_cfg,
294 [SLAVE_CNOC_DDRSS] = &qhs_ddrss_cfg,
295 [SLAVE_DISPLAY_CFG] = &qhs_display_cfg,
296 [SLAVE_GRAPHICS_3D_CFG] = &qhs_gpuss_cfg,
297 [SLAVE_IMEM_CFG] = &qhs_imem_cfg,
298 [SLAVE_IPA_CFG] = &qhs_ipa,
299 [SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router,
300 [SLAVE_LPASS] = &qhs_lpass_cfg,
301 [SLAVE_CNOC_MNOC_CFG] = &qhs_mnoc_cfg,
302 [SLAVE_NPU_CFG] = &qhs_npu_cfg,
303 [SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg,
304 [SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg,
305 [SLAVE_PCIE_2_CFG] = &qhs_pcie_modem_cfg,
306 [SLAVE_PDM] = &qhs_pdm,
307 [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg,
308 [SLAVE_PRNG] = &qhs_prng,
309 [SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
310 [SLAVE_QSPI_0] = &qhs_qspi,
311 [SLAVE_QUP_0] = &qhs_qup0,
312 [SLAVE_QUP_1] = &qhs_qup1,
313 [SLAVE_QUP_2] = &qhs_qup2,
314 [SLAVE_SDCC_2] = &qhs_sdc2,
315 [SLAVE_SDCC_4] = &qhs_sdc4,
316 [SLAVE_SNOC_CFG] = &qhs_snoc_cfg,
317 [SLAVE_TCSR] = &qhs_tcsr,
318 [SLAVE_TLMM_NORTH] = &qhs_tlmm0,
319 [SLAVE_TLMM_SOUTH] = &qhs_tlmm1,
320 [SLAVE_TLMM_WEST] = &qhs_tlmm2,
321 [SLAVE_TSIF] = &qhs_tsif,
322 [SLAVE_UFS_CARD_CFG] = &qhs_ufs_card_cfg,
323 [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg,
324 [SLAVE_USB3] = &qhs_usb3_0,
325 [SLAVE_USB3_1] = &qhs_usb3_1,
326 [SLAVE_VENUS_CFG] = &qhs_venus_cfg,
327 [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg,
328 [SLAVE_CNOC_A2NOC] = &qns_cnoc_a2noc,
329 [SLAVE_SERVICE_CNOC] = &srvc_cnoc,
330};
331
332static struct qcom_icc_desc sm8250_config_noc = {
333 .nodes = config_noc_nodes,
334 .num_nodes = ARRAY_SIZE(config_noc_nodes),
335 .bcms = config_noc_bcms,
336 .num_bcms = ARRAY_SIZE(config_noc_bcms),
337};
338
339static struct qcom_icc_bcm *dc_noc_bcms[] = {
340};
341
342static struct qcom_icc_node *dc_noc_nodes[] = {
343 [MASTER_CNOC_DC_NOC] = &qhm_cnoc_dc_noc,
344 [SLAVE_LLCC_CFG] = &qhs_llcc,
345 [SLAVE_GEM_NOC_CFG] = &qhs_memnoc,
346};
347
348static struct qcom_icc_desc sm8250_dc_noc = {
349 .nodes = dc_noc_nodes,
350 .num_nodes = ARRAY_SIZE(dc_noc_nodes),
351 .bcms = dc_noc_bcms,
352 .num_bcms = ARRAY_SIZE(dc_noc_bcms),
353};
354
355static struct qcom_icc_bcm *gem_noc_bcms[] = {
356 &bcm_sh0,
357 &bcm_sh2,
358 &bcm_sh3,
359 &bcm_sh4,
360};
361
362static struct qcom_icc_node *gem_noc_nodes[] = {
363 [MASTER_GPU_TCU] = &alm_gpu_tcu,
364 [MASTER_SYS_TCU] = &alm_sys_tcu,
365 [MASTER_AMPSS_M0] = &chm_apps,
366 [MASTER_GEM_NOC_CFG] = &qhm_gemnoc_cfg,
367 [MASTER_COMPUTE_NOC] = &qnm_cmpnoc,
368 [MASTER_GRAPHICS_3D] = &qnm_gpu,
369 [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf,
370 [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf,
371 [MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie,
372 [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc,
373 [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
374 [SLAVE_GEM_NOC_SNOC] = &qns_gem_noc_snoc,
375 [SLAVE_LLCC] = &qns_llcc,
376 [SLAVE_MEM_NOC_PCIE_SNOC] = &qns_sys_pcie,
377 [SLAVE_SERVICE_GEM_NOC_1] = &srvc_even_gemnoc,
378 [SLAVE_SERVICE_GEM_NOC_2] = &srvc_odd_gemnoc,
379 [SLAVE_SERVICE_GEM_NOC] = &srvc_sys_gemnoc,
380};
381
382static struct qcom_icc_desc sm8250_gem_noc = {
383 .nodes = gem_noc_nodes,
384 .num_nodes = ARRAY_SIZE(gem_noc_nodes),
385 .bcms = gem_noc_bcms,
386 .num_bcms = ARRAY_SIZE(gem_noc_bcms),
387};
388
389static struct qcom_icc_bcm *ipa_virt_bcms[] = {
390 &bcm_ip0,
391};
392
393static struct qcom_icc_node *ipa_virt_nodes[] = {
394 [MASTER_IPA_CORE] = &ipa_core_master,
395 [SLAVE_IPA_CORE] = &ipa_core_slave,
396};
397
398static struct qcom_icc_desc sm8250_ipa_virt = {
399 .nodes = ipa_virt_nodes,
400 .num_nodes = ARRAY_SIZE(ipa_virt_nodes),
401 .bcms = ipa_virt_bcms,
402 .num_bcms = ARRAY_SIZE(ipa_virt_bcms),
403};
404
405static struct qcom_icc_bcm *mc_virt_bcms[] = {
406 &bcm_acv,
407 &bcm_mc0,
408};
409
410static struct qcom_icc_node *mc_virt_nodes[] = {
411 [MASTER_LLCC] = &llcc_mc,
412 [SLAVE_EBI_CH0] = &ebi,
413};
414
415static struct qcom_icc_desc sm8250_mc_virt = {
416 .nodes = mc_virt_nodes,
417 .num_nodes = ARRAY_SIZE(mc_virt_nodes),
418 .bcms = mc_virt_bcms,
419 .num_bcms = ARRAY_SIZE(mc_virt_bcms),
420};
421
422static struct qcom_icc_bcm *mmss_noc_bcms[] = {
423 &bcm_mm0,
424 &bcm_mm1,
425 &bcm_mm2,
426 &bcm_mm3,
427};
428
429static struct qcom_icc_node *mmss_noc_nodes[] = {
430 [MASTER_CNOC_MNOC_CFG] = &qhm_mnoc_cfg,
431 [MASTER_CAMNOC_HF] = &qnm_camnoc_hf,
432 [MASTER_CAMNOC_ICP] = &qnm_camnoc_icp,
433 [MASTER_CAMNOC_SF] = &qnm_camnoc_sf,
434 [MASTER_VIDEO_P0] = &qnm_video0,
435 [MASTER_VIDEO_P1] = &qnm_video1,
436 [MASTER_VIDEO_PROC] = &qnm_video_cvp,
437 [MASTER_MDP_PORT0] = &qxm_mdp0,
438 [MASTER_MDP_PORT1] = &qxm_mdp1,
439 [MASTER_ROTATOR] = &qxm_rot,
440 [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
441 [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf,
442 [SLAVE_SERVICE_MNOC] = &srvc_mnoc,
443};
444
445static struct qcom_icc_desc sm8250_mmss_noc = {
446 .nodes = mmss_noc_nodes,
447 .num_nodes = ARRAY_SIZE(mmss_noc_nodes),
448 .bcms = mmss_noc_bcms,
449 .num_bcms = ARRAY_SIZE(mmss_noc_bcms),
450};
451
452static struct qcom_icc_bcm *npu_noc_bcms[] = {
453};
454
455static struct qcom_icc_node *npu_noc_nodes[] = {
456 [MASTER_NPU_SYS] = &amm_npu_sys,
457 [MASTER_NPU_CDP] = &amm_npu_sys_cdp_w,
458 [MASTER_NPU_NOC_CFG] = &qhm_cfg,
459 [SLAVE_NPU_CAL_DP0] = &qhs_cal_dp0,
460 [SLAVE_NPU_CAL_DP1] = &qhs_cal_dp1,
461 [SLAVE_NPU_CP] = &qhs_cp,
462 [SLAVE_NPU_INT_DMA_BWMON_CFG] = &qhs_dma_bwmon,
463 [SLAVE_NPU_DPM] = &qhs_dpm,
464 [SLAVE_ISENSE_CFG] = &qhs_isense,
465 [SLAVE_NPU_LLM_CFG] = &qhs_llm,
466 [SLAVE_NPU_TCM] = &qhs_tcm,
467 [SLAVE_NPU_COMPUTE_NOC] = &qns_npu_sys,
468 [SLAVE_SERVICE_NPU_NOC] = &srvc_noc,
469};
470
471static struct qcom_icc_desc sm8250_npu_noc = {
472 .nodes = npu_noc_nodes,
473 .num_nodes = ARRAY_SIZE(npu_noc_nodes),
474 .bcms = npu_noc_bcms,
475 .num_bcms = ARRAY_SIZE(npu_noc_bcms),
476};
477
478static struct qcom_icc_bcm *system_noc_bcms[] = {
479 &bcm_sn0,
480 &bcm_sn1,
481 &bcm_sn11,
482 &bcm_sn2,
483 &bcm_sn3,
484 &bcm_sn4,
485 &bcm_sn5,
486 &bcm_sn6,
487 &bcm_sn7,
488 &bcm_sn8,
489 &bcm_sn9,
490};
491
492static struct qcom_icc_node *system_noc_nodes[] = {
493 [MASTER_SNOC_CFG] = &qhm_snoc_cfg,
494 [A1NOC_SNOC_MAS] = &qnm_aggre1_noc,
495 [A2NOC_SNOC_MAS] = &qnm_aggre2_noc,
496 [MASTER_GEM_NOC_SNOC] = &qnm_gemnoc,
497 [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie,
498 [MASTER_PIMEM] = &qxm_pimem,
499 [MASTER_GIC] = &xm_gic,
500 [SLAVE_APPSS] = &qhs_apss,
501 [SNOC_CNOC_SLV] = &qns_cnoc,
502 [SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc,
503 [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
504 [SLAVE_OCIMEM] = &qxs_imem,
505 [SLAVE_PIMEM] = &qxs_pimem,
506 [SLAVE_SERVICE_SNOC] = &srvc_snoc,
507 [SLAVE_PCIE_0] = &xs_pcie_0,
508 [SLAVE_PCIE_1] = &xs_pcie_1,
509 [SLAVE_PCIE_2] = &xs_pcie_modem,
510 [SLAVE_QDSS_STM] = &xs_qdss_stm,
511 [SLAVE_TCU] = &xs_sys_tcu_cfg,
512};
513
514static struct qcom_icc_desc sm8250_system_noc = {
515 .nodes = system_noc_nodes,
516 .num_nodes = ARRAY_SIZE(system_noc_nodes),
517 .bcms = system_noc_bcms,
518 .num_bcms = ARRAY_SIZE(system_noc_bcms),
519};
520
521static const struct of_device_id qnoc_of_match[] = {
522 { .compatible = "qcom,sm8250-aggre1-noc",
523 .data = &sm8250_aggre1_noc},
524 { .compatible = "qcom,sm8250-aggre2-noc",
525 .data = &sm8250_aggre2_noc},
526 { .compatible = "qcom,sm8250-compute-noc",
527 .data = &sm8250_compute_noc},
528 { .compatible = "qcom,sm8250-config-noc",
529 .data = &sm8250_config_noc},
530 { .compatible = "qcom,sm8250-dc-noc",
531 .data = &sm8250_dc_noc},
532 { .compatible = "qcom,sm8250-gem-noc",
533 .data = &sm8250_gem_noc},
534 { .compatible = "qcom,sm8250-ipa-virt",
535 .data = &sm8250_ipa_virt},
536 { .compatible = "qcom,sm8250-mc-virt",
537 .data = &sm8250_mc_virt},
538 { .compatible = "qcom,sm8250-mmss-noc",
539 .data = &sm8250_mmss_noc},
540 { .compatible = "qcom,sm8250-npu-noc",
541 .data = &sm8250_npu_noc},
542 { .compatible = "qcom,sm8250-system-noc",
543 .data = &sm8250_system_noc},
544 { }
545};
546MODULE_DEVICE_TABLE(of, qnoc_of_match);
547
548static struct platform_driver qnoc_driver = {
549 .probe = qcom_icc_rpmh_probe,
550 .remove = qcom_icc_rpmh_remove,
551 .driver = {
552 .name = "qnoc-sm8250",
553 .of_match_table = qnoc_of_match,
554 },
555};
556module_platform_driver(qnoc_driver);
557
558MODULE_DESCRIPTION("Qualcomm SM8250 NoC driver");
559MODULE_LICENSE("GPL v2");
560
