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12#include <dt-bindings/firmware/imx/rsrc.h>
13#include <linux/bitfield.h>
14#include <linux/can.h>
15#include <linux/can/dev.h>
16#include <linux/can/error.h>
17#include <linux/can/led.h>
18#include <linux/clk.h>
19#include <linux/delay.h>
20#include <linux/firmware/imx/sci.h>
21#include <linux/interrupt.h>
22#include <linux/io.h>
23#include <linux/mfd/syscon.h>
24#include <linux/module.h>
25#include <linux/netdevice.h>
26#include <linux/of.h>
27#include <linux/of_device.h>
28#include <linux/pinctrl/consumer.h>
29#include <linux/platform_device.h>
30#include <linux/can/platform/flexcan.h>
31#include <linux/pm_runtime.h>
32#include <linux/regmap.h>
33#include <linux/regulator/consumer.h>
34
35#include "flexcan.h"
36
37#define DRV_NAME "flexcan"
38
39
40#define FLEXCAN_NAPI_WEIGHT (8 + 2)
41
42
43#define FLEXCAN_MCR_MDIS BIT(31)
44#define FLEXCAN_MCR_FRZ BIT(30)
45#define FLEXCAN_MCR_FEN BIT(29)
46#define FLEXCAN_MCR_HALT BIT(28)
47#define FLEXCAN_MCR_NOT_RDY BIT(27)
48#define FLEXCAN_MCR_WAK_MSK BIT(26)
49#define FLEXCAN_MCR_SOFTRST BIT(25)
50#define FLEXCAN_MCR_FRZ_ACK BIT(24)
51#define FLEXCAN_MCR_SUPV BIT(23)
52#define FLEXCAN_MCR_SLF_WAK BIT(22)
53#define FLEXCAN_MCR_WRN_EN BIT(21)
54#define FLEXCAN_MCR_LPM_ACK BIT(20)
55#define FLEXCAN_MCR_WAK_SRC BIT(19)
56#define FLEXCAN_MCR_DOZE BIT(18)
57#define FLEXCAN_MCR_SRX_DIS BIT(17)
58#define FLEXCAN_MCR_IRMQ BIT(16)
59#define FLEXCAN_MCR_LPRIO_EN BIT(13)
60#define FLEXCAN_MCR_AEN BIT(12)
61#define FLEXCAN_MCR_FDEN BIT(11)
62
63#define FLEXCAN_MCR_MAXMB(x) ((x) & 0x7f)
64#define FLEXCAN_MCR_IDAM_A (0x0 << 8)
65#define FLEXCAN_MCR_IDAM_B (0x1 << 8)
66#define FLEXCAN_MCR_IDAM_C (0x2 << 8)
67#define FLEXCAN_MCR_IDAM_D (0x3 << 8)
68
69
70#define FLEXCAN_CTRL_PRESDIV(x) (((x) & 0xff) << 24)
71#define FLEXCAN_CTRL_RJW(x) (((x) & 0x03) << 22)
72#define FLEXCAN_CTRL_PSEG1(x) (((x) & 0x07) << 19)
73#define FLEXCAN_CTRL_PSEG2(x) (((x) & 0x07) << 16)
74#define FLEXCAN_CTRL_BOFF_MSK BIT(15)
75#define FLEXCAN_CTRL_ERR_MSK BIT(14)
76#define FLEXCAN_CTRL_CLK_SRC BIT(13)
77#define FLEXCAN_CTRL_LPB BIT(12)
78#define FLEXCAN_CTRL_TWRN_MSK BIT(11)
79#define FLEXCAN_CTRL_RWRN_MSK BIT(10)
80#define FLEXCAN_CTRL_SMP BIT(7)
81#define FLEXCAN_CTRL_BOFF_REC BIT(6)
82#define FLEXCAN_CTRL_TSYN BIT(5)
83#define FLEXCAN_CTRL_LBUF BIT(4)
84#define FLEXCAN_CTRL_LOM BIT(3)
85#define FLEXCAN_CTRL_PROPSEG(x) ((x) & 0x07)
86#define FLEXCAN_CTRL_ERR_BUS (FLEXCAN_CTRL_ERR_MSK)
87#define FLEXCAN_CTRL_ERR_STATE \
88 (FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \
89 FLEXCAN_CTRL_BOFF_MSK)
90#define FLEXCAN_CTRL_ERR_ALL \
91 (FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE)
92
93
94#define FLEXCAN_CTRL2_ECRWRE BIT(29)
95#define FLEXCAN_CTRL2_WRMFRZ BIT(28)
96#define FLEXCAN_CTRL2_RFFN(x) (((x) & 0x0f) << 24)
97#define FLEXCAN_CTRL2_TASD(x) (((x) & 0x1f) << 19)
98#define FLEXCAN_CTRL2_MRP BIT(18)
99#define FLEXCAN_CTRL2_RRS BIT(17)
100#define FLEXCAN_CTRL2_EACEN BIT(16)
101#define FLEXCAN_CTRL2_ISOCANFDEN BIT(12)
102
103
104#define FLEXCAN_MECR_ECRWRDIS BIT(31)
105#define FLEXCAN_MECR_HANCEI_MSK BIT(19)
106#define FLEXCAN_MECR_FANCEI_MSK BIT(18)
107#define FLEXCAN_MECR_CEI_MSK BIT(16)
108#define FLEXCAN_MECR_HAERRIE BIT(15)
109#define FLEXCAN_MECR_FAERRIE BIT(14)
110#define FLEXCAN_MECR_EXTERRIE BIT(13)
111#define FLEXCAN_MECR_RERRDIS BIT(9)
112#define FLEXCAN_MECR_ECCDIS BIT(8)
113#define FLEXCAN_MECR_NCEFAFRZ BIT(7)
114
115
116#define FLEXCAN_ESR_TWRN_INT BIT(17)
117#define FLEXCAN_ESR_RWRN_INT BIT(16)
118#define FLEXCAN_ESR_BIT1_ERR BIT(15)
119#define FLEXCAN_ESR_BIT0_ERR BIT(14)
120#define FLEXCAN_ESR_ACK_ERR BIT(13)
121#define FLEXCAN_ESR_CRC_ERR BIT(12)
122#define FLEXCAN_ESR_FRM_ERR BIT(11)
123#define FLEXCAN_ESR_STF_ERR BIT(10)
124#define FLEXCAN_ESR_TX_WRN BIT(9)
125#define FLEXCAN_ESR_RX_WRN BIT(8)
126#define FLEXCAN_ESR_IDLE BIT(7)
127#define FLEXCAN_ESR_TXRX BIT(6)
128#define FLEXCAN_EST_FLT_CONF_SHIFT (4)
129#define FLEXCAN_ESR_FLT_CONF_MASK (0x3 << FLEXCAN_EST_FLT_CONF_SHIFT)
130#define FLEXCAN_ESR_FLT_CONF_ACTIVE (0x0 << FLEXCAN_EST_FLT_CONF_SHIFT)
131#define FLEXCAN_ESR_FLT_CONF_PASSIVE (0x1 << FLEXCAN_EST_FLT_CONF_SHIFT)
132#define FLEXCAN_ESR_BOFF_INT BIT(2)
133#define FLEXCAN_ESR_ERR_INT BIT(1)
134#define FLEXCAN_ESR_WAK_INT BIT(0)
135#define FLEXCAN_ESR_ERR_BUS \
136 (FLEXCAN_ESR_BIT1_ERR | FLEXCAN_ESR_BIT0_ERR | \
137 FLEXCAN_ESR_ACK_ERR | FLEXCAN_ESR_CRC_ERR | \
138 FLEXCAN_ESR_FRM_ERR | FLEXCAN_ESR_STF_ERR)
139#define FLEXCAN_ESR_ERR_STATE \
140 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | FLEXCAN_ESR_BOFF_INT)
141#define FLEXCAN_ESR_ERR_ALL \
142 (FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE)
143#define FLEXCAN_ESR_ALL_INT \
144 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | \
145 FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT)
146
147
148#define FLEXCAN_CBT_BTF BIT(31)
149#define FLEXCAN_CBT_EPRESDIV_MASK GENMASK(30, 21)
150#define FLEXCAN_CBT_ERJW_MASK GENMASK(20, 16)
151#define FLEXCAN_CBT_EPROPSEG_MASK GENMASK(15, 10)
152#define FLEXCAN_CBT_EPSEG1_MASK GENMASK(9, 5)
153#define FLEXCAN_CBT_EPSEG2_MASK GENMASK(4, 0)
154
155
156#define FLEXCAN_FDCTRL_FDRATE BIT(31)
157#define FLEXCAN_FDCTRL_MBDSR1 GENMASK(20, 19)
158#define FLEXCAN_FDCTRL_MBDSR0 GENMASK(17, 16)
159#define FLEXCAN_FDCTRL_MBDSR_8 0x0
160#define FLEXCAN_FDCTRL_MBDSR_12 0x1
161#define FLEXCAN_FDCTRL_MBDSR_32 0x2
162#define FLEXCAN_FDCTRL_MBDSR_64 0x3
163#define FLEXCAN_FDCTRL_TDCEN BIT(15)
164#define FLEXCAN_FDCTRL_TDCFAIL BIT(14)
165#define FLEXCAN_FDCTRL_TDCOFF GENMASK(12, 8)
166#define FLEXCAN_FDCTRL_TDCVAL GENMASK(5, 0)
167
168
169#define FLEXCAN_FDCBT_FPRESDIV_MASK GENMASK(29, 20)
170#define FLEXCAN_FDCBT_FRJW_MASK GENMASK(18, 16)
171#define FLEXCAN_FDCBT_FPROPSEG_MASK GENMASK(14, 10)
172#define FLEXCAN_FDCBT_FPSEG1_MASK GENMASK(7, 5)
173#define FLEXCAN_FDCBT_FPSEG2_MASK GENMASK(2, 0)
174
175
176
177#define FLEXCAN_TX_MB_RESERVED_RX_FIFO 8
178#define FLEXCAN_TX_MB_RESERVED_RX_MAILBOX 0
179#define FLEXCAN_RX_MB_RX_MAILBOX_FIRST (FLEXCAN_TX_MB_RESERVED_RX_MAILBOX + 1)
180#define FLEXCAN_IFLAG_MB(x) BIT_ULL(x)
181#define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW BIT(7)
182#define FLEXCAN_IFLAG_RX_FIFO_WARN BIT(6)
183#define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE BIT(5)
184
185
186#define FLEXCAN_MB_CODE_MASK (0xf << 24)
187#define FLEXCAN_MB_CODE_RX_BUSY_BIT (0x1 << 24)
188#define FLEXCAN_MB_CODE_RX_INACTIVE (0x0 << 24)
189#define FLEXCAN_MB_CODE_RX_EMPTY (0x4 << 24)
190#define FLEXCAN_MB_CODE_RX_FULL (0x2 << 24)
191#define FLEXCAN_MB_CODE_RX_OVERRUN (0x6 << 24)
192#define FLEXCAN_MB_CODE_RX_RANSWER (0xa << 24)
193
194#define FLEXCAN_MB_CODE_TX_INACTIVE (0x8 << 24)
195#define FLEXCAN_MB_CODE_TX_ABORT (0x9 << 24)
196#define FLEXCAN_MB_CODE_TX_DATA (0xc << 24)
197#define FLEXCAN_MB_CODE_TX_TANSWER (0xe << 24)
198
199#define FLEXCAN_MB_CNT_EDL BIT(31)
200#define FLEXCAN_MB_CNT_BRS BIT(30)
201#define FLEXCAN_MB_CNT_ESI BIT(29)
202#define FLEXCAN_MB_CNT_SRR BIT(22)
203#define FLEXCAN_MB_CNT_IDE BIT(21)
204#define FLEXCAN_MB_CNT_RTR BIT(20)
205#define FLEXCAN_MB_CNT_LENGTH(x) (((x) & 0xf) << 16)
206#define FLEXCAN_MB_CNT_TIMESTAMP(x) ((x) & 0xffff)
207
208#define FLEXCAN_TIMEOUT_US (250)
209
210
211struct flexcan_mb {
212 u32 can_ctrl;
213 u32 can_id;
214 u32 data[];
215};
216
217
218struct flexcan_regs {
219 u32 mcr;
220 u32 ctrl;
221 u32 timer;
222 u32 tcr;
223 u32 rxgmask;
224 u32 rx14mask;
225 u32 rx15mask;
226 u32 ecr;
227 u32 esr;
228 u32 imask2;
229 u32 imask1;
230 u32 iflag2;
231 u32 iflag1;
232 union {
233 u32 gfwr_mx28;
234 u32 ctrl2;
235 };
236 u32 esr2;
237 u32 imeur;
238 u32 lrfr;
239 u32 crcr;
240 u32 rxfgmask;
241 u32 rxfir;
242 u32 cbt;
243 u32 _reserved2;
244 u32 dbg1;
245 u32 dbg2;
246 u32 _reserved3[8];
247 struct_group(init,
248 u8 mb[2][512];
249
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259 u32 _reserved4[256];
260 u32 rximr[64];
261 u32 _reserved5[24];
262 u32 gfwr_mx6;
263 u32 _reserved6[39];
264 u32 _rxfir[6];
265 u32 _reserved8[2];
266 u32 _rxmgmask;
267 u32 _rxfgmask;
268 u32 _rx14mask;
269 u32 _rx15mask;
270 u32 tx_smb[4];
271 u32 rx_smb0[4];
272 u32 rx_smb1[4];
273 );
274 u32 mecr;
275 u32 erriar;
276 u32 erridpr;
277 u32 errippr;
278 u32 rerrar;
279 u32 rerrdr;
280 u32 rerrsynr;
281 u32 errsr;
282 u32 _reserved7[64];
283 u32 fdctrl;
284 u32 fdcbt;
285 u32 fdcrc;
286 u32 _reserved9[199];
287 struct_group(init_fd,
288 u32 tx_smb_fd[18];
289 u32 rx_smb0_fd[18];
290 u32 rx_smb1_fd[18];
291 );
292};
293
294static_assert(sizeof(struct flexcan_regs) == 0x4 * 18 + 0xfb8);
295
296static const struct flexcan_devtype_data fsl_mcf5441x_devtype_data = {
297 .quirks = FLEXCAN_QUIRK_BROKEN_PERR_STATE |
298 FLEXCAN_QUIRK_NR_IRQ_3 | FLEXCAN_QUIRK_NR_MB_16 |
299 FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX |
300 FLEXCAN_QUIRK_SUPPPORT_RX_FIFO,
301};
302
303static const struct flexcan_devtype_data fsl_p1010_devtype_data = {
304 .quirks = FLEXCAN_QUIRK_BROKEN_WERR_STATE |
305 FLEXCAN_QUIRK_BROKEN_PERR_STATE |
306 FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN |
307 FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX |
308 FLEXCAN_QUIRK_SUPPPORT_RX_FIFO,
309};
310
311static const struct flexcan_devtype_data fsl_imx25_devtype_data = {
312 .quirks = FLEXCAN_QUIRK_BROKEN_WERR_STATE |
313 FLEXCAN_QUIRK_BROKEN_PERR_STATE |
314 FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX |
315 FLEXCAN_QUIRK_SUPPPORT_RX_FIFO,
316};
317
318static const struct flexcan_devtype_data fsl_imx28_devtype_data = {
319 .quirks = FLEXCAN_QUIRK_BROKEN_PERR_STATE |
320 FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX |
321 FLEXCAN_QUIRK_SUPPPORT_RX_FIFO,
322};
323
324static const struct flexcan_devtype_data fsl_imx6q_devtype_data = {
325 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
326 FLEXCAN_QUIRK_USE_RX_MAILBOX | FLEXCAN_QUIRK_BROKEN_PERR_STATE |
327 FLEXCAN_QUIRK_SETUP_STOP_MODE_GPR |
328 FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX |
329 FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX_RTR,
330};
331
332static const struct flexcan_devtype_data fsl_imx8qm_devtype_data = {
333 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
334 FLEXCAN_QUIRK_USE_RX_MAILBOX | FLEXCAN_QUIRK_BROKEN_PERR_STATE |
335 FLEXCAN_QUIRK_SUPPORT_FD | FLEXCAN_QUIRK_SETUP_STOP_MODE_SCFW |
336 FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX |
337 FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX_RTR,
338};
339
340static struct flexcan_devtype_data fsl_imx8mp_devtype_data = {
341 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
342 FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_USE_RX_MAILBOX |
343 FLEXCAN_QUIRK_BROKEN_PERR_STATE | FLEXCAN_QUIRK_SETUP_STOP_MODE_GPR |
344 FLEXCAN_QUIRK_SUPPORT_FD | FLEXCAN_QUIRK_SUPPORT_ECC |
345 FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX |
346 FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX_RTR,
347};
348
349static const struct flexcan_devtype_data fsl_vf610_devtype_data = {
350 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
351 FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_USE_RX_MAILBOX |
352 FLEXCAN_QUIRK_BROKEN_PERR_STATE | FLEXCAN_QUIRK_SUPPORT_ECC |
353 FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX |
354 FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX_RTR,
355};
356
357static const struct flexcan_devtype_data fsl_ls1021a_r2_devtype_data = {
358 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
359 FLEXCAN_QUIRK_BROKEN_PERR_STATE | FLEXCAN_QUIRK_USE_RX_MAILBOX |
360 FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX |
361 FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX_RTR,
362};
363
364static const struct flexcan_devtype_data fsl_lx2160a_r1_devtype_data = {
365 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
366 FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_BROKEN_PERR_STATE |
367 FLEXCAN_QUIRK_USE_RX_MAILBOX | FLEXCAN_QUIRK_SUPPORT_FD |
368 FLEXCAN_QUIRK_SUPPORT_ECC |
369 FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX |
370 FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX_RTR,
371};
372
373static const struct can_bittiming_const flexcan_bittiming_const = {
374 .name = DRV_NAME,
375 .tseg1_min = 4,
376 .tseg1_max = 16,
377 .tseg2_min = 2,
378 .tseg2_max = 8,
379 .sjw_max = 4,
380 .brp_min = 1,
381 .brp_max = 256,
382 .brp_inc = 1,
383};
384
385static const struct can_bittiming_const flexcan_fd_bittiming_const = {
386 .name = DRV_NAME,
387 .tseg1_min = 2,
388 .tseg1_max = 96,
389 .tseg2_min = 2,
390 .tseg2_max = 32,
391 .sjw_max = 16,
392 .brp_min = 1,
393 .brp_max = 1024,
394 .brp_inc = 1,
395};
396
397static const struct can_bittiming_const flexcan_fd_data_bittiming_const = {
398 .name = DRV_NAME,
399 .tseg1_min = 2,
400 .tseg1_max = 39,
401 .tseg2_min = 2,
402 .tseg2_max = 8,
403 .sjw_max = 4,
404 .brp_min = 1,
405 .brp_max = 1024,
406 .brp_inc = 1,
407};
408
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420
421
422static inline u32 flexcan_read_be(void __iomem *addr)
423{
424 return ioread32be(addr);
425}
426
427static inline void flexcan_write_be(u32 val, void __iomem *addr)
428{
429 iowrite32be(val, addr);
430}
431
432static inline u32 flexcan_read_le(void __iomem *addr)
433{
434 return ioread32(addr);
435}
436
437static inline void flexcan_write_le(u32 val, void __iomem *addr)
438{
439 iowrite32(val, addr);
440}
441
442static struct flexcan_mb __iomem *flexcan_get_mb(const struct flexcan_priv *priv,
443 u8 mb_index)
444{
445 u8 bank_size;
446 bool bank;
447
448 if (WARN_ON(mb_index >= priv->mb_count))
449 return NULL;
450
451 bank_size = sizeof(priv->regs->mb[0]) / priv->mb_size;
452
453 bank = mb_index >= bank_size;
454 if (bank)
455 mb_index -= bank_size;
456
457 return (struct flexcan_mb __iomem *)
458 (&priv->regs->mb[bank][priv->mb_size * mb_index]);
459}
460
461static int flexcan_low_power_enter_ack(struct flexcan_priv *priv)
462{
463 struct flexcan_regs __iomem *regs = priv->regs;
464 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
465
466 while (timeout-- && !(priv->read(®s->mcr) & FLEXCAN_MCR_LPM_ACK))
467 udelay(10);
468
469 if (!(priv->read(®s->mcr) & FLEXCAN_MCR_LPM_ACK))
470 return -ETIMEDOUT;
471
472 return 0;
473}
474
475static int flexcan_low_power_exit_ack(struct flexcan_priv *priv)
476{
477 struct flexcan_regs __iomem *regs = priv->regs;
478 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
479
480 while (timeout-- && (priv->read(®s->mcr) & FLEXCAN_MCR_LPM_ACK))
481 udelay(10);
482
483 if (priv->read(®s->mcr) & FLEXCAN_MCR_LPM_ACK)
484 return -ETIMEDOUT;
485
486 return 0;
487}
488
489static void flexcan_enable_wakeup_irq(struct flexcan_priv *priv, bool enable)
490{
491 struct flexcan_regs __iomem *regs = priv->regs;
492 u32 reg_mcr;
493
494 reg_mcr = priv->read(®s->mcr);
495
496 if (enable)
497 reg_mcr |= FLEXCAN_MCR_WAK_MSK;
498 else
499 reg_mcr &= ~FLEXCAN_MCR_WAK_MSK;
500
501 priv->write(reg_mcr, ®s->mcr);
502}
503
504static int flexcan_stop_mode_enable_scfw(struct flexcan_priv *priv, bool enabled)
505{
506 u8 idx = priv->scu_idx;
507 u32 rsrc_id, val;
508
509 rsrc_id = IMX_SC_R_CAN(idx);
510
511 if (enabled)
512 val = 1;
513 else
514 val = 0;
515
516
517 return imx_sc_misc_set_control(priv->sc_ipc_handle, rsrc_id,
518 IMX_SC_C_IPG_STOP, val);
519}
520
521static inline int flexcan_enter_stop_mode(struct flexcan_priv *priv)
522{
523 struct flexcan_regs __iomem *regs = priv->regs;
524 u32 reg_mcr;
525 int ret;
526
527 reg_mcr = priv->read(®s->mcr);
528 reg_mcr |= FLEXCAN_MCR_SLF_WAK;
529 priv->write(reg_mcr, ®s->mcr);
530
531
532 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE_SCFW) {
533 ret = flexcan_stop_mode_enable_scfw(priv, true);
534 if (ret < 0)
535 return ret;
536 } else {
537 regmap_update_bits(priv->stm.gpr, priv->stm.req_gpr,
538 1 << priv->stm.req_bit, 1 << priv->stm.req_bit);
539 }
540
541 return flexcan_low_power_enter_ack(priv);
542}
543
544static inline int flexcan_exit_stop_mode(struct flexcan_priv *priv)
545{
546 struct flexcan_regs __iomem *regs = priv->regs;
547 u32 reg_mcr;
548 int ret;
549
550
551 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE_SCFW) {
552 ret = flexcan_stop_mode_enable_scfw(priv, false);
553 if (ret < 0)
554 return ret;
555 } else {
556 regmap_update_bits(priv->stm.gpr, priv->stm.req_gpr,
557 1 << priv->stm.req_bit, 0);
558 }
559
560 reg_mcr = priv->read(®s->mcr);
561 reg_mcr &= ~FLEXCAN_MCR_SLF_WAK;
562 priv->write(reg_mcr, ®s->mcr);
563
564 return flexcan_low_power_exit_ack(priv);
565}
566
567static inline void flexcan_error_irq_enable(const struct flexcan_priv *priv)
568{
569 struct flexcan_regs __iomem *regs = priv->regs;
570 u32 reg_ctrl = (priv->reg_ctrl_default | FLEXCAN_CTRL_ERR_MSK);
571
572 priv->write(reg_ctrl, ®s->ctrl);
573}
574
575static inline void flexcan_error_irq_disable(const struct flexcan_priv *priv)
576{
577 struct flexcan_regs __iomem *regs = priv->regs;
578 u32 reg_ctrl = (priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_MSK);
579
580 priv->write(reg_ctrl, ®s->ctrl);
581}
582
583static int flexcan_clks_enable(const struct flexcan_priv *priv)
584{
585 int err = 0;
586
587 if (priv->clk_ipg) {
588 err = clk_prepare_enable(priv->clk_ipg);
589 if (err)
590 return err;
591 }
592
593 if (priv->clk_per) {
594 err = clk_prepare_enable(priv->clk_per);
595 if (err)
596 clk_disable_unprepare(priv->clk_ipg);
597 }
598
599 return err;
600}
601
602static void flexcan_clks_disable(const struct flexcan_priv *priv)
603{
604 clk_disable_unprepare(priv->clk_per);
605 clk_disable_unprepare(priv->clk_ipg);
606}
607
608static inline int flexcan_transceiver_enable(const struct flexcan_priv *priv)
609{
610 if (!priv->reg_xceiver)
611 return 0;
612
613 return regulator_enable(priv->reg_xceiver);
614}
615
616static inline int flexcan_transceiver_disable(const struct flexcan_priv *priv)
617{
618 if (!priv->reg_xceiver)
619 return 0;
620
621 return regulator_disable(priv->reg_xceiver);
622}
623
624static int flexcan_chip_enable(struct flexcan_priv *priv)
625{
626 struct flexcan_regs __iomem *regs = priv->regs;
627 u32 reg;
628
629 reg = priv->read(®s->mcr);
630 reg &= ~FLEXCAN_MCR_MDIS;
631 priv->write(reg, ®s->mcr);
632
633 return flexcan_low_power_exit_ack(priv);
634}
635
636static int flexcan_chip_disable(struct flexcan_priv *priv)
637{
638 struct flexcan_regs __iomem *regs = priv->regs;
639 u32 reg;
640
641 reg = priv->read(®s->mcr);
642 reg |= FLEXCAN_MCR_MDIS;
643 priv->write(reg, ®s->mcr);
644
645 return flexcan_low_power_enter_ack(priv);
646}
647
648static int flexcan_chip_freeze(struct flexcan_priv *priv)
649{
650 struct flexcan_regs __iomem *regs = priv->regs;
651 unsigned int timeout;
652 u32 bitrate = priv->can.bittiming.bitrate;
653 u32 reg;
654
655 if (bitrate)
656 timeout = 1000 * 1000 * 10 / bitrate;
657 else
658 timeout = FLEXCAN_TIMEOUT_US / 10;
659
660 reg = priv->read(®s->mcr);
661 reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT;
662 priv->write(reg, ®s->mcr);
663
664 while (timeout-- && !(priv->read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK))
665 udelay(100);
666
667 if (!(priv->read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK))
668 return -ETIMEDOUT;
669
670 return 0;
671}
672
673static int flexcan_chip_unfreeze(struct flexcan_priv *priv)
674{
675 struct flexcan_regs __iomem *regs = priv->regs;
676 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
677 u32 reg;
678
679 reg = priv->read(®s->mcr);
680 reg &= ~FLEXCAN_MCR_HALT;
681 priv->write(reg, ®s->mcr);
682
683 while (timeout-- && (priv->read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK))
684 udelay(10);
685
686 if (priv->read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK)
687 return -ETIMEDOUT;
688
689 return 0;
690}
691
692static int flexcan_chip_softreset(struct flexcan_priv *priv)
693{
694 struct flexcan_regs __iomem *regs = priv->regs;
695 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
696
697 priv->write(FLEXCAN_MCR_SOFTRST, ®s->mcr);
698 while (timeout-- && (priv->read(®s->mcr) & FLEXCAN_MCR_SOFTRST))
699 udelay(10);
700
701 if (priv->read(®s->mcr) & FLEXCAN_MCR_SOFTRST)
702 return -ETIMEDOUT;
703
704 return 0;
705}
706
707static int __flexcan_get_berr_counter(const struct net_device *dev,
708 struct can_berr_counter *bec)
709{
710 const struct flexcan_priv *priv = netdev_priv(dev);
711 struct flexcan_regs __iomem *regs = priv->regs;
712 u32 reg = priv->read(®s->ecr);
713
714 bec->txerr = (reg >> 0) & 0xff;
715 bec->rxerr = (reg >> 8) & 0xff;
716
717 return 0;
718}
719
720static int flexcan_get_berr_counter(const struct net_device *dev,
721 struct can_berr_counter *bec)
722{
723 const struct flexcan_priv *priv = netdev_priv(dev);
724 int err;
725
726 err = pm_runtime_get_sync(priv->dev);
727 if (err < 0) {
728 pm_runtime_put_noidle(priv->dev);
729 return err;
730 }
731
732 err = __flexcan_get_berr_counter(dev, bec);
733
734 pm_runtime_put(priv->dev);
735
736 return err;
737}
738
739static netdev_tx_t flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev)
740{
741 const struct flexcan_priv *priv = netdev_priv(dev);
742 struct canfd_frame *cfd = (struct canfd_frame *)skb->data;
743 u32 can_id;
744 u32 data;
745 u32 ctrl = FLEXCAN_MB_CODE_TX_DATA | ((can_fd_len2dlc(cfd->len)) << 16);
746 int i;
747
748 if (can_dropped_invalid_skb(dev, skb))
749 return NETDEV_TX_OK;
750
751 netif_stop_queue(dev);
752
753 if (cfd->can_id & CAN_EFF_FLAG) {
754 can_id = cfd->can_id & CAN_EFF_MASK;
755 ctrl |= FLEXCAN_MB_CNT_IDE | FLEXCAN_MB_CNT_SRR;
756 } else {
757 can_id = (cfd->can_id & CAN_SFF_MASK) << 18;
758 }
759
760 if (cfd->can_id & CAN_RTR_FLAG)
761 ctrl |= FLEXCAN_MB_CNT_RTR;
762
763 if (can_is_canfd_skb(skb)) {
764 ctrl |= FLEXCAN_MB_CNT_EDL;
765
766 if (cfd->flags & CANFD_BRS)
767 ctrl |= FLEXCAN_MB_CNT_BRS;
768 }
769
770 for (i = 0; i < cfd->len; i += sizeof(u32)) {
771 data = be32_to_cpup((__be32 *)&cfd->data[i]);
772 priv->write(data, &priv->tx_mb->data[i / sizeof(u32)]);
773 }
774
775 can_put_echo_skb(skb, dev, 0, 0);
776
777 priv->write(can_id, &priv->tx_mb->can_id);
778 priv->write(ctrl, &priv->tx_mb->can_ctrl);
779
780
781
782
783 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
784 &priv->tx_mb_reserved->can_ctrl);
785 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
786 &priv->tx_mb_reserved->can_ctrl);
787
788 return NETDEV_TX_OK;
789}
790
791static void flexcan_irq_bus_err(struct net_device *dev, u32 reg_esr)
792{
793 struct flexcan_priv *priv = netdev_priv(dev);
794 struct flexcan_regs __iomem *regs = priv->regs;
795 struct sk_buff *skb;
796 struct can_frame *cf;
797 bool rx_errors = false, tx_errors = false;
798 u32 timestamp;
799 int err;
800
801 timestamp = priv->read(®s->timer) << 16;
802
803 skb = alloc_can_err_skb(dev, &cf);
804 if (unlikely(!skb))
805 return;
806
807 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
808
809 if (reg_esr & FLEXCAN_ESR_BIT1_ERR) {
810 netdev_dbg(dev, "BIT1_ERR irq\n");
811 cf->data[2] |= CAN_ERR_PROT_BIT1;
812 tx_errors = true;
813 }
814 if (reg_esr & FLEXCAN_ESR_BIT0_ERR) {
815 netdev_dbg(dev, "BIT0_ERR irq\n");
816 cf->data[2] |= CAN_ERR_PROT_BIT0;
817 tx_errors = true;
818 }
819 if (reg_esr & FLEXCAN_ESR_ACK_ERR) {
820 netdev_dbg(dev, "ACK_ERR irq\n");
821 cf->can_id |= CAN_ERR_ACK;
822 cf->data[3] = CAN_ERR_PROT_LOC_ACK;
823 tx_errors = true;
824 }
825 if (reg_esr & FLEXCAN_ESR_CRC_ERR) {
826 netdev_dbg(dev, "CRC_ERR irq\n");
827 cf->data[2] |= CAN_ERR_PROT_BIT;
828 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ;
829 rx_errors = true;
830 }
831 if (reg_esr & FLEXCAN_ESR_FRM_ERR) {
832 netdev_dbg(dev, "FRM_ERR irq\n");
833 cf->data[2] |= CAN_ERR_PROT_FORM;
834 rx_errors = true;
835 }
836 if (reg_esr & FLEXCAN_ESR_STF_ERR) {
837 netdev_dbg(dev, "STF_ERR irq\n");
838 cf->data[2] |= CAN_ERR_PROT_STUFF;
839 rx_errors = true;
840 }
841
842 priv->can.can_stats.bus_error++;
843 if (rx_errors)
844 dev->stats.rx_errors++;
845 if (tx_errors)
846 dev->stats.tx_errors++;
847
848 err = can_rx_offload_queue_sorted(&priv->offload, skb, timestamp);
849 if (err)
850 dev->stats.rx_fifo_errors++;
851}
852
853static void flexcan_irq_state(struct net_device *dev, u32 reg_esr)
854{
855 struct flexcan_priv *priv = netdev_priv(dev);
856 struct flexcan_regs __iomem *regs = priv->regs;
857 struct sk_buff *skb;
858 struct can_frame *cf;
859 enum can_state new_state, rx_state, tx_state;
860 int flt;
861 struct can_berr_counter bec;
862 u32 timestamp;
863 int err;
864
865 flt = reg_esr & FLEXCAN_ESR_FLT_CONF_MASK;
866 if (likely(flt == FLEXCAN_ESR_FLT_CONF_ACTIVE)) {
867 tx_state = unlikely(reg_esr & FLEXCAN_ESR_TX_WRN) ?
868 CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE;
869 rx_state = unlikely(reg_esr & FLEXCAN_ESR_RX_WRN) ?
870 CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE;
871 new_state = max(tx_state, rx_state);
872 } else {
873 __flexcan_get_berr_counter(dev, &bec);
874 new_state = flt == FLEXCAN_ESR_FLT_CONF_PASSIVE ?
875 CAN_STATE_ERROR_PASSIVE : CAN_STATE_BUS_OFF;
876 rx_state = bec.rxerr >= bec.txerr ? new_state : 0;
877 tx_state = bec.rxerr <= bec.txerr ? new_state : 0;
878 }
879
880
881 if (likely(new_state == priv->can.state))
882 return;
883
884 timestamp = priv->read(®s->timer) << 16;
885
886 skb = alloc_can_err_skb(dev, &cf);
887 if (unlikely(!skb))
888 return;
889
890 can_change_state(dev, cf, tx_state, rx_state);
891
892 if (unlikely(new_state == CAN_STATE_BUS_OFF))
893 can_bus_off(dev);
894
895 err = can_rx_offload_queue_sorted(&priv->offload, skb, timestamp);
896 if (err)
897 dev->stats.rx_fifo_errors++;
898}
899
900static inline u64 flexcan_read64_mask(struct flexcan_priv *priv, void __iomem *addr, u64 mask)
901{
902 u64 reg = 0;
903
904 if (upper_32_bits(mask))
905 reg = (u64)priv->read(addr - 4) << 32;
906 if (lower_32_bits(mask))
907 reg |= priv->read(addr);
908
909 return reg & mask;
910}
911
912static inline void flexcan_write64(struct flexcan_priv *priv, u64 val, void __iomem *addr)
913{
914 if (upper_32_bits(val))
915 priv->write(upper_32_bits(val), addr - 4);
916 if (lower_32_bits(val))
917 priv->write(lower_32_bits(val), addr);
918}
919
920static inline u64 flexcan_read_reg_iflag_rx(struct flexcan_priv *priv)
921{
922 return flexcan_read64_mask(priv, &priv->regs->iflag1, priv->rx_mask);
923}
924
925static inline u64 flexcan_read_reg_iflag_tx(struct flexcan_priv *priv)
926{
927 return flexcan_read64_mask(priv, &priv->regs->iflag1, priv->tx_mask);
928}
929
930static inline struct flexcan_priv *rx_offload_to_priv(struct can_rx_offload *offload)
931{
932 return container_of(offload, struct flexcan_priv, offload);
933}
934
935static struct sk_buff *flexcan_mailbox_read(struct can_rx_offload *offload,
936 unsigned int n, u32 *timestamp,
937 bool drop)
938{
939 struct flexcan_priv *priv = rx_offload_to_priv(offload);
940 struct flexcan_regs __iomem *regs = priv->regs;
941 struct flexcan_mb __iomem *mb;
942 struct sk_buff *skb;
943 struct canfd_frame *cfd;
944 u32 reg_ctrl, reg_id, reg_iflag1;
945 int i;
946
947 if (unlikely(drop)) {
948 skb = ERR_PTR(-ENOBUFS);
949 goto mark_as_read;
950 }
951
952 mb = flexcan_get_mb(priv, n);
953
954 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_USE_RX_MAILBOX) {
955 u32 code;
956
957 do {
958 reg_ctrl = priv->read(&mb->can_ctrl);
959 } while (reg_ctrl & FLEXCAN_MB_CODE_RX_BUSY_BIT);
960
961
962 code = reg_ctrl & FLEXCAN_MB_CODE_MASK;
963 if ((code != FLEXCAN_MB_CODE_RX_FULL) &&
964 (code != FLEXCAN_MB_CODE_RX_OVERRUN))
965 return NULL;
966
967 if (code == FLEXCAN_MB_CODE_RX_OVERRUN) {
968
969 offload->dev->stats.rx_over_errors++;
970 offload->dev->stats.rx_errors++;
971 }
972 } else {
973 reg_iflag1 = priv->read(®s->iflag1);
974 if (!(reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE))
975 return NULL;
976
977 reg_ctrl = priv->read(&mb->can_ctrl);
978 }
979
980 if (reg_ctrl & FLEXCAN_MB_CNT_EDL)
981 skb = alloc_canfd_skb(offload->dev, &cfd);
982 else
983 skb = alloc_can_skb(offload->dev, (struct can_frame **)&cfd);
984 if (unlikely(!skb)) {
985 skb = ERR_PTR(-ENOMEM);
986 goto mark_as_read;
987 }
988
989
990 *timestamp = reg_ctrl << 16;
991
992 reg_id = priv->read(&mb->can_id);
993 if (reg_ctrl & FLEXCAN_MB_CNT_IDE)
994 cfd->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
995 else
996 cfd->can_id = (reg_id >> 18) & CAN_SFF_MASK;
997
998 if (reg_ctrl & FLEXCAN_MB_CNT_EDL) {
999 cfd->len = can_fd_dlc2len((reg_ctrl >> 16) & 0xf);
1000
1001 if (reg_ctrl & FLEXCAN_MB_CNT_BRS)
1002 cfd->flags |= CANFD_BRS;
1003 } else {
1004 cfd->len = can_cc_dlc2len((reg_ctrl >> 16) & 0xf);
1005
1006 if (reg_ctrl & FLEXCAN_MB_CNT_RTR)
1007 cfd->can_id |= CAN_RTR_FLAG;
1008 }
1009
1010 if (reg_ctrl & FLEXCAN_MB_CNT_ESI)
1011 cfd->flags |= CANFD_ESI;
1012
1013 for (i = 0; i < cfd->len; i += sizeof(u32)) {
1014 __be32 data = cpu_to_be32(priv->read(&mb->data[i / sizeof(u32)]));
1015 *(__be32 *)(cfd->data + i) = data;
1016 }
1017
1018 mark_as_read:
1019 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_USE_RX_MAILBOX)
1020 flexcan_write64(priv, FLEXCAN_IFLAG_MB(n), ®s->iflag1);
1021 else
1022 priv->write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, ®s->iflag1);
1023
1024
1025
1026
1027
1028 priv->read(®s->timer);
1029
1030 return skb;
1031}
1032
1033static irqreturn_t flexcan_irq(int irq, void *dev_id)
1034{
1035 struct net_device *dev = dev_id;
1036 struct net_device_stats *stats = &dev->stats;
1037 struct flexcan_priv *priv = netdev_priv(dev);
1038 struct flexcan_regs __iomem *regs = priv->regs;
1039 irqreturn_t handled = IRQ_NONE;
1040 u64 reg_iflag_tx;
1041 u32 reg_esr;
1042 enum can_state last_state = priv->can.state;
1043
1044
1045 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_USE_RX_MAILBOX) {
1046 u64 reg_iflag_rx;
1047 int ret;
1048
1049 while ((reg_iflag_rx = flexcan_read_reg_iflag_rx(priv))) {
1050 handled = IRQ_HANDLED;
1051 ret = can_rx_offload_irq_offload_timestamp(&priv->offload,
1052 reg_iflag_rx);
1053 if (!ret)
1054 break;
1055 }
1056 } else {
1057 u32 reg_iflag1;
1058
1059 reg_iflag1 = priv->read(®s->iflag1);
1060 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE) {
1061 handled = IRQ_HANDLED;
1062 can_rx_offload_irq_offload_fifo(&priv->offload);
1063 }
1064
1065
1066 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) {
1067 handled = IRQ_HANDLED;
1068 priv->write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW,
1069 ®s->iflag1);
1070 dev->stats.rx_over_errors++;
1071 dev->stats.rx_errors++;
1072 }
1073 }
1074
1075 reg_iflag_tx = flexcan_read_reg_iflag_tx(priv);
1076
1077
1078 if (reg_iflag_tx & priv->tx_mask) {
1079 u32 reg_ctrl = priv->read(&priv->tx_mb->can_ctrl);
1080
1081 handled = IRQ_HANDLED;
1082 stats->tx_bytes +=
1083 can_rx_offload_get_echo_skb(&priv->offload, 0,
1084 reg_ctrl << 16, NULL);
1085 stats->tx_packets++;
1086 can_led_event(dev, CAN_LED_EVENT_TX);
1087
1088
1089 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
1090 &priv->tx_mb->can_ctrl);
1091 flexcan_write64(priv, priv->tx_mask, ®s->iflag1);
1092 netif_wake_queue(dev);
1093 }
1094
1095 reg_esr = priv->read(®s->esr);
1096
1097
1098 if (reg_esr & (FLEXCAN_ESR_ALL_INT | FLEXCAN_ESR_WAK_INT)) {
1099 handled = IRQ_HANDLED;
1100 priv->write(reg_esr & (FLEXCAN_ESR_ALL_INT | FLEXCAN_ESR_WAK_INT), ®s->esr);
1101 }
1102
1103
1104 if ((reg_esr & FLEXCAN_ESR_ERR_STATE) ||
1105 (priv->devtype_data.quirks & (FLEXCAN_QUIRK_BROKEN_WERR_STATE |
1106 FLEXCAN_QUIRK_BROKEN_PERR_STATE)))
1107 flexcan_irq_state(dev, reg_esr);
1108
1109
1110 if ((reg_esr & FLEXCAN_ESR_ERR_BUS) &&
1111 (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING))
1112 flexcan_irq_bus_err(dev, reg_esr);
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126 if ((last_state != priv->can.state) &&
1127 (priv->devtype_data.quirks & FLEXCAN_QUIRK_BROKEN_PERR_STATE) &&
1128 !(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) {
1129 switch (priv->can.state) {
1130 case CAN_STATE_ERROR_ACTIVE:
1131 if (priv->devtype_data.quirks &
1132 FLEXCAN_QUIRK_BROKEN_WERR_STATE)
1133 flexcan_error_irq_enable(priv);
1134 else
1135 flexcan_error_irq_disable(priv);
1136 break;
1137
1138 case CAN_STATE_ERROR_WARNING:
1139 flexcan_error_irq_enable(priv);
1140 break;
1141
1142 case CAN_STATE_ERROR_PASSIVE:
1143 case CAN_STATE_BUS_OFF:
1144 flexcan_error_irq_disable(priv);
1145 break;
1146
1147 default:
1148 break;
1149 }
1150 }
1151
1152 if (handled)
1153 can_rx_offload_irq_finish(&priv->offload);
1154
1155 return handled;
1156}
1157
1158static void flexcan_set_bittiming_ctrl(const struct net_device *dev)
1159{
1160 const struct flexcan_priv *priv = netdev_priv(dev);
1161 const struct can_bittiming *bt = &priv->can.bittiming;
1162 struct flexcan_regs __iomem *regs = priv->regs;
1163 u32 reg;
1164
1165 reg = priv->read(®s->ctrl);
1166 reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) |
1167 FLEXCAN_CTRL_RJW(0x3) |
1168 FLEXCAN_CTRL_PSEG1(0x7) |
1169 FLEXCAN_CTRL_PSEG2(0x7) |
1170 FLEXCAN_CTRL_PROPSEG(0x7));
1171
1172 reg |= FLEXCAN_CTRL_PRESDIV(bt->brp - 1) |
1173 FLEXCAN_CTRL_PSEG1(bt->phase_seg1 - 1) |
1174 FLEXCAN_CTRL_PSEG2(bt->phase_seg2 - 1) |
1175 FLEXCAN_CTRL_RJW(bt->sjw - 1) |
1176 FLEXCAN_CTRL_PROPSEG(bt->prop_seg - 1);
1177
1178 netdev_dbg(dev, "writing ctrl=0x%08x\n", reg);
1179 priv->write(reg, ®s->ctrl);
1180
1181
1182 netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__,
1183 priv->read(®s->mcr), priv->read(®s->ctrl));
1184}
1185
1186static void flexcan_set_bittiming_cbt(const struct net_device *dev)
1187{
1188 struct flexcan_priv *priv = netdev_priv(dev);
1189 struct can_bittiming *bt = &priv->can.bittiming;
1190 struct can_bittiming *dbt = &priv->can.data_bittiming;
1191 struct flexcan_regs __iomem *regs = priv->regs;
1192 u32 reg_cbt, reg_fdctrl;
1193
1194
1195
1196
1197
1198
1199
1200
1201 if (bt->phase_seg1 > 0x20) {
1202 bt->prop_seg += (bt->phase_seg1 - 0x20);
1203 bt->phase_seg1 = 0x20;
1204 }
1205
1206 reg_cbt = FLEXCAN_CBT_BTF |
1207 FIELD_PREP(FLEXCAN_CBT_EPRESDIV_MASK, bt->brp - 1) |
1208 FIELD_PREP(FLEXCAN_CBT_ERJW_MASK, bt->sjw - 1) |
1209 FIELD_PREP(FLEXCAN_CBT_EPROPSEG_MASK, bt->prop_seg - 1) |
1210 FIELD_PREP(FLEXCAN_CBT_EPSEG1_MASK, bt->phase_seg1 - 1) |
1211 FIELD_PREP(FLEXCAN_CBT_EPSEG2_MASK, bt->phase_seg2 - 1);
1212
1213 netdev_dbg(dev, "writing cbt=0x%08x\n", reg_cbt);
1214 priv->write(reg_cbt, ®s->cbt);
1215
1216 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
1217 u32 reg_fdcbt, reg_ctrl2;
1218
1219 if (bt->brp != dbt->brp)
1220 netdev_warn(dev, "Data brp=%d and brp=%d don't match, this may result in a phase error. Consider using different bitrate and/or data bitrate.\n",
1221 dbt->brp, bt->brp);
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231 if (dbt->phase_seg1 > 0x8) {
1232 dbt->prop_seg += (dbt->phase_seg1 - 0x8);
1233 dbt->phase_seg1 = 0x8;
1234 }
1235
1236 reg_fdcbt = priv->read(®s->fdcbt);
1237 reg_fdcbt &= ~(FIELD_PREP(FLEXCAN_FDCBT_FPRESDIV_MASK, 0x3ff) |
1238 FIELD_PREP(FLEXCAN_FDCBT_FRJW_MASK, 0x7) |
1239 FIELD_PREP(FLEXCAN_FDCBT_FPROPSEG_MASK, 0x1f) |
1240 FIELD_PREP(FLEXCAN_FDCBT_FPSEG1_MASK, 0x7) |
1241 FIELD_PREP(FLEXCAN_FDCBT_FPSEG2_MASK, 0x7));
1242
1243 reg_fdcbt |= FIELD_PREP(FLEXCAN_FDCBT_FPRESDIV_MASK, dbt->brp - 1) |
1244 FIELD_PREP(FLEXCAN_FDCBT_FRJW_MASK, dbt->sjw - 1) |
1245 FIELD_PREP(FLEXCAN_FDCBT_FPROPSEG_MASK, dbt->prop_seg) |
1246 FIELD_PREP(FLEXCAN_FDCBT_FPSEG1_MASK, dbt->phase_seg1 - 1) |
1247 FIELD_PREP(FLEXCAN_FDCBT_FPSEG2_MASK, dbt->phase_seg2 - 1);
1248
1249 netdev_dbg(dev, "writing fdcbt=0x%08x\n", reg_fdcbt);
1250 priv->write(reg_fdcbt, ®s->fdcbt);
1251
1252
1253 reg_ctrl2 = priv->read(®s->ctrl2);
1254 reg_ctrl2 &= ~FLEXCAN_CTRL2_ISOCANFDEN;
1255 if (!(priv->can.ctrlmode & CAN_CTRLMODE_FD_NON_ISO))
1256 reg_ctrl2 |= FLEXCAN_CTRL2_ISOCANFDEN;
1257
1258 netdev_dbg(dev, "writing ctrl2=0x%08x\n", reg_ctrl2);
1259 priv->write(reg_ctrl2, ®s->ctrl2);
1260 }
1261
1262
1263 reg_fdctrl = priv->read(®s->fdctrl);
1264 reg_fdctrl &= ~(FLEXCAN_FDCTRL_FDRATE |
1265 FIELD_PREP(FLEXCAN_FDCTRL_TDCOFF, 0x1f));
1266
1267 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
1268 reg_fdctrl |= FLEXCAN_FDCTRL_FDRATE;
1269
1270 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
1271
1272 reg_fdctrl &= ~FLEXCAN_FDCTRL_TDCEN;
1273 } else {
1274 reg_fdctrl |= FLEXCAN_FDCTRL_TDCEN |
1275 FIELD_PREP(FLEXCAN_FDCTRL_TDCOFF,
1276 ((dbt->phase_seg1 - 1) +
1277 dbt->prop_seg + 2) *
1278 ((dbt->brp - 1 ) + 1));
1279 }
1280 }
1281
1282 netdev_dbg(dev, "writing fdctrl=0x%08x\n", reg_fdctrl);
1283 priv->write(reg_fdctrl, ®s->fdctrl);
1284
1285 netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x ctrl2=0x%08x fdctrl=0x%08x cbt=0x%08x fdcbt=0x%08x\n",
1286 __func__,
1287 priv->read(®s->mcr), priv->read(®s->ctrl),
1288 priv->read(®s->ctrl2), priv->read(®s->fdctrl),
1289 priv->read(®s->cbt), priv->read(®s->fdcbt));
1290}
1291
1292static void flexcan_set_bittiming(struct net_device *dev)
1293{
1294 const struct flexcan_priv *priv = netdev_priv(dev);
1295 struct flexcan_regs __iomem *regs = priv->regs;
1296 u32 reg;
1297
1298 reg = priv->read(®s->ctrl);
1299 reg &= ~(FLEXCAN_CTRL_LPB | FLEXCAN_CTRL_SMP |
1300 FLEXCAN_CTRL_LOM);
1301
1302 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
1303 reg |= FLEXCAN_CTRL_LPB;
1304 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
1305 reg |= FLEXCAN_CTRL_LOM;
1306 if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
1307 reg |= FLEXCAN_CTRL_SMP;
1308
1309 netdev_dbg(dev, "writing ctrl=0x%08x\n", reg);
1310 priv->write(reg, ®s->ctrl);
1311
1312 if (priv->can.ctrlmode_supported & CAN_CTRLMODE_FD)
1313 return flexcan_set_bittiming_cbt(dev);
1314 else
1315 return flexcan_set_bittiming_ctrl(dev);
1316}
1317
1318static void flexcan_ram_init(struct net_device *dev)
1319{
1320 struct flexcan_priv *priv = netdev_priv(dev);
1321 struct flexcan_regs __iomem *regs = priv->regs;
1322 u32 reg_ctrl2;
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332 reg_ctrl2 = priv->read(®s->ctrl2);
1333 reg_ctrl2 |= FLEXCAN_CTRL2_WRMFRZ;
1334 priv->write(reg_ctrl2, ®s->ctrl2);
1335
1336 memset_io(®s->init, 0, sizeof(regs->init));
1337
1338 if (priv->can.ctrlmode & CAN_CTRLMODE_FD)
1339 memset_io(®s->init_fd, 0, sizeof(regs->init_fd));
1340
1341 reg_ctrl2 &= ~FLEXCAN_CTRL2_WRMFRZ;
1342 priv->write(reg_ctrl2, ®s->ctrl2);
1343}
1344
1345static int flexcan_rx_offload_setup(struct net_device *dev)
1346{
1347 struct flexcan_priv *priv = netdev_priv(dev);
1348 int err;
1349
1350 if (priv->can.ctrlmode & CAN_CTRLMODE_FD)
1351 priv->mb_size = sizeof(struct flexcan_mb) + CANFD_MAX_DLEN;
1352 else
1353 priv->mb_size = sizeof(struct flexcan_mb) + CAN_MAX_DLEN;
1354
1355 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_NR_MB_16)
1356 priv->mb_count = 16;
1357 else
1358 priv->mb_count = (sizeof(priv->regs->mb[0]) / priv->mb_size) +
1359 (sizeof(priv->regs->mb[1]) / priv->mb_size);
1360
1361 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_USE_RX_MAILBOX)
1362 priv->tx_mb_reserved =
1363 flexcan_get_mb(priv, FLEXCAN_TX_MB_RESERVED_RX_MAILBOX);
1364 else
1365 priv->tx_mb_reserved =
1366 flexcan_get_mb(priv, FLEXCAN_TX_MB_RESERVED_RX_FIFO);
1367 priv->tx_mb_idx = priv->mb_count - 1;
1368 priv->tx_mb = flexcan_get_mb(priv, priv->tx_mb_idx);
1369 priv->tx_mask = FLEXCAN_IFLAG_MB(priv->tx_mb_idx);
1370
1371 priv->offload.mailbox_read = flexcan_mailbox_read;
1372
1373 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_USE_RX_MAILBOX) {
1374 priv->offload.mb_first = FLEXCAN_RX_MB_RX_MAILBOX_FIRST;
1375 priv->offload.mb_last = priv->mb_count - 2;
1376
1377 priv->rx_mask = GENMASK_ULL(priv->offload.mb_last,
1378 priv->offload.mb_first);
1379 err = can_rx_offload_add_timestamp(dev, &priv->offload);
1380 } else {
1381 priv->rx_mask = FLEXCAN_IFLAG_RX_FIFO_OVERFLOW |
1382 FLEXCAN_IFLAG_RX_FIFO_AVAILABLE;
1383 err = can_rx_offload_add_fifo(dev, &priv->offload,
1384 FLEXCAN_NAPI_WEIGHT);
1385 }
1386
1387 return err;
1388}
1389
1390static void flexcan_chip_interrupts_enable(const struct net_device *dev)
1391{
1392 const struct flexcan_priv *priv = netdev_priv(dev);
1393 struct flexcan_regs __iomem *regs = priv->regs;
1394 u64 reg_imask;
1395
1396 disable_irq(dev->irq);
1397 priv->write(priv->reg_ctrl_default, ®s->ctrl);
1398 reg_imask = priv->rx_mask | priv->tx_mask;
1399 priv->write(upper_32_bits(reg_imask), ®s->imask2);
1400 priv->write(lower_32_bits(reg_imask), ®s->imask1);
1401 enable_irq(dev->irq);
1402}
1403
1404static void flexcan_chip_interrupts_disable(const struct net_device *dev)
1405{
1406 const struct flexcan_priv *priv = netdev_priv(dev);
1407 struct flexcan_regs __iomem *regs = priv->regs;
1408
1409 priv->write(0, ®s->imask2);
1410 priv->write(0, ®s->imask1);
1411 priv->write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
1412 ®s->ctrl);
1413}
1414
1415
1416
1417
1418
1419
1420static int flexcan_chip_start(struct net_device *dev)
1421{
1422 struct flexcan_priv *priv = netdev_priv(dev);
1423 struct flexcan_regs __iomem *regs = priv->regs;
1424 u32 reg_mcr, reg_ctrl, reg_ctrl2, reg_mecr;
1425 int err, i;
1426 struct flexcan_mb __iomem *mb;
1427
1428
1429 err = flexcan_chip_enable(priv);
1430 if (err)
1431 return err;
1432
1433
1434 err = flexcan_chip_softreset(priv);
1435 if (err)
1436 goto out_chip_disable;
1437
1438 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SUPPORT_ECC)
1439 flexcan_ram_init(dev);
1440
1441 flexcan_set_bittiming(dev);
1442
1443
1444 err = flexcan_chip_freeze(priv);
1445 if (err)
1446 goto out_chip_disable;
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456 reg_mcr = priv->read(®s->mcr);
1457 reg_mcr &= ~FLEXCAN_MCR_MAXMB(0xff);
1458 reg_mcr |= FLEXCAN_MCR_SUPV | FLEXCAN_MCR_WRN_EN | FLEXCAN_MCR_IRMQ |
1459 FLEXCAN_MCR_IDAM_C | FLEXCAN_MCR_MAXMB(priv->tx_mb_idx);
1460
1461
1462
1463
1464
1465
1466
1467 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_USE_RX_MAILBOX)
1468 reg_mcr &= ~FLEXCAN_MCR_FEN;
1469 else
1470 reg_mcr |= FLEXCAN_MCR_FEN;
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
1485 reg_mcr &= ~FLEXCAN_MCR_SRX_DIS;
1486 else
1487 reg_mcr |= FLEXCAN_MCR_SRX_DIS;
1488
1489
1490 if (priv->can.ctrlmode & CAN_CTRLMODE_FD)
1491 reg_mcr |= FLEXCAN_MCR_FDEN;
1492 else
1493 reg_mcr &= ~FLEXCAN_MCR_FDEN;
1494
1495 netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr);
1496 priv->write(reg_mcr, ®s->mcr);
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509 reg_ctrl = priv->read(®s->ctrl);
1510 reg_ctrl &= ~FLEXCAN_CTRL_TSYN;
1511 reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF |
1512 FLEXCAN_CTRL_ERR_STATE;
1513
1514
1515
1516
1517
1518 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_BROKEN_WERR_STATE ||
1519 priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)
1520 reg_ctrl |= FLEXCAN_CTRL_ERR_MSK;
1521 else
1522 reg_ctrl &= ~FLEXCAN_CTRL_ERR_MSK;
1523
1524
1525 priv->reg_ctrl_default = reg_ctrl;
1526
1527 reg_ctrl &= ~FLEXCAN_CTRL_ERR_ALL;
1528 netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl);
1529 priv->write(reg_ctrl, ®s->ctrl);
1530
1531 if ((priv->devtype_data.quirks & FLEXCAN_QUIRK_ENABLE_EACEN_RRS)) {
1532 reg_ctrl2 = priv->read(®s->ctrl2);
1533 reg_ctrl2 |= FLEXCAN_CTRL2_EACEN | FLEXCAN_CTRL2_RRS;
1534 priv->write(reg_ctrl2, ®s->ctrl2);
1535 }
1536
1537 if (priv->can.ctrlmode_supported & CAN_CTRLMODE_FD) {
1538 u32 reg_fdctrl;
1539
1540 reg_fdctrl = priv->read(®s->fdctrl);
1541 reg_fdctrl &= ~(FIELD_PREP(FLEXCAN_FDCTRL_MBDSR1, 0x3) |
1542 FIELD_PREP(FLEXCAN_FDCTRL_MBDSR0, 0x3));
1543
1544 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
1545 reg_fdctrl |=
1546 FIELD_PREP(FLEXCAN_FDCTRL_MBDSR1,
1547 FLEXCAN_FDCTRL_MBDSR_64) |
1548 FIELD_PREP(FLEXCAN_FDCTRL_MBDSR0,
1549 FLEXCAN_FDCTRL_MBDSR_64);
1550 } else {
1551 reg_fdctrl |=
1552 FIELD_PREP(FLEXCAN_FDCTRL_MBDSR1,
1553 FLEXCAN_FDCTRL_MBDSR_8) |
1554 FIELD_PREP(FLEXCAN_FDCTRL_MBDSR0,
1555 FLEXCAN_FDCTRL_MBDSR_8);
1556 }
1557
1558 netdev_dbg(dev, "%s: writing fdctrl=0x%08x",
1559 __func__, reg_fdctrl);
1560 priv->write(reg_fdctrl, ®s->fdctrl);
1561 }
1562
1563 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_USE_RX_MAILBOX) {
1564 for (i = priv->offload.mb_first; i <= priv->offload.mb_last; i++) {
1565 mb = flexcan_get_mb(priv, i);
1566 priv->write(FLEXCAN_MB_CODE_RX_EMPTY,
1567 &mb->can_ctrl);
1568 }
1569 } else {
1570
1571 for (i = FLEXCAN_TX_MB_RESERVED_RX_FIFO; i < priv->mb_count; i++) {
1572 mb = flexcan_get_mb(priv, i);
1573 priv->write(FLEXCAN_MB_CODE_RX_INACTIVE,
1574 &mb->can_ctrl);
1575 }
1576 }
1577
1578
1579 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
1580 &priv->tx_mb_reserved->can_ctrl);
1581
1582
1583 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
1584 &priv->tx_mb->can_ctrl);
1585
1586
1587 priv->write(0x0, ®s->rxgmask);
1588 priv->write(0x0, ®s->rx14mask);
1589 priv->write(0x0, ®s->rx15mask);
1590
1591 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_DISABLE_RXFG)
1592 priv->write(0x0, ®s->rxfgmask);
1593
1594
1595 for (i = 0; i < priv->mb_count; i++)
1596 priv->write(0, ®s->rximr[i]);
1597
1598
1599
1600
1601
1602
1603
1604
1605 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_DISABLE_MECR) {
1606
1607
1608
1609
1610
1611
1612
1613 reg_ctrl2 = priv->read(®s->ctrl2);
1614 reg_ctrl2 |= FLEXCAN_CTRL2_ECRWRE;
1615 priv->write(reg_ctrl2, ®s->ctrl2);
1616
1617
1618 reg_mecr = priv->read(®s->mecr);
1619 reg_mecr &= ~FLEXCAN_MECR_ECRWRDIS;
1620 priv->write(reg_mecr, ®s->mecr);
1621
1622
1623 reg_mecr &= ~(FLEXCAN_MECR_NCEFAFRZ | FLEXCAN_MECR_HANCEI_MSK |
1624 FLEXCAN_MECR_FANCEI_MSK);
1625 priv->write(reg_mecr, ®s->mecr);
1626
1627
1628
1629
1630 reg_mecr |= FLEXCAN_MECR_ECRWRDIS;
1631 priv->write(reg_mecr, ®s->mecr);
1632
1633 reg_ctrl2 &= ~FLEXCAN_CTRL2_ECRWRE;
1634 priv->write(reg_ctrl2, ®s->ctrl2);
1635 }
1636
1637
1638 err = flexcan_chip_unfreeze(priv);
1639 if (err)
1640 goto out_chip_disable;
1641
1642 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1643
1644
1645 netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__,
1646 priv->read(®s->mcr), priv->read(®s->ctrl));
1647
1648 return 0;
1649
1650 out_chip_disable:
1651 flexcan_chip_disable(priv);
1652 return err;
1653}
1654
1655
1656
1657
1658
1659static int __flexcan_chip_stop(struct net_device *dev, bool disable_on_error)
1660{
1661 struct flexcan_priv *priv = netdev_priv(dev);
1662 int err;
1663
1664
1665 err = flexcan_chip_freeze(priv);
1666 if (err && !disable_on_error)
1667 return err;
1668 err = flexcan_chip_disable(priv);
1669 if (err && !disable_on_error)
1670 goto out_chip_unfreeze;
1671
1672 priv->can.state = CAN_STATE_STOPPED;
1673
1674 return 0;
1675
1676 out_chip_unfreeze:
1677 flexcan_chip_unfreeze(priv);
1678
1679 return err;
1680}
1681
1682static inline int flexcan_chip_stop_disable_on_error(struct net_device *dev)
1683{
1684 return __flexcan_chip_stop(dev, true);
1685}
1686
1687static inline int flexcan_chip_stop(struct net_device *dev)
1688{
1689 return __flexcan_chip_stop(dev, false);
1690}
1691
1692static int flexcan_open(struct net_device *dev)
1693{
1694 struct flexcan_priv *priv = netdev_priv(dev);
1695 int err;
1696
1697 if ((priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) &&
1698 (priv->can.ctrlmode & CAN_CTRLMODE_FD)) {
1699 netdev_err(dev, "Three Samples mode and CAN-FD mode can't be used together\n");
1700 return -EINVAL;
1701 }
1702
1703 err = pm_runtime_get_sync(priv->dev);
1704 if (err < 0) {
1705 pm_runtime_put_noidle(priv->dev);
1706 return err;
1707 }
1708
1709 err = open_candev(dev);
1710 if (err)
1711 goto out_runtime_put;
1712
1713 err = flexcan_transceiver_enable(priv);
1714 if (err)
1715 goto out_close;
1716
1717 err = flexcan_rx_offload_setup(dev);
1718 if (err)
1719 goto out_transceiver_disable;
1720
1721 err = flexcan_chip_start(dev);
1722 if (err)
1723 goto out_can_rx_offload_del;
1724
1725 can_rx_offload_enable(&priv->offload);
1726
1727 err = request_irq(dev->irq, flexcan_irq, IRQF_SHARED, dev->name, dev);
1728 if (err)
1729 goto out_can_rx_offload_disable;
1730
1731 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_NR_IRQ_3) {
1732 err = request_irq(priv->irq_boff,
1733 flexcan_irq, IRQF_SHARED, dev->name, dev);
1734 if (err)
1735 goto out_free_irq;
1736
1737 err = request_irq(priv->irq_err,
1738 flexcan_irq, IRQF_SHARED, dev->name, dev);
1739 if (err)
1740 goto out_free_irq_boff;
1741 }
1742
1743 flexcan_chip_interrupts_enable(dev);
1744
1745 can_led_event(dev, CAN_LED_EVENT_OPEN);
1746
1747 netif_start_queue(dev);
1748
1749 return 0;
1750
1751 out_free_irq_boff:
1752 free_irq(priv->irq_boff, dev);
1753 out_free_irq:
1754 free_irq(dev->irq, dev);
1755 out_can_rx_offload_disable:
1756 can_rx_offload_disable(&priv->offload);
1757 flexcan_chip_stop(dev);
1758 out_can_rx_offload_del:
1759 can_rx_offload_del(&priv->offload);
1760 out_transceiver_disable:
1761 flexcan_transceiver_disable(priv);
1762 out_close:
1763 close_candev(dev);
1764 out_runtime_put:
1765 pm_runtime_put(priv->dev);
1766
1767 return err;
1768}
1769
1770static int flexcan_close(struct net_device *dev)
1771{
1772 struct flexcan_priv *priv = netdev_priv(dev);
1773
1774 netif_stop_queue(dev);
1775 flexcan_chip_interrupts_disable(dev);
1776
1777 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_NR_IRQ_3) {
1778 free_irq(priv->irq_err, dev);
1779 free_irq(priv->irq_boff, dev);
1780 }
1781
1782 free_irq(dev->irq, dev);
1783 can_rx_offload_disable(&priv->offload);
1784 flexcan_chip_stop_disable_on_error(dev);
1785
1786 can_rx_offload_del(&priv->offload);
1787 flexcan_transceiver_disable(priv);
1788 close_candev(dev);
1789
1790 pm_runtime_put(priv->dev);
1791
1792 can_led_event(dev, CAN_LED_EVENT_STOP);
1793
1794 return 0;
1795}
1796
1797static int flexcan_set_mode(struct net_device *dev, enum can_mode mode)
1798{
1799 int err;
1800
1801 switch (mode) {
1802 case CAN_MODE_START:
1803 err = flexcan_chip_start(dev);
1804 if (err)
1805 return err;
1806
1807 flexcan_chip_interrupts_enable(dev);
1808
1809 netif_wake_queue(dev);
1810 break;
1811
1812 default:
1813 return -EOPNOTSUPP;
1814 }
1815
1816 return 0;
1817}
1818
1819static const struct net_device_ops flexcan_netdev_ops = {
1820 .ndo_open = flexcan_open,
1821 .ndo_stop = flexcan_close,
1822 .ndo_start_xmit = flexcan_start_xmit,
1823 .ndo_change_mtu = can_change_mtu,
1824};
1825
1826static int register_flexcandev(struct net_device *dev)
1827{
1828 struct flexcan_priv *priv = netdev_priv(dev);
1829 struct flexcan_regs __iomem *regs = priv->regs;
1830 u32 reg, err;
1831
1832 err = flexcan_clks_enable(priv);
1833 if (err)
1834 return err;
1835
1836
1837 err = flexcan_chip_disable(priv);
1838 if (err)
1839 goto out_clks_disable;
1840
1841 reg = priv->read(®s->ctrl);
1842 if (priv->clk_src)
1843 reg |= FLEXCAN_CTRL_CLK_SRC;
1844 else
1845 reg &= ~FLEXCAN_CTRL_CLK_SRC;
1846 priv->write(reg, ®s->ctrl);
1847
1848 err = flexcan_chip_enable(priv);
1849 if (err)
1850 goto out_chip_disable;
1851
1852
1853 err = flexcan_chip_freeze(priv);
1854 if (err)
1855 goto out_chip_disable;
1856
1857
1858 reg = priv->read(®s->mcr);
1859 reg |= FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV;
1860 priv->write(reg, ®s->mcr);
1861
1862
1863
1864
1865
1866
1867 reg = priv->read(®s->mcr);
1868 if (!(reg & FLEXCAN_MCR_FEN)) {
1869 netdev_err(dev, "Could not enable RX FIFO, unsupported core\n");
1870 err = -ENODEV;
1871 goto out_chip_disable;
1872 }
1873
1874 err = register_candev(dev);
1875 if (err)
1876 goto out_chip_disable;
1877
1878
1879
1880
1881 flexcan_chip_disable(priv);
1882 pm_runtime_put(priv->dev);
1883
1884 return 0;
1885
1886 out_chip_disable:
1887 flexcan_chip_disable(priv);
1888 out_clks_disable:
1889 flexcan_clks_disable(priv);
1890 return err;
1891}
1892
1893static void unregister_flexcandev(struct net_device *dev)
1894{
1895 unregister_candev(dev);
1896}
1897
1898static int flexcan_setup_stop_mode_gpr(struct platform_device *pdev)
1899{
1900 struct net_device *dev = platform_get_drvdata(pdev);
1901 struct device_node *np = pdev->dev.of_node;
1902 struct device_node *gpr_np;
1903 struct flexcan_priv *priv;
1904 phandle phandle;
1905 u32 out_val[3];
1906 int ret;
1907
1908 if (!np)
1909 return -EINVAL;
1910
1911
1912
1913
1914 ret = of_property_read_u32_array(np, "fsl,stop-mode", out_val,
1915 ARRAY_SIZE(out_val));
1916 if (ret) {
1917 dev_dbg(&pdev->dev, "no stop-mode property\n");
1918 return ret;
1919 }
1920 phandle = *out_val;
1921
1922 gpr_np = of_find_node_by_phandle(phandle);
1923 if (!gpr_np) {
1924 dev_dbg(&pdev->dev, "could not find gpr node by phandle\n");
1925 return -ENODEV;
1926 }
1927
1928 priv = netdev_priv(dev);
1929 priv->stm.gpr = syscon_node_to_regmap(gpr_np);
1930 if (IS_ERR(priv->stm.gpr)) {
1931 dev_dbg(&pdev->dev, "could not find gpr regmap\n");
1932 ret = PTR_ERR(priv->stm.gpr);
1933 goto out_put_node;
1934 }
1935
1936 priv->stm.req_gpr = out_val[1];
1937 priv->stm.req_bit = out_val[2];
1938
1939 dev_dbg(&pdev->dev,
1940 "gpr %s req_gpr=0x02%x req_bit=%u\n",
1941 gpr_np->full_name, priv->stm.req_gpr, priv->stm.req_bit);
1942
1943 return 0;
1944
1945out_put_node:
1946 of_node_put(gpr_np);
1947 return ret;
1948}
1949
1950static int flexcan_setup_stop_mode_scfw(struct platform_device *pdev)
1951{
1952 struct net_device *dev = platform_get_drvdata(pdev);
1953 struct flexcan_priv *priv;
1954 u8 scu_idx;
1955 int ret;
1956
1957 ret = of_property_read_u8(pdev->dev.of_node, "fsl,scu-index", &scu_idx);
1958 if (ret < 0) {
1959 dev_dbg(&pdev->dev, "failed to get scu index\n");
1960 return ret;
1961 }
1962
1963 priv = netdev_priv(dev);
1964 priv->scu_idx = scu_idx;
1965
1966
1967 return imx_scu_get_handle(&priv->sc_ipc_handle);
1968}
1969
1970
1971
1972
1973
1974
1975static int flexcan_setup_stop_mode(struct platform_device *pdev)
1976{
1977 struct net_device *dev = platform_get_drvdata(pdev);
1978 struct flexcan_priv *priv;
1979 int ret;
1980
1981 priv = netdev_priv(dev);
1982
1983 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE_SCFW)
1984 ret = flexcan_setup_stop_mode_scfw(pdev);
1985 else if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE_GPR)
1986 ret = flexcan_setup_stop_mode_gpr(pdev);
1987 else
1988
1989 return 0;
1990
1991 if (ret)
1992 return ret;
1993
1994 device_set_wakeup_capable(&pdev->dev, true);
1995
1996 if (of_property_read_bool(pdev->dev.of_node, "wakeup-source"))
1997 device_set_wakeup_enable(&pdev->dev, true);
1998
1999 return 0;
2000}
2001
2002static const struct of_device_id flexcan_of_match[] = {
2003 { .compatible = "fsl,imx8qm-flexcan", .data = &fsl_imx8qm_devtype_data, },
2004 { .compatible = "fsl,imx8mp-flexcan", .data = &fsl_imx8mp_devtype_data, },
2005 { .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, },
2006 { .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, },
2007 { .compatible = "fsl,imx53-flexcan", .data = &fsl_imx25_devtype_data, },
2008 { .compatible = "fsl,imx35-flexcan", .data = &fsl_imx25_devtype_data, },
2009 { .compatible = "fsl,imx25-flexcan", .data = &fsl_imx25_devtype_data, },
2010 { .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, },
2011 { .compatible = "fsl,vf610-flexcan", .data = &fsl_vf610_devtype_data, },
2012 { .compatible = "fsl,ls1021ar2-flexcan", .data = &fsl_ls1021a_r2_devtype_data, },
2013 { .compatible = "fsl,lx2160ar1-flexcan", .data = &fsl_lx2160a_r1_devtype_data, },
2014 { },
2015};
2016MODULE_DEVICE_TABLE(of, flexcan_of_match);
2017
2018static const struct platform_device_id flexcan_id_table[] = {
2019 {
2020 .name = "flexcan-mcf5441x",
2021 .driver_data = (kernel_ulong_t)&fsl_mcf5441x_devtype_data,
2022 }, {
2023
2024 },
2025};
2026MODULE_DEVICE_TABLE(platform, flexcan_id_table);
2027
2028static int flexcan_probe(struct platform_device *pdev)
2029{
2030 const struct of_device_id *of_id;
2031 const struct flexcan_devtype_data *devtype_data;
2032 struct net_device *dev;
2033 struct flexcan_priv *priv;
2034 struct regulator *reg_xceiver;
2035 struct clk *clk_ipg = NULL, *clk_per = NULL;
2036 struct flexcan_regs __iomem *regs;
2037 struct flexcan_platform_data *pdata;
2038 int err, irq;
2039 u8 clk_src = 1;
2040 u32 clock_freq = 0;
2041
2042 reg_xceiver = devm_regulator_get_optional(&pdev->dev, "xceiver");
2043 if (PTR_ERR(reg_xceiver) == -EPROBE_DEFER)
2044 return -EPROBE_DEFER;
2045 else if (PTR_ERR(reg_xceiver) == -ENODEV)
2046 reg_xceiver = NULL;
2047 else if (IS_ERR(reg_xceiver))
2048 return PTR_ERR(reg_xceiver);
2049
2050 if (pdev->dev.of_node) {
2051 of_property_read_u32(pdev->dev.of_node,
2052 "clock-frequency", &clock_freq);
2053 of_property_read_u8(pdev->dev.of_node,
2054 "fsl,clk-source", &clk_src);
2055 } else {
2056 pdata = dev_get_platdata(&pdev->dev);
2057 if (pdata) {
2058 clock_freq = pdata->clock_frequency;
2059 clk_src = pdata->clk_src;
2060 }
2061 }
2062
2063 if (!clock_freq) {
2064 clk_ipg = devm_clk_get(&pdev->dev, "ipg");
2065 if (IS_ERR(clk_ipg)) {
2066 dev_err(&pdev->dev, "no ipg clock defined\n");
2067 return PTR_ERR(clk_ipg);
2068 }
2069
2070 clk_per = devm_clk_get(&pdev->dev, "per");
2071 if (IS_ERR(clk_per)) {
2072 dev_err(&pdev->dev, "no per clock defined\n");
2073 return PTR_ERR(clk_per);
2074 }
2075 clock_freq = clk_get_rate(clk_per);
2076 }
2077
2078 irq = platform_get_irq(pdev, 0);
2079 if (irq <= 0)
2080 return -ENODEV;
2081
2082 regs = devm_platform_ioremap_resource(pdev, 0);
2083 if (IS_ERR(regs))
2084 return PTR_ERR(regs);
2085
2086 of_id = of_match_device(flexcan_of_match, &pdev->dev);
2087 if (of_id)
2088 devtype_data = of_id->data;
2089 else if (platform_get_device_id(pdev)->driver_data)
2090 devtype_data = (struct flexcan_devtype_data *)
2091 platform_get_device_id(pdev)->driver_data;
2092 else
2093 return -ENODEV;
2094
2095 if ((devtype_data->quirks & FLEXCAN_QUIRK_SUPPORT_FD) &&
2096 !((devtype_data->quirks &
2097 (FLEXCAN_QUIRK_USE_RX_MAILBOX |
2098 FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX |
2099 FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX_RTR |
2100 FLEXCAN_QUIRK_SUPPPORT_RX_FIFO)) ==
2101 (FLEXCAN_QUIRK_USE_RX_MAILBOX |
2102 FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX |
2103 FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX_RTR))) {
2104 dev_err(&pdev->dev, "CAN-FD mode doesn't work in RX-FIFO mode!\n");
2105 return -EINVAL;
2106 }
2107
2108 if ((devtype_data->quirks &
2109 (FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX |
2110 FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX_RTR)) ==
2111 FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX_RTR) {
2112 dev_err(&pdev->dev,
2113 "Quirks (0x%08x) inconsistent: RX_MAILBOX_RX supported but not RX_MAILBOX\n",
2114 devtype_data->quirks);
2115 return -EINVAL;
2116 }
2117
2118 dev = alloc_candev(sizeof(struct flexcan_priv), 1);
2119 if (!dev)
2120 return -ENOMEM;
2121
2122 platform_set_drvdata(pdev, dev);
2123 SET_NETDEV_DEV(dev, &pdev->dev);
2124
2125 dev->netdev_ops = &flexcan_netdev_ops;
2126 flexcan_set_ethtool_ops(dev);
2127 dev->irq = irq;
2128 dev->flags |= IFF_ECHO;
2129
2130 priv = netdev_priv(dev);
2131 priv->devtype_data = *devtype_data;
2132
2133 if (of_property_read_bool(pdev->dev.of_node, "big-endian") ||
2134 priv->devtype_data.quirks & FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN) {
2135 priv->read = flexcan_read_be;
2136 priv->write = flexcan_write_be;
2137 } else {
2138 priv->read = flexcan_read_le;
2139 priv->write = flexcan_write_le;
2140 }
2141
2142 priv->dev = &pdev->dev;
2143 priv->can.clock.freq = clock_freq;
2144 priv->can.do_set_mode = flexcan_set_mode;
2145 priv->can.do_get_berr_counter = flexcan_get_berr_counter;
2146 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
2147 CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_3_SAMPLES |
2148 CAN_CTRLMODE_BERR_REPORTING;
2149 priv->regs = regs;
2150 priv->clk_ipg = clk_ipg;
2151 priv->clk_per = clk_per;
2152 priv->clk_src = clk_src;
2153 priv->reg_xceiver = reg_xceiver;
2154
2155 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_NR_IRQ_3) {
2156 priv->irq_boff = platform_get_irq(pdev, 1);
2157 if (priv->irq_boff <= 0) {
2158 err = -ENODEV;
2159 goto failed_platform_get_irq;
2160 }
2161 priv->irq_err = platform_get_irq(pdev, 2);
2162 if (priv->irq_err <= 0) {
2163 err = -ENODEV;
2164 goto failed_platform_get_irq;
2165 }
2166 }
2167
2168 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SUPPORT_FD) {
2169 priv->can.ctrlmode_supported |= CAN_CTRLMODE_FD |
2170 CAN_CTRLMODE_FD_NON_ISO;
2171 priv->can.bittiming_const = &flexcan_fd_bittiming_const;
2172 priv->can.data_bittiming_const =
2173 &flexcan_fd_data_bittiming_const;
2174 } else {
2175 priv->can.bittiming_const = &flexcan_bittiming_const;
2176 }
2177
2178 pm_runtime_get_noresume(&pdev->dev);
2179 pm_runtime_set_active(&pdev->dev);
2180 pm_runtime_enable(&pdev->dev);
2181
2182 err = register_flexcandev(dev);
2183 if (err) {
2184 dev_err(&pdev->dev, "registering netdev failed\n");
2185 goto failed_register;
2186 }
2187
2188 err = flexcan_setup_stop_mode(pdev);
2189 if (err < 0) {
2190 if (err != -EPROBE_DEFER)
2191 dev_err(&pdev->dev, "setup stop mode failed\n");
2192 goto failed_setup_stop_mode;
2193 }
2194
2195 of_can_transceiver(dev);
2196 devm_can_led_init(dev);
2197
2198 return 0;
2199
2200 failed_setup_stop_mode:
2201 unregister_flexcandev(dev);
2202 failed_register:
2203 pm_runtime_put_noidle(&pdev->dev);
2204 pm_runtime_disable(&pdev->dev);
2205 failed_platform_get_irq:
2206 free_candev(dev);
2207 return err;
2208}
2209
2210static int flexcan_remove(struct platform_device *pdev)
2211{
2212 struct net_device *dev = platform_get_drvdata(pdev);
2213
2214 device_set_wakeup_enable(&pdev->dev, false);
2215 device_set_wakeup_capable(&pdev->dev, false);
2216 unregister_flexcandev(dev);
2217 pm_runtime_disable(&pdev->dev);
2218 free_candev(dev);
2219
2220 return 0;
2221}
2222
2223static int __maybe_unused flexcan_suspend(struct device *device)
2224{
2225 struct net_device *dev = dev_get_drvdata(device);
2226 struct flexcan_priv *priv = netdev_priv(dev);
2227 int err;
2228
2229 if (netif_running(dev)) {
2230
2231
2232
2233 if (device_may_wakeup(device)) {
2234 enable_irq_wake(dev->irq);
2235 err = flexcan_enter_stop_mode(priv);
2236 if (err)
2237 return err;
2238 } else {
2239 err = flexcan_chip_stop(dev);
2240 if (err)
2241 return err;
2242
2243 flexcan_chip_interrupts_disable(dev);
2244
2245 err = pinctrl_pm_select_sleep_state(device);
2246 if (err)
2247 return err;
2248 }
2249 netif_stop_queue(dev);
2250 netif_device_detach(dev);
2251 }
2252 priv->can.state = CAN_STATE_SLEEPING;
2253
2254 return 0;
2255}
2256
2257static int __maybe_unused flexcan_resume(struct device *device)
2258{
2259 struct net_device *dev = dev_get_drvdata(device);
2260 struct flexcan_priv *priv = netdev_priv(dev);
2261 int err;
2262
2263 priv->can.state = CAN_STATE_ERROR_ACTIVE;
2264 if (netif_running(dev)) {
2265 netif_device_attach(dev);
2266 netif_start_queue(dev);
2267 if (device_may_wakeup(device)) {
2268 disable_irq_wake(dev->irq);
2269 err = flexcan_exit_stop_mode(priv);
2270 if (err)
2271 return err;
2272 } else {
2273 err = pinctrl_pm_select_default_state(device);
2274 if (err)
2275 return err;
2276
2277 err = flexcan_chip_start(dev);
2278 if (err)
2279 return err;
2280
2281 flexcan_chip_interrupts_enable(dev);
2282 }
2283 }
2284
2285 return 0;
2286}
2287
2288static int __maybe_unused flexcan_runtime_suspend(struct device *device)
2289{
2290 struct net_device *dev = dev_get_drvdata(device);
2291 struct flexcan_priv *priv = netdev_priv(dev);
2292
2293 flexcan_clks_disable(priv);
2294
2295 return 0;
2296}
2297
2298static int __maybe_unused flexcan_runtime_resume(struct device *device)
2299{
2300 struct net_device *dev = dev_get_drvdata(device);
2301 struct flexcan_priv *priv = netdev_priv(dev);
2302
2303 return flexcan_clks_enable(priv);
2304}
2305
2306static int __maybe_unused flexcan_noirq_suspend(struct device *device)
2307{
2308 struct net_device *dev = dev_get_drvdata(device);
2309 struct flexcan_priv *priv = netdev_priv(dev);
2310
2311 if (netif_running(dev)) {
2312 int err;
2313
2314 if (device_may_wakeup(device))
2315 flexcan_enable_wakeup_irq(priv, true);
2316
2317 err = pm_runtime_force_suspend(device);
2318 if (err)
2319 return err;
2320 }
2321
2322 return 0;
2323}
2324
2325static int __maybe_unused flexcan_noirq_resume(struct device *device)
2326{
2327 struct net_device *dev = dev_get_drvdata(device);
2328 struct flexcan_priv *priv = netdev_priv(dev);
2329
2330 if (netif_running(dev)) {
2331 int err;
2332
2333 err = pm_runtime_force_resume(device);
2334 if (err)
2335 return err;
2336
2337 if (device_may_wakeup(device))
2338 flexcan_enable_wakeup_irq(priv, false);
2339 }
2340
2341 return 0;
2342}
2343
2344static const struct dev_pm_ops flexcan_pm_ops = {
2345 SET_SYSTEM_SLEEP_PM_OPS(flexcan_suspend, flexcan_resume)
2346 SET_RUNTIME_PM_OPS(flexcan_runtime_suspend, flexcan_runtime_resume, NULL)
2347 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(flexcan_noirq_suspend, flexcan_noirq_resume)
2348};
2349
2350static struct platform_driver flexcan_driver = {
2351 .driver = {
2352 .name = DRV_NAME,
2353 .pm = &flexcan_pm_ops,
2354 .of_match_table = flexcan_of_match,
2355 },
2356 .probe = flexcan_probe,
2357 .remove = flexcan_remove,
2358 .id_table = flexcan_id_table,
2359};
2360
2361module_platform_driver(flexcan_driver);
2362
2363MODULE_AUTHOR("Sascha Hauer <kernel@pengutronix.de>, "
2364 "Marc Kleine-Budde <kernel@pengutronix.de>");
2365MODULE_LICENSE("GPL v2");
2366MODULE_DESCRIPTION("CAN port driver for flexcan based chip");
2367