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93#include <linux/bitfield.h>
94#include <linux/bitops.h>
95#include <linux/interrupt.h>
96#include <linux/irqdomain.h>
97#include <linux/mutex.h>
98#include <linux/of_irq.h>
99#include <linux/regmap.h>
100#include <linux/if_bridge.h>
101
102#include "realtek-smi-core.h"
103
104
105#define RTL8365MB_CHIP_ID_8365MB_VC 0x6367
106#define RTL8365MB_CPU_PORT_NUM_8365MB_VC 6
107#define RTL8365MB_LEARN_LIMIT_MAX_8365MB_VC 2112
108
109
110#define RTL8365MB_PHYADDRMAX 7
111#define RTL8365MB_NUM_PHYREGS 32
112#define RTL8365MB_PHYREGMAX (RTL8365MB_NUM_PHYREGS - 1)
113#define RTL8365MB_MAX_NUM_PORTS (RTL8365MB_CPU_PORT_NUM_8365MB_VC + 1)
114
115
116#define RTL8365MB_CHIP_ID_REG 0x1300
117
118#define RTL8365MB_CHIP_VER_REG 0x1301
119
120#define RTL8365MB_MAGIC_REG 0x13C2
121#define RTL8365MB_MAGIC_VALUE 0x0249
122
123
124#define RTL8365MB_CHIP_RESET_REG 0x1322
125#define RTL8365MB_CHIP_RESET_SW_MASK 0x0002
126#define RTL8365MB_CHIP_RESET_HW_MASK 0x0001
127
128
129#define RTL8365MB_INTR_POLARITY_REG 0x1100
130#define RTL8365MB_INTR_POLARITY_MASK 0x0001
131#define RTL8365MB_INTR_POLARITY_HIGH 0
132#define RTL8365MB_INTR_POLARITY_LOW 1
133
134
135#define RTL8365MB_INTR_CTRL_REG 0x1101
136#define RTL8365MB_INTR_STATUS_REG 0x1102
137#define RTL8365MB_INTR_SLIENT_START_2_MASK 0x1000
138#define RTL8365MB_INTR_SLIENT_START_MASK 0x0800
139#define RTL8365MB_INTR_ACL_ACTION_MASK 0x0200
140#define RTL8365MB_INTR_CABLE_DIAG_FIN_MASK 0x0100
141#define RTL8365MB_INTR_INTERRUPT_8051_MASK 0x0080
142#define RTL8365MB_INTR_LOOP_DETECTION_MASK 0x0040
143#define RTL8365MB_INTR_GREEN_TIMER_MASK 0x0020
144#define RTL8365MB_INTR_SPECIAL_CONGEST_MASK 0x0010
145#define RTL8365MB_INTR_SPEED_CHANGE_MASK 0x0008
146#define RTL8365MB_INTR_LEARN_OVER_MASK 0x0004
147#define RTL8365MB_INTR_METER_EXCEEDED_MASK 0x0002
148#define RTL8365MB_INTR_LINK_CHANGE_MASK 0x0001
149#define RTL8365MB_INTR_ALL_MASK \
150 (RTL8365MB_INTR_SLIENT_START_2_MASK | \
151 RTL8365MB_INTR_SLIENT_START_MASK | \
152 RTL8365MB_INTR_ACL_ACTION_MASK | \
153 RTL8365MB_INTR_CABLE_DIAG_FIN_MASK | \
154 RTL8365MB_INTR_INTERRUPT_8051_MASK | \
155 RTL8365MB_INTR_LOOP_DETECTION_MASK | \
156 RTL8365MB_INTR_GREEN_TIMER_MASK | \
157 RTL8365MB_INTR_SPECIAL_CONGEST_MASK | \
158 RTL8365MB_INTR_SPEED_CHANGE_MASK | \
159 RTL8365MB_INTR_LEARN_OVER_MASK | \
160 RTL8365MB_INTR_METER_EXCEEDED_MASK | \
161 RTL8365MB_INTR_LINK_CHANGE_MASK)
162
163
164#define RTL8365MB_PORT_LINKDOWN_IND_REG 0x1106
165#define RTL8365MB_PORT_LINKDOWN_IND_MASK 0x07FF
166
167#define RTL8365MB_PORT_LINKUP_IND_REG 0x1107
168#define RTL8365MB_PORT_LINKUP_IND_MASK 0x07FF
169
170
171#define RTL8365MB_INDIRECT_ACCESS_CTRL_REG 0x1F00
172#define RTL8365MB_INDIRECT_ACCESS_CTRL_RW_MASK 0x0002
173#define RTL8365MB_INDIRECT_ACCESS_CTRL_RW_READ 0
174#define RTL8365MB_INDIRECT_ACCESS_CTRL_RW_WRITE 1
175#define RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_MASK 0x0001
176#define RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_VALUE 1
177#define RTL8365MB_INDIRECT_ACCESS_STATUS_REG 0x1F01
178#define RTL8365MB_INDIRECT_ACCESS_ADDRESS_REG 0x1F02
179#define RTL8365MB_INDIRECT_ACCESS_ADDRESS_OCPADR_5_1_MASK GENMASK(4, 0)
180#define RTL8365MB_INDIRECT_ACCESS_ADDRESS_PHYNUM_MASK GENMASK(7, 5)
181#define RTL8365MB_INDIRECT_ACCESS_ADDRESS_OCPADR_9_6_MASK GENMASK(11, 8)
182#define RTL8365MB_PHY_BASE 0x2000
183#define RTL8365MB_INDIRECT_ACCESS_WRITE_DATA_REG 0x1F03
184#define RTL8365MB_INDIRECT_ACCESS_READ_DATA_REG 0x1F04
185
186
187#define RTL8365MB_GPHY_OCP_MSB_0_REG 0x1D15
188#define RTL8365MB_GPHY_OCP_MSB_0_CFG_CPU_OCPADR_MASK 0x0FC0
189#define RTL8365MB_PHY_OCP_ADDR_PREFIX_MASK 0xFC00
190
191
192#define RTL8365MB_PHY_OCP_ADDR_PHYREG_BASE 0xA400
193
194
195#define RTL8365MB_EXT_PORT_MODE_DISABLE 0
196#define RTL8365MB_EXT_PORT_MODE_RGMII 1
197#define RTL8365MB_EXT_PORT_MODE_MII_MAC 2
198#define RTL8365MB_EXT_PORT_MODE_MII_PHY 3
199#define RTL8365MB_EXT_PORT_MODE_TMII_MAC 4
200#define RTL8365MB_EXT_PORT_MODE_TMII_PHY 5
201#define RTL8365MB_EXT_PORT_MODE_GMII 6
202#define RTL8365MB_EXT_PORT_MODE_RMII_MAC 7
203#define RTL8365MB_EXT_PORT_MODE_RMII_PHY 8
204#define RTL8365MB_EXT_PORT_MODE_SGMII 9
205#define RTL8365MB_EXT_PORT_MODE_HSGMII 10
206#define RTL8365MB_EXT_PORT_MODE_1000X_100FX 11
207#define RTL8365MB_EXT_PORT_MODE_1000X 12
208#define RTL8365MB_EXT_PORT_MODE_100FX 13
209
210
211#define RTL8365MB_DIGITAL_INTERFACE_SELECT_REG0 0x1305
212#define RTL8365MB_DIGITAL_INTERFACE_SELECT_REG1 0x13C3
213#define RTL8365MB_DIGITAL_INTERFACE_SELECT_REG(_extport) \
214 (RTL8365MB_DIGITAL_INTERFACE_SELECT_REG0 + \
215 ((_extport) >> 1) * (0x13C3 - 0x1305))
216#define RTL8365MB_DIGITAL_INTERFACE_SELECT_MODE_MASK(_extport) \
217 (0xF << (((_extport) % 2)))
218#define RTL8365MB_DIGITAL_INTERFACE_SELECT_MODE_OFFSET(_extport) \
219 (((_extport) % 2) * 4)
220
221
222#define RTL8365MB_EXT_RGMXF_REG1 0x1307
223#define RTL8365MB_EXT_RGMXF_REG2 0x13C5
224#define RTL8365MB_EXT_RGMXF_REG(_extport) \
225 (RTL8365MB_EXT_RGMXF_REG1 + \
226 (((_extport) >> 1) * (0x13C5 - 0x1307)))
227#define RTL8365MB_EXT_RGMXF_RXDELAY_MASK 0x0007
228#define RTL8365MB_EXT_RGMXF_TXDELAY_MASK 0x0008
229
230
231#define RTL8365MB_PORT_SPEED_10M 0
232#define RTL8365MB_PORT_SPEED_100M 1
233#define RTL8365MB_PORT_SPEED_1000M 2
234
235
236#define RTL8365MB_DIGITAL_INTERFACE_FORCE_REG0 0x1310
237#define RTL8365MB_DIGITAL_INTERFACE_FORCE_REG1 0x1311
238#define RTL8365MB_DIGITAL_INTERFACE_FORCE_REG2 0x13C4
239#define RTL8365MB_DIGITAL_INTERFACE_FORCE_REG(_extport) \
240 (RTL8365MB_DIGITAL_INTERFACE_FORCE_REG0 + \
241 ((_extport) & 0x1) + \
242 ((((_extport) >> 1) & 0x1) * (0x13C4 - 0x1310)))
243#define RTL8365MB_DIGITAL_INTERFACE_FORCE_EN_MASK 0x1000
244#define RTL8365MB_DIGITAL_INTERFACE_FORCE_NWAY_MASK 0x0080
245#define RTL8365MB_DIGITAL_INTERFACE_FORCE_TXPAUSE_MASK 0x0040
246#define RTL8365MB_DIGITAL_INTERFACE_FORCE_RXPAUSE_MASK 0x0020
247#define RTL8365MB_DIGITAL_INTERFACE_FORCE_LINK_MASK 0x0010
248#define RTL8365MB_DIGITAL_INTERFACE_FORCE_DUPLEX_MASK 0x0004
249#define RTL8365MB_DIGITAL_INTERFACE_FORCE_SPEED_MASK 0x0003
250
251
252#define RTL8365MB_CPU_PORT_MASK_REG 0x1219
253#define RTL8365MB_CPU_PORT_MASK_MASK 0x07FF
254
255
256#define RTL8365MB_CPU_CTRL_REG 0x121A
257#define RTL8365MB_CPU_CTRL_TRAP_PORT_EXT_MASK 0x0400
258#define RTL8365MB_CPU_CTRL_TAG_FORMAT_MASK 0x0200
259#define RTL8365MB_CPU_CTRL_RXBYTECOUNT_MASK 0x0080
260#define RTL8365MB_CPU_CTRL_TAG_POSITION_MASK 0x0040
261#define RTL8365MB_CPU_CTRL_TRAP_PORT_MASK 0x0038
262#define RTL8365MB_CPU_CTRL_INSERTMODE_MASK 0x0006
263#define RTL8365MB_CPU_CTRL_EN_MASK 0x0001
264
265
266#define RTL8365MB_CFG0_MAX_LEN_REG 0x088C
267#define RTL8365MB_CFG0_MAX_LEN_MASK 0x3FFF
268
269
270#define RTL8365MB_LUT_PORT_LEARN_LIMIT_BASE 0x0A20
271#define RTL8365MB_LUT_PORT_LEARN_LIMIT_REG(_physport) \
272 (RTL8365MB_LUT_PORT_LEARN_LIMIT_BASE + (_physport))
273
274
275#define RTL8365MB_PORT_ISOLATION_REG_BASE 0x08A2
276#define RTL8365MB_PORT_ISOLATION_REG(_physport) \
277 (RTL8365MB_PORT_ISOLATION_REG_BASE + (_physport))
278#define RTL8365MB_PORT_ISOLATION_MASK 0x07FF
279
280
281#define RTL8365MB_MSTI_CTRL_BASE 0x0A00
282#define RTL8365MB_MSTI_CTRL_REG(_msti, _physport) \
283 (RTL8365MB_MSTI_CTRL_BASE + ((_msti) << 1) + ((_physport) >> 3))
284#define RTL8365MB_MSTI_CTRL_PORT_STATE_OFFSET(_physport) ((_physport) << 1)
285#define RTL8365MB_MSTI_CTRL_PORT_STATE_MASK(_physport) \
286 (0x3 << RTL8365MB_MSTI_CTRL_PORT_STATE_OFFSET((_physport)))
287
288
289#define RTL8365MB_MIB_COUNTER_BASE 0x1000
290#define RTL8365MB_MIB_COUNTER_REG(_x) (RTL8365MB_MIB_COUNTER_BASE + (_x))
291
292
293#define RTL8365MB_MIB_ADDRESS_REG 0x1004
294#define RTL8365MB_MIB_ADDRESS_PORT_OFFSET 0x007C
295#define RTL8365MB_MIB_ADDRESS(_p, _x) \
296 (((RTL8365MB_MIB_ADDRESS_PORT_OFFSET) * (_p) + (_x)) >> 2)
297
298#define RTL8365MB_MIB_CTRL0_REG 0x1005
299#define RTL8365MB_MIB_CTRL0_RESET_MASK 0x0002
300#define RTL8365MB_MIB_CTRL0_BUSY_MASK 0x0001
301
302
303
304
305
306
307
308#define RTL8365MB_STATS_INTERVAL_JIFFIES (3 * HZ)
309
310enum rtl8365mb_mib_counter_index {
311 RTL8365MB_MIB_ifInOctets,
312 RTL8365MB_MIB_dot3StatsFCSErrors,
313 RTL8365MB_MIB_dot3StatsSymbolErrors,
314 RTL8365MB_MIB_dot3InPauseFrames,
315 RTL8365MB_MIB_dot3ControlInUnknownOpcodes,
316 RTL8365MB_MIB_etherStatsFragments,
317 RTL8365MB_MIB_etherStatsJabbers,
318 RTL8365MB_MIB_ifInUcastPkts,
319 RTL8365MB_MIB_etherStatsDropEvents,
320 RTL8365MB_MIB_ifInMulticastPkts,
321 RTL8365MB_MIB_ifInBroadcastPkts,
322 RTL8365MB_MIB_inMldChecksumError,
323 RTL8365MB_MIB_inIgmpChecksumError,
324 RTL8365MB_MIB_inMldSpecificQuery,
325 RTL8365MB_MIB_inMldGeneralQuery,
326 RTL8365MB_MIB_inIgmpSpecificQuery,
327 RTL8365MB_MIB_inIgmpGeneralQuery,
328 RTL8365MB_MIB_inMldLeaves,
329 RTL8365MB_MIB_inIgmpLeaves,
330 RTL8365MB_MIB_etherStatsOctets,
331 RTL8365MB_MIB_etherStatsUnderSizePkts,
332 RTL8365MB_MIB_etherOversizeStats,
333 RTL8365MB_MIB_etherStatsPkts64Octets,
334 RTL8365MB_MIB_etherStatsPkts65to127Octets,
335 RTL8365MB_MIB_etherStatsPkts128to255Octets,
336 RTL8365MB_MIB_etherStatsPkts256to511Octets,
337 RTL8365MB_MIB_etherStatsPkts512to1023Octets,
338 RTL8365MB_MIB_etherStatsPkts1024to1518Octets,
339 RTL8365MB_MIB_ifOutOctets,
340 RTL8365MB_MIB_dot3StatsSingleCollisionFrames,
341 RTL8365MB_MIB_dot3StatsMultipleCollisionFrames,
342 RTL8365MB_MIB_dot3StatsDeferredTransmissions,
343 RTL8365MB_MIB_dot3StatsLateCollisions,
344 RTL8365MB_MIB_etherStatsCollisions,
345 RTL8365MB_MIB_dot3StatsExcessiveCollisions,
346 RTL8365MB_MIB_dot3OutPauseFrames,
347 RTL8365MB_MIB_ifOutDiscards,
348 RTL8365MB_MIB_dot1dTpPortInDiscards,
349 RTL8365MB_MIB_ifOutUcastPkts,
350 RTL8365MB_MIB_ifOutMulticastPkts,
351 RTL8365MB_MIB_ifOutBroadcastPkts,
352 RTL8365MB_MIB_outOampduPkts,
353 RTL8365MB_MIB_inOampduPkts,
354 RTL8365MB_MIB_inIgmpJoinsSuccess,
355 RTL8365MB_MIB_inIgmpJoinsFail,
356 RTL8365MB_MIB_inMldJoinsSuccess,
357 RTL8365MB_MIB_inMldJoinsFail,
358 RTL8365MB_MIB_inReportSuppressionDrop,
359 RTL8365MB_MIB_inLeaveSuppressionDrop,
360 RTL8365MB_MIB_outIgmpReports,
361 RTL8365MB_MIB_outIgmpLeaves,
362 RTL8365MB_MIB_outIgmpGeneralQuery,
363 RTL8365MB_MIB_outIgmpSpecificQuery,
364 RTL8365MB_MIB_outMldReports,
365 RTL8365MB_MIB_outMldLeaves,
366 RTL8365MB_MIB_outMldGeneralQuery,
367 RTL8365MB_MIB_outMldSpecificQuery,
368 RTL8365MB_MIB_inKnownMulticastPkts,
369 RTL8365MB_MIB_END,
370};
371
372struct rtl8365mb_mib_counter {
373 u32 offset;
374 u32 length;
375 const char *name;
376};
377
378#define RTL8365MB_MAKE_MIB_COUNTER(_offset, _length, _name) \
379 [RTL8365MB_MIB_ ## _name] = { _offset, _length, #_name }
380
381static struct rtl8365mb_mib_counter rtl8365mb_mib_counters[] = {
382 RTL8365MB_MAKE_MIB_COUNTER(0, 4, ifInOctets),
383 RTL8365MB_MAKE_MIB_COUNTER(4, 2, dot3StatsFCSErrors),
384 RTL8365MB_MAKE_MIB_COUNTER(6, 2, dot3StatsSymbolErrors),
385 RTL8365MB_MAKE_MIB_COUNTER(8, 2, dot3InPauseFrames),
386 RTL8365MB_MAKE_MIB_COUNTER(10, 2, dot3ControlInUnknownOpcodes),
387 RTL8365MB_MAKE_MIB_COUNTER(12, 2, etherStatsFragments),
388 RTL8365MB_MAKE_MIB_COUNTER(14, 2, etherStatsJabbers),
389 RTL8365MB_MAKE_MIB_COUNTER(16, 2, ifInUcastPkts),
390 RTL8365MB_MAKE_MIB_COUNTER(18, 2, etherStatsDropEvents),
391 RTL8365MB_MAKE_MIB_COUNTER(20, 2, ifInMulticastPkts),
392 RTL8365MB_MAKE_MIB_COUNTER(22, 2, ifInBroadcastPkts),
393 RTL8365MB_MAKE_MIB_COUNTER(24, 2, inMldChecksumError),
394 RTL8365MB_MAKE_MIB_COUNTER(26, 2, inIgmpChecksumError),
395 RTL8365MB_MAKE_MIB_COUNTER(28, 2, inMldSpecificQuery),
396 RTL8365MB_MAKE_MIB_COUNTER(30, 2, inMldGeneralQuery),
397 RTL8365MB_MAKE_MIB_COUNTER(32, 2, inIgmpSpecificQuery),
398 RTL8365MB_MAKE_MIB_COUNTER(34, 2, inIgmpGeneralQuery),
399 RTL8365MB_MAKE_MIB_COUNTER(36, 2, inMldLeaves),
400 RTL8365MB_MAKE_MIB_COUNTER(38, 2, inIgmpLeaves),
401 RTL8365MB_MAKE_MIB_COUNTER(40, 4, etherStatsOctets),
402 RTL8365MB_MAKE_MIB_COUNTER(44, 2, etherStatsUnderSizePkts),
403 RTL8365MB_MAKE_MIB_COUNTER(46, 2, etherOversizeStats),
404 RTL8365MB_MAKE_MIB_COUNTER(48, 2, etherStatsPkts64Octets),
405 RTL8365MB_MAKE_MIB_COUNTER(50, 2, etherStatsPkts65to127Octets),
406 RTL8365MB_MAKE_MIB_COUNTER(52, 2, etherStatsPkts128to255Octets),
407 RTL8365MB_MAKE_MIB_COUNTER(54, 2, etherStatsPkts256to511Octets),
408 RTL8365MB_MAKE_MIB_COUNTER(56, 2, etherStatsPkts512to1023Octets),
409 RTL8365MB_MAKE_MIB_COUNTER(58, 2, etherStatsPkts1024to1518Octets),
410 RTL8365MB_MAKE_MIB_COUNTER(60, 4, ifOutOctets),
411 RTL8365MB_MAKE_MIB_COUNTER(64, 2, dot3StatsSingleCollisionFrames),
412 RTL8365MB_MAKE_MIB_COUNTER(66, 2, dot3StatsMultipleCollisionFrames),
413 RTL8365MB_MAKE_MIB_COUNTER(68, 2, dot3StatsDeferredTransmissions),
414 RTL8365MB_MAKE_MIB_COUNTER(70, 2, dot3StatsLateCollisions),
415 RTL8365MB_MAKE_MIB_COUNTER(72, 2, etherStatsCollisions),
416 RTL8365MB_MAKE_MIB_COUNTER(74, 2, dot3StatsExcessiveCollisions),
417 RTL8365MB_MAKE_MIB_COUNTER(76, 2, dot3OutPauseFrames),
418 RTL8365MB_MAKE_MIB_COUNTER(78, 2, ifOutDiscards),
419 RTL8365MB_MAKE_MIB_COUNTER(80, 2, dot1dTpPortInDiscards),
420 RTL8365MB_MAKE_MIB_COUNTER(82, 2, ifOutUcastPkts),
421 RTL8365MB_MAKE_MIB_COUNTER(84, 2, ifOutMulticastPkts),
422 RTL8365MB_MAKE_MIB_COUNTER(86, 2, ifOutBroadcastPkts),
423 RTL8365MB_MAKE_MIB_COUNTER(88, 2, outOampduPkts),
424 RTL8365MB_MAKE_MIB_COUNTER(90, 2, inOampduPkts),
425 RTL8365MB_MAKE_MIB_COUNTER(92, 4, inIgmpJoinsSuccess),
426 RTL8365MB_MAKE_MIB_COUNTER(96, 2, inIgmpJoinsFail),
427 RTL8365MB_MAKE_MIB_COUNTER(98, 2, inMldJoinsSuccess),
428 RTL8365MB_MAKE_MIB_COUNTER(100, 2, inMldJoinsFail),
429 RTL8365MB_MAKE_MIB_COUNTER(102, 2, inReportSuppressionDrop),
430 RTL8365MB_MAKE_MIB_COUNTER(104, 2, inLeaveSuppressionDrop),
431 RTL8365MB_MAKE_MIB_COUNTER(106, 2, outIgmpReports),
432 RTL8365MB_MAKE_MIB_COUNTER(108, 2, outIgmpLeaves),
433 RTL8365MB_MAKE_MIB_COUNTER(110, 2, outIgmpGeneralQuery),
434 RTL8365MB_MAKE_MIB_COUNTER(112, 2, outIgmpSpecificQuery),
435 RTL8365MB_MAKE_MIB_COUNTER(114, 2, outMldReports),
436 RTL8365MB_MAKE_MIB_COUNTER(116, 2, outMldLeaves),
437 RTL8365MB_MAKE_MIB_COUNTER(118, 2, outMldGeneralQuery),
438 RTL8365MB_MAKE_MIB_COUNTER(120, 2, outMldSpecificQuery),
439 RTL8365MB_MAKE_MIB_COUNTER(122, 2, inKnownMulticastPkts),
440};
441
442static_assert(ARRAY_SIZE(rtl8365mb_mib_counters) == RTL8365MB_MIB_END);
443
444struct rtl8365mb_jam_tbl_entry {
445 u16 reg;
446 u16 val;
447};
448
449
450static const struct rtl8365mb_jam_tbl_entry rtl8365mb_init_jam_8365mb_vc[] = {
451 { 0x13EB, 0x15BB }, { 0x1303, 0x06D6 }, { 0x1304, 0x0700 },
452 { 0x13E2, 0x003F }, { 0x13F9, 0x0090 }, { 0x121E, 0x03CA },
453 { 0x1233, 0x0352 }, { 0x1237, 0x00A0 }, { 0x123A, 0x0030 },
454 { 0x1239, 0x0084 }, { 0x0301, 0x1000 }, { 0x1349, 0x001F },
455 { 0x18E0, 0x4004 }, { 0x122B, 0x241C }, { 0x1305, 0xC000 },
456 { 0x13F0, 0x0000 },
457};
458
459static const struct rtl8365mb_jam_tbl_entry rtl8365mb_init_jam_common[] = {
460 { 0x1200, 0x7FCB }, { 0x0884, 0x0003 }, { 0x06EB, 0x0001 },
461 { 0x03Fa, 0x0007 }, { 0x08C8, 0x00C0 }, { 0x0A30, 0x020E },
462 { 0x0800, 0x0000 }, { 0x0802, 0x0000 }, { 0x09DA, 0x0013 },
463 { 0x1D32, 0x0002 },
464};
465
466enum rtl8365mb_stp_state {
467 RTL8365MB_STP_STATE_DISABLED = 0,
468 RTL8365MB_STP_STATE_BLOCKING = 1,
469 RTL8365MB_STP_STATE_LEARNING = 2,
470 RTL8365MB_STP_STATE_FORWARDING = 3,
471};
472
473enum rtl8365mb_cpu_insert {
474 RTL8365MB_CPU_INSERT_TO_ALL = 0,
475 RTL8365MB_CPU_INSERT_TO_TRAPPING = 1,
476 RTL8365MB_CPU_INSERT_TO_NONE = 2,
477};
478
479enum rtl8365mb_cpu_position {
480 RTL8365MB_CPU_POS_AFTER_SA = 0,
481 RTL8365MB_CPU_POS_BEFORE_CRC = 1,
482};
483
484enum rtl8365mb_cpu_format {
485 RTL8365MB_CPU_FORMAT_8BYTES = 0,
486 RTL8365MB_CPU_FORMAT_4BYTES = 1,
487};
488
489enum rtl8365mb_cpu_rxlen {
490 RTL8365MB_CPU_RXLEN_72BYTES = 0,
491 RTL8365MB_CPU_RXLEN_64BYTES = 1,
492};
493
494
495
496
497
498
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505
506
507struct rtl8365mb_cpu {
508 bool enable;
509 u32 mask;
510 u32 trap_port;
511 enum rtl8365mb_cpu_insert insert;
512 enum rtl8365mb_cpu_position position;
513 enum rtl8365mb_cpu_rxlen rx_length;
514 enum rtl8365mb_cpu_format format;
515};
516
517
518
519
520
521
522
523
524
525
526struct rtl8365mb_port {
527 struct realtek_smi *smi;
528 unsigned int index;
529 struct rtnl_link_stats64 stats;
530 spinlock_t stats_lock;
531 struct delayed_work mib_work;
532};
533
534
535
536
537
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539
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550struct rtl8365mb {
551 struct realtek_smi *smi;
552 int irq;
553 u32 chip_id;
554 u32 chip_ver;
555 u32 port_mask;
556 u32 learn_limit_max;
557 struct rtl8365mb_cpu cpu;
558 struct mutex mib_lock;
559 struct rtl8365mb_port ports[RTL8365MB_MAX_NUM_PORTS];
560 const struct rtl8365mb_jam_tbl_entry *jam_table;
561 size_t jam_size;
562};
563
564static int rtl8365mb_phy_poll_busy(struct realtek_smi *smi)
565{
566 u32 val;
567
568 return regmap_read_poll_timeout(smi->map,
569 RTL8365MB_INDIRECT_ACCESS_STATUS_REG,
570 val, !val, 10, 100);
571}
572
573static int rtl8365mb_phy_ocp_prepare(struct realtek_smi *smi, int phy,
574 u32 ocp_addr)
575{
576 u32 val;
577 int ret;
578
579
580 val = FIELD_GET(RTL8365MB_PHY_OCP_ADDR_PREFIX_MASK, ocp_addr);
581 ret = regmap_update_bits(
582 smi->map, RTL8365MB_GPHY_OCP_MSB_0_REG,
583 RTL8365MB_GPHY_OCP_MSB_0_CFG_CPU_OCPADR_MASK,
584 FIELD_PREP(RTL8365MB_GPHY_OCP_MSB_0_CFG_CPU_OCPADR_MASK, val));
585 if (ret)
586 return ret;
587
588
589 val = RTL8365MB_PHY_BASE;
590 val |= FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_ADDRESS_PHYNUM_MASK, phy);
591 val |= FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_ADDRESS_OCPADR_5_1_MASK,
592 ocp_addr >> 1);
593 val |= FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_ADDRESS_OCPADR_9_6_MASK,
594 ocp_addr >> 6);
595 ret = regmap_write(smi->map, RTL8365MB_INDIRECT_ACCESS_ADDRESS_REG,
596 val);
597 if (ret)
598 return ret;
599
600 return 0;
601}
602
603static int rtl8365mb_phy_ocp_read(struct realtek_smi *smi, int phy,
604 u32 ocp_addr, u16 *data)
605{
606 u32 val;
607 int ret;
608
609 ret = rtl8365mb_phy_poll_busy(smi);
610 if (ret)
611 return ret;
612
613 ret = rtl8365mb_phy_ocp_prepare(smi, phy, ocp_addr);
614 if (ret)
615 return ret;
616
617
618 val = FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_MASK,
619 RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_VALUE) |
620 FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_CTRL_RW_MASK,
621 RTL8365MB_INDIRECT_ACCESS_CTRL_RW_READ);
622 ret = regmap_write(smi->map, RTL8365MB_INDIRECT_ACCESS_CTRL_REG, val);
623 if (ret)
624 return ret;
625
626 ret = rtl8365mb_phy_poll_busy(smi);
627 if (ret)
628 return ret;
629
630
631 ret = regmap_read(smi->map, RTL8365MB_INDIRECT_ACCESS_READ_DATA_REG,
632 &val);
633 if (ret)
634 return ret;
635
636 *data = val & 0xFFFF;
637
638 return 0;
639}
640
641static int rtl8365mb_phy_ocp_write(struct realtek_smi *smi, int phy,
642 u32 ocp_addr, u16 data)
643{
644 u32 val;
645 int ret;
646
647 ret = rtl8365mb_phy_poll_busy(smi);
648 if (ret)
649 return ret;
650
651 ret = rtl8365mb_phy_ocp_prepare(smi, phy, ocp_addr);
652 if (ret)
653 return ret;
654
655
656 ret = regmap_write(smi->map, RTL8365MB_INDIRECT_ACCESS_WRITE_DATA_REG,
657 data);
658 if (ret)
659 return ret;
660
661
662 val = FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_MASK,
663 RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_VALUE) |
664 FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_CTRL_RW_MASK,
665 RTL8365MB_INDIRECT_ACCESS_CTRL_RW_WRITE);
666 ret = regmap_write(smi->map, RTL8365MB_INDIRECT_ACCESS_CTRL_REG, val);
667 if (ret)
668 return ret;
669
670 ret = rtl8365mb_phy_poll_busy(smi);
671 if (ret)
672 return ret;
673
674 return 0;
675}
676
677static int rtl8365mb_phy_read(struct realtek_smi *smi, int phy, int regnum)
678{
679 u32 ocp_addr;
680 u16 val;
681 int ret;
682
683 if (phy > RTL8365MB_PHYADDRMAX)
684 return -EINVAL;
685
686 if (regnum > RTL8365MB_PHYREGMAX)
687 return -EINVAL;
688
689 ocp_addr = RTL8365MB_PHY_OCP_ADDR_PHYREG_BASE + regnum * 2;
690
691 ret = rtl8365mb_phy_ocp_read(smi, phy, ocp_addr, &val);
692 if (ret) {
693 dev_err(smi->dev,
694 "failed to read PHY%d reg %02x @ %04x, ret %d\n", phy,
695 regnum, ocp_addr, ret);
696 return ret;
697 }
698
699 dev_dbg(smi->dev, "read PHY%d register 0x%02x @ %04x, val <- %04x\n",
700 phy, regnum, ocp_addr, val);
701
702 return val;
703}
704
705static int rtl8365mb_phy_write(struct realtek_smi *smi, int phy, int regnum,
706 u16 val)
707{
708 u32 ocp_addr;
709 int ret;
710
711 if (phy > RTL8365MB_PHYADDRMAX)
712 return -EINVAL;
713
714 if (regnum > RTL8365MB_PHYREGMAX)
715 return -EINVAL;
716
717 ocp_addr = RTL8365MB_PHY_OCP_ADDR_PHYREG_BASE + regnum * 2;
718
719 ret = rtl8365mb_phy_ocp_write(smi, phy, ocp_addr, val);
720 if (ret) {
721 dev_err(smi->dev,
722 "failed to write PHY%d reg %02x @ %04x, ret %d\n", phy,
723 regnum, ocp_addr, ret);
724 return ret;
725 }
726
727 dev_dbg(smi->dev, "write PHY%d register 0x%02x @ %04x, val -> %04x\n",
728 phy, regnum, ocp_addr, val);
729
730 return 0;
731}
732
733static enum dsa_tag_protocol
734rtl8365mb_get_tag_protocol(struct dsa_switch *ds, int port,
735 enum dsa_tag_protocol mp)
736{
737 return DSA_TAG_PROTO_RTL8_4;
738}
739
740static int rtl8365mb_ext_config_rgmii(struct realtek_smi *smi, int port,
741 phy_interface_t interface)
742{
743 struct device_node *dn;
744 struct dsa_port *dp;
745 int tx_delay = 0;
746 int rx_delay = 0;
747 int ext_port;
748 u32 val;
749 int ret;
750
751 if (port == smi->cpu_port) {
752 ext_port = 1;
753 } else {
754 dev_err(smi->dev, "only one EXT port is currently supported\n");
755 return -EINVAL;
756 }
757
758 dp = dsa_to_port(smi->ds, port);
759 dn = dp->dn;
760
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783 if (!of_property_read_u32(dn, "tx-internal-delay-ps", &val)) {
784 val = val / 1000;
785
786 if (val == 0 || val == 2)
787 tx_delay = val / 2;
788 else
789 dev_warn(smi->dev,
790 "EXT port TX delay must be 0 or 2 ns\n");
791 }
792
793 if (!of_property_read_u32(dn, "rx-internal-delay-ps", &val)) {
794 val = DIV_ROUND_CLOSEST(val, 300);
795
796 if (val <= 7)
797 rx_delay = val;
798 else
799 dev_warn(smi->dev,
800 "EXT port RX delay must be 0 to 2.1 ns\n");
801 }
802
803 ret = regmap_update_bits(
804 smi->map, RTL8365MB_EXT_RGMXF_REG(ext_port),
805 RTL8365MB_EXT_RGMXF_TXDELAY_MASK |
806 RTL8365MB_EXT_RGMXF_RXDELAY_MASK,
807 FIELD_PREP(RTL8365MB_EXT_RGMXF_TXDELAY_MASK, tx_delay) |
808 FIELD_PREP(RTL8365MB_EXT_RGMXF_RXDELAY_MASK, rx_delay));
809 if (ret)
810 return ret;
811
812 ret = regmap_update_bits(
813 smi->map, RTL8365MB_DIGITAL_INTERFACE_SELECT_REG(ext_port),
814 RTL8365MB_DIGITAL_INTERFACE_SELECT_MODE_MASK(ext_port),
815 RTL8365MB_EXT_PORT_MODE_RGMII
816 << RTL8365MB_DIGITAL_INTERFACE_SELECT_MODE_OFFSET(
817 ext_port));
818 if (ret)
819 return ret;
820
821 return 0;
822}
823
824static int rtl8365mb_ext_config_forcemode(struct realtek_smi *smi, int port,
825 bool link, int speed, int duplex,
826 bool tx_pause, bool rx_pause)
827{
828 u32 r_tx_pause;
829 u32 r_rx_pause;
830 u32 r_duplex;
831 u32 r_speed;
832 u32 r_link;
833 int ext_port;
834 int val;
835 int ret;
836
837 if (port == smi->cpu_port) {
838 ext_port = 1;
839 } else {
840 dev_err(smi->dev, "only one EXT port is currently supported\n");
841 return -EINVAL;
842 }
843
844 if (link) {
845
846 r_link = 1;
847 r_rx_pause = rx_pause ? 1 : 0;
848 r_tx_pause = tx_pause ? 1 : 0;
849
850 if (speed == SPEED_1000) {
851 r_speed = RTL8365MB_PORT_SPEED_1000M;
852 } else if (speed == SPEED_100) {
853 r_speed = RTL8365MB_PORT_SPEED_100M;
854 } else if (speed == SPEED_10) {
855 r_speed = RTL8365MB_PORT_SPEED_10M;
856 } else {
857 dev_err(smi->dev, "unsupported port speed %s\n",
858 phy_speed_to_str(speed));
859 return -EINVAL;
860 }
861
862 if (duplex == DUPLEX_FULL) {
863 r_duplex = 1;
864 } else if (duplex == DUPLEX_HALF) {
865 r_duplex = 0;
866 } else {
867 dev_err(smi->dev, "unsupported duplex %s\n",
868 phy_duplex_to_str(duplex));
869 return -EINVAL;
870 }
871 } else {
872
873 r_link = 0;
874 r_tx_pause = 0;
875 r_rx_pause = 0;
876 r_speed = 0;
877 r_duplex = 0;
878 }
879
880 val = FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_EN_MASK, 1) |
881 FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_TXPAUSE_MASK,
882 r_tx_pause) |
883 FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_RXPAUSE_MASK,
884 r_rx_pause) |
885 FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_LINK_MASK, r_link) |
886 FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_DUPLEX_MASK,
887 r_duplex) |
888 FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_SPEED_MASK, r_speed);
889 ret = regmap_write(smi->map,
890 RTL8365MB_DIGITAL_INTERFACE_FORCE_REG(ext_port),
891 val);
892 if (ret)
893 return ret;
894
895 return 0;
896}
897
898static bool rtl8365mb_phy_mode_supported(struct dsa_switch *ds, int port,
899 phy_interface_t interface)
900{
901 if (dsa_is_user_port(ds, port) &&
902 (interface == PHY_INTERFACE_MODE_NA ||
903 interface == PHY_INTERFACE_MODE_INTERNAL ||
904 interface == PHY_INTERFACE_MODE_GMII))
905
906 return true;
907 else if (dsa_is_cpu_port(ds, port) &&
908 phy_interface_mode_is_rgmii(interface))
909
910 return true;
911
912 return false;
913}
914
915static void rtl8365mb_phylink_validate(struct dsa_switch *ds, int port,
916 unsigned long *supported,
917 struct phylink_link_state *state)
918{
919 struct realtek_smi *smi = ds->priv;
920 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0 };
921
922
923
924
925
926 if (state->interface != PHY_INTERFACE_MODE_NA &&
927 !rtl8365mb_phy_mode_supported(ds, port, state->interface)) {
928 dev_err(smi->dev, "phy mode %s is unsupported on port %d\n",
929 phy_modes(state->interface), port);
930 linkmode_zero(supported);
931 return;
932 }
933
934 phylink_set_port_modes(mask);
935
936 phylink_set(mask, Autoneg);
937 phylink_set(mask, Pause);
938 phylink_set(mask, Asym_Pause);
939
940 phylink_set(mask, 10baseT_Half);
941 phylink_set(mask, 10baseT_Full);
942 phylink_set(mask, 100baseT_Half);
943 phylink_set(mask, 100baseT_Full);
944 phylink_set(mask, 1000baseT_Full);
945
946 linkmode_and(supported, supported, mask);
947 linkmode_and(state->advertising, state->advertising, mask);
948}
949
950static void rtl8365mb_phylink_mac_config(struct dsa_switch *ds, int port,
951 unsigned int mode,
952 const struct phylink_link_state *state)
953{
954 struct realtek_smi *smi = ds->priv;
955 int ret;
956
957 if (!rtl8365mb_phy_mode_supported(ds, port, state->interface)) {
958 dev_err(smi->dev, "phy mode %s is unsupported on port %d\n",
959 phy_modes(state->interface), port);
960 return;
961 }
962
963 if (mode != MLO_AN_PHY && mode != MLO_AN_FIXED) {
964 dev_err(smi->dev,
965 "port %d supports only conventional PHY or fixed-link\n",
966 port);
967 return;
968 }
969
970 if (phy_interface_mode_is_rgmii(state->interface)) {
971 ret = rtl8365mb_ext_config_rgmii(smi, port, state->interface);
972 if (ret)
973 dev_err(smi->dev,
974 "failed to configure RGMII mode on port %d: %d\n",
975 port, ret);
976 return;
977 }
978
979
980
981
982}
983
984static void rtl8365mb_phylink_mac_link_down(struct dsa_switch *ds, int port,
985 unsigned int mode,
986 phy_interface_t interface)
987{
988 struct realtek_smi *smi = ds->priv;
989 struct rtl8365mb_port *p;
990 struct rtl8365mb *mb;
991 int ret;
992
993 mb = smi->chip_data;
994 p = &mb->ports[port];
995 cancel_delayed_work_sync(&p->mib_work);
996
997 if (phy_interface_mode_is_rgmii(interface)) {
998 ret = rtl8365mb_ext_config_forcemode(smi, port, false, 0, 0,
999 false, false);
1000 if (ret)
1001 dev_err(smi->dev,
1002 "failed to reset forced mode on port %d: %d\n",
1003 port, ret);
1004
1005 return;
1006 }
1007}
1008
1009static void rtl8365mb_phylink_mac_link_up(struct dsa_switch *ds, int port,
1010 unsigned int mode,
1011 phy_interface_t interface,
1012 struct phy_device *phydev, int speed,
1013 int duplex, bool tx_pause,
1014 bool rx_pause)
1015{
1016 struct realtek_smi *smi = ds->priv;
1017 struct rtl8365mb_port *p;
1018 struct rtl8365mb *mb;
1019 int ret;
1020
1021 mb = smi->chip_data;
1022 p = &mb->ports[port];
1023 schedule_delayed_work(&p->mib_work, 0);
1024
1025 if (phy_interface_mode_is_rgmii(interface)) {
1026 ret = rtl8365mb_ext_config_forcemode(smi, port, true, speed,
1027 duplex, tx_pause,
1028 rx_pause);
1029 if (ret)
1030 dev_err(smi->dev,
1031 "failed to force mode on port %d: %d\n", port,
1032 ret);
1033
1034 return;
1035 }
1036}
1037
1038static void rtl8365mb_port_stp_state_set(struct dsa_switch *ds, int port,
1039 u8 state)
1040{
1041 struct realtek_smi *smi = ds->priv;
1042 enum rtl8365mb_stp_state val;
1043 int msti = 0;
1044
1045 switch (state) {
1046 case BR_STATE_DISABLED:
1047 val = RTL8365MB_STP_STATE_DISABLED;
1048 break;
1049 case BR_STATE_BLOCKING:
1050 case BR_STATE_LISTENING:
1051 val = RTL8365MB_STP_STATE_BLOCKING;
1052 break;
1053 case BR_STATE_LEARNING:
1054 val = RTL8365MB_STP_STATE_LEARNING;
1055 break;
1056 case BR_STATE_FORWARDING:
1057 val = RTL8365MB_STP_STATE_FORWARDING;
1058 break;
1059 default:
1060 dev_err(smi->dev, "invalid STP state: %u\n", state);
1061 return;
1062 }
1063
1064 regmap_update_bits(smi->map, RTL8365MB_MSTI_CTRL_REG(msti, port),
1065 RTL8365MB_MSTI_CTRL_PORT_STATE_MASK(port),
1066 val << RTL8365MB_MSTI_CTRL_PORT_STATE_OFFSET(port));
1067}
1068
1069static int rtl8365mb_port_set_learning(struct realtek_smi *smi, int port,
1070 bool enable)
1071{
1072 struct rtl8365mb *mb = smi->chip_data;
1073
1074
1075
1076
1077
1078
1079 return regmap_write(smi->map, RTL8365MB_LUT_PORT_LEARN_LIMIT_REG(port),
1080 enable ? mb->learn_limit_max : 0);
1081}
1082
1083static int rtl8365mb_port_set_isolation(struct realtek_smi *smi, int port,
1084 u32 mask)
1085{
1086 return regmap_write(smi->map, RTL8365MB_PORT_ISOLATION_REG(port), mask);
1087}
1088
1089static int rtl8365mb_mib_counter_read(struct realtek_smi *smi, int port,
1090 u32 offset, u32 length, u64 *mibvalue)
1091{
1092 u64 tmpvalue = 0;
1093 u32 val;
1094 int ret;
1095 int i;
1096
1097
1098
1099
1100
1101 ret = regmap_write(smi->map, RTL8365MB_MIB_ADDRESS_REG,
1102 RTL8365MB_MIB_ADDRESS(port, offset));
1103 if (ret)
1104 return ret;
1105
1106
1107 ret = regmap_read_poll_timeout(smi->map, RTL8365MB_MIB_CTRL0_REG, val,
1108 !(val & RTL8365MB_MIB_CTRL0_BUSY_MASK),
1109 10, 100);
1110 if (ret)
1111 return ret;
1112
1113
1114 if (val & RTL8365MB_MIB_CTRL0_RESET_MASK)
1115 return -EIO;
1116
1117
1118
1119
1120
1121
1122 if (length == 4)
1123 offset = 3;
1124 else
1125 offset = (offset + 1) % 4;
1126
1127
1128 for (i = 0; i < length; i++) {
1129 ret = regmap_read(smi->map,
1130 RTL8365MB_MIB_COUNTER_REG(offset - i), &val);
1131 if (ret)
1132 return ret;
1133
1134 tmpvalue = ((tmpvalue) << 16) | (val & 0xFFFF);
1135 }
1136
1137
1138 *mibvalue = tmpvalue;
1139
1140 return 0;
1141}
1142
1143static void rtl8365mb_get_ethtool_stats(struct dsa_switch *ds, int port, u64 *data)
1144{
1145 struct realtek_smi *smi = ds->priv;
1146 struct rtl8365mb *mb;
1147 int ret;
1148 int i;
1149
1150 mb = smi->chip_data;
1151
1152 mutex_lock(&mb->mib_lock);
1153 for (i = 0; i < RTL8365MB_MIB_END; i++) {
1154 struct rtl8365mb_mib_counter *mib = &rtl8365mb_mib_counters[i];
1155
1156 ret = rtl8365mb_mib_counter_read(smi, port, mib->offset,
1157 mib->length, &data[i]);
1158 if (ret) {
1159 dev_err(smi->dev,
1160 "failed to read port %d counters: %d\n", port,
1161 ret);
1162 break;
1163 }
1164 }
1165 mutex_unlock(&mb->mib_lock);
1166}
1167
1168static void rtl8365mb_get_strings(struct dsa_switch *ds, int port, u32 stringset, u8 *data)
1169{
1170 int i;
1171
1172 if (stringset != ETH_SS_STATS)
1173 return;
1174
1175 for (i = 0; i < RTL8365MB_MIB_END; i++) {
1176 struct rtl8365mb_mib_counter *mib = &rtl8365mb_mib_counters[i];
1177
1178 strncpy(data + i * ETH_GSTRING_LEN, mib->name, ETH_GSTRING_LEN);
1179 }
1180}
1181
1182static int rtl8365mb_get_sset_count(struct dsa_switch *ds, int port, int sset)
1183{
1184 if (sset != ETH_SS_STATS)
1185 return -EOPNOTSUPP;
1186
1187 return RTL8365MB_MIB_END;
1188}
1189
1190static void rtl8365mb_get_phy_stats(struct dsa_switch *ds, int port,
1191 struct ethtool_eth_phy_stats *phy_stats)
1192{
1193 struct realtek_smi *smi = ds->priv;
1194 struct rtl8365mb_mib_counter *mib;
1195 struct rtl8365mb *mb;
1196
1197 mb = smi->chip_data;
1198 mib = &rtl8365mb_mib_counters[RTL8365MB_MIB_dot3StatsSymbolErrors];
1199
1200 mutex_lock(&mb->mib_lock);
1201 rtl8365mb_mib_counter_read(smi, port, mib->offset, mib->length,
1202 &phy_stats->SymbolErrorDuringCarrier);
1203 mutex_unlock(&mb->mib_lock);
1204}
1205
1206static void rtl8365mb_get_mac_stats(struct dsa_switch *ds, int port,
1207 struct ethtool_eth_mac_stats *mac_stats)
1208{
1209 u64 cnt[RTL8365MB_MIB_END] = {
1210 [RTL8365MB_MIB_ifOutOctets] = 1,
1211 [RTL8365MB_MIB_ifOutUcastPkts] = 1,
1212 [RTL8365MB_MIB_ifOutMulticastPkts] = 1,
1213 [RTL8365MB_MIB_ifOutBroadcastPkts] = 1,
1214 [RTL8365MB_MIB_dot3OutPauseFrames] = 1,
1215 [RTL8365MB_MIB_ifOutDiscards] = 1,
1216 [RTL8365MB_MIB_ifInOctets] = 1,
1217 [RTL8365MB_MIB_ifInUcastPkts] = 1,
1218 [RTL8365MB_MIB_ifInMulticastPkts] = 1,
1219 [RTL8365MB_MIB_ifInBroadcastPkts] = 1,
1220 [RTL8365MB_MIB_dot3InPauseFrames] = 1,
1221 [RTL8365MB_MIB_dot3StatsSingleCollisionFrames] = 1,
1222 [RTL8365MB_MIB_dot3StatsMultipleCollisionFrames] = 1,
1223 [RTL8365MB_MIB_dot3StatsFCSErrors] = 1,
1224 [RTL8365MB_MIB_dot3StatsDeferredTransmissions] = 1,
1225 [RTL8365MB_MIB_dot3StatsLateCollisions] = 1,
1226 [RTL8365MB_MIB_dot3StatsExcessiveCollisions] = 1,
1227
1228 };
1229 struct realtek_smi *smi = ds->priv;
1230 struct rtl8365mb *mb;
1231 int ret;
1232 int i;
1233
1234 mb = smi->chip_data;
1235
1236 mutex_lock(&mb->mib_lock);
1237 for (i = 0; i < RTL8365MB_MIB_END; i++) {
1238 struct rtl8365mb_mib_counter *mib = &rtl8365mb_mib_counters[i];
1239
1240
1241 if (!cnt[i])
1242 continue;
1243
1244 ret = rtl8365mb_mib_counter_read(smi, port, mib->offset,
1245 mib->length, &cnt[i]);
1246 if (ret)
1247 break;
1248 }
1249 mutex_unlock(&mb->mib_lock);
1250
1251
1252
1253
1254
1255
1256
1257 mac_stats->FramesTransmittedOK = cnt[RTL8365MB_MIB_ifOutUcastPkts] +
1258 cnt[RTL8365MB_MIB_ifOutMulticastPkts] +
1259 cnt[RTL8365MB_MIB_ifOutBroadcastPkts] +
1260 cnt[RTL8365MB_MIB_dot3OutPauseFrames] -
1261 cnt[RTL8365MB_MIB_ifOutDiscards];
1262 mac_stats->SingleCollisionFrames =
1263 cnt[RTL8365MB_MIB_dot3StatsSingleCollisionFrames];
1264 mac_stats->MultipleCollisionFrames =
1265 cnt[RTL8365MB_MIB_dot3StatsMultipleCollisionFrames];
1266 mac_stats->FramesReceivedOK = cnt[RTL8365MB_MIB_ifInUcastPkts] +
1267 cnt[RTL8365MB_MIB_ifInMulticastPkts] +
1268 cnt[RTL8365MB_MIB_ifInBroadcastPkts] +
1269 cnt[RTL8365MB_MIB_dot3InPauseFrames];
1270 mac_stats->FrameCheckSequenceErrors =
1271 cnt[RTL8365MB_MIB_dot3StatsFCSErrors];
1272 mac_stats->OctetsTransmittedOK = cnt[RTL8365MB_MIB_ifOutOctets] -
1273 18 * mac_stats->FramesTransmittedOK;
1274 mac_stats->FramesWithDeferredXmissions =
1275 cnt[RTL8365MB_MIB_dot3StatsDeferredTransmissions];
1276 mac_stats->LateCollisions = cnt[RTL8365MB_MIB_dot3StatsLateCollisions];
1277 mac_stats->FramesAbortedDueToXSColls =
1278 cnt[RTL8365MB_MIB_dot3StatsExcessiveCollisions];
1279 mac_stats->OctetsReceivedOK = cnt[RTL8365MB_MIB_ifInOctets] -
1280 18 * mac_stats->FramesReceivedOK;
1281 mac_stats->MulticastFramesXmittedOK =
1282 cnt[RTL8365MB_MIB_ifOutMulticastPkts];
1283 mac_stats->BroadcastFramesXmittedOK =
1284 cnt[RTL8365MB_MIB_ifOutBroadcastPkts];
1285 mac_stats->MulticastFramesReceivedOK =
1286 cnt[RTL8365MB_MIB_ifInMulticastPkts];
1287 mac_stats->BroadcastFramesReceivedOK =
1288 cnt[RTL8365MB_MIB_ifInBroadcastPkts];
1289}
1290
1291static void rtl8365mb_get_ctrl_stats(struct dsa_switch *ds, int port,
1292 struct ethtool_eth_ctrl_stats *ctrl_stats)
1293{
1294 struct realtek_smi *smi = ds->priv;
1295 struct rtl8365mb_mib_counter *mib;
1296 struct rtl8365mb *mb;
1297
1298 mb = smi->chip_data;
1299 mib = &rtl8365mb_mib_counters[RTL8365MB_MIB_dot3ControlInUnknownOpcodes];
1300
1301 mutex_lock(&mb->mib_lock);
1302 rtl8365mb_mib_counter_read(smi, port, mib->offset, mib->length,
1303 &ctrl_stats->UnsupportedOpcodesReceived);
1304 mutex_unlock(&mb->mib_lock);
1305}
1306
1307static void rtl8365mb_stats_update(struct realtek_smi *smi, int port)
1308{
1309 u64 cnt[RTL8365MB_MIB_END] = {
1310 [RTL8365MB_MIB_ifOutOctets] = 1,
1311 [RTL8365MB_MIB_ifOutUcastPkts] = 1,
1312 [RTL8365MB_MIB_ifOutMulticastPkts] = 1,
1313 [RTL8365MB_MIB_ifOutBroadcastPkts] = 1,
1314 [RTL8365MB_MIB_ifOutDiscards] = 1,
1315 [RTL8365MB_MIB_ifInOctets] = 1,
1316 [RTL8365MB_MIB_ifInUcastPkts] = 1,
1317 [RTL8365MB_MIB_ifInMulticastPkts] = 1,
1318 [RTL8365MB_MIB_ifInBroadcastPkts] = 1,
1319 [RTL8365MB_MIB_etherStatsDropEvents] = 1,
1320 [RTL8365MB_MIB_etherStatsCollisions] = 1,
1321 [RTL8365MB_MIB_etherStatsFragments] = 1,
1322 [RTL8365MB_MIB_etherStatsJabbers] = 1,
1323 [RTL8365MB_MIB_dot3StatsFCSErrors] = 1,
1324 [RTL8365MB_MIB_dot3StatsLateCollisions] = 1,
1325 };
1326 struct rtl8365mb *mb = smi->chip_data;
1327 struct rtnl_link_stats64 *stats;
1328 int ret;
1329 int i;
1330
1331 stats = &mb->ports[port].stats;
1332
1333 mutex_lock(&mb->mib_lock);
1334 for (i = 0; i < RTL8365MB_MIB_END; i++) {
1335 struct rtl8365mb_mib_counter *c = &rtl8365mb_mib_counters[i];
1336
1337
1338 if (!cnt[i])
1339 continue;
1340
1341 ret = rtl8365mb_mib_counter_read(smi, port, c->offset,
1342 c->length, &cnt[i]);
1343 if (ret)
1344 break;
1345 }
1346 mutex_unlock(&mb->mib_lock);
1347
1348
1349 if (ret)
1350 return;
1351
1352 spin_lock(&mb->ports[port].stats_lock);
1353
1354 stats->rx_packets = cnt[RTL8365MB_MIB_ifInUcastPkts] +
1355 cnt[RTL8365MB_MIB_ifInMulticastPkts] +
1356 cnt[RTL8365MB_MIB_ifInBroadcastPkts] -
1357 cnt[RTL8365MB_MIB_ifOutDiscards];
1358
1359 stats->tx_packets = cnt[RTL8365MB_MIB_ifOutUcastPkts] +
1360 cnt[RTL8365MB_MIB_ifOutMulticastPkts] +
1361 cnt[RTL8365MB_MIB_ifOutBroadcastPkts];
1362
1363
1364 stats->rx_bytes = cnt[RTL8365MB_MIB_ifInOctets] - 4 * stats->rx_packets;
1365 stats->tx_bytes =
1366 cnt[RTL8365MB_MIB_ifOutOctets] - 4 * stats->tx_packets;
1367
1368 stats->rx_dropped = cnt[RTL8365MB_MIB_etherStatsDropEvents];
1369 stats->tx_dropped = cnt[RTL8365MB_MIB_ifOutDiscards];
1370
1371 stats->multicast = cnt[RTL8365MB_MIB_ifInMulticastPkts];
1372 stats->collisions = cnt[RTL8365MB_MIB_etherStatsCollisions];
1373
1374 stats->rx_length_errors = cnt[RTL8365MB_MIB_etherStatsFragments] +
1375 cnt[RTL8365MB_MIB_etherStatsJabbers];
1376 stats->rx_crc_errors = cnt[RTL8365MB_MIB_dot3StatsFCSErrors];
1377 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors;
1378
1379 stats->tx_aborted_errors = cnt[RTL8365MB_MIB_ifOutDiscards];
1380 stats->tx_window_errors = cnt[RTL8365MB_MIB_dot3StatsLateCollisions];
1381 stats->tx_errors = stats->tx_aborted_errors + stats->tx_window_errors;
1382
1383 spin_unlock(&mb->ports[port].stats_lock);
1384}
1385
1386static void rtl8365mb_stats_poll(struct work_struct *work)
1387{
1388 struct rtl8365mb_port *p = container_of(to_delayed_work(work),
1389 struct rtl8365mb_port,
1390 mib_work);
1391 struct realtek_smi *smi = p->smi;
1392
1393 rtl8365mb_stats_update(smi, p->index);
1394
1395 schedule_delayed_work(&p->mib_work, RTL8365MB_STATS_INTERVAL_JIFFIES);
1396}
1397
1398static void rtl8365mb_get_stats64(struct dsa_switch *ds, int port,
1399 struct rtnl_link_stats64 *s)
1400{
1401 struct realtek_smi *smi = ds->priv;
1402 struct rtl8365mb_port *p;
1403 struct rtl8365mb *mb;
1404
1405 mb = smi->chip_data;
1406 p = &mb->ports[port];
1407
1408 spin_lock(&p->stats_lock);
1409 memcpy(s, &p->stats, sizeof(*s));
1410 spin_unlock(&p->stats_lock);
1411}
1412
1413static void rtl8365mb_stats_setup(struct realtek_smi *smi)
1414{
1415 struct rtl8365mb *mb = smi->chip_data;
1416 int i;
1417
1418
1419
1420
1421 mutex_init(&mb->mib_lock);
1422
1423 for (i = 0; i < smi->num_ports; i++) {
1424 struct rtl8365mb_port *p = &mb->ports[i];
1425
1426 if (dsa_is_unused_port(smi->ds, i))
1427 continue;
1428
1429
1430 spin_lock_init(&p->stats_lock);
1431
1432
1433
1434
1435 INIT_DELAYED_WORK(&p->mib_work, rtl8365mb_stats_poll);
1436 }
1437}
1438
1439static void rtl8365mb_stats_teardown(struct realtek_smi *smi)
1440{
1441 struct rtl8365mb *mb = smi->chip_data;
1442 int i;
1443
1444 for (i = 0; i < smi->num_ports; i++) {
1445 struct rtl8365mb_port *p = &mb->ports[i];
1446
1447 if (dsa_is_unused_port(smi->ds, i))
1448 continue;
1449
1450 cancel_delayed_work_sync(&p->mib_work);
1451 }
1452}
1453
1454static int rtl8365mb_get_and_clear_status_reg(struct realtek_smi *smi, u32 reg,
1455 u32 *val)
1456{
1457 int ret;
1458
1459 ret = regmap_read(smi->map, reg, val);
1460 if (ret)
1461 return ret;
1462
1463 return regmap_write(smi->map, reg, *val);
1464}
1465
1466static irqreturn_t rtl8365mb_irq(int irq, void *data)
1467{
1468 struct realtek_smi *smi = data;
1469 unsigned long line_changes = 0;
1470 struct rtl8365mb *mb;
1471 u32 stat;
1472 int line;
1473 int ret;
1474
1475 mb = smi->chip_data;
1476
1477 ret = rtl8365mb_get_and_clear_status_reg(smi, RTL8365MB_INTR_STATUS_REG,
1478 &stat);
1479 if (ret)
1480 goto out_error;
1481
1482 if (stat & RTL8365MB_INTR_LINK_CHANGE_MASK) {
1483 u32 linkdown_ind;
1484 u32 linkup_ind;
1485 u32 val;
1486
1487 ret = rtl8365mb_get_and_clear_status_reg(
1488 smi, RTL8365MB_PORT_LINKUP_IND_REG, &val);
1489 if (ret)
1490 goto out_error;
1491
1492 linkup_ind = FIELD_GET(RTL8365MB_PORT_LINKUP_IND_MASK, val);
1493
1494 ret = rtl8365mb_get_and_clear_status_reg(
1495 smi, RTL8365MB_PORT_LINKDOWN_IND_REG, &val);
1496 if (ret)
1497 goto out_error;
1498
1499 linkdown_ind = FIELD_GET(RTL8365MB_PORT_LINKDOWN_IND_MASK, val);
1500
1501 line_changes = (linkup_ind | linkdown_ind) & mb->port_mask;
1502 }
1503
1504 if (!line_changes)
1505 goto out_none;
1506
1507 for_each_set_bit(line, &line_changes, smi->num_ports) {
1508 int child_irq = irq_find_mapping(smi->irqdomain, line);
1509
1510 handle_nested_irq(child_irq);
1511 }
1512
1513 return IRQ_HANDLED;
1514
1515out_error:
1516 dev_err(smi->dev, "failed to read interrupt status: %d\n", ret);
1517
1518out_none:
1519 return IRQ_NONE;
1520}
1521
1522static struct irq_chip rtl8365mb_irq_chip = {
1523 .name = "rtl8365mb",
1524
1525};
1526
1527static int rtl8365mb_irq_map(struct irq_domain *domain, unsigned int irq,
1528 irq_hw_number_t hwirq)
1529{
1530 irq_set_chip_data(irq, domain->host_data);
1531 irq_set_chip_and_handler(irq, &rtl8365mb_irq_chip, handle_simple_irq);
1532 irq_set_nested_thread(irq, 1);
1533 irq_set_noprobe(irq);
1534
1535 return 0;
1536}
1537
1538static void rtl8365mb_irq_unmap(struct irq_domain *d, unsigned int irq)
1539{
1540 irq_set_nested_thread(irq, 0);
1541 irq_set_chip_and_handler(irq, NULL, NULL);
1542 irq_set_chip_data(irq, NULL);
1543}
1544
1545static const struct irq_domain_ops rtl8365mb_irqdomain_ops = {
1546 .map = rtl8365mb_irq_map,
1547 .unmap = rtl8365mb_irq_unmap,
1548 .xlate = irq_domain_xlate_onecell,
1549};
1550
1551static int rtl8365mb_set_irq_enable(struct realtek_smi *smi, bool enable)
1552{
1553 return regmap_update_bits(smi->map, RTL8365MB_INTR_CTRL_REG,
1554 RTL8365MB_INTR_LINK_CHANGE_MASK,
1555 FIELD_PREP(RTL8365MB_INTR_LINK_CHANGE_MASK,
1556 enable ? 1 : 0));
1557}
1558
1559static int rtl8365mb_irq_enable(struct realtek_smi *smi)
1560{
1561 return rtl8365mb_set_irq_enable(smi, true);
1562}
1563
1564static int rtl8365mb_irq_disable(struct realtek_smi *smi)
1565{
1566 return rtl8365mb_set_irq_enable(smi, false);
1567}
1568
1569static int rtl8365mb_irq_setup(struct realtek_smi *smi)
1570{
1571 struct rtl8365mb *mb = smi->chip_data;
1572 struct device_node *intc;
1573 u32 irq_trig;
1574 int virq;
1575 int irq;
1576 u32 val;
1577 int ret;
1578 int i;
1579
1580 intc = of_get_child_by_name(smi->dev->of_node, "interrupt-controller");
1581 if (!intc) {
1582 dev_err(smi->dev, "missing child interrupt-controller node\n");
1583 return -EINVAL;
1584 }
1585
1586
1587 irq = of_irq_get(intc, 0);
1588 if (irq <= 0) {
1589 if (irq != -EPROBE_DEFER)
1590 dev_err(smi->dev, "failed to get parent irq: %d\n",
1591 irq);
1592 ret = irq ? irq : -EINVAL;
1593 goto out_put_node;
1594 }
1595
1596 smi->irqdomain = irq_domain_add_linear(intc, smi->num_ports,
1597 &rtl8365mb_irqdomain_ops, smi);
1598 if (!smi->irqdomain) {
1599 dev_err(smi->dev, "failed to add irq domain\n");
1600 ret = -ENOMEM;
1601 goto out_put_node;
1602 }
1603
1604 for (i = 0; i < smi->num_ports; i++) {
1605 virq = irq_create_mapping(smi->irqdomain, i);
1606 if (!virq) {
1607 dev_err(smi->dev,
1608 "failed to create irq domain mapping\n");
1609 ret = -EINVAL;
1610 goto out_remove_irqdomain;
1611 }
1612
1613 irq_set_parent(virq, irq);
1614 }
1615
1616
1617 irq_trig = irqd_get_trigger_type(irq_get_irq_data(irq));
1618 switch (irq_trig) {
1619 case IRQF_TRIGGER_RISING:
1620 case IRQF_TRIGGER_HIGH:
1621 val = RTL8365MB_INTR_POLARITY_HIGH;
1622 break;
1623 case IRQF_TRIGGER_FALLING:
1624 case IRQF_TRIGGER_LOW:
1625 val = RTL8365MB_INTR_POLARITY_LOW;
1626 break;
1627 default:
1628 dev_err(smi->dev, "unsupported irq trigger type %u\n",
1629 irq_trig);
1630 ret = -EINVAL;
1631 goto out_remove_irqdomain;
1632 }
1633
1634 ret = regmap_update_bits(smi->map, RTL8365MB_INTR_POLARITY_REG,
1635 RTL8365MB_INTR_POLARITY_MASK,
1636 FIELD_PREP(RTL8365MB_INTR_POLARITY_MASK, val));
1637 if (ret)
1638 goto out_remove_irqdomain;
1639
1640
1641 ret = rtl8365mb_irq_disable(smi);
1642 if (ret)
1643 goto out_remove_irqdomain;
1644
1645
1646 ret = regmap_write(smi->map, RTL8365MB_INTR_STATUS_REG,
1647 RTL8365MB_INTR_ALL_MASK);
1648 if (ret)
1649 goto out_remove_irqdomain;
1650
1651 ret = request_threaded_irq(irq, NULL, rtl8365mb_irq, IRQF_ONESHOT,
1652 "rtl8365mb", smi);
1653 if (ret) {
1654 dev_err(smi->dev, "failed to request irq: %d\n", ret);
1655 goto out_remove_irqdomain;
1656 }
1657
1658
1659 mb->irq = irq;
1660
1661 ret = rtl8365mb_irq_enable(smi);
1662 if (ret)
1663 goto out_free_irq;
1664
1665 of_node_put(intc);
1666
1667 return 0;
1668
1669out_free_irq:
1670 free_irq(mb->irq, smi);
1671 mb->irq = 0;
1672
1673out_remove_irqdomain:
1674 for (i = 0; i < smi->num_ports; i++) {
1675 virq = irq_find_mapping(smi->irqdomain, i);
1676 irq_dispose_mapping(virq);
1677 }
1678
1679 irq_domain_remove(smi->irqdomain);
1680 smi->irqdomain = NULL;
1681
1682out_put_node:
1683 of_node_put(intc);
1684
1685 return ret;
1686}
1687
1688static void rtl8365mb_irq_teardown(struct realtek_smi *smi)
1689{
1690 struct rtl8365mb *mb = smi->chip_data;
1691 int virq;
1692 int i;
1693
1694 if (mb->irq) {
1695 free_irq(mb->irq, smi);
1696 mb->irq = 0;
1697 }
1698
1699 if (smi->irqdomain) {
1700 for (i = 0; i < smi->num_ports; i++) {
1701 virq = irq_find_mapping(smi->irqdomain, i);
1702 irq_dispose_mapping(virq);
1703 }
1704
1705 irq_domain_remove(smi->irqdomain);
1706 smi->irqdomain = NULL;
1707 }
1708}
1709
1710static int rtl8365mb_cpu_config(struct realtek_smi *smi)
1711{
1712 struct rtl8365mb *mb = smi->chip_data;
1713 struct rtl8365mb_cpu *cpu = &mb->cpu;
1714 u32 val;
1715 int ret;
1716
1717 ret = regmap_update_bits(smi->map, RTL8365MB_CPU_PORT_MASK_REG,
1718 RTL8365MB_CPU_PORT_MASK_MASK,
1719 FIELD_PREP(RTL8365MB_CPU_PORT_MASK_MASK,
1720 cpu->mask));
1721 if (ret)
1722 return ret;
1723
1724 val = FIELD_PREP(RTL8365MB_CPU_CTRL_EN_MASK, cpu->enable ? 1 : 0) |
1725 FIELD_PREP(RTL8365MB_CPU_CTRL_INSERTMODE_MASK, cpu->insert) |
1726 FIELD_PREP(RTL8365MB_CPU_CTRL_TAG_POSITION_MASK, cpu->position) |
1727 FIELD_PREP(RTL8365MB_CPU_CTRL_RXBYTECOUNT_MASK, cpu->rx_length) |
1728 FIELD_PREP(RTL8365MB_CPU_CTRL_TAG_FORMAT_MASK, cpu->format) |
1729 FIELD_PREP(RTL8365MB_CPU_CTRL_TRAP_PORT_MASK, cpu->trap_port) |
1730 FIELD_PREP(RTL8365MB_CPU_CTRL_TRAP_PORT_EXT_MASK,
1731 cpu->trap_port >> 3);
1732 ret = regmap_write(smi->map, RTL8365MB_CPU_CTRL_REG, val);
1733 if (ret)
1734 return ret;
1735
1736 return 0;
1737}
1738
1739static int rtl8365mb_switch_init(struct realtek_smi *smi)
1740{
1741 struct rtl8365mb *mb = smi->chip_data;
1742 int ret;
1743 int i;
1744
1745
1746 if (mb->jam_table) {
1747 for (i = 0; i < mb->jam_size; i++) {
1748 ret = regmap_write(smi->map, mb->jam_table[i].reg,
1749 mb->jam_table[i].val);
1750 if (ret)
1751 return ret;
1752 }
1753 }
1754
1755
1756 for (i = 0; i < ARRAY_SIZE(rtl8365mb_init_jam_common); i++) {
1757 ret = regmap_write(smi->map, rtl8365mb_init_jam_common[i].reg,
1758 rtl8365mb_init_jam_common[i].val);
1759 if (ret)
1760 return ret;
1761 }
1762
1763 return 0;
1764}
1765
1766static int rtl8365mb_reset_chip(struct realtek_smi *smi)
1767{
1768 u32 val;
1769
1770 realtek_smi_write_reg_noack(smi, RTL8365MB_CHIP_RESET_REG,
1771 FIELD_PREP(RTL8365MB_CHIP_RESET_HW_MASK,
1772 1));
1773
1774
1775
1776
1777 msleep(100);
1778 return regmap_read_poll_timeout(smi->map, RTL8365MB_CHIP_RESET_REG, val,
1779 !(val & RTL8365MB_CHIP_RESET_HW_MASK),
1780 20000, 1e6);
1781}
1782
1783static int rtl8365mb_setup(struct dsa_switch *ds)
1784{
1785 struct realtek_smi *smi = ds->priv;
1786 struct rtl8365mb *mb;
1787 int ret;
1788 int i;
1789
1790 mb = smi->chip_data;
1791
1792 ret = rtl8365mb_reset_chip(smi);
1793 if (ret) {
1794 dev_err(smi->dev, "failed to reset chip: %d\n", ret);
1795 goto out_error;
1796 }
1797
1798
1799 ret = rtl8365mb_switch_init(smi);
1800 if (ret) {
1801 dev_err(smi->dev, "failed to initialize switch: %d\n", ret);
1802 goto out_error;
1803 }
1804
1805
1806 ret = rtl8365mb_irq_setup(smi);
1807 if (ret == -EPROBE_DEFER)
1808 return ret;
1809 else if (ret)
1810 dev_info(smi->dev, "no interrupt support\n");
1811
1812
1813 ret = rtl8365mb_cpu_config(smi);
1814 if (ret)
1815 goto out_teardown_irq;
1816
1817
1818 for (i = 0; i < smi->num_ports; i++) {
1819 struct rtl8365mb_port *p = &mb->ports[i];
1820
1821 if (dsa_is_unused_port(smi->ds, i))
1822 continue;
1823
1824
1825 p->smi = smi;
1826 p->index = i;
1827
1828
1829 ret = rtl8365mb_port_set_isolation(smi, i, BIT(smi->cpu_port));
1830 if (ret)
1831 goto out_teardown_irq;
1832
1833
1834 ret = rtl8365mb_port_set_learning(smi, i, false);
1835 if (ret)
1836 goto out_teardown_irq;
1837
1838
1839
1840
1841
1842 rtl8365mb_port_stp_state_set(smi->ds, i, BR_STATE_DISABLED);
1843 }
1844
1845
1846 ret = regmap_update_bits(smi->map, RTL8365MB_CFG0_MAX_LEN_REG,
1847 RTL8365MB_CFG0_MAX_LEN_MASK,
1848 FIELD_PREP(RTL8365MB_CFG0_MAX_LEN_MASK, 1536));
1849 if (ret)
1850 goto out_teardown_irq;
1851
1852 ret = realtek_smi_setup_mdio(smi);
1853 if (ret) {
1854 dev_err(smi->dev, "could not set up MDIO bus\n");
1855 goto out_teardown_irq;
1856 }
1857
1858
1859 rtl8365mb_stats_setup(smi);
1860
1861 return 0;
1862
1863out_teardown_irq:
1864 rtl8365mb_irq_teardown(smi);
1865
1866out_error:
1867 return ret;
1868}
1869
1870static void rtl8365mb_teardown(struct dsa_switch *ds)
1871{
1872 struct realtek_smi *smi = ds->priv;
1873
1874 rtl8365mb_stats_teardown(smi);
1875 rtl8365mb_irq_teardown(smi);
1876}
1877
1878static int rtl8365mb_get_chip_id_and_ver(struct regmap *map, u32 *id, u32 *ver)
1879{
1880 int ret;
1881
1882
1883
1884
1885 ret = regmap_write(map, RTL8365MB_MAGIC_REG, RTL8365MB_MAGIC_VALUE);
1886 if (ret)
1887 return ret;
1888
1889 ret = regmap_read(map, RTL8365MB_CHIP_ID_REG, id);
1890 if (ret)
1891 return ret;
1892
1893 ret = regmap_read(map, RTL8365MB_CHIP_VER_REG, ver);
1894 if (ret)
1895 return ret;
1896
1897
1898 ret = regmap_write(map, RTL8365MB_MAGIC_REG, 0);
1899 if (ret)
1900 return ret;
1901
1902 return 0;
1903}
1904
1905static int rtl8365mb_detect(struct realtek_smi *smi)
1906{
1907 struct rtl8365mb *mb = smi->chip_data;
1908 u32 chip_id;
1909 u32 chip_ver;
1910 int ret;
1911
1912 ret = rtl8365mb_get_chip_id_and_ver(smi->map, &chip_id, &chip_ver);
1913 if (ret) {
1914 dev_err(smi->dev, "failed to read chip id and version: %d\n",
1915 ret);
1916 return ret;
1917 }
1918
1919 switch (chip_id) {
1920 case RTL8365MB_CHIP_ID_8365MB_VC:
1921 dev_info(smi->dev,
1922 "found an RTL8365MB-VC switch (ver=0x%04x)\n",
1923 chip_ver);
1924
1925 smi->cpu_port = RTL8365MB_CPU_PORT_NUM_8365MB_VC;
1926 smi->num_ports = smi->cpu_port + 1;
1927
1928 mb->smi = smi;
1929 mb->chip_id = chip_id;
1930 mb->chip_ver = chip_ver;
1931 mb->port_mask = BIT(smi->num_ports) - 1;
1932 mb->learn_limit_max = RTL8365MB_LEARN_LIMIT_MAX_8365MB_VC;
1933 mb->jam_table = rtl8365mb_init_jam_8365mb_vc;
1934 mb->jam_size = ARRAY_SIZE(rtl8365mb_init_jam_8365mb_vc);
1935
1936 mb->cpu.enable = 1;
1937 mb->cpu.mask = BIT(smi->cpu_port);
1938 mb->cpu.trap_port = smi->cpu_port;
1939 mb->cpu.insert = RTL8365MB_CPU_INSERT_TO_ALL;
1940 mb->cpu.position = RTL8365MB_CPU_POS_AFTER_SA;
1941 mb->cpu.rx_length = RTL8365MB_CPU_RXLEN_64BYTES;
1942 mb->cpu.format = RTL8365MB_CPU_FORMAT_8BYTES;
1943
1944 break;
1945 default:
1946 dev_err(smi->dev,
1947 "found an unknown Realtek switch (id=0x%04x, ver=0x%04x)\n",
1948 chip_id, chip_ver);
1949 return -ENODEV;
1950 }
1951
1952 return 0;
1953}
1954
1955static const struct dsa_switch_ops rtl8365mb_switch_ops = {
1956 .get_tag_protocol = rtl8365mb_get_tag_protocol,
1957 .setup = rtl8365mb_setup,
1958 .teardown = rtl8365mb_teardown,
1959 .phylink_validate = rtl8365mb_phylink_validate,
1960 .phylink_mac_config = rtl8365mb_phylink_mac_config,
1961 .phylink_mac_link_down = rtl8365mb_phylink_mac_link_down,
1962 .phylink_mac_link_up = rtl8365mb_phylink_mac_link_up,
1963 .port_stp_state_set = rtl8365mb_port_stp_state_set,
1964 .get_strings = rtl8365mb_get_strings,
1965 .get_ethtool_stats = rtl8365mb_get_ethtool_stats,
1966 .get_sset_count = rtl8365mb_get_sset_count,
1967 .get_eth_phy_stats = rtl8365mb_get_phy_stats,
1968 .get_eth_mac_stats = rtl8365mb_get_mac_stats,
1969 .get_eth_ctrl_stats = rtl8365mb_get_ctrl_stats,
1970 .get_stats64 = rtl8365mb_get_stats64,
1971};
1972
1973static const struct realtek_smi_ops rtl8365mb_smi_ops = {
1974 .detect = rtl8365mb_detect,
1975 .phy_read = rtl8365mb_phy_read,
1976 .phy_write = rtl8365mb_phy_write,
1977};
1978
1979const struct realtek_smi_variant rtl8365mb_variant = {
1980 .ds_ops = &rtl8365mb_switch_ops,
1981 .ops = &rtl8365mb_smi_ops,
1982 .clk_delay = 10,
1983 .cmd_read = 0xb9,
1984 .cmd_write = 0xb8,
1985 .chip_data_sz = sizeof(struct rtl8365mb),
1986};
1987EXPORT_SYMBOL_GPL(rtl8365mb_variant);
1988