1
2
3
4#include <asm/unaligned.h>
5#include <linux/mdio.h>
6#include <linux/module.h>
7#include <linux/fsl/enetc_mdio.h>
8#include <linux/of_platform.h>
9#include <linux/of_mdio.h>
10#include <linux/of_net.h>
11#include <linux/pcs-lynx.h>
12#include "enetc_ierb.h"
13#include "enetc_pf.h"
14
15#define ENETC_DRV_NAME_STR "ENETC PF driver"
16
17static void enetc_pf_get_primary_mac_addr(struct enetc_hw *hw, int si, u8 *addr)
18{
19 u32 upper = __raw_readl(hw->port + ENETC_PSIPMAR0(si));
20 u16 lower = __raw_readw(hw->port + ENETC_PSIPMAR1(si));
21
22 put_unaligned_le32(upper, addr);
23 put_unaligned_le16(lower, addr + 4);
24}
25
26static void enetc_pf_set_primary_mac_addr(struct enetc_hw *hw, int si,
27 const u8 *addr)
28{
29 u32 upper = get_unaligned_le32(addr);
30 u16 lower = get_unaligned_le16(addr + 4);
31
32 __raw_writel(upper, hw->port + ENETC_PSIPMAR0(si));
33 __raw_writew(lower, hw->port + ENETC_PSIPMAR1(si));
34}
35
36static int enetc_pf_set_mac_addr(struct net_device *ndev, void *addr)
37{
38 struct enetc_ndev_priv *priv = netdev_priv(ndev);
39 struct sockaddr *saddr = addr;
40
41 if (!is_valid_ether_addr(saddr->sa_data))
42 return -EADDRNOTAVAIL;
43
44 eth_hw_addr_set(ndev, saddr->sa_data);
45 enetc_pf_set_primary_mac_addr(&priv->si->hw, 0, saddr->sa_data);
46
47 return 0;
48}
49
50static void enetc_set_vlan_promisc(struct enetc_hw *hw, char si_map)
51{
52 u32 val = enetc_port_rd(hw, ENETC_PSIPVMR);
53
54 val &= ~ENETC_PSIPVMR_SET_VP(ENETC_VLAN_PROMISC_MAP_ALL);
55 enetc_port_wr(hw, ENETC_PSIPVMR, ENETC_PSIPVMR_SET_VP(si_map) | val);
56}
57
58static void enetc_enable_si_vlan_promisc(struct enetc_pf *pf, int si_idx)
59{
60 pf->vlan_promisc_simap |= BIT(si_idx);
61 enetc_set_vlan_promisc(&pf->si->hw, pf->vlan_promisc_simap);
62}
63
64static void enetc_disable_si_vlan_promisc(struct enetc_pf *pf, int si_idx)
65{
66 pf->vlan_promisc_simap &= ~BIT(si_idx);
67 enetc_set_vlan_promisc(&pf->si->hw, pf->vlan_promisc_simap);
68}
69
70static void enetc_set_isol_vlan(struct enetc_hw *hw, int si, u16 vlan, u8 qos)
71{
72 u32 val = 0;
73
74 if (vlan)
75 val = ENETC_PSIVLAN_EN | ENETC_PSIVLAN_SET_QOS(qos) | vlan;
76
77 enetc_port_wr(hw, ENETC_PSIVLANR(si), val);
78}
79
80static int enetc_mac_addr_hash_idx(const u8 *addr)
81{
82 u64 fold = __swab64(ether_addr_to_u64(addr)) >> 16;
83 u64 mask = 0;
84 int res = 0;
85 int i;
86
87 for (i = 0; i < 8; i++)
88 mask |= BIT_ULL(i * 6);
89
90 for (i = 0; i < 6; i++)
91 res |= (hweight64(fold & (mask << i)) & 0x1) << i;
92
93 return res;
94}
95
96static void enetc_reset_mac_addr_filter(struct enetc_mac_filter *filter)
97{
98 filter->mac_addr_cnt = 0;
99
100 bitmap_zero(filter->mac_hash_table,
101 ENETC_MADDR_HASH_TBL_SZ);
102}
103
104static void enetc_add_mac_addr_em_filter(struct enetc_mac_filter *filter,
105 const unsigned char *addr)
106{
107
108 ether_addr_copy(filter->mac_addr, addr);
109 filter->mac_addr_cnt++;
110}
111
112static void enetc_add_mac_addr_ht_filter(struct enetc_mac_filter *filter,
113 const unsigned char *addr)
114{
115 int idx = enetc_mac_addr_hash_idx(addr);
116
117
118 __set_bit(idx, filter->mac_hash_table);
119 filter->mac_addr_cnt++;
120}
121
122static void enetc_clear_mac_ht_flt(struct enetc_si *si, int si_idx, int type)
123{
124 bool err = si->errata & ENETC_ERR_UCMCSWP;
125
126 if (type == UC) {
127 enetc_port_wr(&si->hw, ENETC_PSIUMHFR0(si_idx, err), 0);
128 enetc_port_wr(&si->hw, ENETC_PSIUMHFR1(si_idx), 0);
129 } else {
130 enetc_port_wr(&si->hw, ENETC_PSIMMHFR0(si_idx, err), 0);
131 enetc_port_wr(&si->hw, ENETC_PSIMMHFR1(si_idx), 0);
132 }
133}
134
135static void enetc_set_mac_ht_flt(struct enetc_si *si, int si_idx, int type,
136 unsigned long hash)
137{
138 bool err = si->errata & ENETC_ERR_UCMCSWP;
139
140 if (type == UC) {
141 enetc_port_wr(&si->hw, ENETC_PSIUMHFR0(si_idx, err),
142 lower_32_bits(hash));
143 enetc_port_wr(&si->hw, ENETC_PSIUMHFR1(si_idx),
144 upper_32_bits(hash));
145 } else {
146 enetc_port_wr(&si->hw, ENETC_PSIMMHFR0(si_idx, err),
147 lower_32_bits(hash));
148 enetc_port_wr(&si->hw, ENETC_PSIMMHFR1(si_idx),
149 upper_32_bits(hash));
150 }
151}
152
153static void enetc_sync_mac_filters(struct enetc_pf *pf)
154{
155 struct enetc_mac_filter *f = pf->mac_filter;
156 struct enetc_si *si = pf->si;
157 int i, pos;
158
159 pos = EMETC_MAC_ADDR_FILT_RES;
160
161 for (i = 0; i < MADDR_TYPE; i++, f++) {
162 bool em = (f->mac_addr_cnt == 1) && (i == UC);
163 bool clear = !f->mac_addr_cnt;
164
165 if (clear) {
166 if (i == UC)
167 enetc_clear_mac_flt_entry(si, pos);
168
169 enetc_clear_mac_ht_flt(si, 0, i);
170 continue;
171 }
172
173
174 if (em) {
175 int err;
176
177 enetc_clear_mac_ht_flt(si, 0, UC);
178
179 err = enetc_set_mac_flt_entry(si, pos, f->mac_addr,
180 BIT(0));
181 if (!err)
182 continue;
183
184
185 dev_warn(&si->pdev->dev, "fallback to HT filt (%d)\n",
186 err);
187 }
188
189
190 if (i == UC)
191 enetc_clear_mac_flt_entry(si, pos);
192
193 enetc_set_mac_ht_flt(si, 0, i, *f->mac_hash_table);
194 }
195}
196
197static void enetc_pf_set_rx_mode(struct net_device *ndev)
198{
199 struct enetc_ndev_priv *priv = netdev_priv(ndev);
200 struct enetc_pf *pf = enetc_si_priv(priv->si);
201 struct enetc_hw *hw = &priv->si->hw;
202 bool uprom = false, mprom = false;
203 struct enetc_mac_filter *filter;
204 struct netdev_hw_addr *ha;
205 u32 psipmr = 0;
206 bool em;
207
208 if (ndev->flags & IFF_PROMISC) {
209
210 psipmr = ENETC_PSIPMR_SET_UP(0) | ENETC_PSIPMR_SET_MP(0);
211 uprom = true;
212 mprom = true;
213 } else if (ndev->flags & IFF_ALLMULTI) {
214
215 psipmr = ENETC_PSIPMR_SET_MP(0);
216 mprom = true;
217 }
218
219
220 if (!uprom) {
221
222 filter = &pf->mac_filter[UC];
223 enetc_reset_mac_addr_filter(filter);
224
225 em = (netdev_uc_count(ndev) == 1);
226 netdev_for_each_uc_addr(ha, ndev) {
227 if (em) {
228 enetc_add_mac_addr_em_filter(filter, ha->addr);
229 break;
230 }
231
232 enetc_add_mac_addr_ht_filter(filter, ha->addr);
233 }
234 }
235
236 if (!mprom) {
237
238 filter = &pf->mac_filter[MC];
239 enetc_reset_mac_addr_filter(filter);
240
241 netdev_for_each_mc_addr(ha, ndev) {
242 if (!is_multicast_ether_addr(ha->addr))
243 continue;
244
245 enetc_add_mac_addr_ht_filter(filter, ha->addr);
246 }
247 }
248
249 if (!uprom || !mprom)
250
251 enetc_sync_mac_filters(pf);
252
253 psipmr |= enetc_port_rd(hw, ENETC_PSIPMR) &
254 ~(ENETC_PSIPMR_SET_UP(0) | ENETC_PSIPMR_SET_MP(0));
255 enetc_port_wr(hw, ENETC_PSIPMR, psipmr);
256}
257
258static void enetc_set_vlan_ht_filter(struct enetc_hw *hw, int si_idx,
259 unsigned long hash)
260{
261 enetc_port_wr(hw, ENETC_PSIVHFR0(si_idx), lower_32_bits(hash));
262 enetc_port_wr(hw, ENETC_PSIVHFR1(si_idx), upper_32_bits(hash));
263}
264
265static int enetc_vid_hash_idx(unsigned int vid)
266{
267 int res = 0;
268 int i;
269
270 for (i = 0; i < 6; i++)
271 res |= (hweight8(vid & (BIT(i) | BIT(i + 6))) & 0x1) << i;
272
273 return res;
274}
275
276static void enetc_sync_vlan_ht_filter(struct enetc_pf *pf, bool rehash)
277{
278 int i;
279
280 if (rehash) {
281 bitmap_zero(pf->vlan_ht_filter, ENETC_VLAN_HT_SIZE);
282
283 for_each_set_bit(i, pf->active_vlans, VLAN_N_VID) {
284 int hidx = enetc_vid_hash_idx(i);
285
286 __set_bit(hidx, pf->vlan_ht_filter);
287 }
288 }
289
290 enetc_set_vlan_ht_filter(&pf->si->hw, 0, *pf->vlan_ht_filter);
291}
292
293static int enetc_vlan_rx_add_vid(struct net_device *ndev, __be16 prot, u16 vid)
294{
295 struct enetc_ndev_priv *priv = netdev_priv(ndev);
296 struct enetc_pf *pf = enetc_si_priv(priv->si);
297 int idx;
298
299 __set_bit(vid, pf->active_vlans);
300
301 idx = enetc_vid_hash_idx(vid);
302 if (!__test_and_set_bit(idx, pf->vlan_ht_filter))
303 enetc_sync_vlan_ht_filter(pf, false);
304
305 return 0;
306}
307
308static int enetc_vlan_rx_del_vid(struct net_device *ndev, __be16 prot, u16 vid)
309{
310 struct enetc_ndev_priv *priv = netdev_priv(ndev);
311 struct enetc_pf *pf = enetc_si_priv(priv->si);
312
313 __clear_bit(vid, pf->active_vlans);
314 enetc_sync_vlan_ht_filter(pf, true);
315
316 return 0;
317}
318
319static void enetc_set_loopback(struct net_device *ndev, bool en)
320{
321 struct enetc_ndev_priv *priv = netdev_priv(ndev);
322 struct enetc_hw *hw = &priv->si->hw;
323 u32 reg;
324
325 reg = enetc_port_rd(hw, ENETC_PM0_IF_MODE);
326 if (reg & ENETC_PM0_IFM_RG) {
327
328 reg = (reg & ~ENETC_PM0_IFM_RLP) |
329 (en ? ENETC_PM0_IFM_RLP : 0);
330 enetc_port_wr(hw, ENETC_PM0_IF_MODE, reg);
331 } else {
332
333 reg = enetc_port_rd(hw, ENETC_PM0_CMD_CFG);
334 reg = (reg & ~ENETC_PM0_CMD_XGLP) |
335 (en ? ENETC_PM0_CMD_XGLP : 0);
336 reg = (reg & ~ENETC_PM0_CMD_PHY_TX_EN) |
337 (en ? ENETC_PM0_CMD_PHY_TX_EN : 0);
338 enetc_port_wr(hw, ENETC_PM0_CMD_CFG, reg);
339 enetc_port_wr(hw, ENETC_PM1_CMD_CFG, reg);
340 }
341}
342
343static int enetc_pf_set_vf_mac(struct net_device *ndev, int vf, u8 *mac)
344{
345 struct enetc_ndev_priv *priv = netdev_priv(ndev);
346 struct enetc_pf *pf = enetc_si_priv(priv->si);
347 struct enetc_vf_state *vf_state;
348
349 if (vf >= pf->total_vfs)
350 return -EINVAL;
351
352 if (!is_valid_ether_addr(mac))
353 return -EADDRNOTAVAIL;
354
355 vf_state = &pf->vf_state[vf];
356 vf_state->flags |= ENETC_VF_FLAG_PF_SET_MAC;
357 enetc_pf_set_primary_mac_addr(&priv->si->hw, vf + 1, mac);
358 return 0;
359}
360
361static int enetc_pf_set_vf_vlan(struct net_device *ndev, int vf, u16 vlan,
362 u8 qos, __be16 proto)
363{
364 struct enetc_ndev_priv *priv = netdev_priv(ndev);
365 struct enetc_pf *pf = enetc_si_priv(priv->si);
366
367 if (priv->si->errata & ENETC_ERR_VLAN_ISOL)
368 return -EOPNOTSUPP;
369
370 if (vf >= pf->total_vfs)
371 return -EINVAL;
372
373 if (proto != htons(ETH_P_8021Q))
374
375 return -EPROTONOSUPPORT;
376
377 enetc_set_isol_vlan(&priv->si->hw, vf + 1, vlan, qos);
378 return 0;
379}
380
381static int enetc_pf_set_vf_spoofchk(struct net_device *ndev, int vf, bool en)
382{
383 struct enetc_ndev_priv *priv = netdev_priv(ndev);
384 struct enetc_pf *pf = enetc_si_priv(priv->si);
385 u32 cfgr;
386
387 if (vf >= pf->total_vfs)
388 return -EINVAL;
389
390 cfgr = enetc_port_rd(&priv->si->hw, ENETC_PSICFGR0(vf + 1));
391 cfgr = (cfgr & ~ENETC_PSICFGR0_ASE) | (en ? ENETC_PSICFGR0_ASE : 0);
392 enetc_port_wr(&priv->si->hw, ENETC_PSICFGR0(vf + 1), cfgr);
393
394 return 0;
395}
396
397static int enetc_setup_mac_address(struct device_node *np, struct enetc_pf *pf,
398 int si)
399{
400 struct device *dev = &pf->si->pdev->dev;
401 struct enetc_hw *hw = &pf->si->hw;
402 u8 mac_addr[ETH_ALEN] = { 0 };
403 int err;
404
405
406 if (np) {
407 err = of_get_mac_address(np, mac_addr);
408 if (err == -EPROBE_DEFER)
409 return err;
410 }
411
412
413 if (is_zero_ether_addr(mac_addr))
414 enetc_pf_get_primary_mac_addr(hw, si, mac_addr);
415
416
417 if (is_zero_ether_addr(mac_addr)) {
418 eth_random_addr(mac_addr);
419 dev_info(dev, "no MAC address specified for SI%d, using %pM\n",
420 si, mac_addr);
421 }
422
423 enetc_pf_set_primary_mac_addr(hw, si, mac_addr);
424
425 return 0;
426}
427
428static int enetc_setup_mac_addresses(struct device_node *np,
429 struct enetc_pf *pf)
430{
431 int err, i;
432
433
434 err = enetc_setup_mac_address(np, pf, 0);
435 if (err)
436 return err;
437
438 for (i = 0; i < pf->total_vfs; i++) {
439 err = enetc_setup_mac_address(NULL, pf, i + 1);
440 if (err)
441 return err;
442 }
443
444 return 0;
445}
446
447static void enetc_port_assign_rfs_entries(struct enetc_si *si)
448{
449 struct enetc_pf *pf = enetc_si_priv(si);
450 struct enetc_hw *hw = &si->hw;
451 int num_entries, vf_entries, i;
452 u32 val;
453
454
455 val = enetc_port_rd(hw, ENETC_PRFSCAPR);
456 num_entries = ENETC_PRFSCAPR_GET_NUM_RFS(val);
457 vf_entries = num_entries / (pf->total_vfs + 1);
458
459 for (i = 0; i < pf->total_vfs; i++)
460 enetc_port_wr(hw, ENETC_PSIRFSCFGR(i + 1), vf_entries);
461 enetc_port_wr(hw, ENETC_PSIRFSCFGR(0),
462 num_entries - vf_entries * pf->total_vfs);
463
464
465 enetc_port_wr(hw, ENETC_PRFSMR, ENETC_PRFSMR_RFSE);
466}
467
468static void enetc_port_si_configure(struct enetc_si *si)
469{
470 struct enetc_pf *pf = enetc_si_priv(si);
471 struct enetc_hw *hw = &si->hw;
472 int num_rings, i;
473 u32 val;
474
475 val = enetc_port_rd(hw, ENETC_PCAPR0);
476 num_rings = min(ENETC_PCAPR0_RXBDR(val), ENETC_PCAPR0_TXBDR(val));
477
478 val = ENETC_PSICFGR0_SET_TXBDR(ENETC_PF_NUM_RINGS);
479 val |= ENETC_PSICFGR0_SET_RXBDR(ENETC_PF_NUM_RINGS);
480
481 if (unlikely(num_rings < ENETC_PF_NUM_RINGS)) {
482 val = ENETC_PSICFGR0_SET_TXBDR(num_rings);
483 val |= ENETC_PSICFGR0_SET_RXBDR(num_rings);
484
485 dev_warn(&si->pdev->dev, "Found %d rings, expected %d!\n",
486 num_rings, ENETC_PF_NUM_RINGS);
487
488 num_rings = 0;
489 }
490
491
492 val |= ENETC_PSICFGR0_SIVC(ENETC_VLAN_TYPE_C | ENETC_VLAN_TYPE_S);
493
494 enetc_port_wr(hw, ENETC_PSICFGR0(0), val);
495
496 if (num_rings)
497 num_rings -= ENETC_PF_NUM_RINGS;
498
499
500 val = ENETC_PSICFGR0_SIVC(ENETC_VLAN_TYPE_C | ENETC_VLAN_TYPE_S);
501 val |= ENETC_PSICFGR0_VTE | ENETC_PSICFGR0_SIVIE;
502
503 if (num_rings) {
504 num_rings /= pf->total_vfs;
505 val |= ENETC_PSICFGR0_SET_TXBDR(num_rings);
506 val |= ENETC_PSICFGR0_SET_RXBDR(num_rings);
507 }
508
509 for (i = 0; i < pf->total_vfs; i++)
510 enetc_port_wr(hw, ENETC_PSICFGR0(i + 1), val);
511
512
513 val = ENETC_PVCLCTR_OVTPIDL(ENETC_VLAN_TYPE_C | ENETC_VLAN_TYPE_S);
514 enetc_port_wr(hw, ENETC_PVCLCTR, val);
515
516 enetc_port_wr(hw, ENETC_PSIVLANFMR, ENETC_PSIVLANFMR_VS);
517}
518
519static void enetc_configure_port_mac(struct enetc_hw *hw)
520{
521 int tc;
522
523 enetc_port_wr(hw, ENETC_PM0_MAXFRM,
524 ENETC_SET_MAXFRM(ENETC_RX_MAXFRM_SIZE));
525
526 for (tc = 0; tc < 8; tc++)
527 enetc_port_wr(hw, ENETC_PTCMSDUR(tc), ENETC_MAC_MAXFRM_SIZE);
528
529 enetc_port_wr(hw, ENETC_PM0_CMD_CFG, ENETC_PM0_CMD_PHY_TX_EN |
530 ENETC_PM0_CMD_TXP | ENETC_PM0_PROMISC);
531
532 enetc_port_wr(hw, ENETC_PM1_CMD_CFG, ENETC_PM0_CMD_PHY_TX_EN |
533 ENETC_PM0_CMD_TXP | ENETC_PM0_PROMISC);
534
535
536
537
538
539 enetc_port_wr(hw, ENETC_PM0_RX_FIFO, ENETC_PM0_RX_FIFO_VAL);
540}
541
542static void enetc_mac_config(struct enetc_hw *hw, phy_interface_t phy_mode)
543{
544 u32 val;
545
546 if (phy_interface_mode_is_rgmii(phy_mode)) {
547 val = enetc_port_rd(hw, ENETC_PM0_IF_MODE);
548 val &= ~(ENETC_PM0_IFM_EN_AUTO | ENETC_PM0_IFM_IFMODE_MASK);
549 val |= ENETC_PM0_IFM_IFMODE_GMII | ENETC_PM0_IFM_RG;
550 enetc_port_wr(hw, ENETC_PM0_IF_MODE, val);
551 }
552
553 if (phy_mode == PHY_INTERFACE_MODE_USXGMII) {
554 val = ENETC_PM0_IFM_FULL_DPX | ENETC_PM0_IFM_IFMODE_XGMII;
555 enetc_port_wr(hw, ENETC_PM0_IF_MODE, val);
556 }
557}
558
559static void enetc_mac_enable(struct enetc_hw *hw, bool en)
560{
561 u32 val = enetc_port_rd(hw, ENETC_PM0_CMD_CFG);
562
563 val &= ~(ENETC_PM0_TX_EN | ENETC_PM0_RX_EN);
564 val |= en ? (ENETC_PM0_TX_EN | ENETC_PM0_RX_EN) : 0;
565
566 enetc_port_wr(hw, ENETC_PM0_CMD_CFG, val);
567 enetc_port_wr(hw, ENETC_PM1_CMD_CFG, val);
568}
569
570static void enetc_configure_port_pmac(struct enetc_hw *hw)
571{
572 u32 temp;
573
574
575 temp = enetc_port_rd(hw, ENETC_PFPMR);
576 enetc_port_wr(hw, ENETC_PFPMR,
577 temp | ENETC_PFPMR_PMACE | ENETC_PFPMR_MWLM);
578
579 temp = enetc_port_rd(hw, ENETC_MMCSR);
580 enetc_port_wr(hw, ENETC_MMCSR, temp | ENETC_MMCSR_ME);
581}
582
583static void enetc_configure_port(struct enetc_pf *pf)
584{
585 u8 hash_key[ENETC_RSSHASH_KEY_SIZE];
586 struct enetc_hw *hw = &pf->si->hw;
587
588 enetc_configure_port_pmac(hw);
589
590 enetc_configure_port_mac(hw);
591
592 enetc_port_si_configure(pf->si);
593
594
595 get_random_bytes(hash_key, ENETC_RSSHASH_KEY_SIZE);
596 enetc_set_rss_key(hw, hash_key);
597
598
599 enetc_port_assign_rfs_entries(pf->si);
600
601
602 pf->vlan_promisc_simap = ENETC_VLAN_PROMISC_MAP_ALL;
603 enetc_set_vlan_promisc(hw, pf->vlan_promisc_simap);
604
605 enetc_port_wr(hw, ENETC_PSIPMR, 0);
606
607
608 enetc_port_wr(hw, ENETC_PMR, ENETC_PMR_EN);
609}
610
611
612static u16 enetc_msg_pf_set_vf_primary_mac_addr(struct enetc_pf *pf,
613 int vf_id)
614{
615 struct enetc_vf_state *vf_state = &pf->vf_state[vf_id];
616 struct enetc_msg_swbd *msg = &pf->rxmsg[vf_id];
617 struct enetc_msg_cmd_set_primary_mac *cmd;
618 struct device *dev = &pf->si->pdev->dev;
619 u16 cmd_id;
620 char *addr;
621
622 cmd = (struct enetc_msg_cmd_set_primary_mac *)msg->vaddr;
623 cmd_id = cmd->header.id;
624 if (cmd_id != ENETC_MSG_CMD_MNG_ADD)
625 return ENETC_MSG_CMD_STATUS_FAIL;
626
627 addr = cmd->mac.sa_data;
628 if (vf_state->flags & ENETC_VF_FLAG_PF_SET_MAC)
629 dev_warn(dev, "Attempt to override PF set mac addr for VF%d\n",
630 vf_id);
631 else
632 enetc_pf_set_primary_mac_addr(&pf->si->hw, vf_id + 1, addr);
633
634 return ENETC_MSG_CMD_STATUS_OK;
635}
636
637void enetc_msg_handle_rxmsg(struct enetc_pf *pf, int vf_id, u16 *status)
638{
639 struct enetc_msg_swbd *msg = &pf->rxmsg[vf_id];
640 struct device *dev = &pf->si->pdev->dev;
641 struct enetc_msg_cmd_header *cmd_hdr;
642 u16 cmd_type;
643
644 *status = ENETC_MSG_CMD_STATUS_OK;
645 cmd_hdr = (struct enetc_msg_cmd_header *)msg->vaddr;
646 cmd_type = cmd_hdr->type;
647
648 switch (cmd_type) {
649 case ENETC_MSG_CMD_MNG_MAC:
650 *status = enetc_msg_pf_set_vf_primary_mac_addr(pf, vf_id);
651 break;
652 default:
653 dev_err(dev, "command not supported (cmd_type: 0x%x)\n",
654 cmd_type);
655 }
656}
657
658#ifdef CONFIG_PCI_IOV
659static int enetc_sriov_configure(struct pci_dev *pdev, int num_vfs)
660{
661 struct enetc_si *si = pci_get_drvdata(pdev);
662 struct enetc_pf *pf = enetc_si_priv(si);
663 int err;
664
665 if (!num_vfs) {
666 enetc_msg_psi_free(pf);
667 kfree(pf->vf_state);
668 pf->num_vfs = 0;
669 pci_disable_sriov(pdev);
670 } else {
671 pf->num_vfs = num_vfs;
672
673 pf->vf_state = kcalloc(num_vfs, sizeof(struct enetc_vf_state),
674 GFP_KERNEL);
675 if (!pf->vf_state) {
676 pf->num_vfs = 0;
677 return -ENOMEM;
678 }
679
680 err = enetc_msg_psi_init(pf);
681 if (err) {
682 dev_err(&pdev->dev, "enetc_msg_psi_init (%d)\n", err);
683 goto err_msg_psi;
684 }
685
686 err = pci_enable_sriov(pdev, num_vfs);
687 if (err) {
688 dev_err(&pdev->dev, "pci_enable_sriov err %d\n", err);
689 goto err_en_sriov;
690 }
691 }
692
693 return num_vfs;
694
695err_en_sriov:
696 enetc_msg_psi_free(pf);
697err_msg_psi:
698 kfree(pf->vf_state);
699 pf->num_vfs = 0;
700
701 return err;
702}
703#else
704#define enetc_sriov_configure(pdev, num_vfs) (void)0
705#endif
706
707static int enetc_pf_set_features(struct net_device *ndev,
708 netdev_features_t features)
709{
710 netdev_features_t changed = ndev->features ^ features;
711 struct enetc_ndev_priv *priv = netdev_priv(ndev);
712
713 if (changed & NETIF_F_HW_VLAN_CTAG_FILTER) {
714 struct enetc_pf *pf = enetc_si_priv(priv->si);
715
716 if (!!(features & NETIF_F_HW_VLAN_CTAG_FILTER))
717 enetc_disable_si_vlan_promisc(pf, 0);
718 else
719 enetc_enable_si_vlan_promisc(pf, 0);
720 }
721
722 if (changed & NETIF_F_LOOPBACK)
723 enetc_set_loopback(ndev, !!(features & NETIF_F_LOOPBACK));
724
725 return enetc_set_features(ndev, features);
726}
727
728static const struct net_device_ops enetc_ndev_ops = {
729 .ndo_open = enetc_open,
730 .ndo_stop = enetc_close,
731 .ndo_start_xmit = enetc_xmit,
732 .ndo_get_stats = enetc_get_stats,
733 .ndo_set_mac_address = enetc_pf_set_mac_addr,
734 .ndo_set_rx_mode = enetc_pf_set_rx_mode,
735 .ndo_vlan_rx_add_vid = enetc_vlan_rx_add_vid,
736 .ndo_vlan_rx_kill_vid = enetc_vlan_rx_del_vid,
737 .ndo_set_vf_mac = enetc_pf_set_vf_mac,
738 .ndo_set_vf_vlan = enetc_pf_set_vf_vlan,
739 .ndo_set_vf_spoofchk = enetc_pf_set_vf_spoofchk,
740 .ndo_set_features = enetc_pf_set_features,
741 .ndo_eth_ioctl = enetc_ioctl,
742 .ndo_setup_tc = enetc_setup_tc,
743 .ndo_bpf = enetc_setup_bpf,
744 .ndo_xdp_xmit = enetc_xdp_xmit,
745};
746
747static void enetc_pf_netdev_setup(struct enetc_si *si, struct net_device *ndev,
748 const struct net_device_ops *ndev_ops)
749{
750 struct enetc_ndev_priv *priv = netdev_priv(ndev);
751
752 SET_NETDEV_DEV(ndev, &si->pdev->dev);
753 priv->ndev = ndev;
754 priv->si = si;
755 priv->dev = &si->pdev->dev;
756 si->ndev = ndev;
757
758 priv->msg_enable = (NETIF_MSG_WOL << 1) - 1;
759 ndev->netdev_ops = ndev_ops;
760 enetc_set_ethtool_ops(ndev);
761 ndev->watchdog_timeo = 5 * HZ;
762 ndev->max_mtu = ENETC_MAX_MTU;
763
764 ndev->hw_features = NETIF_F_SG | NETIF_F_RXCSUM |
765 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
766 NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_LOOPBACK |
767 NETIF_F_HW_CSUM | NETIF_F_TSO | NETIF_F_TSO6;
768 ndev->features = NETIF_F_HIGHDMA | NETIF_F_SG | NETIF_F_RXCSUM |
769 NETIF_F_HW_VLAN_CTAG_TX |
770 NETIF_F_HW_VLAN_CTAG_RX |
771 NETIF_F_HW_CSUM | NETIF_F_TSO | NETIF_F_TSO6;
772 ndev->vlan_features = NETIF_F_SG | NETIF_F_HW_CSUM |
773 NETIF_F_TSO | NETIF_F_TSO6;
774
775 if (si->num_rss)
776 ndev->hw_features |= NETIF_F_RXHASH;
777
778 ndev->priv_flags |= IFF_UNICAST_FLT;
779
780 if (si->hw_features & ENETC_SI_F_QBV)
781 priv->active_offloads |= ENETC_F_QBV;
782
783 if (si->hw_features & ENETC_SI_F_PSFP && !enetc_psfp_enable(priv)) {
784 priv->active_offloads |= ENETC_F_QCI;
785 ndev->features |= NETIF_F_HW_TC;
786 ndev->hw_features |= NETIF_F_HW_TC;
787 }
788
789
790 enetc_load_primary_mac_addr(&si->hw, ndev);
791}
792
793static int enetc_mdio_probe(struct enetc_pf *pf, struct device_node *np)
794{
795 struct device *dev = &pf->si->pdev->dev;
796 struct enetc_mdio_priv *mdio_priv;
797 struct mii_bus *bus;
798 int err;
799
800 bus = devm_mdiobus_alloc_size(dev, sizeof(*mdio_priv));
801 if (!bus)
802 return -ENOMEM;
803
804 bus->name = "Freescale ENETC MDIO Bus";
805 bus->read = enetc_mdio_read;
806 bus->write = enetc_mdio_write;
807 bus->parent = dev;
808 mdio_priv = bus->priv;
809 mdio_priv->hw = &pf->si->hw;
810 mdio_priv->mdio_base = ENETC_EMDIO_BASE;
811 snprintf(bus->id, MII_BUS_ID_SIZE, "%s", dev_name(dev));
812
813 err = of_mdiobus_register(bus, np);
814 if (err)
815 return dev_err_probe(dev, err, "cannot register MDIO bus\n");
816
817 pf->mdio = bus;
818
819 return 0;
820}
821
822static void enetc_mdio_remove(struct enetc_pf *pf)
823{
824 if (pf->mdio)
825 mdiobus_unregister(pf->mdio);
826}
827
828static int enetc_imdio_create(struct enetc_pf *pf)
829{
830 struct device *dev = &pf->si->pdev->dev;
831 struct enetc_mdio_priv *mdio_priv;
832 struct phylink_pcs *phylink_pcs;
833 struct mdio_device *mdio_device;
834 struct mii_bus *bus;
835 int err;
836
837 bus = mdiobus_alloc_size(sizeof(*mdio_priv));
838 if (!bus)
839 return -ENOMEM;
840
841 bus->name = "Freescale ENETC internal MDIO Bus";
842 bus->read = enetc_mdio_read;
843 bus->write = enetc_mdio_write;
844 bus->parent = dev;
845 bus->phy_mask = ~0;
846 mdio_priv = bus->priv;
847 mdio_priv->hw = &pf->si->hw;
848 mdio_priv->mdio_base = ENETC_PM_IMDIO_BASE;
849 snprintf(bus->id, MII_BUS_ID_SIZE, "%s-imdio", dev_name(dev));
850
851 err = mdiobus_register(bus);
852 if (err) {
853 dev_err(dev, "cannot register internal MDIO bus (%d)\n", err);
854 goto free_mdio_bus;
855 }
856
857 mdio_device = mdio_device_create(bus, 0);
858 if (IS_ERR(mdio_device)) {
859 err = PTR_ERR(mdio_device);
860 dev_err(dev, "cannot create mdio device (%d)\n", err);
861 goto unregister_mdiobus;
862 }
863
864 phylink_pcs = lynx_pcs_create(mdio_device);
865 if (!phylink_pcs) {
866 mdio_device_free(mdio_device);
867 err = -ENOMEM;
868 dev_err(dev, "cannot create lynx pcs (%d)\n", err);
869 goto unregister_mdiobus;
870 }
871
872 pf->imdio = bus;
873 pf->pcs = phylink_pcs;
874
875 return 0;
876
877unregister_mdiobus:
878 mdiobus_unregister(bus);
879free_mdio_bus:
880 mdiobus_free(bus);
881 return err;
882}
883
884static void enetc_imdio_remove(struct enetc_pf *pf)
885{
886 struct mdio_device *mdio_device;
887
888 if (pf->pcs) {
889 mdio_device = lynx_get_mdio_device(pf->pcs);
890 mdio_device_free(mdio_device);
891 lynx_pcs_destroy(pf->pcs);
892 }
893 if (pf->imdio) {
894 mdiobus_unregister(pf->imdio);
895 mdiobus_free(pf->imdio);
896 }
897}
898
899static bool enetc_port_has_pcs(struct enetc_pf *pf)
900{
901 return (pf->if_mode == PHY_INTERFACE_MODE_SGMII ||
902 pf->if_mode == PHY_INTERFACE_MODE_2500BASEX ||
903 pf->if_mode == PHY_INTERFACE_MODE_USXGMII);
904}
905
906static int enetc_mdiobus_create(struct enetc_pf *pf, struct device_node *node)
907{
908 struct device_node *mdio_np;
909 int err;
910
911 mdio_np = of_get_child_by_name(node, "mdio");
912 if (mdio_np) {
913 err = enetc_mdio_probe(pf, mdio_np);
914
915 of_node_put(mdio_np);
916 if (err)
917 return err;
918 }
919
920 if (enetc_port_has_pcs(pf)) {
921 err = enetc_imdio_create(pf);
922 if (err) {
923 enetc_mdio_remove(pf);
924 return err;
925 }
926 }
927
928 return 0;
929}
930
931static void enetc_mdiobus_destroy(struct enetc_pf *pf)
932{
933 enetc_mdio_remove(pf);
934 enetc_imdio_remove(pf);
935}
936
937static void enetc_pl_mac_config(struct phylink_config *config,
938 unsigned int mode,
939 const struct phylink_link_state *state)
940{
941 struct enetc_pf *pf = phylink_to_enetc_pf(config);
942 struct enetc_ndev_priv *priv;
943
944 enetc_mac_config(&pf->si->hw, state->interface);
945
946 priv = netdev_priv(pf->si->ndev);
947 if (pf->pcs)
948 phylink_set_pcs(priv->phylink, pf->pcs);
949}
950
951static void enetc_force_rgmii_mac(struct enetc_hw *hw, int speed, int duplex)
952{
953 u32 old_val, val;
954
955 old_val = val = enetc_port_rd(hw, ENETC_PM0_IF_MODE);
956
957 if (speed == SPEED_1000) {
958 val &= ~ENETC_PM0_IFM_SSP_MASK;
959 val |= ENETC_PM0_IFM_SSP_1000;
960 } else if (speed == SPEED_100) {
961 val &= ~ENETC_PM0_IFM_SSP_MASK;
962 val |= ENETC_PM0_IFM_SSP_100;
963 } else if (speed == SPEED_10) {
964 val &= ~ENETC_PM0_IFM_SSP_MASK;
965 val |= ENETC_PM0_IFM_SSP_10;
966 }
967
968 if (duplex == DUPLEX_FULL)
969 val |= ENETC_PM0_IFM_FULL_DPX;
970 else
971 val &= ~ENETC_PM0_IFM_FULL_DPX;
972
973 if (val == old_val)
974 return;
975
976 enetc_port_wr(hw, ENETC_PM0_IF_MODE, val);
977}
978
979static void enetc_pl_mac_link_up(struct phylink_config *config,
980 struct phy_device *phy, unsigned int mode,
981 phy_interface_t interface, int speed,
982 int duplex, bool tx_pause, bool rx_pause)
983{
984 struct enetc_pf *pf = phylink_to_enetc_pf(config);
985 u32 pause_off_thresh = 0, pause_on_thresh = 0;
986 u32 init_quanta = 0, refresh_quanta = 0;
987 struct enetc_hw *hw = &pf->si->hw;
988 struct enetc_ndev_priv *priv;
989 u32 rbmr, cmd_cfg;
990 int idx;
991
992 priv = netdev_priv(pf->si->ndev);
993 if (priv->active_offloads & ENETC_F_QBV)
994 enetc_sched_speed_set(priv, speed);
995
996 if (!phylink_autoneg_inband(mode) &&
997 phy_interface_mode_is_rgmii(interface))
998 enetc_force_rgmii_mac(hw, speed, duplex);
999
1000
1001 for (idx = 0; idx < priv->num_rx_rings; idx++) {
1002 rbmr = enetc_rxbdr_rd(hw, idx, ENETC_RBMR);
1003
1004 if (tx_pause)
1005 rbmr |= ENETC_RBMR_CM;
1006 else
1007 rbmr &= ~ENETC_RBMR_CM;
1008
1009 enetc_rxbdr_wr(hw, idx, ENETC_RBMR, rbmr);
1010 }
1011
1012 if (tx_pause) {
1013
1014
1015
1016
1017
1018 init_quanta = 0xffff;
1019
1020
1021
1022
1023
1024 refresh_quanta = 0xffff / 2;
1025
1026
1027
1028
1029
1030 pause_on_thresh = 3 * ENETC_MAC_MAXFRM_SIZE;
1031 pause_off_thresh = 1 * ENETC_MAC_MAXFRM_SIZE;
1032 }
1033
1034 enetc_port_wr(hw, ENETC_PM0_PAUSE_QUANTA, init_quanta);
1035 enetc_port_wr(hw, ENETC_PM1_PAUSE_QUANTA, init_quanta);
1036 enetc_port_wr(hw, ENETC_PM0_PAUSE_THRESH, refresh_quanta);
1037 enetc_port_wr(hw, ENETC_PM1_PAUSE_THRESH, refresh_quanta);
1038 enetc_port_wr(hw, ENETC_PPAUONTR, pause_on_thresh);
1039 enetc_port_wr(hw, ENETC_PPAUOFFTR, pause_off_thresh);
1040
1041 cmd_cfg = enetc_port_rd(hw, ENETC_PM0_CMD_CFG);
1042
1043 if (rx_pause)
1044 cmd_cfg &= ~ENETC_PM0_PAUSE_IGN;
1045 else
1046 cmd_cfg |= ENETC_PM0_PAUSE_IGN;
1047
1048 enetc_port_wr(hw, ENETC_PM0_CMD_CFG, cmd_cfg);
1049 enetc_port_wr(hw, ENETC_PM1_CMD_CFG, cmd_cfg);
1050
1051 enetc_mac_enable(hw, true);
1052}
1053
1054static void enetc_pl_mac_link_down(struct phylink_config *config,
1055 unsigned int mode,
1056 phy_interface_t interface)
1057{
1058 struct enetc_pf *pf = phylink_to_enetc_pf(config);
1059
1060 enetc_mac_enable(&pf->si->hw, false);
1061}
1062
1063static const struct phylink_mac_ops enetc_mac_phylink_ops = {
1064 .validate = phylink_generic_validate,
1065 .mac_config = enetc_pl_mac_config,
1066 .mac_link_up = enetc_pl_mac_link_up,
1067 .mac_link_down = enetc_pl_mac_link_down,
1068};
1069
1070static int enetc_phylink_create(struct enetc_ndev_priv *priv,
1071 struct device_node *node)
1072{
1073 struct enetc_pf *pf = enetc_si_priv(priv->si);
1074 struct phylink *phylink;
1075 int err;
1076
1077 pf->phylink_config.dev = &priv->ndev->dev;
1078 pf->phylink_config.type = PHYLINK_NETDEV;
1079 pf->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
1080 MAC_10 | MAC_100 | MAC_1000 | MAC_2500FD;
1081
1082 __set_bit(PHY_INTERFACE_MODE_INTERNAL,
1083 pf->phylink_config.supported_interfaces);
1084 __set_bit(PHY_INTERFACE_MODE_SGMII,
1085 pf->phylink_config.supported_interfaces);
1086 __set_bit(PHY_INTERFACE_MODE_2500BASEX,
1087 pf->phylink_config.supported_interfaces);
1088 __set_bit(PHY_INTERFACE_MODE_USXGMII,
1089 pf->phylink_config.supported_interfaces);
1090 phy_interface_set_rgmii(pf->phylink_config.supported_interfaces);
1091
1092 phylink = phylink_create(&pf->phylink_config, of_fwnode_handle(node),
1093 pf->if_mode, &enetc_mac_phylink_ops);
1094 if (IS_ERR(phylink)) {
1095 err = PTR_ERR(phylink);
1096 return err;
1097 }
1098
1099 priv->phylink = phylink;
1100
1101 return 0;
1102}
1103
1104static void enetc_phylink_destroy(struct enetc_ndev_priv *priv)
1105{
1106 if (priv->phylink)
1107 phylink_destroy(priv->phylink);
1108}
1109
1110
1111
1112
1113static int enetc_init_port_rfs_memory(struct enetc_si *si)
1114{
1115 struct enetc_cmd_rfse rfse = {0};
1116 struct enetc_hw *hw = &si->hw;
1117 int num_rfs, i, err = 0;
1118 u32 val;
1119
1120 val = enetc_port_rd(hw, ENETC_PRFSCAPR);
1121 num_rfs = ENETC_PRFSCAPR_GET_NUM_RFS(val);
1122
1123 for (i = 0; i < num_rfs; i++) {
1124 err = enetc_set_fs_entry(si, &rfse, i);
1125 if (err)
1126 break;
1127 }
1128
1129 return err;
1130}
1131
1132static int enetc_init_port_rss_memory(struct enetc_si *si)
1133{
1134 struct enetc_hw *hw = &si->hw;
1135 int num_rss, err;
1136 int *rss_table;
1137 u32 val;
1138
1139 val = enetc_port_rd(hw, ENETC_PRSSCAPR);
1140 num_rss = ENETC_PRSSCAPR_GET_NUM_RSS(val);
1141 if (!num_rss)
1142 return 0;
1143
1144 rss_table = kcalloc(num_rss, sizeof(*rss_table), GFP_KERNEL);
1145 if (!rss_table)
1146 return -ENOMEM;
1147
1148 err = enetc_set_rss_table(si, rss_table, num_rss);
1149
1150 kfree(rss_table);
1151
1152 return err;
1153}
1154
1155static int enetc_pf_register_with_ierb(struct pci_dev *pdev)
1156{
1157 struct device_node *node = pdev->dev.of_node;
1158 struct platform_device *ierb_pdev;
1159 struct device_node *ierb_node;
1160
1161
1162 if (!node || !of_device_is_available(node))
1163 return 0;
1164
1165 ierb_node = of_find_compatible_node(NULL, NULL,
1166 "fsl,ls1028a-enetc-ierb");
1167 if (!ierb_node || !of_device_is_available(ierb_node))
1168 return -ENODEV;
1169
1170 ierb_pdev = of_find_device_by_node(ierb_node);
1171 of_node_put(ierb_node);
1172
1173 if (!ierb_pdev)
1174 return -EPROBE_DEFER;
1175
1176 return enetc_ierb_register_pf(ierb_pdev, pdev);
1177}
1178
1179static int enetc_pf_probe(struct pci_dev *pdev,
1180 const struct pci_device_id *ent)
1181{
1182 struct device_node *node = pdev->dev.of_node;
1183 struct enetc_ndev_priv *priv;
1184 struct net_device *ndev;
1185 struct enetc_si *si;
1186 struct enetc_pf *pf;
1187 int err;
1188
1189 err = enetc_pf_register_with_ierb(pdev);
1190 if (err == -EPROBE_DEFER)
1191 return err;
1192 if (err)
1193 dev_warn(&pdev->dev,
1194 "Could not register with IERB driver: %pe, please update the device tree\n",
1195 ERR_PTR(err));
1196
1197 err = enetc_pci_probe(pdev, KBUILD_MODNAME, sizeof(*pf));
1198 if (err)
1199 return dev_err_probe(&pdev->dev, err, "PCI probing failed\n");
1200
1201 si = pci_get_drvdata(pdev);
1202 if (!si->hw.port || !si->hw.global) {
1203 err = -ENODEV;
1204 dev_err(&pdev->dev, "could not map PF space, probing a VF?\n");
1205 goto err_map_pf_space;
1206 }
1207
1208 err = enetc_setup_cbdr(&pdev->dev, &si->hw, ENETC_CBDR_DEFAULT_SIZE,
1209 &si->cbd_ring);
1210 if (err)
1211 goto err_setup_cbdr;
1212
1213 err = enetc_init_port_rfs_memory(si);
1214 if (err) {
1215 dev_err(&pdev->dev, "Failed to initialize RFS memory\n");
1216 goto err_init_port_rfs;
1217 }
1218
1219 err = enetc_init_port_rss_memory(si);
1220 if (err) {
1221 dev_err(&pdev->dev, "Failed to initialize RSS memory\n");
1222 goto err_init_port_rss;
1223 }
1224
1225 if (node && !of_device_is_available(node)) {
1226 dev_info(&pdev->dev, "device is disabled, skipping\n");
1227 err = -ENODEV;
1228 goto err_device_disabled;
1229 }
1230
1231 pf = enetc_si_priv(si);
1232 pf->si = si;
1233 pf->total_vfs = pci_sriov_get_totalvfs(pdev);
1234
1235 err = enetc_setup_mac_addresses(node, pf);
1236 if (err)
1237 goto err_setup_mac_addresses;
1238
1239 enetc_configure_port(pf);
1240
1241 enetc_get_si_caps(si);
1242
1243 ndev = alloc_etherdev_mq(sizeof(*priv), ENETC_MAX_NUM_TXQS);
1244 if (!ndev) {
1245 err = -ENOMEM;
1246 dev_err(&pdev->dev, "netdev creation failed\n");
1247 goto err_alloc_netdev;
1248 }
1249
1250 enetc_pf_netdev_setup(si, ndev, &enetc_ndev_ops);
1251
1252 priv = netdev_priv(ndev);
1253
1254 enetc_init_si_rings_params(priv);
1255
1256 err = enetc_alloc_si_resources(priv);
1257 if (err) {
1258 dev_err(&pdev->dev, "SI resource alloc failed\n");
1259 goto err_alloc_si_res;
1260 }
1261
1262 err = enetc_configure_si(priv);
1263 if (err) {
1264 dev_err(&pdev->dev, "Failed to configure SI\n");
1265 goto err_config_si;
1266 }
1267
1268 err = enetc_alloc_msix(priv);
1269 if (err) {
1270 dev_err(&pdev->dev, "MSIX alloc failed\n");
1271 goto err_alloc_msix;
1272 }
1273
1274 if (!of_get_phy_mode(node, &pf->if_mode)) {
1275 err = enetc_mdiobus_create(pf, node);
1276 if (err)
1277 goto err_mdiobus_create;
1278
1279 err = enetc_phylink_create(priv, node);
1280 if (err)
1281 goto err_phylink_create;
1282 }
1283
1284 err = register_netdev(ndev);
1285 if (err)
1286 goto err_reg_netdev;
1287
1288 return 0;
1289
1290err_reg_netdev:
1291 enetc_phylink_destroy(priv);
1292err_phylink_create:
1293 enetc_mdiobus_destroy(pf);
1294err_mdiobus_create:
1295 enetc_free_msix(priv);
1296err_config_si:
1297err_alloc_msix:
1298 enetc_free_si_resources(priv);
1299err_alloc_si_res:
1300 si->ndev = NULL;
1301 free_netdev(ndev);
1302err_alloc_netdev:
1303err_init_port_rss:
1304err_init_port_rfs:
1305err_device_disabled:
1306err_setup_mac_addresses:
1307 enetc_teardown_cbdr(&si->cbd_ring);
1308err_setup_cbdr:
1309err_map_pf_space:
1310 enetc_pci_remove(pdev);
1311
1312 return err;
1313}
1314
1315static void enetc_pf_remove(struct pci_dev *pdev)
1316{
1317 struct enetc_si *si = pci_get_drvdata(pdev);
1318 struct enetc_pf *pf = enetc_si_priv(si);
1319 struct enetc_ndev_priv *priv;
1320
1321 priv = netdev_priv(si->ndev);
1322
1323 if (pf->num_vfs)
1324 enetc_sriov_configure(pdev, 0);
1325
1326 unregister_netdev(si->ndev);
1327
1328 enetc_phylink_destroy(priv);
1329 enetc_mdiobus_destroy(pf);
1330
1331 enetc_free_msix(priv);
1332
1333 enetc_free_si_resources(priv);
1334 enetc_teardown_cbdr(&si->cbd_ring);
1335
1336 free_netdev(si->ndev);
1337
1338 enetc_pci_remove(pdev);
1339}
1340
1341static const struct pci_device_id enetc_pf_id_table[] = {
1342 { PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, ENETC_DEV_ID_PF) },
1343 { 0, }
1344};
1345MODULE_DEVICE_TABLE(pci, enetc_pf_id_table);
1346
1347static struct pci_driver enetc_pf_driver = {
1348 .name = KBUILD_MODNAME,
1349 .id_table = enetc_pf_id_table,
1350 .probe = enetc_pf_probe,
1351 .remove = enetc_pf_remove,
1352#ifdef CONFIG_PCI_IOV
1353 .sriov_configure = enetc_sriov_configure,
1354#endif
1355};
1356module_pci_driver(enetc_pf_driver);
1357
1358MODULE_DESCRIPTION(ENETC_DRV_NAME_STR);
1359MODULE_LICENSE("Dual BSD/GPL");
1360
