1
2
3
4#include <linux/kernel.h>
5#include <linux/module.h>
6#include <linux/export.h>
7#include <linux/err.h>
8#include <linux/device.h>
9#include <linux/pci.h>
10#include <linux/interrupt.h>
11#include <linux/wait.h>
12#include <linux/types.h>
13#include <linux/skbuff.h>
14#include <linux/if_vlan.h>
15#include <linux/log2.h>
16#include <linux/string.h>
17
18#include "pci_hw.h"
19#include "pci.h"
20#include "core.h"
21#include "cmd.h"
22#include "port.h"
23#include "resources.h"
24
25#define mlxsw_pci_write32(mlxsw_pci, reg, val) \
26 iowrite32be(val, (mlxsw_pci)->hw_addr + (MLXSW_PCI_ ## reg))
27#define mlxsw_pci_read32(mlxsw_pci, reg) \
28 ioread32be((mlxsw_pci)->hw_addr + (MLXSW_PCI_ ## reg))
29
30enum mlxsw_pci_queue_type {
31 MLXSW_PCI_QUEUE_TYPE_SDQ,
32 MLXSW_PCI_QUEUE_TYPE_RDQ,
33 MLXSW_PCI_QUEUE_TYPE_CQ,
34 MLXSW_PCI_QUEUE_TYPE_EQ,
35};
36
37#define MLXSW_PCI_QUEUE_TYPE_COUNT 4
38
39static const u16 mlxsw_pci_doorbell_type_offset[] = {
40 MLXSW_PCI_DOORBELL_SDQ_OFFSET,
41 MLXSW_PCI_DOORBELL_RDQ_OFFSET,
42 MLXSW_PCI_DOORBELL_CQ_OFFSET,
43 MLXSW_PCI_DOORBELL_EQ_OFFSET,
44};
45
46static const u16 mlxsw_pci_doorbell_arm_type_offset[] = {
47 0,
48 0,
49 MLXSW_PCI_DOORBELL_ARM_CQ_OFFSET,
50 MLXSW_PCI_DOORBELL_ARM_EQ_OFFSET,
51};
52
53struct mlxsw_pci_mem_item {
54 char *buf;
55 dma_addr_t mapaddr;
56 size_t size;
57};
58
59struct mlxsw_pci_queue_elem_info {
60 char *elem;
61 union {
62 struct {
63 struct sk_buff *skb;
64 } sdq;
65 struct {
66 struct sk_buff *skb;
67 } rdq;
68 } u;
69};
70
71struct mlxsw_pci_queue {
72 spinlock_t lock;
73 struct mlxsw_pci_mem_item mem_item;
74 struct mlxsw_pci_queue_elem_info *elem_info;
75 u16 producer_counter;
76 u16 consumer_counter;
77 u16 count;
78 u8 num;
79 u8 elem_size;
80 enum mlxsw_pci_queue_type type;
81 struct tasklet_struct tasklet;
82 struct mlxsw_pci *pci;
83 union {
84 struct {
85 u32 comp_sdq_count;
86 u32 comp_rdq_count;
87 enum mlxsw_pci_cqe_v v;
88 } cq;
89 struct {
90 u32 ev_cmd_count;
91 u32 ev_comp_count;
92 u32 ev_other_count;
93 } eq;
94 } u;
95};
96
97struct mlxsw_pci_queue_type_group {
98 struct mlxsw_pci_queue *q;
99 u8 count;
100};
101
102struct mlxsw_pci {
103 struct pci_dev *pdev;
104 u8 __iomem *hw_addr;
105 u64 free_running_clock_offset;
106 struct mlxsw_pci_queue_type_group queues[MLXSW_PCI_QUEUE_TYPE_COUNT];
107 u32 doorbell_offset;
108 struct mlxsw_core *core;
109 struct {
110 struct mlxsw_pci_mem_item *items;
111 unsigned int count;
112 } fw_area;
113 struct {
114 struct mlxsw_pci_mem_item out_mbox;
115 struct mlxsw_pci_mem_item in_mbox;
116 struct mutex lock;
117 bool nopoll;
118 wait_queue_head_t wait;
119 bool wait_done;
120 struct {
121 u8 status;
122 u64 out_param;
123 } comp;
124 } cmd;
125 struct mlxsw_bus_info bus_info;
126 const struct pci_device_id *id;
127 enum mlxsw_pci_cqe_v max_cqe_ver;
128 u8 num_sdq_cqs;
129};
130
131static void mlxsw_pci_queue_tasklet_schedule(struct mlxsw_pci_queue *q)
132{
133 tasklet_schedule(&q->tasklet);
134}
135
136static char *__mlxsw_pci_queue_elem_get(struct mlxsw_pci_queue *q,
137 size_t elem_size, int elem_index)
138{
139 return q->mem_item.buf + (elem_size * elem_index);
140}
141
142static struct mlxsw_pci_queue_elem_info *
143mlxsw_pci_queue_elem_info_get(struct mlxsw_pci_queue *q, int elem_index)
144{
145 return &q->elem_info[elem_index];
146}
147
148static struct mlxsw_pci_queue_elem_info *
149mlxsw_pci_queue_elem_info_producer_get(struct mlxsw_pci_queue *q)
150{
151 int index = q->producer_counter & (q->count - 1);
152
153 if ((u16) (q->producer_counter - q->consumer_counter) == q->count)
154 return NULL;
155 return mlxsw_pci_queue_elem_info_get(q, index);
156}
157
158static struct mlxsw_pci_queue_elem_info *
159mlxsw_pci_queue_elem_info_consumer_get(struct mlxsw_pci_queue *q)
160{
161 int index = q->consumer_counter & (q->count - 1);
162
163 return mlxsw_pci_queue_elem_info_get(q, index);
164}
165
166static char *mlxsw_pci_queue_elem_get(struct mlxsw_pci_queue *q, int elem_index)
167{
168 return mlxsw_pci_queue_elem_info_get(q, elem_index)->elem;
169}
170
171static bool mlxsw_pci_elem_hw_owned(struct mlxsw_pci_queue *q, bool owner_bit)
172{
173 return owner_bit != !!(q->consumer_counter & q->count);
174}
175
176static struct mlxsw_pci_queue_type_group *
177mlxsw_pci_queue_type_group_get(struct mlxsw_pci *mlxsw_pci,
178 enum mlxsw_pci_queue_type q_type)
179{
180 return &mlxsw_pci->queues[q_type];
181}
182
183static u8 __mlxsw_pci_queue_count(struct mlxsw_pci *mlxsw_pci,
184 enum mlxsw_pci_queue_type q_type)
185{
186 struct mlxsw_pci_queue_type_group *queue_group;
187
188 queue_group = mlxsw_pci_queue_type_group_get(mlxsw_pci, q_type);
189 return queue_group->count;
190}
191
192static u8 mlxsw_pci_sdq_count(struct mlxsw_pci *mlxsw_pci)
193{
194 return __mlxsw_pci_queue_count(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_SDQ);
195}
196
197static u8 mlxsw_pci_cq_count(struct mlxsw_pci *mlxsw_pci)
198{
199 return __mlxsw_pci_queue_count(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_CQ);
200}
201
202static struct mlxsw_pci_queue *
203__mlxsw_pci_queue_get(struct mlxsw_pci *mlxsw_pci,
204 enum mlxsw_pci_queue_type q_type, u8 q_num)
205{
206 return &mlxsw_pci->queues[q_type].q[q_num];
207}
208
209static struct mlxsw_pci_queue *mlxsw_pci_sdq_get(struct mlxsw_pci *mlxsw_pci,
210 u8 q_num)
211{
212 return __mlxsw_pci_queue_get(mlxsw_pci,
213 MLXSW_PCI_QUEUE_TYPE_SDQ, q_num);
214}
215
216static struct mlxsw_pci_queue *mlxsw_pci_rdq_get(struct mlxsw_pci *mlxsw_pci,
217 u8 q_num)
218{
219 return __mlxsw_pci_queue_get(mlxsw_pci,
220 MLXSW_PCI_QUEUE_TYPE_RDQ, q_num);
221}
222
223static struct mlxsw_pci_queue *mlxsw_pci_cq_get(struct mlxsw_pci *mlxsw_pci,
224 u8 q_num)
225{
226 return __mlxsw_pci_queue_get(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_CQ, q_num);
227}
228
229static struct mlxsw_pci_queue *mlxsw_pci_eq_get(struct mlxsw_pci *mlxsw_pci,
230 u8 q_num)
231{
232 return __mlxsw_pci_queue_get(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_EQ, q_num);
233}
234
235static void __mlxsw_pci_queue_doorbell_set(struct mlxsw_pci *mlxsw_pci,
236 struct mlxsw_pci_queue *q,
237 u16 val)
238{
239 mlxsw_pci_write32(mlxsw_pci,
240 DOORBELL(mlxsw_pci->doorbell_offset,
241 mlxsw_pci_doorbell_type_offset[q->type],
242 q->num), val);
243}
244
245static void __mlxsw_pci_queue_doorbell_arm_set(struct mlxsw_pci *mlxsw_pci,
246 struct mlxsw_pci_queue *q,
247 u16 val)
248{
249 mlxsw_pci_write32(mlxsw_pci,
250 DOORBELL(mlxsw_pci->doorbell_offset,
251 mlxsw_pci_doorbell_arm_type_offset[q->type],
252 q->num), val);
253}
254
255static void mlxsw_pci_queue_doorbell_producer_ring(struct mlxsw_pci *mlxsw_pci,
256 struct mlxsw_pci_queue *q)
257{
258 wmb();
259 __mlxsw_pci_queue_doorbell_set(mlxsw_pci, q, q->producer_counter);
260}
261
262static void mlxsw_pci_queue_doorbell_consumer_ring(struct mlxsw_pci *mlxsw_pci,
263 struct mlxsw_pci_queue *q)
264{
265 wmb();
266 __mlxsw_pci_queue_doorbell_set(mlxsw_pci, q,
267 q->consumer_counter + q->count);
268}
269
270static void
271mlxsw_pci_queue_doorbell_arm_consumer_ring(struct mlxsw_pci *mlxsw_pci,
272 struct mlxsw_pci_queue *q)
273{
274 wmb();
275 __mlxsw_pci_queue_doorbell_arm_set(mlxsw_pci, q, q->consumer_counter);
276}
277
278static dma_addr_t __mlxsw_pci_queue_page_get(struct mlxsw_pci_queue *q,
279 int page_index)
280{
281 return q->mem_item.mapaddr + MLXSW_PCI_PAGE_SIZE * page_index;
282}
283
284static int mlxsw_pci_sdq_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
285 struct mlxsw_pci_queue *q)
286{
287 int tclass;
288 int lp;
289 int i;
290 int err;
291
292 q->producer_counter = 0;
293 q->consumer_counter = 0;
294 tclass = q->num == MLXSW_PCI_SDQ_EMAD_INDEX ? MLXSW_PCI_SDQ_EMAD_TC :
295 MLXSW_PCI_SDQ_CTL_TC;
296 lp = q->num == MLXSW_PCI_SDQ_EMAD_INDEX ? MLXSW_CMD_MBOX_SW2HW_DQ_SDQ_LP_IGNORE_WQE :
297 MLXSW_CMD_MBOX_SW2HW_DQ_SDQ_LP_WQE;
298
299
300 mlxsw_cmd_mbox_sw2hw_dq_cq_set(mbox, q->num);
301 mlxsw_cmd_mbox_sw2hw_dq_sdq_lp_set(mbox, lp);
302 mlxsw_cmd_mbox_sw2hw_dq_sdq_tclass_set(mbox, tclass);
303 mlxsw_cmd_mbox_sw2hw_dq_log2_dq_sz_set(mbox, 3);
304 for (i = 0; i < MLXSW_PCI_AQ_PAGES; i++) {
305 dma_addr_t mapaddr = __mlxsw_pci_queue_page_get(q, i);
306
307 mlxsw_cmd_mbox_sw2hw_dq_pa_set(mbox, i, mapaddr);
308 }
309
310 err = mlxsw_cmd_sw2hw_sdq(mlxsw_pci->core, mbox, q->num);
311 if (err)
312 return err;
313 mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q);
314 return 0;
315}
316
317static void mlxsw_pci_sdq_fini(struct mlxsw_pci *mlxsw_pci,
318 struct mlxsw_pci_queue *q)
319{
320 mlxsw_cmd_hw2sw_sdq(mlxsw_pci->core, q->num);
321}
322
323static int mlxsw_pci_wqe_frag_map(struct mlxsw_pci *mlxsw_pci, char *wqe,
324 int index, char *frag_data, size_t frag_len,
325 int direction)
326{
327 struct pci_dev *pdev = mlxsw_pci->pdev;
328 dma_addr_t mapaddr;
329
330 mapaddr = dma_map_single(&pdev->dev, frag_data, frag_len, direction);
331 if (unlikely(dma_mapping_error(&pdev->dev, mapaddr))) {
332 dev_err_ratelimited(&pdev->dev, "failed to dma map tx frag\n");
333 return -EIO;
334 }
335 mlxsw_pci_wqe_address_set(wqe, index, mapaddr);
336 mlxsw_pci_wqe_byte_count_set(wqe, index, frag_len);
337 return 0;
338}
339
340static void mlxsw_pci_wqe_frag_unmap(struct mlxsw_pci *mlxsw_pci, char *wqe,
341 int index, int direction)
342{
343 struct pci_dev *pdev = mlxsw_pci->pdev;
344 size_t frag_len = mlxsw_pci_wqe_byte_count_get(wqe, index);
345 dma_addr_t mapaddr = mlxsw_pci_wqe_address_get(wqe, index);
346
347 if (!frag_len)
348 return;
349 dma_unmap_single(&pdev->dev, mapaddr, frag_len, direction);
350}
351
352static int mlxsw_pci_rdq_skb_alloc(struct mlxsw_pci *mlxsw_pci,
353 struct mlxsw_pci_queue_elem_info *elem_info)
354{
355 size_t buf_len = MLXSW_PORT_MAX_MTU;
356 char *wqe = elem_info->elem;
357 struct sk_buff *skb;
358 int err;
359
360 skb = netdev_alloc_skb_ip_align(NULL, buf_len);
361 if (!skb)
362 return -ENOMEM;
363
364 err = mlxsw_pci_wqe_frag_map(mlxsw_pci, wqe, 0, skb->data,
365 buf_len, DMA_FROM_DEVICE);
366 if (err)
367 goto err_frag_map;
368
369 elem_info->u.rdq.skb = skb;
370 return 0;
371
372err_frag_map:
373 dev_kfree_skb_any(skb);
374 return err;
375}
376
377static void mlxsw_pci_rdq_skb_free(struct mlxsw_pci *mlxsw_pci,
378 struct mlxsw_pci_queue_elem_info *elem_info)
379{
380 struct sk_buff *skb;
381 char *wqe;
382
383 skb = elem_info->u.rdq.skb;
384 wqe = elem_info->elem;
385
386 mlxsw_pci_wqe_frag_unmap(mlxsw_pci, wqe, 0, DMA_FROM_DEVICE);
387 dev_kfree_skb_any(skb);
388}
389
390static int mlxsw_pci_rdq_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
391 struct mlxsw_pci_queue *q)
392{
393 struct mlxsw_pci_queue_elem_info *elem_info;
394 u8 sdq_count = mlxsw_pci_sdq_count(mlxsw_pci);
395 int i;
396 int err;
397
398 q->producer_counter = 0;
399 q->consumer_counter = 0;
400
401
402
403
404 mlxsw_cmd_mbox_sw2hw_dq_cq_set(mbox, sdq_count + q->num);
405 mlxsw_cmd_mbox_sw2hw_dq_log2_dq_sz_set(mbox, 3);
406 for (i = 0; i < MLXSW_PCI_AQ_PAGES; i++) {
407 dma_addr_t mapaddr = __mlxsw_pci_queue_page_get(q, i);
408
409 mlxsw_cmd_mbox_sw2hw_dq_pa_set(mbox, i, mapaddr);
410 }
411
412 err = mlxsw_cmd_sw2hw_rdq(mlxsw_pci->core, mbox, q->num);
413 if (err)
414 return err;
415
416 mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q);
417
418 for (i = 0; i < q->count; i++) {
419 elem_info = mlxsw_pci_queue_elem_info_producer_get(q);
420 BUG_ON(!elem_info);
421 err = mlxsw_pci_rdq_skb_alloc(mlxsw_pci, elem_info);
422 if (err)
423 goto rollback;
424
425 q->producer_counter++;
426 mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q);
427 }
428
429 return 0;
430
431rollback:
432 for (i--; i >= 0; i--) {
433 elem_info = mlxsw_pci_queue_elem_info_get(q, i);
434 mlxsw_pci_rdq_skb_free(mlxsw_pci, elem_info);
435 }
436 mlxsw_cmd_hw2sw_rdq(mlxsw_pci->core, q->num);
437
438 return err;
439}
440
441static void mlxsw_pci_rdq_fini(struct mlxsw_pci *mlxsw_pci,
442 struct mlxsw_pci_queue *q)
443{
444 struct mlxsw_pci_queue_elem_info *elem_info;
445 int i;
446
447 mlxsw_cmd_hw2sw_rdq(mlxsw_pci->core, q->num);
448 for (i = 0; i < q->count; i++) {
449 elem_info = mlxsw_pci_queue_elem_info_get(q, i);
450 mlxsw_pci_rdq_skb_free(mlxsw_pci, elem_info);
451 }
452}
453
454static void mlxsw_pci_cq_pre_init(struct mlxsw_pci *mlxsw_pci,
455 struct mlxsw_pci_queue *q)
456{
457 q->u.cq.v = mlxsw_pci->max_cqe_ver;
458
459
460 if (q->u.cq.v == MLXSW_PCI_CQE_V2 &&
461 q->num < mlxsw_pci->num_sdq_cqs)
462 q->u.cq.v = MLXSW_PCI_CQE_V1;
463}
464
465static int mlxsw_pci_cq_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
466 struct mlxsw_pci_queue *q)
467{
468 int i;
469 int err;
470
471 q->consumer_counter = 0;
472
473 for (i = 0; i < q->count; i++) {
474 char *elem = mlxsw_pci_queue_elem_get(q, i);
475
476 mlxsw_pci_cqe_owner_set(q->u.cq.v, elem, 1);
477 }
478
479 if (q->u.cq.v == MLXSW_PCI_CQE_V1)
480 mlxsw_cmd_mbox_sw2hw_cq_cqe_ver_set(mbox,
481 MLXSW_CMD_MBOX_SW2HW_CQ_CQE_VER_1);
482 else if (q->u.cq.v == MLXSW_PCI_CQE_V2)
483 mlxsw_cmd_mbox_sw2hw_cq_cqe_ver_set(mbox,
484 MLXSW_CMD_MBOX_SW2HW_CQ_CQE_VER_2);
485
486 mlxsw_cmd_mbox_sw2hw_cq_c_eqn_set(mbox, MLXSW_PCI_EQ_COMP_NUM);
487 mlxsw_cmd_mbox_sw2hw_cq_st_set(mbox, 0);
488 mlxsw_cmd_mbox_sw2hw_cq_log_cq_size_set(mbox, ilog2(q->count));
489 for (i = 0; i < MLXSW_PCI_AQ_PAGES; i++) {
490 dma_addr_t mapaddr = __mlxsw_pci_queue_page_get(q, i);
491
492 mlxsw_cmd_mbox_sw2hw_cq_pa_set(mbox, i, mapaddr);
493 }
494 err = mlxsw_cmd_sw2hw_cq(mlxsw_pci->core, mbox, q->num);
495 if (err)
496 return err;
497 mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci, q);
498 mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci, q);
499 return 0;
500}
501
502static void mlxsw_pci_cq_fini(struct mlxsw_pci *mlxsw_pci,
503 struct mlxsw_pci_queue *q)
504{
505 mlxsw_cmd_hw2sw_cq(mlxsw_pci->core, q->num);
506}
507
508static void mlxsw_pci_cqe_sdq_handle(struct mlxsw_pci *mlxsw_pci,
509 struct mlxsw_pci_queue *q,
510 u16 consumer_counter_limit,
511 char *cqe)
512{
513 struct pci_dev *pdev = mlxsw_pci->pdev;
514 struct mlxsw_pci_queue_elem_info *elem_info;
515 struct mlxsw_tx_info tx_info;
516 char *wqe;
517 struct sk_buff *skb;
518 int i;
519
520 spin_lock(&q->lock);
521 elem_info = mlxsw_pci_queue_elem_info_consumer_get(q);
522 tx_info = mlxsw_skb_cb(elem_info->u.sdq.skb)->tx_info;
523 skb = elem_info->u.sdq.skb;
524 wqe = elem_info->elem;
525 for (i = 0; i < MLXSW_PCI_WQE_SG_ENTRIES; i++)
526 mlxsw_pci_wqe_frag_unmap(mlxsw_pci, wqe, i, DMA_TO_DEVICE);
527
528 if (unlikely(!tx_info.is_emad &&
529 skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
530 mlxsw_core_ptp_transmitted(mlxsw_pci->core, skb,
531 tx_info.local_port);
532 skb = NULL;
533 }
534
535 if (skb)
536 dev_kfree_skb_any(skb);
537 elem_info->u.sdq.skb = NULL;
538
539 if (q->consumer_counter++ != consumer_counter_limit)
540 dev_dbg_ratelimited(&pdev->dev, "Consumer counter does not match limit in SDQ\n");
541 spin_unlock(&q->lock);
542}
543
544static void mlxsw_pci_cqe_rdq_md_tx_port_init(struct sk_buff *skb,
545 const char *cqe)
546{
547 struct mlxsw_skb_cb *cb = mlxsw_skb_cb(skb);
548
549 if (mlxsw_pci_cqe2_tx_lag_get(cqe)) {
550 cb->rx_md_info.tx_port_is_lag = true;
551 cb->rx_md_info.tx_lag_id = mlxsw_pci_cqe2_tx_lag_id_get(cqe);
552 cb->rx_md_info.tx_lag_port_index =
553 mlxsw_pci_cqe2_tx_lag_subport_get(cqe);
554 } else {
555 cb->rx_md_info.tx_port_is_lag = false;
556 cb->rx_md_info.tx_sys_port =
557 mlxsw_pci_cqe2_tx_system_port_get(cqe);
558 }
559
560 if (cb->rx_md_info.tx_sys_port != MLXSW_PCI_CQE2_TX_PORT_MULTI_PORT &&
561 cb->rx_md_info.tx_sys_port != MLXSW_PCI_CQE2_TX_PORT_INVALID)
562 cb->rx_md_info.tx_port_valid = 1;
563 else
564 cb->rx_md_info.tx_port_valid = 0;
565}
566
567static void mlxsw_pci_cqe_rdq_md_init(struct sk_buff *skb, const char *cqe)
568{
569 struct mlxsw_skb_cb *cb = mlxsw_skb_cb(skb);
570
571 cb->rx_md_info.tx_congestion = mlxsw_pci_cqe2_mirror_cong_get(cqe);
572 if (cb->rx_md_info.tx_congestion != MLXSW_PCI_CQE2_MIRROR_CONG_INVALID)
573 cb->rx_md_info.tx_congestion_valid = 1;
574 else
575 cb->rx_md_info.tx_congestion_valid = 0;
576 cb->rx_md_info.tx_congestion <<= MLXSW_PCI_CQE2_MIRROR_CONG_SHIFT;
577
578 cb->rx_md_info.latency = mlxsw_pci_cqe2_mirror_latency_get(cqe);
579 if (cb->rx_md_info.latency != MLXSW_PCI_CQE2_MIRROR_LATENCY_INVALID)
580 cb->rx_md_info.latency_valid = 1;
581 else
582 cb->rx_md_info.latency_valid = 0;
583
584 cb->rx_md_info.tx_tc = mlxsw_pci_cqe2_mirror_tclass_get(cqe);
585 if (cb->rx_md_info.tx_tc != MLXSW_PCI_CQE2_MIRROR_TCLASS_INVALID)
586 cb->rx_md_info.tx_tc_valid = 1;
587 else
588 cb->rx_md_info.tx_tc_valid = 0;
589
590 mlxsw_pci_cqe_rdq_md_tx_port_init(skb, cqe);
591}
592
593static void mlxsw_pci_cqe_rdq_handle(struct mlxsw_pci *mlxsw_pci,
594 struct mlxsw_pci_queue *q,
595 u16 consumer_counter_limit,
596 enum mlxsw_pci_cqe_v cqe_v, char *cqe)
597{
598 struct pci_dev *pdev = mlxsw_pci->pdev;
599 struct mlxsw_pci_queue_elem_info *elem_info;
600 struct mlxsw_rx_info rx_info = {};
601 char wqe[MLXSW_PCI_WQE_SIZE];
602 struct sk_buff *skb;
603 u16 byte_count;
604 int err;
605
606 elem_info = mlxsw_pci_queue_elem_info_consumer_get(q);
607 skb = elem_info->u.rdq.skb;
608 memcpy(wqe, elem_info->elem, MLXSW_PCI_WQE_SIZE);
609
610 if (q->consumer_counter++ != consumer_counter_limit)
611 dev_dbg_ratelimited(&pdev->dev, "Consumer counter does not match limit in RDQ\n");
612
613 err = mlxsw_pci_rdq_skb_alloc(mlxsw_pci, elem_info);
614 if (err) {
615 dev_err_ratelimited(&pdev->dev, "Failed to alloc skb for RDQ\n");
616 goto out;
617 }
618
619 mlxsw_pci_wqe_frag_unmap(mlxsw_pci, wqe, 0, DMA_FROM_DEVICE);
620
621 if (mlxsw_pci_cqe_lag_get(cqe_v, cqe)) {
622 rx_info.is_lag = true;
623 rx_info.u.lag_id = mlxsw_pci_cqe_lag_id_get(cqe_v, cqe);
624 rx_info.lag_port_index =
625 mlxsw_pci_cqe_lag_subport_get(cqe_v, cqe);
626 } else {
627 rx_info.is_lag = false;
628 rx_info.u.sys_port = mlxsw_pci_cqe_system_port_get(cqe);
629 }
630
631 rx_info.trap_id = mlxsw_pci_cqe_trap_id_get(cqe);
632
633 if (rx_info.trap_id == MLXSW_TRAP_ID_DISCARD_INGRESS_ACL ||
634 rx_info.trap_id == MLXSW_TRAP_ID_DISCARD_EGRESS_ACL) {
635 u32 cookie_index = 0;
636
637 if (mlxsw_pci->max_cqe_ver >= MLXSW_PCI_CQE_V2)
638 cookie_index = mlxsw_pci_cqe2_user_def_val_orig_pkt_len_get(cqe);
639 mlxsw_skb_cb(skb)->rx_md_info.cookie_index = cookie_index;
640 } else if (rx_info.trap_id >= MLXSW_TRAP_ID_MIRROR_SESSION0 &&
641 rx_info.trap_id <= MLXSW_TRAP_ID_MIRROR_SESSION7 &&
642 mlxsw_pci->max_cqe_ver >= MLXSW_PCI_CQE_V2) {
643 rx_info.mirror_reason = mlxsw_pci_cqe2_mirror_reason_get(cqe);
644 mlxsw_pci_cqe_rdq_md_init(skb, cqe);
645 } else if (rx_info.trap_id == MLXSW_TRAP_ID_PKT_SAMPLE &&
646 mlxsw_pci->max_cqe_ver >= MLXSW_PCI_CQE_V2) {
647 mlxsw_pci_cqe_rdq_md_tx_port_init(skb, cqe);
648 }
649
650 byte_count = mlxsw_pci_cqe_byte_count_get(cqe);
651 if (mlxsw_pci_cqe_crc_get(cqe_v, cqe))
652 byte_count -= ETH_FCS_LEN;
653 skb_put(skb, byte_count);
654 mlxsw_core_skb_receive(mlxsw_pci->core, skb, &rx_info);
655
656out:
657
658 q->producer_counter++;
659 mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q);
660 return;
661}
662
663static char *mlxsw_pci_cq_sw_cqe_get(struct mlxsw_pci_queue *q)
664{
665 struct mlxsw_pci_queue_elem_info *elem_info;
666 char *elem;
667 bool owner_bit;
668
669 elem_info = mlxsw_pci_queue_elem_info_consumer_get(q);
670 elem = elem_info->elem;
671 owner_bit = mlxsw_pci_cqe_owner_get(q->u.cq.v, elem);
672 if (mlxsw_pci_elem_hw_owned(q, owner_bit))
673 return NULL;
674 q->consumer_counter++;
675 rmb();
676 return elem;
677}
678
679static void mlxsw_pci_cq_tasklet(struct tasklet_struct *t)
680{
681 struct mlxsw_pci_queue *q = from_tasklet(q, t, tasklet);
682 struct mlxsw_pci *mlxsw_pci = q->pci;
683 char *cqe;
684 int items = 0;
685 int credits = q->count >> 1;
686
687 while ((cqe = mlxsw_pci_cq_sw_cqe_get(q))) {
688 u16 wqe_counter = mlxsw_pci_cqe_wqe_counter_get(cqe);
689 u8 sendq = mlxsw_pci_cqe_sr_get(q->u.cq.v, cqe);
690 u8 dqn = mlxsw_pci_cqe_dqn_get(q->u.cq.v, cqe);
691 char ncqe[MLXSW_PCI_CQE_SIZE_MAX];
692
693 memcpy(ncqe, cqe, q->elem_size);
694 mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci, q);
695
696 if (sendq) {
697 struct mlxsw_pci_queue *sdq;
698
699 sdq = mlxsw_pci_sdq_get(mlxsw_pci, dqn);
700 mlxsw_pci_cqe_sdq_handle(mlxsw_pci, sdq,
701 wqe_counter, ncqe);
702 q->u.cq.comp_sdq_count++;
703 } else {
704 struct mlxsw_pci_queue *rdq;
705
706 rdq = mlxsw_pci_rdq_get(mlxsw_pci, dqn);
707 mlxsw_pci_cqe_rdq_handle(mlxsw_pci, rdq,
708 wqe_counter, q->u.cq.v, ncqe);
709 q->u.cq.comp_rdq_count++;
710 }
711 if (++items == credits)
712 break;
713 }
714 if (items)
715 mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci, q);
716}
717
718static u16 mlxsw_pci_cq_elem_count(const struct mlxsw_pci_queue *q)
719{
720 return q->u.cq.v == MLXSW_PCI_CQE_V2 ? MLXSW_PCI_CQE2_COUNT :
721 MLXSW_PCI_CQE01_COUNT;
722}
723
724static u8 mlxsw_pci_cq_elem_size(const struct mlxsw_pci_queue *q)
725{
726 return q->u.cq.v == MLXSW_PCI_CQE_V2 ? MLXSW_PCI_CQE2_SIZE :
727 MLXSW_PCI_CQE01_SIZE;
728}
729
730static int mlxsw_pci_eq_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
731 struct mlxsw_pci_queue *q)
732{
733 int i;
734 int err;
735
736 q->consumer_counter = 0;
737
738 for (i = 0; i < q->count; i++) {
739 char *elem = mlxsw_pci_queue_elem_get(q, i);
740
741 mlxsw_pci_eqe_owner_set(elem, 1);
742 }
743
744 mlxsw_cmd_mbox_sw2hw_eq_int_msix_set(mbox, 1);
745 mlxsw_cmd_mbox_sw2hw_eq_st_set(mbox, 1);
746 mlxsw_cmd_mbox_sw2hw_eq_log_eq_size_set(mbox, ilog2(q->count));
747 for (i = 0; i < MLXSW_PCI_AQ_PAGES; i++) {
748 dma_addr_t mapaddr = __mlxsw_pci_queue_page_get(q, i);
749
750 mlxsw_cmd_mbox_sw2hw_eq_pa_set(mbox, i, mapaddr);
751 }
752 err = mlxsw_cmd_sw2hw_eq(mlxsw_pci->core, mbox, q->num);
753 if (err)
754 return err;
755 mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci, q);
756 mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci, q);
757 return 0;
758}
759
760static void mlxsw_pci_eq_fini(struct mlxsw_pci *mlxsw_pci,
761 struct mlxsw_pci_queue *q)
762{
763 mlxsw_cmd_hw2sw_eq(mlxsw_pci->core, q->num);
764}
765
766static void mlxsw_pci_eq_cmd_event(struct mlxsw_pci *mlxsw_pci, char *eqe)
767{
768 mlxsw_pci->cmd.comp.status = mlxsw_pci_eqe_cmd_status_get(eqe);
769 mlxsw_pci->cmd.comp.out_param =
770 ((u64) mlxsw_pci_eqe_cmd_out_param_h_get(eqe)) << 32 |
771 mlxsw_pci_eqe_cmd_out_param_l_get(eqe);
772 mlxsw_pci->cmd.wait_done = true;
773 wake_up(&mlxsw_pci->cmd.wait);
774}
775
776static char *mlxsw_pci_eq_sw_eqe_get(struct mlxsw_pci_queue *q)
777{
778 struct mlxsw_pci_queue_elem_info *elem_info;
779 char *elem;
780 bool owner_bit;
781
782 elem_info = mlxsw_pci_queue_elem_info_consumer_get(q);
783 elem = elem_info->elem;
784 owner_bit = mlxsw_pci_eqe_owner_get(elem);
785 if (mlxsw_pci_elem_hw_owned(q, owner_bit))
786 return NULL;
787 q->consumer_counter++;
788 rmb();
789 return elem;
790}
791
792static void mlxsw_pci_eq_tasklet(struct tasklet_struct *t)
793{
794 struct mlxsw_pci_queue *q = from_tasklet(q, t, tasklet);
795 struct mlxsw_pci *mlxsw_pci = q->pci;
796 u8 cq_count = mlxsw_pci_cq_count(mlxsw_pci);
797 unsigned long active_cqns[BITS_TO_LONGS(MLXSW_PCI_CQS_MAX)];
798 char *eqe;
799 u8 cqn;
800 bool cq_handle = false;
801 int items = 0;
802 int credits = q->count >> 1;
803
804 memset(&active_cqns, 0, sizeof(active_cqns));
805
806 while ((eqe = mlxsw_pci_eq_sw_eqe_get(q))) {
807
808
809
810
811
812 switch (q->num) {
813 case MLXSW_PCI_EQ_ASYNC_NUM:
814 mlxsw_pci_eq_cmd_event(mlxsw_pci, eqe);
815 q->u.eq.ev_cmd_count++;
816 break;
817 case MLXSW_PCI_EQ_COMP_NUM:
818 cqn = mlxsw_pci_eqe_cqn_get(eqe);
819 set_bit(cqn, active_cqns);
820 cq_handle = true;
821 q->u.eq.ev_comp_count++;
822 break;
823 default:
824 q->u.eq.ev_other_count++;
825 }
826 if (++items == credits)
827 break;
828 }
829 if (items) {
830 mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci, q);
831 mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci, q);
832 }
833
834 if (!cq_handle)
835 return;
836 for_each_set_bit(cqn, active_cqns, cq_count) {
837 q = mlxsw_pci_cq_get(mlxsw_pci, cqn);
838 mlxsw_pci_queue_tasklet_schedule(q);
839 }
840}
841
842struct mlxsw_pci_queue_ops {
843 const char *name;
844 enum mlxsw_pci_queue_type type;
845 void (*pre_init)(struct mlxsw_pci *mlxsw_pci,
846 struct mlxsw_pci_queue *q);
847 int (*init)(struct mlxsw_pci *mlxsw_pci, char *mbox,
848 struct mlxsw_pci_queue *q);
849 void (*fini)(struct mlxsw_pci *mlxsw_pci,
850 struct mlxsw_pci_queue *q);
851 void (*tasklet)(struct tasklet_struct *t);
852 u16 (*elem_count_f)(const struct mlxsw_pci_queue *q);
853 u8 (*elem_size_f)(const struct mlxsw_pci_queue *q);
854 u16 elem_count;
855 u8 elem_size;
856};
857
858static const struct mlxsw_pci_queue_ops mlxsw_pci_sdq_ops = {
859 .type = MLXSW_PCI_QUEUE_TYPE_SDQ,
860 .init = mlxsw_pci_sdq_init,
861 .fini = mlxsw_pci_sdq_fini,
862 .elem_count = MLXSW_PCI_WQE_COUNT,
863 .elem_size = MLXSW_PCI_WQE_SIZE,
864};
865
866static const struct mlxsw_pci_queue_ops mlxsw_pci_rdq_ops = {
867 .type = MLXSW_PCI_QUEUE_TYPE_RDQ,
868 .init = mlxsw_pci_rdq_init,
869 .fini = mlxsw_pci_rdq_fini,
870 .elem_count = MLXSW_PCI_WQE_COUNT,
871 .elem_size = MLXSW_PCI_WQE_SIZE
872};
873
874static const struct mlxsw_pci_queue_ops mlxsw_pci_cq_ops = {
875 .type = MLXSW_PCI_QUEUE_TYPE_CQ,
876 .pre_init = mlxsw_pci_cq_pre_init,
877 .init = mlxsw_pci_cq_init,
878 .fini = mlxsw_pci_cq_fini,
879 .tasklet = mlxsw_pci_cq_tasklet,
880 .elem_count_f = mlxsw_pci_cq_elem_count,
881 .elem_size_f = mlxsw_pci_cq_elem_size
882};
883
884static const struct mlxsw_pci_queue_ops mlxsw_pci_eq_ops = {
885 .type = MLXSW_PCI_QUEUE_TYPE_EQ,
886 .init = mlxsw_pci_eq_init,
887 .fini = mlxsw_pci_eq_fini,
888 .tasklet = mlxsw_pci_eq_tasklet,
889 .elem_count = MLXSW_PCI_EQE_COUNT,
890 .elem_size = MLXSW_PCI_EQE_SIZE
891};
892
893static int mlxsw_pci_queue_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
894 const struct mlxsw_pci_queue_ops *q_ops,
895 struct mlxsw_pci_queue *q, u8 q_num)
896{
897 struct mlxsw_pci_mem_item *mem_item = &q->mem_item;
898 int i;
899 int err;
900
901 q->num = q_num;
902 if (q_ops->pre_init)
903 q_ops->pre_init(mlxsw_pci, q);
904
905 spin_lock_init(&q->lock);
906 q->count = q_ops->elem_count_f ? q_ops->elem_count_f(q) :
907 q_ops->elem_count;
908 q->elem_size = q_ops->elem_size_f ? q_ops->elem_size_f(q) :
909 q_ops->elem_size;
910 q->type = q_ops->type;
911 q->pci = mlxsw_pci;
912
913 if (q_ops->tasklet)
914 tasklet_setup(&q->tasklet, q_ops->tasklet);
915
916 mem_item->size = MLXSW_PCI_AQ_SIZE;
917 mem_item->buf = dma_alloc_coherent(&mlxsw_pci->pdev->dev,
918 mem_item->size, &mem_item->mapaddr,
919 GFP_KERNEL);
920 if (!mem_item->buf)
921 return -ENOMEM;
922
923 q->elem_info = kcalloc(q->count, sizeof(*q->elem_info), GFP_KERNEL);
924 if (!q->elem_info) {
925 err = -ENOMEM;
926 goto err_elem_info_alloc;
927 }
928
929
930
931
932 for (i = 0; i < q->count; i++) {
933 struct mlxsw_pci_queue_elem_info *elem_info;
934
935 elem_info = mlxsw_pci_queue_elem_info_get(q, i);
936 elem_info->elem =
937 __mlxsw_pci_queue_elem_get(q, q->elem_size, i);
938 }
939
940 mlxsw_cmd_mbox_zero(mbox);
941 err = q_ops->init(mlxsw_pci, mbox, q);
942 if (err)
943 goto err_q_ops_init;
944 return 0;
945
946err_q_ops_init:
947 kfree(q->elem_info);
948err_elem_info_alloc:
949 dma_free_coherent(&mlxsw_pci->pdev->dev, mem_item->size,
950 mem_item->buf, mem_item->mapaddr);
951 return err;
952}
953
954static void mlxsw_pci_queue_fini(struct mlxsw_pci *mlxsw_pci,
955 const struct mlxsw_pci_queue_ops *q_ops,
956 struct mlxsw_pci_queue *q)
957{
958 struct mlxsw_pci_mem_item *mem_item = &q->mem_item;
959
960 q_ops->fini(mlxsw_pci, q);
961 kfree(q->elem_info);
962 dma_free_coherent(&mlxsw_pci->pdev->dev, mem_item->size,
963 mem_item->buf, mem_item->mapaddr);
964}
965
966static int mlxsw_pci_queue_group_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
967 const struct mlxsw_pci_queue_ops *q_ops,
968 u8 num_qs)
969{
970 struct mlxsw_pci_queue_type_group *queue_group;
971 int i;
972 int err;
973
974 queue_group = mlxsw_pci_queue_type_group_get(mlxsw_pci, q_ops->type);
975 queue_group->q = kcalloc(num_qs, sizeof(*queue_group->q), GFP_KERNEL);
976 if (!queue_group->q)
977 return -ENOMEM;
978
979 for (i = 0; i < num_qs; i++) {
980 err = mlxsw_pci_queue_init(mlxsw_pci, mbox, q_ops,
981 &queue_group->q[i], i);
982 if (err)
983 goto err_queue_init;
984 }
985 queue_group->count = num_qs;
986
987 return 0;
988
989err_queue_init:
990 for (i--; i >= 0; i--)
991 mlxsw_pci_queue_fini(mlxsw_pci, q_ops, &queue_group->q[i]);
992 kfree(queue_group->q);
993 return err;
994}
995
996static void mlxsw_pci_queue_group_fini(struct mlxsw_pci *mlxsw_pci,
997 const struct mlxsw_pci_queue_ops *q_ops)
998{
999 struct mlxsw_pci_queue_type_group *queue_group;
1000 int i;
1001
1002 queue_group = mlxsw_pci_queue_type_group_get(mlxsw_pci, q_ops->type);
1003 for (i = 0; i < queue_group->count; i++)
1004 mlxsw_pci_queue_fini(mlxsw_pci, q_ops, &queue_group->q[i]);
1005 kfree(queue_group->q);
1006}
1007
1008static int mlxsw_pci_aqs_init(struct mlxsw_pci *mlxsw_pci, char *mbox)
1009{
1010 struct pci_dev *pdev = mlxsw_pci->pdev;
1011 u8 num_sdqs;
1012 u8 sdq_log2sz;
1013 u8 num_rdqs;
1014 u8 rdq_log2sz;
1015 u8 num_cqs;
1016 u8 cq_log2sz;
1017 u8 cqv2_log2sz;
1018 u8 num_eqs;
1019 u8 eq_log2sz;
1020 int err;
1021
1022 mlxsw_cmd_mbox_zero(mbox);
1023 err = mlxsw_cmd_query_aq_cap(mlxsw_pci->core, mbox);
1024 if (err)
1025 return err;
1026
1027 num_sdqs = mlxsw_cmd_mbox_query_aq_cap_max_num_sdqs_get(mbox);
1028 sdq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_sdq_sz_get(mbox);
1029 num_rdqs = mlxsw_cmd_mbox_query_aq_cap_max_num_rdqs_get(mbox);
1030 rdq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_rdq_sz_get(mbox);
1031 num_cqs = mlxsw_cmd_mbox_query_aq_cap_max_num_cqs_get(mbox);
1032 cq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_cq_sz_get(mbox);
1033 cqv2_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_cqv2_sz_get(mbox);
1034 num_eqs = mlxsw_cmd_mbox_query_aq_cap_max_num_eqs_get(mbox);
1035 eq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_eq_sz_get(mbox);
1036
1037 if (num_sdqs + num_rdqs > num_cqs ||
1038 num_sdqs < MLXSW_PCI_SDQS_MIN ||
1039 num_cqs > MLXSW_PCI_CQS_MAX || num_eqs != MLXSW_PCI_EQS_COUNT) {
1040 dev_err(&pdev->dev, "Unsupported number of queues\n");
1041 return -EINVAL;
1042 }
1043
1044 if ((1 << sdq_log2sz != MLXSW_PCI_WQE_COUNT) ||
1045 (1 << rdq_log2sz != MLXSW_PCI_WQE_COUNT) ||
1046 (1 << cq_log2sz != MLXSW_PCI_CQE01_COUNT) ||
1047 (mlxsw_pci->max_cqe_ver == MLXSW_PCI_CQE_V2 &&
1048 (1 << cqv2_log2sz != MLXSW_PCI_CQE2_COUNT)) ||
1049 (1 << eq_log2sz != MLXSW_PCI_EQE_COUNT)) {
1050 dev_err(&pdev->dev, "Unsupported number of async queue descriptors\n");
1051 return -EINVAL;
1052 }
1053
1054 mlxsw_pci->num_sdq_cqs = num_sdqs;
1055
1056 err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_eq_ops,
1057 num_eqs);
1058 if (err) {
1059 dev_err(&pdev->dev, "Failed to initialize event queues\n");
1060 return err;
1061 }
1062
1063 err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_cq_ops,
1064 num_cqs);
1065 if (err) {
1066 dev_err(&pdev->dev, "Failed to initialize completion queues\n");
1067 goto err_cqs_init;
1068 }
1069
1070 err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_sdq_ops,
1071 num_sdqs);
1072 if (err) {
1073 dev_err(&pdev->dev, "Failed to initialize send descriptor queues\n");
1074 goto err_sdqs_init;
1075 }
1076
1077 err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_rdq_ops,
1078 num_rdqs);
1079 if (err) {
1080 dev_err(&pdev->dev, "Failed to initialize receive descriptor queues\n");
1081 goto err_rdqs_init;
1082 }
1083
1084
1085 mlxsw_pci->cmd.nopoll = true;
1086 return 0;
1087
1088err_rdqs_init:
1089 mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_sdq_ops);
1090err_sdqs_init:
1091 mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_cq_ops);
1092err_cqs_init:
1093 mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_eq_ops);
1094 return err;
1095}
1096
1097static void mlxsw_pci_aqs_fini(struct mlxsw_pci *mlxsw_pci)
1098{
1099 mlxsw_pci->cmd.nopoll = false;
1100 mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_rdq_ops);
1101 mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_sdq_ops);
1102 mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_cq_ops);
1103 mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_eq_ops);
1104}
1105
1106static void
1107mlxsw_pci_config_profile_swid_config(struct mlxsw_pci *mlxsw_pci,
1108 char *mbox, int index,
1109 const struct mlxsw_swid_config *swid)
1110{
1111 u8 mask = 0;
1112
1113 if (swid->used_type) {
1114 mlxsw_cmd_mbox_config_profile_swid_config_type_set(
1115 mbox, index, swid->type);
1116 mask |= 1;
1117 }
1118 if (swid->used_properties) {
1119 mlxsw_cmd_mbox_config_profile_swid_config_properties_set(
1120 mbox, index, swid->properties);
1121 mask |= 2;
1122 }
1123 mlxsw_cmd_mbox_config_profile_swid_config_mask_set(mbox, index, mask);
1124}
1125
1126static int
1127mlxsw_pci_profile_get_kvd_sizes(const struct mlxsw_pci *mlxsw_pci,
1128 const struct mlxsw_config_profile *profile,
1129 struct mlxsw_res *res)
1130{
1131 u64 single_size, double_size, linear_size;
1132 int err;
1133
1134 err = mlxsw_core_kvd_sizes_get(mlxsw_pci->core, profile,
1135 &single_size, &double_size,
1136 &linear_size);
1137 if (err)
1138 return err;
1139
1140 MLXSW_RES_SET(res, KVD_SINGLE_SIZE, single_size);
1141 MLXSW_RES_SET(res, KVD_DOUBLE_SIZE, double_size);
1142 MLXSW_RES_SET(res, KVD_LINEAR_SIZE, linear_size);
1143
1144 return 0;
1145}
1146
1147static int mlxsw_pci_config_profile(struct mlxsw_pci *mlxsw_pci, char *mbox,
1148 const struct mlxsw_config_profile *profile,
1149 struct mlxsw_res *res)
1150{
1151 int i;
1152 int err;
1153
1154 mlxsw_cmd_mbox_zero(mbox);
1155
1156 if (profile->used_max_vepa_channels) {
1157 mlxsw_cmd_mbox_config_profile_set_max_vepa_channels_set(
1158 mbox, 1);
1159 mlxsw_cmd_mbox_config_profile_max_vepa_channels_set(
1160 mbox, profile->max_vepa_channels);
1161 }
1162 if (profile->used_max_mid) {
1163 mlxsw_cmd_mbox_config_profile_set_max_mid_set(
1164 mbox, 1);
1165 mlxsw_cmd_mbox_config_profile_max_mid_set(
1166 mbox, profile->max_mid);
1167 }
1168 if (profile->used_max_pgt) {
1169 mlxsw_cmd_mbox_config_profile_set_max_pgt_set(
1170 mbox, 1);
1171 mlxsw_cmd_mbox_config_profile_max_pgt_set(
1172 mbox, profile->max_pgt);
1173 }
1174 if (profile->used_max_system_port) {
1175 mlxsw_cmd_mbox_config_profile_set_max_system_port_set(
1176 mbox, 1);
1177 mlxsw_cmd_mbox_config_profile_max_system_port_set(
1178 mbox, profile->max_system_port);
1179 }
1180 if (profile->used_max_vlan_groups) {
1181 mlxsw_cmd_mbox_config_profile_set_max_vlan_groups_set(
1182 mbox, 1);
1183 mlxsw_cmd_mbox_config_profile_max_vlan_groups_set(
1184 mbox, profile->max_vlan_groups);
1185 }
1186 if (profile->used_max_regions) {
1187 mlxsw_cmd_mbox_config_profile_set_max_regions_set(
1188 mbox, 1);
1189 mlxsw_cmd_mbox_config_profile_max_regions_set(
1190 mbox, profile->max_regions);
1191 }
1192 if (profile->used_flood_tables) {
1193 mlxsw_cmd_mbox_config_profile_set_flood_tables_set(
1194 mbox, 1);
1195 mlxsw_cmd_mbox_config_profile_max_flood_tables_set(
1196 mbox, profile->max_flood_tables);
1197 mlxsw_cmd_mbox_config_profile_max_vid_flood_tables_set(
1198 mbox, profile->max_vid_flood_tables);
1199 mlxsw_cmd_mbox_config_profile_max_fid_offset_flood_tables_set(
1200 mbox, profile->max_fid_offset_flood_tables);
1201 mlxsw_cmd_mbox_config_profile_fid_offset_flood_table_size_set(
1202 mbox, profile->fid_offset_flood_table_size);
1203 mlxsw_cmd_mbox_config_profile_max_fid_flood_tables_set(
1204 mbox, profile->max_fid_flood_tables);
1205 mlxsw_cmd_mbox_config_profile_fid_flood_table_size_set(
1206 mbox, profile->fid_flood_table_size);
1207 }
1208 if (profile->used_flood_mode) {
1209 mlxsw_cmd_mbox_config_profile_set_flood_mode_set(
1210 mbox, 1);
1211 mlxsw_cmd_mbox_config_profile_flood_mode_set(
1212 mbox, profile->flood_mode);
1213 }
1214 if (profile->used_max_ib_mc) {
1215 mlxsw_cmd_mbox_config_profile_set_max_ib_mc_set(
1216 mbox, 1);
1217 mlxsw_cmd_mbox_config_profile_max_ib_mc_set(
1218 mbox, profile->max_ib_mc);
1219 }
1220 if (profile->used_max_pkey) {
1221 mlxsw_cmd_mbox_config_profile_set_max_pkey_set(
1222 mbox, 1);
1223 mlxsw_cmd_mbox_config_profile_max_pkey_set(
1224 mbox, profile->max_pkey);
1225 }
1226 if (profile->used_ar_sec) {
1227 mlxsw_cmd_mbox_config_profile_set_ar_sec_set(
1228 mbox, 1);
1229 mlxsw_cmd_mbox_config_profile_ar_sec_set(
1230 mbox, profile->ar_sec);
1231 }
1232 if (profile->used_adaptive_routing_group_cap) {
1233 mlxsw_cmd_mbox_config_profile_set_adaptive_routing_group_cap_set(
1234 mbox, 1);
1235 mlxsw_cmd_mbox_config_profile_adaptive_routing_group_cap_set(
1236 mbox, profile->adaptive_routing_group_cap);
1237 }
1238 if (profile->used_kvd_sizes && MLXSW_RES_VALID(res, KVD_SIZE)) {
1239 err = mlxsw_pci_profile_get_kvd_sizes(mlxsw_pci, profile, res);
1240 if (err)
1241 return err;
1242
1243 mlxsw_cmd_mbox_config_profile_set_kvd_linear_size_set(mbox, 1);
1244 mlxsw_cmd_mbox_config_profile_kvd_linear_size_set(mbox,
1245 MLXSW_RES_GET(res, KVD_LINEAR_SIZE));
1246 mlxsw_cmd_mbox_config_profile_set_kvd_hash_single_size_set(mbox,
1247 1);
1248 mlxsw_cmd_mbox_config_profile_kvd_hash_single_size_set(mbox,
1249 MLXSW_RES_GET(res, KVD_SINGLE_SIZE));
1250 mlxsw_cmd_mbox_config_profile_set_kvd_hash_double_size_set(
1251 mbox, 1);
1252 mlxsw_cmd_mbox_config_profile_kvd_hash_double_size_set(mbox,
1253 MLXSW_RES_GET(res, KVD_DOUBLE_SIZE));
1254 }
1255 if (profile->used_kvh_xlt_cache_mode) {
1256 mlxsw_cmd_mbox_config_profile_set_kvh_xlt_cache_mode_set(
1257 mbox, 1);
1258 mlxsw_cmd_mbox_config_profile_kvh_xlt_cache_mode_set(
1259 mbox, profile->kvh_xlt_cache_mode);
1260 }
1261
1262 for (i = 0; i < MLXSW_CONFIG_PROFILE_SWID_COUNT; i++)
1263 mlxsw_pci_config_profile_swid_config(mlxsw_pci, mbox, i,
1264 &profile->swid_config[i]);
1265
1266 if (mlxsw_pci->max_cqe_ver > MLXSW_PCI_CQE_V0) {
1267 mlxsw_cmd_mbox_config_profile_set_cqe_version_set(mbox, 1);
1268 mlxsw_cmd_mbox_config_profile_cqe_version_set(mbox, 1);
1269 }
1270
1271 return mlxsw_cmd_config_profile_set(mlxsw_pci->core, mbox);
1272}
1273
1274static int mlxsw_pci_boardinfo_xm_process(struct mlxsw_pci *mlxsw_pci,
1275 struct mlxsw_bus_info *bus_info,
1276 char *mbox)
1277{
1278 int count = mlxsw_cmd_mbox_boardinfo_xm_num_local_ports_get(mbox);
1279 int i;
1280
1281 if (!mlxsw_cmd_mbox_boardinfo_xm_exists_get(mbox))
1282 return 0;
1283
1284 bus_info->xm_exists = true;
1285
1286 if (count > MLXSW_BUS_INFO_XM_LOCAL_PORTS_MAX) {
1287 dev_err(&mlxsw_pci->pdev->dev, "Invalid number of XM local ports\n");
1288 return -EINVAL;
1289 }
1290 bus_info->xm_local_ports_count = count;
1291 for (i = 0; i < count; i++)
1292 bus_info->xm_local_ports[i] =
1293 mlxsw_cmd_mbox_boardinfo_xm_local_port_entry_get(mbox,
1294 i);
1295 return 0;
1296}
1297
1298static int mlxsw_pci_boardinfo(struct mlxsw_pci *mlxsw_pci, char *mbox)
1299{
1300 struct mlxsw_bus_info *bus_info = &mlxsw_pci->bus_info;
1301 int err;
1302
1303 mlxsw_cmd_mbox_zero(mbox);
1304 err = mlxsw_cmd_boardinfo(mlxsw_pci->core, mbox);
1305 if (err)
1306 return err;
1307 mlxsw_cmd_mbox_boardinfo_vsd_memcpy_from(mbox, bus_info->vsd);
1308 mlxsw_cmd_mbox_boardinfo_psid_memcpy_from(mbox, bus_info->psid);
1309
1310 return mlxsw_pci_boardinfo_xm_process(mlxsw_pci, bus_info, mbox);
1311}
1312
1313static int mlxsw_pci_fw_area_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
1314 u16 num_pages)
1315{
1316 struct mlxsw_pci_mem_item *mem_item;
1317 int nent = 0;
1318 int i;
1319 int err;
1320
1321 mlxsw_pci->fw_area.items = kcalloc(num_pages, sizeof(*mem_item),
1322 GFP_KERNEL);
1323 if (!mlxsw_pci->fw_area.items)
1324 return -ENOMEM;
1325 mlxsw_pci->fw_area.count = num_pages;
1326
1327 mlxsw_cmd_mbox_zero(mbox);
1328 for (i = 0; i < num_pages; i++) {
1329 mem_item = &mlxsw_pci->fw_area.items[i];
1330
1331 mem_item->size = MLXSW_PCI_PAGE_SIZE;
1332 mem_item->buf = dma_alloc_coherent(&mlxsw_pci->pdev->dev,
1333 mem_item->size,
1334 &mem_item->mapaddr, GFP_KERNEL);
1335 if (!mem_item->buf) {
1336 err = -ENOMEM;
1337 goto err_alloc;
1338 }
1339 mlxsw_cmd_mbox_map_fa_pa_set(mbox, nent, mem_item->mapaddr);
1340 mlxsw_cmd_mbox_map_fa_log2size_set(mbox, nent, 0);
1341 if (++nent == MLXSW_CMD_MAP_FA_VPM_ENTRIES_MAX) {
1342 err = mlxsw_cmd_map_fa(mlxsw_pci->core, mbox, nent);
1343 if (err)
1344 goto err_cmd_map_fa;
1345 nent = 0;
1346 mlxsw_cmd_mbox_zero(mbox);
1347 }
1348 }
1349
1350 if (nent) {
1351 err = mlxsw_cmd_map_fa(mlxsw_pci->core, mbox, nent);
1352 if (err)
1353 goto err_cmd_map_fa;
1354 }
1355
1356 return 0;
1357
1358err_cmd_map_fa:
1359err_alloc:
1360 for (i--; i >= 0; i--) {
1361 mem_item = &mlxsw_pci->fw_area.items[i];
1362
1363 dma_free_coherent(&mlxsw_pci->pdev->dev, mem_item->size,
1364 mem_item->buf, mem_item->mapaddr);
1365 }
1366 kfree(mlxsw_pci->fw_area.items);
1367 return err;
1368}
1369
1370static void mlxsw_pci_fw_area_fini(struct mlxsw_pci *mlxsw_pci)
1371{
1372 struct mlxsw_pci_mem_item *mem_item;
1373 int i;
1374
1375 mlxsw_cmd_unmap_fa(mlxsw_pci->core);
1376
1377 for (i = 0; i < mlxsw_pci->fw_area.count; i++) {
1378 mem_item = &mlxsw_pci->fw_area.items[i];
1379
1380 dma_free_coherent(&mlxsw_pci->pdev->dev, mem_item->size,
1381 mem_item->buf, mem_item->mapaddr);
1382 }
1383 kfree(mlxsw_pci->fw_area.items);
1384}
1385
1386static irqreturn_t mlxsw_pci_eq_irq_handler(int irq, void *dev_id)
1387{
1388 struct mlxsw_pci *mlxsw_pci = dev_id;
1389 struct mlxsw_pci_queue *q;
1390 int i;
1391
1392 for (i = 0; i < MLXSW_PCI_EQS_COUNT; i++) {
1393 q = mlxsw_pci_eq_get(mlxsw_pci, i);
1394 mlxsw_pci_queue_tasklet_schedule(q);
1395 }
1396 return IRQ_HANDLED;
1397}
1398
1399static int mlxsw_pci_mbox_alloc(struct mlxsw_pci *mlxsw_pci,
1400 struct mlxsw_pci_mem_item *mbox)
1401{
1402 struct pci_dev *pdev = mlxsw_pci->pdev;
1403 int err = 0;
1404
1405 mbox->size = MLXSW_CMD_MBOX_SIZE;
1406 mbox->buf = dma_alloc_coherent(&pdev->dev, MLXSW_CMD_MBOX_SIZE,
1407 &mbox->mapaddr, GFP_KERNEL);
1408 if (!mbox->buf) {
1409 dev_err(&pdev->dev, "Failed allocating memory for mailbox\n");
1410 err = -ENOMEM;
1411 }
1412
1413 return err;
1414}
1415
1416static void mlxsw_pci_mbox_free(struct mlxsw_pci *mlxsw_pci,
1417 struct mlxsw_pci_mem_item *mbox)
1418{
1419 struct pci_dev *pdev = mlxsw_pci->pdev;
1420
1421 dma_free_coherent(&pdev->dev, MLXSW_CMD_MBOX_SIZE, mbox->buf,
1422 mbox->mapaddr);
1423}
1424
1425static int mlxsw_pci_sys_ready_wait(struct mlxsw_pci *mlxsw_pci,
1426 const struct pci_device_id *id,
1427 u32 *p_sys_status)
1428{
1429 unsigned long end;
1430 u32 val;
1431
1432
1433 msleep(MLXSW_PCI_SW_RESET_WAIT_MSECS);
1434
1435 end = jiffies + msecs_to_jiffies(MLXSW_PCI_SW_RESET_TIMEOUT_MSECS);
1436 do {
1437 val = mlxsw_pci_read32(mlxsw_pci, FW_READY);
1438 if ((val & MLXSW_PCI_FW_READY_MASK) == MLXSW_PCI_FW_READY_MAGIC)
1439 return 0;
1440 cond_resched();
1441 } while (time_before(jiffies, end));
1442
1443 *p_sys_status = val & MLXSW_PCI_FW_READY_MASK;
1444
1445 return -EBUSY;
1446}
1447
1448static int mlxsw_pci_sw_reset(struct mlxsw_pci *mlxsw_pci,
1449 const struct pci_device_id *id)
1450{
1451 struct pci_dev *pdev = mlxsw_pci->pdev;
1452 char mrsr_pl[MLXSW_REG_MRSR_LEN];
1453 u32 sys_status;
1454 int err;
1455
1456 err = mlxsw_pci_sys_ready_wait(mlxsw_pci, id, &sys_status);
1457 if (err) {
1458 dev_err(&pdev->dev, "Failed to reach system ready status before reset. Status is 0x%x\n",
1459 sys_status);
1460 return err;
1461 }
1462
1463 mlxsw_reg_mrsr_pack(mrsr_pl);
1464 err = mlxsw_reg_write(mlxsw_pci->core, MLXSW_REG(mrsr), mrsr_pl);
1465 if (err)
1466 return err;
1467
1468 err = mlxsw_pci_sys_ready_wait(mlxsw_pci, id, &sys_status);
1469 if (err) {
1470 dev_err(&pdev->dev, "Failed to reach system ready status after reset. Status is 0x%x\n",
1471 sys_status);
1472 return err;
1473 }
1474
1475 return 0;
1476}
1477
1478static int mlxsw_pci_alloc_irq_vectors(struct mlxsw_pci *mlxsw_pci)
1479{
1480 int err;
1481
1482 err = pci_alloc_irq_vectors(mlxsw_pci->pdev, 1, 1, PCI_IRQ_MSIX);
1483 if (err < 0)
1484 dev_err(&mlxsw_pci->pdev->dev, "MSI-X init failed\n");
1485 return err;
1486}
1487
1488static void mlxsw_pci_free_irq_vectors(struct mlxsw_pci *mlxsw_pci)
1489{
1490 pci_free_irq_vectors(mlxsw_pci->pdev);
1491}
1492
1493static int mlxsw_pci_init(void *bus_priv, struct mlxsw_core *mlxsw_core,
1494 const struct mlxsw_config_profile *profile,
1495 struct mlxsw_res *res)
1496{
1497 struct mlxsw_pci *mlxsw_pci = bus_priv;
1498 struct pci_dev *pdev = mlxsw_pci->pdev;
1499 char *mbox;
1500 u16 num_pages;
1501 int err;
1502
1503 mlxsw_pci->core = mlxsw_core;
1504
1505 mbox = mlxsw_cmd_mbox_alloc();
1506 if (!mbox)
1507 return -ENOMEM;
1508
1509 err = mlxsw_pci_sw_reset(mlxsw_pci, mlxsw_pci->id);
1510 if (err)
1511 goto err_sw_reset;
1512
1513 err = mlxsw_pci_alloc_irq_vectors(mlxsw_pci);
1514 if (err < 0) {
1515 dev_err(&pdev->dev, "MSI-X init failed\n");
1516 goto err_alloc_irq;
1517 }
1518
1519 err = mlxsw_cmd_query_fw(mlxsw_core, mbox);
1520 if (err)
1521 goto err_query_fw;
1522
1523 mlxsw_pci->bus_info.fw_rev.major =
1524 mlxsw_cmd_mbox_query_fw_fw_rev_major_get(mbox);
1525 mlxsw_pci->bus_info.fw_rev.minor =
1526 mlxsw_cmd_mbox_query_fw_fw_rev_minor_get(mbox);
1527 mlxsw_pci->bus_info.fw_rev.subminor =
1528 mlxsw_cmd_mbox_query_fw_fw_rev_subminor_get(mbox);
1529
1530 if (mlxsw_cmd_mbox_query_fw_cmd_interface_rev_get(mbox) != 1) {
1531 dev_err(&pdev->dev, "Unsupported cmd interface revision ID queried from hw\n");
1532 err = -EINVAL;
1533 goto err_iface_rev;
1534 }
1535 if (mlxsw_cmd_mbox_query_fw_doorbell_page_bar_get(mbox) != 0) {
1536 dev_err(&pdev->dev, "Unsupported doorbell page bar queried from hw\n");
1537 err = -EINVAL;
1538 goto err_doorbell_page_bar;
1539 }
1540
1541 mlxsw_pci->doorbell_offset =
1542 mlxsw_cmd_mbox_query_fw_doorbell_page_offset_get(mbox);
1543
1544 if (mlxsw_cmd_mbox_query_fw_fr_rn_clk_bar_get(mbox) != 0) {
1545 dev_err(&pdev->dev, "Unsupported free running clock BAR queried from hw\n");
1546 err = -EINVAL;
1547 goto err_fr_rn_clk_bar;
1548 }
1549
1550 mlxsw_pci->free_running_clock_offset =
1551 mlxsw_cmd_mbox_query_fw_free_running_clock_offset_get(mbox);
1552
1553 num_pages = mlxsw_cmd_mbox_query_fw_fw_pages_get(mbox);
1554 err = mlxsw_pci_fw_area_init(mlxsw_pci, mbox, num_pages);
1555 if (err)
1556 goto err_fw_area_init;
1557
1558 err = mlxsw_pci_boardinfo(mlxsw_pci, mbox);
1559 if (err)
1560 goto err_boardinfo;
1561
1562 err = mlxsw_core_resources_query(mlxsw_core, mbox, res);
1563 if (err)
1564 goto err_query_resources;
1565
1566 if (MLXSW_CORE_RES_VALID(mlxsw_core, CQE_V2) &&
1567 MLXSW_CORE_RES_GET(mlxsw_core, CQE_V2))
1568 mlxsw_pci->max_cqe_ver = MLXSW_PCI_CQE_V2;
1569 else if (MLXSW_CORE_RES_VALID(mlxsw_core, CQE_V1) &&
1570 MLXSW_CORE_RES_GET(mlxsw_core, CQE_V1))
1571 mlxsw_pci->max_cqe_ver = MLXSW_PCI_CQE_V1;
1572 else if ((MLXSW_CORE_RES_VALID(mlxsw_core, CQE_V0) &&
1573 MLXSW_CORE_RES_GET(mlxsw_core, CQE_V0)) ||
1574 !MLXSW_CORE_RES_VALID(mlxsw_core, CQE_V0)) {
1575 mlxsw_pci->max_cqe_ver = MLXSW_PCI_CQE_V0;
1576 } else {
1577 dev_err(&pdev->dev, "Invalid supported CQE version combination reported\n");
1578 goto err_cqe_v_check;
1579 }
1580
1581 err = mlxsw_pci_config_profile(mlxsw_pci, mbox, profile, res);
1582 if (err)
1583 goto err_config_profile;
1584
1585 err = mlxsw_pci_aqs_init(mlxsw_pci, mbox);
1586 if (err)
1587 goto err_aqs_init;
1588
1589 err = request_irq(pci_irq_vector(pdev, 0),
1590 mlxsw_pci_eq_irq_handler, 0,
1591 mlxsw_pci->bus_info.device_kind, mlxsw_pci);
1592 if (err) {
1593 dev_err(&pdev->dev, "IRQ request failed\n");
1594 goto err_request_eq_irq;
1595 }
1596
1597 goto mbox_put;
1598
1599err_request_eq_irq:
1600 mlxsw_pci_aqs_fini(mlxsw_pci);
1601err_aqs_init:
1602err_config_profile:
1603err_cqe_v_check:
1604err_query_resources:
1605err_boardinfo:
1606 mlxsw_pci_fw_area_fini(mlxsw_pci);
1607err_fw_area_init:
1608err_fr_rn_clk_bar:
1609err_doorbell_page_bar:
1610err_iface_rev:
1611err_query_fw:
1612 mlxsw_pci_free_irq_vectors(mlxsw_pci);
1613err_alloc_irq:
1614err_sw_reset:
1615mbox_put:
1616 mlxsw_cmd_mbox_free(mbox);
1617 return err;
1618}
1619
1620static void mlxsw_pci_fini(void *bus_priv)
1621{
1622 struct mlxsw_pci *mlxsw_pci = bus_priv;
1623
1624 free_irq(pci_irq_vector(mlxsw_pci->pdev, 0), mlxsw_pci);
1625 mlxsw_pci_aqs_fini(mlxsw_pci);
1626 mlxsw_pci_fw_area_fini(mlxsw_pci);
1627 mlxsw_pci_free_irq_vectors(mlxsw_pci);
1628}
1629
1630static struct mlxsw_pci_queue *
1631mlxsw_pci_sdq_pick(struct mlxsw_pci *mlxsw_pci,
1632 const struct mlxsw_tx_info *tx_info)
1633{
1634 u8 ctl_sdq_count = mlxsw_pci_sdq_count(mlxsw_pci) - 1;
1635 u8 sdqn;
1636
1637 if (tx_info->is_emad) {
1638 sdqn = MLXSW_PCI_SDQ_EMAD_INDEX;
1639 } else {
1640 BUILD_BUG_ON(MLXSW_PCI_SDQ_EMAD_INDEX != 0);
1641 sdqn = 1 + (tx_info->local_port % ctl_sdq_count);
1642 }
1643
1644 return mlxsw_pci_sdq_get(mlxsw_pci, sdqn);
1645}
1646
1647static bool mlxsw_pci_skb_transmit_busy(void *bus_priv,
1648 const struct mlxsw_tx_info *tx_info)
1649{
1650 struct mlxsw_pci *mlxsw_pci = bus_priv;
1651 struct mlxsw_pci_queue *q = mlxsw_pci_sdq_pick(mlxsw_pci, tx_info);
1652
1653 return !mlxsw_pci_queue_elem_info_producer_get(q);
1654}
1655
1656static int mlxsw_pci_skb_transmit(void *bus_priv, struct sk_buff *skb,
1657 const struct mlxsw_tx_info *tx_info)
1658{
1659 struct mlxsw_pci *mlxsw_pci = bus_priv;
1660 struct mlxsw_pci_queue *q;
1661 struct mlxsw_pci_queue_elem_info *elem_info;
1662 char *wqe;
1663 int i;
1664 int err;
1665
1666 if (skb_shinfo(skb)->nr_frags > MLXSW_PCI_WQE_SG_ENTRIES - 1) {
1667 err = skb_linearize(skb);
1668 if (err)
1669 return err;
1670 }
1671
1672 q = mlxsw_pci_sdq_pick(mlxsw_pci, tx_info);
1673 spin_lock_bh(&q->lock);
1674 elem_info = mlxsw_pci_queue_elem_info_producer_get(q);
1675 if (!elem_info) {
1676
1677 err = -EAGAIN;
1678 goto unlock;
1679 }
1680 mlxsw_skb_cb(skb)->tx_info = *tx_info;
1681 elem_info->u.sdq.skb = skb;
1682
1683 wqe = elem_info->elem;
1684 mlxsw_pci_wqe_c_set(wqe, 1);
1685 mlxsw_pci_wqe_lp_set(wqe, 0);
1686 mlxsw_pci_wqe_type_set(wqe, MLXSW_PCI_WQE_TYPE_ETHERNET);
1687
1688 err = mlxsw_pci_wqe_frag_map(mlxsw_pci, wqe, 0, skb->data,
1689 skb_headlen(skb), DMA_TO_DEVICE);
1690 if (err)
1691 goto unlock;
1692
1693 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1694 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1695
1696 err = mlxsw_pci_wqe_frag_map(mlxsw_pci, wqe, i + 1,
1697 skb_frag_address(frag),
1698 skb_frag_size(frag),
1699 DMA_TO_DEVICE);
1700 if (err)
1701 goto unmap_frags;
1702 }
1703
1704 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP))
1705 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1706
1707
1708 for (i++; i < MLXSW_PCI_WQE_SG_ENTRIES; i++)
1709 mlxsw_pci_wqe_byte_count_set(wqe, i, 0);
1710
1711
1712 q->producer_counter++;
1713 mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q);
1714
1715 goto unlock;
1716
1717unmap_frags:
1718 for (; i >= 0; i--)
1719 mlxsw_pci_wqe_frag_unmap(mlxsw_pci, wqe, i, DMA_TO_DEVICE);
1720unlock:
1721 spin_unlock_bh(&q->lock);
1722 return err;
1723}
1724
1725static int mlxsw_pci_cmd_exec(void *bus_priv, u16 opcode, u8 opcode_mod,
1726 u32 in_mod, bool out_mbox_direct,
1727 char *in_mbox, size_t in_mbox_size,
1728 char *out_mbox, size_t out_mbox_size,
1729 u8 *p_status)
1730{
1731 struct mlxsw_pci *mlxsw_pci = bus_priv;
1732 dma_addr_t in_mapaddr = 0, out_mapaddr = 0;
1733 bool evreq = mlxsw_pci->cmd.nopoll;
1734 unsigned long timeout = msecs_to_jiffies(MLXSW_PCI_CIR_TIMEOUT_MSECS);
1735 bool *p_wait_done = &mlxsw_pci->cmd.wait_done;
1736 int err;
1737
1738 *p_status = MLXSW_CMD_STATUS_OK;
1739
1740 err = mutex_lock_interruptible(&mlxsw_pci->cmd.lock);
1741 if (err)
1742 return err;
1743
1744 if (in_mbox) {
1745 memcpy(mlxsw_pci->cmd.in_mbox.buf, in_mbox, in_mbox_size);
1746 in_mapaddr = mlxsw_pci->cmd.in_mbox.mapaddr;
1747 }
1748 mlxsw_pci_write32(mlxsw_pci, CIR_IN_PARAM_HI, upper_32_bits(in_mapaddr));
1749 mlxsw_pci_write32(mlxsw_pci, CIR_IN_PARAM_LO, lower_32_bits(in_mapaddr));
1750
1751 if (out_mbox)
1752 out_mapaddr = mlxsw_pci->cmd.out_mbox.mapaddr;
1753 mlxsw_pci_write32(mlxsw_pci, CIR_OUT_PARAM_HI, upper_32_bits(out_mapaddr));
1754 mlxsw_pci_write32(mlxsw_pci, CIR_OUT_PARAM_LO, lower_32_bits(out_mapaddr));
1755
1756 mlxsw_pci_write32(mlxsw_pci, CIR_IN_MODIFIER, in_mod);
1757 mlxsw_pci_write32(mlxsw_pci, CIR_TOKEN, 0);
1758
1759 *p_wait_done = false;
1760
1761 wmb();
1762 mlxsw_pci_write32(mlxsw_pci, CIR_CTRL,
1763 MLXSW_PCI_CIR_CTRL_GO_BIT |
1764 (evreq ? MLXSW_PCI_CIR_CTRL_EVREQ_BIT : 0) |
1765 (opcode_mod << MLXSW_PCI_CIR_CTRL_OPCODE_MOD_SHIFT) |
1766 opcode);
1767
1768 if (!evreq) {
1769 unsigned long end;
1770
1771 end = jiffies + timeout;
1772 do {
1773 u32 ctrl = mlxsw_pci_read32(mlxsw_pci, CIR_CTRL);
1774
1775 if (!(ctrl & MLXSW_PCI_CIR_CTRL_GO_BIT)) {
1776 *p_wait_done = true;
1777 *p_status = ctrl >> MLXSW_PCI_CIR_CTRL_STATUS_SHIFT;
1778 break;
1779 }
1780 cond_resched();
1781 } while (time_before(jiffies, end));
1782 } else {
1783 wait_event_timeout(mlxsw_pci->cmd.wait, *p_wait_done, timeout);
1784 *p_status = mlxsw_pci->cmd.comp.status;
1785 }
1786
1787 err = 0;
1788 if (*p_wait_done) {
1789 if (*p_status)
1790 err = -EIO;
1791 } else {
1792 err = -ETIMEDOUT;
1793 }
1794
1795 if (!err && out_mbox && out_mbox_direct) {
1796
1797
1798
1799
1800 __be32 tmp;
1801
1802 if (!evreq) {
1803 tmp = cpu_to_be32(mlxsw_pci_read32(mlxsw_pci,
1804 CIR_OUT_PARAM_HI));
1805 memcpy(out_mbox, &tmp, sizeof(tmp));
1806 tmp = cpu_to_be32(mlxsw_pci_read32(mlxsw_pci,
1807 CIR_OUT_PARAM_LO));
1808 memcpy(out_mbox + sizeof(tmp), &tmp, sizeof(tmp));
1809 }
1810 } else if (!err && out_mbox) {
1811 memcpy(out_mbox, mlxsw_pci->cmd.out_mbox.buf, out_mbox_size);
1812 }
1813
1814 mutex_unlock(&mlxsw_pci->cmd.lock);
1815
1816 return err;
1817}
1818
1819static u32 mlxsw_pci_read_frc_h(void *bus_priv)
1820{
1821 struct mlxsw_pci *mlxsw_pci = bus_priv;
1822 u64 frc_offset;
1823
1824 frc_offset = mlxsw_pci->free_running_clock_offset;
1825 return mlxsw_pci_read32(mlxsw_pci, FREE_RUNNING_CLOCK_H(frc_offset));
1826}
1827
1828static u32 mlxsw_pci_read_frc_l(void *bus_priv)
1829{
1830 struct mlxsw_pci *mlxsw_pci = bus_priv;
1831 u64 frc_offset;
1832
1833 frc_offset = mlxsw_pci->free_running_clock_offset;
1834 return mlxsw_pci_read32(mlxsw_pci, FREE_RUNNING_CLOCK_L(frc_offset));
1835}
1836
1837static const struct mlxsw_bus mlxsw_pci_bus = {
1838 .kind = "pci",
1839 .init = mlxsw_pci_init,
1840 .fini = mlxsw_pci_fini,
1841 .skb_transmit_busy = mlxsw_pci_skb_transmit_busy,
1842 .skb_transmit = mlxsw_pci_skb_transmit,
1843 .cmd_exec = mlxsw_pci_cmd_exec,
1844 .read_frc_h = mlxsw_pci_read_frc_h,
1845 .read_frc_l = mlxsw_pci_read_frc_l,
1846 .features = MLXSW_BUS_F_TXRX | MLXSW_BUS_F_RESET,
1847};
1848
1849static int mlxsw_pci_cmd_init(struct mlxsw_pci *mlxsw_pci)
1850{
1851 int err;
1852
1853 mutex_init(&mlxsw_pci->cmd.lock);
1854 init_waitqueue_head(&mlxsw_pci->cmd.wait);
1855
1856 err = mlxsw_pci_mbox_alloc(mlxsw_pci, &mlxsw_pci->cmd.in_mbox);
1857 if (err)
1858 goto err_in_mbox_alloc;
1859
1860 err = mlxsw_pci_mbox_alloc(mlxsw_pci, &mlxsw_pci->cmd.out_mbox);
1861 if (err)
1862 goto err_out_mbox_alloc;
1863
1864 return 0;
1865
1866err_out_mbox_alloc:
1867 mlxsw_pci_mbox_free(mlxsw_pci, &mlxsw_pci->cmd.in_mbox);
1868err_in_mbox_alloc:
1869 mutex_destroy(&mlxsw_pci->cmd.lock);
1870 return err;
1871}
1872
1873static void mlxsw_pci_cmd_fini(struct mlxsw_pci *mlxsw_pci)
1874{
1875 mlxsw_pci_mbox_free(mlxsw_pci, &mlxsw_pci->cmd.out_mbox);
1876 mlxsw_pci_mbox_free(mlxsw_pci, &mlxsw_pci->cmd.in_mbox);
1877 mutex_destroy(&mlxsw_pci->cmd.lock);
1878}
1879
1880static int mlxsw_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1881{
1882 const char *driver_name = dev_driver_string(&pdev->dev);
1883 struct mlxsw_pci *mlxsw_pci;
1884 int err;
1885
1886 mlxsw_pci = kzalloc(sizeof(*mlxsw_pci), GFP_KERNEL);
1887 if (!mlxsw_pci)
1888 return -ENOMEM;
1889
1890 err = pci_enable_device(pdev);
1891 if (err) {
1892 dev_err(&pdev->dev, "pci_enable_device failed\n");
1893 goto err_pci_enable_device;
1894 }
1895
1896 err = pci_request_regions(pdev, driver_name);
1897 if (err) {
1898 dev_err(&pdev->dev, "pci_request_regions failed\n");
1899 goto err_pci_request_regions;
1900 }
1901
1902 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
1903 if (err) {
1904 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
1905 if (err) {
1906 dev_err(&pdev->dev, "dma_set_mask failed\n");
1907 goto err_pci_set_dma_mask;
1908 }
1909 }
1910
1911 if (pci_resource_len(pdev, 0) < MLXSW_PCI_BAR0_SIZE) {
1912 dev_err(&pdev->dev, "invalid PCI region size\n");
1913 err = -EINVAL;
1914 goto err_pci_resource_len_check;
1915 }
1916
1917 mlxsw_pci->hw_addr = ioremap(pci_resource_start(pdev, 0),
1918 pci_resource_len(pdev, 0));
1919 if (!mlxsw_pci->hw_addr) {
1920 dev_err(&pdev->dev, "ioremap failed\n");
1921 err = -EIO;
1922 goto err_ioremap;
1923 }
1924 pci_set_master(pdev);
1925
1926 mlxsw_pci->pdev = pdev;
1927 pci_set_drvdata(pdev, mlxsw_pci);
1928
1929 err = mlxsw_pci_cmd_init(mlxsw_pci);
1930 if (err)
1931 goto err_pci_cmd_init;
1932
1933 mlxsw_pci->bus_info.device_kind = driver_name;
1934 mlxsw_pci->bus_info.device_name = pci_name(mlxsw_pci->pdev);
1935 mlxsw_pci->bus_info.dev = &pdev->dev;
1936 mlxsw_pci->bus_info.read_frc_capable = true;
1937 mlxsw_pci->id = id;
1938
1939 err = mlxsw_core_bus_device_register(&mlxsw_pci->bus_info,
1940 &mlxsw_pci_bus, mlxsw_pci, false,
1941 NULL, NULL);
1942 if (err) {
1943 dev_err(&pdev->dev, "cannot register bus device\n");
1944 goto err_bus_device_register;
1945 }
1946
1947 return 0;
1948
1949err_bus_device_register:
1950 mlxsw_pci_cmd_fini(mlxsw_pci);
1951err_pci_cmd_init:
1952 iounmap(mlxsw_pci->hw_addr);
1953err_ioremap:
1954err_pci_resource_len_check:
1955err_pci_set_dma_mask:
1956 pci_release_regions(pdev);
1957err_pci_request_regions:
1958 pci_disable_device(pdev);
1959err_pci_enable_device:
1960 kfree(mlxsw_pci);
1961 return err;
1962}
1963
1964static void mlxsw_pci_remove(struct pci_dev *pdev)
1965{
1966 struct mlxsw_pci *mlxsw_pci = pci_get_drvdata(pdev);
1967
1968 mlxsw_core_bus_device_unregister(mlxsw_pci->core, false);
1969 mlxsw_pci_cmd_fini(mlxsw_pci);
1970 iounmap(mlxsw_pci->hw_addr);
1971 pci_release_regions(mlxsw_pci->pdev);
1972 pci_disable_device(mlxsw_pci->pdev);
1973 kfree(mlxsw_pci);
1974}
1975
1976int mlxsw_pci_driver_register(struct pci_driver *pci_driver)
1977{
1978 pci_driver->probe = mlxsw_pci_probe;
1979 pci_driver->remove = mlxsw_pci_remove;
1980 pci_driver->shutdown = mlxsw_pci_remove;
1981 return pci_register_driver(pci_driver);
1982}
1983EXPORT_SYMBOL(mlxsw_pci_driver_register);
1984
1985void mlxsw_pci_driver_unregister(struct pci_driver *pci_driver)
1986{
1987 pci_unregister_driver(pci_driver);
1988}
1989EXPORT_SYMBOL(mlxsw_pci_driver_unregister);
1990
1991static int __init mlxsw_pci_module_init(void)
1992{
1993 return 0;
1994}
1995
1996static void __exit mlxsw_pci_module_exit(void)
1997{
1998}
1999
2000module_init(mlxsw_pci_module_init);
2001module_exit(mlxsw_pci_module_exit);
2002
2003MODULE_LICENSE("Dual BSD/GPL");
2004MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
2005MODULE_DESCRIPTION("Mellanox switch PCI interface driver");
2006