1
2
3
4#ifndef _MLXSW_REG_H
5#define _MLXSW_REG_H
6
7#include <linux/kernel.h>
8#include <linux/string.h>
9#include <linux/bitops.h>
10#include <linux/if_vlan.h>
11
12#include "item.h"
13#include "port.h"
14
15struct mlxsw_reg_info {
16 u16 id;
17 u16 len;
18 const char *name;
19};
20
21#define MLXSW_REG_DEFINE(_name, _id, _len) \
22static const struct mlxsw_reg_info mlxsw_reg_##_name = { \
23 .id = _id, \
24 .len = _len, \
25 .name = #_name, \
26}
27
28#define MLXSW_REG(type) (&mlxsw_reg_##type)
29#define MLXSW_REG_LEN(type) MLXSW_REG(type)->len
30#define MLXSW_REG_ZERO(type, payload) memset(payload, 0, MLXSW_REG(type)->len)
31
32
33
34
35
36#define MLXSW_REG_SGCR_ID 0x2000
37#define MLXSW_REG_SGCR_LEN 0x10
38
39MLXSW_REG_DEFINE(sgcr, MLXSW_REG_SGCR_ID, MLXSW_REG_SGCR_LEN);
40
41
42
43
44
45
46
47MLXSW_ITEM32(reg, sgcr, llb, 0x04, 0, 1);
48
49static inline void mlxsw_reg_sgcr_pack(char *payload, bool llb)
50{
51 MLXSW_REG_ZERO(sgcr, payload);
52 mlxsw_reg_sgcr_llb_set(payload, !!llb);
53}
54
55
56
57
58
59#define MLXSW_REG_SPAD_ID 0x2002
60#define MLXSW_REG_SPAD_LEN 0x10
61
62MLXSW_REG_DEFINE(spad, MLXSW_REG_SPAD_ID, MLXSW_REG_SPAD_LEN);
63
64
65
66
67
68
69
70MLXSW_ITEM_BUF(reg, spad, base_mac, 0x02, 6);
71
72
73
74
75
76#define MLXSW_REG_SSPR_ID 0x2008
77#define MLXSW_REG_SSPR_LEN 0x8
78
79MLXSW_REG_DEFINE(sspr, MLXSW_REG_SSPR_ID, MLXSW_REG_SSPR_LEN);
80
81
82
83
84
85
86
87
88
89
90
91MLXSW_ITEM32(reg, sspr, m, 0x00, 31, 1);
92
93
94
95
96
97
98MLXSW_ITEM32_LP(reg, sspr, 0x00, 16, 0x00, 12);
99
100
101
102
103
104
105
106MLXSW_ITEM32(reg, sspr, sub_port, 0x00, 8, 8);
107
108
109
110
111
112
113
114
115
116MLXSW_ITEM32(reg, sspr, system_port, 0x04, 0, 16);
117
118static inline void mlxsw_reg_sspr_pack(char *payload, u16 local_port)
119{
120 MLXSW_REG_ZERO(sspr, payload);
121 mlxsw_reg_sspr_m_set(payload, 1);
122 mlxsw_reg_sspr_local_port_set(payload, local_port);
123 mlxsw_reg_sspr_sub_port_set(payload, 0);
124 mlxsw_reg_sspr_system_port_set(payload, local_port);
125}
126
127
128
129
130
131
132#define MLXSW_REG_SFDAT_ID 0x2009
133#define MLXSW_REG_SFDAT_LEN 0x8
134
135MLXSW_REG_DEFINE(sfdat, MLXSW_REG_SFDAT_ID, MLXSW_REG_SFDAT_LEN);
136
137
138
139
140
141MLXSW_ITEM32(reg, sfdat, swid, 0x00, 24, 8);
142
143
144
145
146
147
148
149
150MLXSW_ITEM32(reg, sfdat, age_time, 0x04, 0, 20);
151
152static inline void mlxsw_reg_sfdat_pack(char *payload, u32 age_time)
153{
154 MLXSW_REG_ZERO(sfdat, payload);
155 mlxsw_reg_sfdat_swid_set(payload, 0);
156 mlxsw_reg_sfdat_age_time_set(payload, age_time);
157}
158
159
160
161
162
163
164
165
166#define MLXSW_REG_SFD_ID 0x200A
167#define MLXSW_REG_SFD_BASE_LEN 0x10
168#define MLXSW_REG_SFD_REC_LEN 0x10
169#define MLXSW_REG_SFD_REC_MAX_COUNT 64
170#define MLXSW_REG_SFD_LEN (MLXSW_REG_SFD_BASE_LEN + \
171 MLXSW_REG_SFD_REC_LEN * MLXSW_REG_SFD_REC_MAX_COUNT)
172
173MLXSW_REG_DEFINE(sfd, MLXSW_REG_SFD_ID, MLXSW_REG_SFD_LEN);
174
175
176
177
178
179MLXSW_ITEM32(reg, sfd, swid, 0x00, 24, 8);
180
181enum mlxsw_reg_sfd_op {
182
183 MLXSW_REG_SFD_OP_QUERY_DUMP = 0,
184
185 MLXSW_REG_SFD_OP_QUERY_QUERY = 1,
186
187 MLXSW_REG_SFD_OP_QUERY_QUERY_AND_CLEAR_ACTIVITY = 2,
188
189
190
191 MLXSW_REG_SFD_OP_WRITE_TEST = 0,
192
193
194
195
196 MLXSW_REG_SFD_OP_WRITE_EDIT = 1,
197
198
199
200
201
202 MLXSW_REG_SFD_OP_WRITE_REMOVE = 2,
203
204
205
206 MLXSW_REG_SFD_OP_WRITE_REMOVE_NOTIFICATION = 2,
207};
208
209
210
211
212
213MLXSW_ITEM32(reg, sfd, op, 0x04, 30, 2);
214
215
216
217
218
219
220
221
222MLXSW_ITEM32(reg, sfd, record_locator, 0x04, 0, 30);
223
224
225
226
227
228
229
230
231MLXSW_ITEM32(reg, sfd, num_rec, 0x08, 0, 8);
232
233static inline void mlxsw_reg_sfd_pack(char *payload, enum mlxsw_reg_sfd_op op,
234 u32 record_locator)
235{
236 MLXSW_REG_ZERO(sfd, payload);
237 mlxsw_reg_sfd_op_set(payload, op);
238 mlxsw_reg_sfd_record_locator_set(payload, record_locator);
239}
240
241
242
243
244
245MLXSW_ITEM32_INDEXED(reg, sfd, rec_swid, MLXSW_REG_SFD_BASE_LEN, 24, 8,
246 MLXSW_REG_SFD_REC_LEN, 0x00, false);
247
248enum mlxsw_reg_sfd_rec_type {
249 MLXSW_REG_SFD_REC_TYPE_UNICAST = 0x0,
250 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG = 0x1,
251 MLXSW_REG_SFD_REC_TYPE_MULTICAST = 0x2,
252 MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL = 0xC,
253};
254
255
256
257
258
259MLXSW_ITEM32_INDEXED(reg, sfd, rec_type, MLXSW_REG_SFD_BASE_LEN, 20, 4,
260 MLXSW_REG_SFD_REC_LEN, 0x00, false);
261
262enum mlxsw_reg_sfd_rec_policy {
263
264 MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY = 0,
265
266
267
268 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_MLAG = 1,
269
270 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_INGRESS = 3,
271};
272
273
274
275
276
277MLXSW_ITEM32_INDEXED(reg, sfd, rec_policy, MLXSW_REG_SFD_BASE_LEN, 18, 2,
278 MLXSW_REG_SFD_REC_LEN, 0x00, false);
279
280
281
282
283
284
285
286MLXSW_ITEM32_INDEXED(reg, sfd, rec_a, MLXSW_REG_SFD_BASE_LEN, 16, 1,
287 MLXSW_REG_SFD_REC_LEN, 0x00, false);
288
289
290
291
292
293MLXSW_ITEM_BUF_INDEXED(reg, sfd, rec_mac, MLXSW_REG_SFD_BASE_LEN, 6,
294 MLXSW_REG_SFD_REC_LEN, 0x02);
295
296enum mlxsw_reg_sfd_rec_action {
297
298 MLXSW_REG_SFD_REC_ACTION_NOP = 0,
299
300 MLXSW_REG_SFD_REC_ACTION_MIRROR_TO_CPU = 1,
301
302 MLXSW_REG_SFD_REC_ACTION_TRAP = 2,
303
304 MLXSW_REG_SFD_REC_ACTION_FORWARD_IP_ROUTER = 3,
305 MLXSW_REG_SFD_REC_ACTION_DISCARD_ERROR = 15,
306};
307
308
309
310
311
312
313MLXSW_ITEM32_INDEXED(reg, sfd, rec_action, MLXSW_REG_SFD_BASE_LEN, 28, 4,
314 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
315
316
317
318
319
320
321
322MLXSW_ITEM32_INDEXED(reg, sfd, uc_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8,
323 MLXSW_REG_SFD_REC_LEN, 0x08, false);
324
325
326
327
328
329
330
331
332
333
334
335MLXSW_ITEM32_INDEXED(reg, sfd, uc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
336 MLXSW_REG_SFD_REC_LEN, 0x08, false);
337
338
339
340
341
342MLXSW_ITEM32_INDEXED(reg, sfd, uc_system_port, MLXSW_REG_SFD_BASE_LEN, 0, 16,
343 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
344
345static inline void mlxsw_reg_sfd_rec_pack(char *payload, int rec_index,
346 enum mlxsw_reg_sfd_rec_type rec_type,
347 const char *mac,
348 enum mlxsw_reg_sfd_rec_action action)
349{
350 u8 num_rec = mlxsw_reg_sfd_num_rec_get(payload);
351
352 if (rec_index >= num_rec)
353 mlxsw_reg_sfd_num_rec_set(payload, rec_index + 1);
354 mlxsw_reg_sfd_rec_swid_set(payload, rec_index, 0);
355 mlxsw_reg_sfd_rec_type_set(payload, rec_index, rec_type);
356 mlxsw_reg_sfd_rec_mac_memcpy_to(payload, rec_index, mac);
357 mlxsw_reg_sfd_rec_action_set(payload, rec_index, action);
358}
359
360static inline void mlxsw_reg_sfd_uc_pack(char *payload, int rec_index,
361 enum mlxsw_reg_sfd_rec_policy policy,
362 const char *mac, u16 fid_vid,
363 enum mlxsw_reg_sfd_rec_action action,
364 u16 local_port)
365{
366 mlxsw_reg_sfd_rec_pack(payload, rec_index,
367 MLXSW_REG_SFD_REC_TYPE_UNICAST, mac, action);
368 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy);
369 mlxsw_reg_sfd_uc_sub_port_set(payload, rec_index, 0);
370 mlxsw_reg_sfd_uc_fid_vid_set(payload, rec_index, fid_vid);
371 mlxsw_reg_sfd_uc_system_port_set(payload, rec_index, local_port);
372}
373
374
375
376
377
378
379MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8,
380 MLXSW_REG_SFD_REC_LEN, 0x08, false);
381
382
383
384
385
386
387
388
389
390
391
392MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
393 MLXSW_REG_SFD_REC_LEN, 0x08, false);
394
395
396
397
398
399MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_vid, MLXSW_REG_SFD_BASE_LEN, 16, 12,
400 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
401
402
403
404
405
406MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_id, MLXSW_REG_SFD_BASE_LEN, 0, 10,
407 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
408
409static inline void
410mlxsw_reg_sfd_uc_lag_pack(char *payload, int rec_index,
411 enum mlxsw_reg_sfd_rec_policy policy,
412 const char *mac, u16 fid_vid,
413 enum mlxsw_reg_sfd_rec_action action, u16 lag_vid,
414 u16 lag_id)
415{
416 mlxsw_reg_sfd_rec_pack(payload, rec_index,
417 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG,
418 mac, action);
419 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy);
420 mlxsw_reg_sfd_uc_lag_sub_port_set(payload, rec_index, 0);
421 mlxsw_reg_sfd_uc_lag_fid_vid_set(payload, rec_index, fid_vid);
422 mlxsw_reg_sfd_uc_lag_lag_vid_set(payload, rec_index, lag_vid);
423 mlxsw_reg_sfd_uc_lag_lag_id_set(payload, rec_index, lag_id);
424}
425
426
427
428
429
430
431
432
433MLXSW_ITEM32_INDEXED(reg, sfd, mc_pgi, MLXSW_REG_SFD_BASE_LEN, 16, 13,
434 MLXSW_REG_SFD_REC_LEN, 0x08, false);
435
436
437
438
439
440
441MLXSW_ITEM32_INDEXED(reg, sfd, mc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
442 MLXSW_REG_SFD_REC_LEN, 0x08, false);
443
444
445
446
447
448
449
450MLXSW_ITEM32_INDEXED(reg, sfd, mc_mid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
451 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
452
453static inline void
454mlxsw_reg_sfd_mc_pack(char *payload, int rec_index,
455 const char *mac, u16 fid_vid,
456 enum mlxsw_reg_sfd_rec_action action, u16 mid)
457{
458 mlxsw_reg_sfd_rec_pack(payload, rec_index,
459 MLXSW_REG_SFD_REC_TYPE_MULTICAST, mac, action);
460 mlxsw_reg_sfd_mc_pgi_set(payload, rec_index, 0x1FFF);
461 mlxsw_reg_sfd_mc_fid_vid_set(payload, rec_index, fid_vid);
462 mlxsw_reg_sfd_mc_mid_set(payload, rec_index, mid);
463}
464
465
466
467
468
469
470
471MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_msb, MLXSW_REG_SFD_BASE_LEN, 24,
472 8, MLXSW_REG_SFD_REC_LEN, 0x08, false);
473
474
475
476
477
478MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_fid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
479 MLXSW_REG_SFD_REC_LEN, 0x08, false);
480
481enum mlxsw_reg_sfd_uc_tunnel_protocol {
482 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV4,
483 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV6,
484};
485
486
487
488
489
490MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_protocol, MLXSW_REG_SFD_BASE_LEN, 27,
491 1, MLXSW_REG_SFD_REC_LEN, 0x0C, false);
492
493
494
495
496
497
498
499
500MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_lsb, MLXSW_REG_SFD_BASE_LEN, 0,
501 24, MLXSW_REG_SFD_REC_LEN, 0x0C, false);
502
503static inline void
504mlxsw_reg_sfd_uc_tunnel_pack(char *payload, int rec_index,
505 enum mlxsw_reg_sfd_rec_policy policy,
506 const char *mac, u16 fid,
507 enum mlxsw_reg_sfd_rec_action action,
508 enum mlxsw_reg_sfd_uc_tunnel_protocol proto)
509{
510 mlxsw_reg_sfd_rec_pack(payload, rec_index,
511 MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL, mac,
512 action);
513 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy);
514 mlxsw_reg_sfd_uc_tunnel_fid_set(payload, rec_index, fid);
515 mlxsw_reg_sfd_uc_tunnel_protocol_set(payload, rec_index, proto);
516}
517
518static inline void
519mlxsw_reg_sfd_uc_tunnel_pack4(char *payload, int rec_index,
520 enum mlxsw_reg_sfd_rec_policy policy,
521 const char *mac, u16 fid,
522 enum mlxsw_reg_sfd_rec_action action, u32 uip)
523{
524 mlxsw_reg_sfd_uc_tunnel_uip_msb_set(payload, rec_index, uip >> 24);
525 mlxsw_reg_sfd_uc_tunnel_uip_lsb_set(payload, rec_index, uip);
526 mlxsw_reg_sfd_uc_tunnel_pack(payload, rec_index, policy, mac, fid,
527 action,
528 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV4);
529}
530
531static inline void
532mlxsw_reg_sfd_uc_tunnel_pack6(char *payload, int rec_index, const char *mac,
533 u16 fid, enum mlxsw_reg_sfd_rec_action action,
534 u32 uip_ptr)
535{
536 mlxsw_reg_sfd_uc_tunnel_uip_lsb_set(payload, rec_index, uip_ptr);
537
538 mlxsw_reg_sfd_uc_tunnel_pack(payload, rec_index,
539 MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY,
540 mac, fid, action,
541 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV6);
542}
543
544enum mlxsw_reg_tunnel_port {
545 MLXSW_REG_TUNNEL_PORT_NVE,
546 MLXSW_REG_TUNNEL_PORT_VPLS,
547 MLXSW_REG_TUNNEL_PORT_FLEX_TUNNEL0,
548 MLXSW_REG_TUNNEL_PORT_FLEX_TUNNEL1,
549};
550
551
552
553
554
555
556#define MLXSW_REG_SFN_ID 0x200B
557#define MLXSW_REG_SFN_BASE_LEN 0x10
558#define MLXSW_REG_SFN_REC_LEN 0x10
559#define MLXSW_REG_SFN_REC_MAX_COUNT 64
560#define MLXSW_REG_SFN_LEN (MLXSW_REG_SFN_BASE_LEN + \
561 MLXSW_REG_SFN_REC_LEN * MLXSW_REG_SFN_REC_MAX_COUNT)
562
563MLXSW_REG_DEFINE(sfn, MLXSW_REG_SFN_ID, MLXSW_REG_SFN_LEN);
564
565
566
567
568
569MLXSW_ITEM32(reg, sfn, swid, 0x00, 24, 8);
570
571
572
573
574
575MLXSW_ITEM32(reg, sfn, end, 0x04, 20, 1);
576
577
578
579
580
581
582
583
584
585MLXSW_ITEM32(reg, sfn, num_rec, 0x04, 0, 8);
586
587static inline void mlxsw_reg_sfn_pack(char *payload)
588{
589 MLXSW_REG_ZERO(sfn, payload);
590 mlxsw_reg_sfn_swid_set(payload, 0);
591 mlxsw_reg_sfn_end_set(payload, 0);
592 mlxsw_reg_sfn_num_rec_set(payload, MLXSW_REG_SFN_REC_MAX_COUNT);
593}
594
595
596
597
598
599MLXSW_ITEM32_INDEXED(reg, sfn, rec_swid, MLXSW_REG_SFN_BASE_LEN, 24, 8,
600 MLXSW_REG_SFN_REC_LEN, 0x00, false);
601
602enum mlxsw_reg_sfn_rec_type {
603
604 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC = 0x5,
605
606 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC_LAG = 0x6,
607
608 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC = 0x7,
609
610 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC_LAG = 0x8,
611
612 MLXSW_REG_SFN_REC_TYPE_LEARNED_UNICAST_TUNNEL = 0xD,
613
614 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_UNICAST_TUNNEL = 0xE,
615};
616
617
618
619
620
621MLXSW_ITEM32_INDEXED(reg, sfn, rec_type, MLXSW_REG_SFN_BASE_LEN, 20, 4,
622 MLXSW_REG_SFN_REC_LEN, 0x00, false);
623
624
625
626
627
628MLXSW_ITEM_BUF_INDEXED(reg, sfn, rec_mac, MLXSW_REG_SFN_BASE_LEN, 6,
629 MLXSW_REG_SFN_REC_LEN, 0x02);
630
631
632
633
634
635
636MLXSW_ITEM32_INDEXED(reg, sfn, mac_sub_port, MLXSW_REG_SFN_BASE_LEN, 16, 8,
637 MLXSW_REG_SFN_REC_LEN, 0x08, false);
638
639
640
641
642
643MLXSW_ITEM32_INDEXED(reg, sfn, mac_fid, MLXSW_REG_SFN_BASE_LEN, 0, 16,
644 MLXSW_REG_SFN_REC_LEN, 0x08, false);
645
646
647
648
649
650MLXSW_ITEM32_INDEXED(reg, sfn, mac_system_port, MLXSW_REG_SFN_BASE_LEN, 0, 16,
651 MLXSW_REG_SFN_REC_LEN, 0x0C, false);
652
653static inline void mlxsw_reg_sfn_mac_unpack(char *payload, int rec_index,
654 char *mac, u16 *p_vid,
655 u16 *p_local_port)
656{
657 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac);
658 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index);
659 *p_local_port = mlxsw_reg_sfn_mac_system_port_get(payload, rec_index);
660}
661
662
663
664
665
666MLXSW_ITEM32_INDEXED(reg, sfn, mac_lag_lag_id, MLXSW_REG_SFN_BASE_LEN, 0, 10,
667 MLXSW_REG_SFN_REC_LEN, 0x0C, false);
668
669static inline void mlxsw_reg_sfn_mac_lag_unpack(char *payload, int rec_index,
670 char *mac, u16 *p_vid,
671 u16 *p_lag_id)
672{
673 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac);
674 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index);
675 *p_lag_id = mlxsw_reg_sfn_mac_lag_lag_id_get(payload, rec_index);
676}
677
678
679
680
681
682
683
684MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_msb, MLXSW_REG_SFN_BASE_LEN, 24,
685 8, MLXSW_REG_SFN_REC_LEN, 0x08, false);
686
687enum mlxsw_reg_sfn_uc_tunnel_protocol {
688 MLXSW_REG_SFN_UC_TUNNEL_PROTOCOL_IPV4,
689 MLXSW_REG_SFN_UC_TUNNEL_PROTOCOL_IPV6,
690};
691
692
693
694
695
696MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_protocol, MLXSW_REG_SFN_BASE_LEN, 27,
697 1, MLXSW_REG_SFN_REC_LEN, 0x0C, false);
698
699
700
701
702
703
704
705MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_lsb, MLXSW_REG_SFN_BASE_LEN, 0,
706 24, MLXSW_REG_SFN_REC_LEN, 0x0C, false);
707
708
709
710
711
712
713MLXSW_ITEM32_INDEXED(reg, sfn, tunnel_port, MLXSW_REG_SFN_BASE_LEN, 0, 4,
714 MLXSW_REG_SFN_REC_LEN, 0x10, false);
715
716static inline void
717mlxsw_reg_sfn_uc_tunnel_unpack(char *payload, int rec_index, char *mac,
718 u16 *p_fid, u32 *p_uip,
719 enum mlxsw_reg_sfn_uc_tunnel_protocol *p_proto)
720{
721 u32 uip_msb, uip_lsb;
722
723 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac);
724 *p_fid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index);
725 uip_msb = mlxsw_reg_sfn_uc_tunnel_uip_msb_get(payload, rec_index);
726 uip_lsb = mlxsw_reg_sfn_uc_tunnel_uip_lsb_get(payload, rec_index);
727 *p_uip = uip_msb << 24 | uip_lsb;
728 *p_proto = mlxsw_reg_sfn_uc_tunnel_protocol_get(payload, rec_index);
729}
730
731
732
733
734
735#define MLXSW_REG_SPMS_ID 0x200D
736#define MLXSW_REG_SPMS_LEN 0x404
737
738MLXSW_REG_DEFINE(spms, MLXSW_REG_SPMS_ID, MLXSW_REG_SPMS_LEN);
739
740
741
742
743
744MLXSW_ITEM32_LP(reg, spms, 0x00, 16, 0x00, 12);
745
746enum mlxsw_reg_spms_state {
747 MLXSW_REG_SPMS_STATE_NO_CHANGE,
748 MLXSW_REG_SPMS_STATE_DISCARDING,
749 MLXSW_REG_SPMS_STATE_LEARNING,
750 MLXSW_REG_SPMS_STATE_FORWARDING,
751};
752
753
754
755
756
757
758
759
760
761MLXSW_ITEM_BIT_ARRAY(reg, spms, state, 0x04, 0x400, 2);
762
763static inline void mlxsw_reg_spms_pack(char *payload, u16 local_port)
764{
765 MLXSW_REG_ZERO(spms, payload);
766 mlxsw_reg_spms_local_port_set(payload, local_port);
767}
768
769static inline void mlxsw_reg_spms_vid_pack(char *payload, u16 vid,
770 enum mlxsw_reg_spms_state state)
771{
772 mlxsw_reg_spms_state_set(payload, vid, state);
773}
774
775
776
777
778
779#define MLXSW_REG_SPVID_ID 0x200E
780#define MLXSW_REG_SPVID_LEN 0x08
781
782MLXSW_REG_DEFINE(spvid, MLXSW_REG_SPVID_ID, MLXSW_REG_SPVID_LEN);
783
784
785
786
787
788
789MLXSW_ITEM32(reg, spvid, tport, 0x00, 24, 1);
790
791
792
793
794
795
796MLXSW_ITEM32_LP(reg, spvid, 0x00, 16, 0x00, 12);
797
798
799
800
801
802
803MLXSW_ITEM32(reg, spvid, sub_port, 0x00, 8, 8);
804
805
806
807
808
809
810
811MLXSW_ITEM32(reg, spvid, egr_et_set, 0x04, 24, 1);
812
813
814
815
816
817
818
819
820
821
822
823MLXSW_ITEM32(reg, spvid, et_vlan, 0x04, 16, 2);
824
825
826
827
828
829MLXSW_ITEM32(reg, spvid, pvid, 0x04, 0, 12);
830
831static inline void mlxsw_reg_spvid_pack(char *payload, u16 local_port, u16 pvid,
832 u8 et_vlan)
833{
834 MLXSW_REG_ZERO(spvid, payload);
835 mlxsw_reg_spvid_local_port_set(payload, local_port);
836 mlxsw_reg_spvid_pvid_set(payload, pvid);
837 mlxsw_reg_spvid_et_vlan_set(payload, et_vlan);
838}
839
840
841
842
843
844
845
846#define MLXSW_REG_SPVM_ID 0x200F
847#define MLXSW_REG_SPVM_BASE_LEN 0x04
848#define MLXSW_REG_SPVM_REC_LEN 0x04
849#define MLXSW_REG_SPVM_REC_MAX_COUNT 255
850#define MLXSW_REG_SPVM_LEN (MLXSW_REG_SPVM_BASE_LEN + \
851 MLXSW_REG_SPVM_REC_LEN * MLXSW_REG_SPVM_REC_MAX_COUNT)
852
853MLXSW_REG_DEFINE(spvm, MLXSW_REG_SPVM_ID, MLXSW_REG_SPVM_LEN);
854
855
856
857
858
859
860
861MLXSW_ITEM32(reg, spvm, pt, 0x00, 31, 1);
862
863
864
865
866
867
868MLXSW_ITEM32(reg, spvm, pte, 0x00, 30, 1);
869
870
871
872
873
874MLXSW_ITEM32_LP(reg, spvm, 0x00, 16, 0x00, 12);
875
876
877
878
879
880
881MLXSW_ITEM32(reg, spvm, sub_port, 0x00, 8, 8);
882
883
884
885
886
887MLXSW_ITEM32(reg, spvm, num_rec, 0x00, 0, 8);
888
889
890
891
892
893MLXSW_ITEM32_INDEXED(reg, spvm, rec_i,
894 MLXSW_REG_SPVM_BASE_LEN, 14, 1,
895 MLXSW_REG_SPVM_REC_LEN, 0, false);
896
897
898
899
900
901MLXSW_ITEM32_INDEXED(reg, spvm, rec_e,
902 MLXSW_REG_SPVM_BASE_LEN, 13, 1,
903 MLXSW_REG_SPVM_REC_LEN, 0, false);
904
905
906
907
908
909
910MLXSW_ITEM32_INDEXED(reg, spvm, rec_u,
911 MLXSW_REG_SPVM_BASE_LEN, 12, 1,
912 MLXSW_REG_SPVM_REC_LEN, 0, false);
913
914
915
916
917
918MLXSW_ITEM32_INDEXED(reg, spvm, rec_vid,
919 MLXSW_REG_SPVM_BASE_LEN, 0, 12,
920 MLXSW_REG_SPVM_REC_LEN, 0, false);
921
922static inline void mlxsw_reg_spvm_pack(char *payload, u16 local_port,
923 u16 vid_begin, u16 vid_end,
924 bool is_member, bool untagged)
925{
926 int size = vid_end - vid_begin + 1;
927 int i;
928
929 MLXSW_REG_ZERO(spvm, payload);
930 mlxsw_reg_spvm_local_port_set(payload, local_port);
931 mlxsw_reg_spvm_num_rec_set(payload, size);
932
933 for (i = 0; i < size; i++) {
934 mlxsw_reg_spvm_rec_i_set(payload, i, is_member);
935 mlxsw_reg_spvm_rec_e_set(payload, i, is_member);
936 mlxsw_reg_spvm_rec_u_set(payload, i, untagged);
937 mlxsw_reg_spvm_rec_vid_set(payload, i, vid_begin + i);
938 }
939}
940
941
942
943
944
945
946#define MLXSW_REG_SPAFT_ID 0x2010
947#define MLXSW_REG_SPAFT_LEN 0x08
948
949MLXSW_REG_DEFINE(spaft, MLXSW_REG_SPAFT_ID, MLXSW_REG_SPAFT_LEN);
950
951
952
953
954
955
956
957MLXSW_ITEM32_LP(reg, spaft, 0x00, 16, 0x00, 12);
958
959
960
961
962
963
964MLXSW_ITEM32(reg, spaft, sub_port, 0x00, 8, 8);
965
966
967
968
969
970MLXSW_ITEM32(reg, spaft, allow_untagged, 0x04, 31, 1);
971
972
973
974
975
976MLXSW_ITEM32(reg, spaft, allow_prio_tagged, 0x04, 30, 1);
977
978
979
980
981
982MLXSW_ITEM32(reg, spaft, allow_tagged, 0x04, 29, 1);
983
984static inline void mlxsw_reg_spaft_pack(char *payload, u16 local_port,
985 bool allow_untagged)
986{
987 MLXSW_REG_ZERO(spaft, payload);
988 mlxsw_reg_spaft_local_port_set(payload, local_port);
989 mlxsw_reg_spaft_allow_untagged_set(payload, allow_untagged);
990 mlxsw_reg_spaft_allow_prio_tagged_set(payload, allow_untagged);
991 mlxsw_reg_spaft_allow_tagged_set(payload, true);
992}
993
994
995
996
997
998
999#define MLXSW_REG_SFGC_ID 0x2011
1000#define MLXSW_REG_SFGC_LEN 0x10
1001
1002MLXSW_REG_DEFINE(sfgc, MLXSW_REG_SFGC_ID, MLXSW_REG_SFGC_LEN);
1003
1004enum mlxsw_reg_sfgc_type {
1005 MLXSW_REG_SFGC_TYPE_BROADCAST,
1006 MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST,
1007 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4,
1008 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6,
1009 MLXSW_REG_SFGC_TYPE_RESERVED,
1010 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP,
1011 MLXSW_REG_SFGC_TYPE_IPV4_LINK_LOCAL,
1012 MLXSW_REG_SFGC_TYPE_IPV6_ALL_HOST,
1013 MLXSW_REG_SFGC_TYPE_MAX,
1014};
1015
1016
1017
1018
1019
1020MLXSW_ITEM32(reg, sfgc, type, 0x00, 0, 4);
1021
1022enum mlxsw_reg_sfgc_bridge_type {
1023 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID = 0,
1024 MLXSW_REG_SFGC_BRIDGE_TYPE_VFID = 1,
1025};
1026
1027
1028
1029
1030
1031
1032MLXSW_ITEM32(reg, sfgc, bridge_type, 0x04, 24, 3);
1033
1034enum mlxsw_flood_table_type {
1035 MLXSW_REG_SFGC_TABLE_TYPE_VID = 1,
1036 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE = 2,
1037 MLXSW_REG_SFGC_TABLE_TYPE_ANY = 0,
1038 MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFSET = 3,
1039 MLXSW_REG_SFGC_TABLE_TYPE_FID = 4,
1040};
1041
1042
1043
1044
1045
1046
1047
1048MLXSW_ITEM32(reg, sfgc, table_type, 0x04, 16, 3);
1049
1050
1051
1052
1053
1054
1055MLXSW_ITEM32(reg, sfgc, flood_table, 0x04, 0, 6);
1056
1057
1058
1059
1060
1061MLXSW_ITEM32(reg, sfgc, mid, 0x08, 0, 16);
1062
1063
1064
1065
1066
1067MLXSW_ITEM32(reg, sfgc, counter_set_type, 0x0C, 24, 8);
1068
1069
1070
1071
1072
1073MLXSW_ITEM32(reg, sfgc, counter_index, 0x0C, 0, 24);
1074
1075static inline void
1076mlxsw_reg_sfgc_pack(char *payload, enum mlxsw_reg_sfgc_type type,
1077 enum mlxsw_reg_sfgc_bridge_type bridge_type,
1078 enum mlxsw_flood_table_type table_type,
1079 unsigned int flood_table)
1080{
1081 MLXSW_REG_ZERO(sfgc, payload);
1082 mlxsw_reg_sfgc_type_set(payload, type);
1083 mlxsw_reg_sfgc_bridge_type_set(payload, bridge_type);
1084 mlxsw_reg_sfgc_table_type_set(payload, table_type);
1085 mlxsw_reg_sfgc_flood_table_set(payload, flood_table);
1086 mlxsw_reg_sfgc_mid_set(payload, MLXSW_PORT_MID);
1087}
1088
1089
1090
1091
1092
1093
1094#define MLXSW_REG_SFDF_ID 0x2013
1095#define MLXSW_REG_SFDF_LEN 0x14
1096
1097MLXSW_REG_DEFINE(sfdf, MLXSW_REG_SFDF_ID, MLXSW_REG_SFDF_LEN);
1098
1099
1100
1101
1102
1103MLXSW_ITEM32(reg, sfdf, swid, 0x00, 24, 8);
1104
1105enum mlxsw_reg_sfdf_flush_type {
1106 MLXSW_REG_SFDF_FLUSH_PER_SWID,
1107 MLXSW_REG_SFDF_FLUSH_PER_FID,
1108 MLXSW_REG_SFDF_FLUSH_PER_PORT,
1109 MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID,
1110 MLXSW_REG_SFDF_FLUSH_PER_LAG,
1111 MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID,
1112 MLXSW_REG_SFDF_FLUSH_PER_NVE,
1113 MLXSW_REG_SFDF_FLUSH_PER_NVE_AND_FID,
1114};
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130MLXSW_ITEM32(reg, sfdf, flush_type, 0x04, 28, 4);
1131
1132
1133
1134
1135
1136
1137
1138MLXSW_ITEM32(reg, sfdf, flush_static, 0x04, 24, 1);
1139
1140static inline void mlxsw_reg_sfdf_pack(char *payload,
1141 enum mlxsw_reg_sfdf_flush_type type)
1142{
1143 MLXSW_REG_ZERO(sfdf, payload);
1144 mlxsw_reg_sfdf_flush_type_set(payload, type);
1145 mlxsw_reg_sfdf_flush_static_set(payload, true);
1146}
1147
1148
1149
1150
1151
1152MLXSW_ITEM32(reg, sfdf, fid, 0x0C, 0, 16);
1153
1154
1155
1156
1157
1158MLXSW_ITEM32(reg, sfdf, system_port, 0x0C, 0, 16);
1159
1160
1161
1162
1163
1164MLXSW_ITEM32(reg, sfdf, port_fid_system_port, 0x08, 0, 16);
1165
1166
1167
1168
1169
1170MLXSW_ITEM32(reg, sfdf, lag_id, 0x0C, 0, 10);
1171
1172
1173
1174
1175
1176MLXSW_ITEM32(reg, sfdf, lag_fid_lag_id, 0x08, 0, 10);
1177
1178
1179
1180
1181
1182
1183
1184#define MLXSW_REG_SLDR_ID 0x2014
1185#define MLXSW_REG_SLDR_LEN 0x0C
1186
1187MLXSW_REG_DEFINE(sldr, MLXSW_REG_SLDR_ID, MLXSW_REG_SLDR_LEN);
1188
1189enum mlxsw_reg_sldr_op {
1190
1191 MLXSW_REG_SLDR_OP_LAG_CREATE,
1192 MLXSW_REG_SLDR_OP_LAG_DESTROY,
1193
1194 MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST,
1195
1196 MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST,
1197};
1198
1199
1200
1201
1202
1203MLXSW_ITEM32(reg, sldr, op, 0x00, 29, 3);
1204
1205
1206
1207
1208
1209MLXSW_ITEM32(reg, sldr, lag_id, 0x00, 0, 10);
1210
1211static inline void mlxsw_reg_sldr_lag_create_pack(char *payload, u8 lag_id)
1212{
1213 MLXSW_REG_ZERO(sldr, payload);
1214 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_CREATE);
1215 mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1216}
1217
1218static inline void mlxsw_reg_sldr_lag_destroy_pack(char *payload, u8 lag_id)
1219{
1220 MLXSW_REG_ZERO(sldr, payload);
1221 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_DESTROY);
1222 mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1223}
1224
1225
1226
1227
1228
1229
1230
1231MLXSW_ITEM32(reg, sldr, num_ports, 0x04, 24, 8);
1232
1233
1234
1235
1236
1237MLXSW_ITEM32_INDEXED(reg, sldr, system_port, 0x08, 0, 16, 4, 0, false);
1238
1239static inline void mlxsw_reg_sldr_lag_add_port_pack(char *payload, u8 lag_id,
1240 u16 local_port)
1241{
1242 MLXSW_REG_ZERO(sldr, payload);
1243 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST);
1244 mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1245 mlxsw_reg_sldr_num_ports_set(payload, 1);
1246 mlxsw_reg_sldr_system_port_set(payload, 0, local_port);
1247}
1248
1249static inline void mlxsw_reg_sldr_lag_remove_port_pack(char *payload, u8 lag_id,
1250 u16 local_port)
1251{
1252 MLXSW_REG_ZERO(sldr, payload);
1253 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST);
1254 mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1255 mlxsw_reg_sldr_num_ports_set(payload, 1);
1256 mlxsw_reg_sldr_system_port_set(payload, 0, local_port);
1257}
1258
1259
1260
1261
1262
1263
1264#define MLXSW_REG_SLCR_ID 0x2015
1265#define MLXSW_REG_SLCR_LEN 0x10
1266
1267MLXSW_REG_DEFINE(slcr, MLXSW_REG_SLCR_ID, MLXSW_REG_SLCR_LEN);
1268
1269enum mlxsw_reg_slcr_pp {
1270
1271 MLXSW_REG_SLCR_PP_GLOBAL,
1272
1273 MLXSW_REG_SLCR_PP_PER_PORT,
1274};
1275
1276
1277
1278
1279
1280
1281MLXSW_ITEM32(reg, slcr, pp, 0x00, 24, 1);
1282
1283
1284
1285
1286
1287
1288
1289
1290MLXSW_ITEM32_LP(reg, slcr, 0x00, 16, 0x00, 12);
1291
1292enum mlxsw_reg_slcr_type {
1293 MLXSW_REG_SLCR_TYPE_CRC,
1294 MLXSW_REG_SLCR_TYPE_XOR,
1295 MLXSW_REG_SLCR_TYPE_RANDOM,
1296};
1297
1298
1299
1300
1301
1302MLXSW_ITEM32(reg, slcr, type, 0x00, 0, 4);
1303
1304
1305#define MLXSW_REG_SLCR_LAG_HASH_IN_PORT BIT(0)
1306
1307#define MLXSW_REG_SLCR_LAG_HASH_SMAC_IP BIT(1)
1308
1309#define MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP BIT(2)
1310#define MLXSW_REG_SLCR_LAG_HASH_SMAC \
1311 (MLXSW_REG_SLCR_LAG_HASH_SMAC_IP | \
1312 MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP)
1313
1314#define MLXSW_REG_SLCR_LAG_HASH_DMAC_IP BIT(3)
1315
1316#define MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP BIT(4)
1317#define MLXSW_REG_SLCR_LAG_HASH_DMAC \
1318 (MLXSW_REG_SLCR_LAG_HASH_DMAC_IP | \
1319 MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP)
1320
1321#define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP BIT(5)
1322
1323#define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP BIT(6)
1324#define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE \
1325 (MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP | \
1326 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP)
1327
1328#define MLXSW_REG_SLCR_LAG_HASH_VLANID_IP BIT(7)
1329
1330#define MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP BIT(8)
1331#define MLXSW_REG_SLCR_LAG_HASH_VLANID \
1332 (MLXSW_REG_SLCR_LAG_HASH_VLANID_IP | \
1333 MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP)
1334
1335#define MLXSW_REG_SLCR_LAG_HASH_SIP BIT(9)
1336
1337#define MLXSW_REG_SLCR_LAG_HASH_DIP BIT(10)
1338
1339#define MLXSW_REG_SLCR_LAG_HASH_SPORT BIT(11)
1340
1341#define MLXSW_REG_SLCR_LAG_HASH_DPORT BIT(12)
1342
1343#define MLXSW_REG_SLCR_LAG_HASH_IPPROTO BIT(13)
1344
1345#define MLXSW_REG_SLCR_LAG_HASH_FLOWLABEL BIT(14)
1346
1347#define MLXSW_REG_SLCR_LAG_HASH_FCOE_SID BIT(15)
1348
1349#define MLXSW_REG_SLCR_LAG_HASH_FCOE_DID BIT(16)
1350
1351#define MLXSW_REG_SLCR_LAG_HASH_FCOE_OXID BIT(17)
1352
1353#define MLXSW_REG_SLCR_LAG_HASH_ROCE_DQP BIT(19)
1354
1355
1356
1357
1358
1359
1360
1361
1362MLXSW_ITEM32(reg, slcr, lag_hash, 0x04, 0, 20);
1363
1364
1365
1366
1367
1368MLXSW_ITEM32(reg, slcr, seed, 0x08, 0, 32);
1369
1370static inline void mlxsw_reg_slcr_pack(char *payload, u16 lag_hash, u32 seed)
1371{
1372 MLXSW_REG_ZERO(slcr, payload);
1373 mlxsw_reg_slcr_pp_set(payload, MLXSW_REG_SLCR_PP_GLOBAL);
1374 mlxsw_reg_slcr_type_set(payload, MLXSW_REG_SLCR_TYPE_CRC);
1375 mlxsw_reg_slcr_lag_hash_set(payload, lag_hash);
1376 mlxsw_reg_slcr_seed_set(payload, seed);
1377}
1378
1379
1380
1381
1382
1383
1384#define MLXSW_REG_SLCOR_ID 0x2016
1385#define MLXSW_REG_SLCOR_LEN 0x10
1386
1387MLXSW_REG_DEFINE(slcor, MLXSW_REG_SLCOR_ID, MLXSW_REG_SLCOR_LEN);
1388
1389enum mlxsw_reg_slcor_col {
1390
1391 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT,
1392 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED,
1393 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_DISABLED,
1394 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT,
1395};
1396
1397
1398
1399
1400
1401MLXSW_ITEM32(reg, slcor, col, 0x00, 30, 2);
1402
1403
1404
1405
1406
1407
1408MLXSW_ITEM32_LP(reg, slcor, 0x00, 16, 0x00, 12);
1409
1410
1411
1412
1413
1414MLXSW_ITEM32(reg, slcor, lag_id, 0x00, 0, 10);
1415
1416
1417
1418
1419
1420
1421MLXSW_ITEM32(reg, slcor, port_index, 0x04, 0, 10);
1422
1423static inline void mlxsw_reg_slcor_pack(char *payload,
1424 u16 local_port, u16 lag_id,
1425 enum mlxsw_reg_slcor_col col)
1426{
1427 MLXSW_REG_ZERO(slcor, payload);
1428 mlxsw_reg_slcor_col_set(payload, col);
1429 mlxsw_reg_slcor_local_port_set(payload, local_port);
1430 mlxsw_reg_slcor_lag_id_set(payload, lag_id);
1431}
1432
1433static inline void mlxsw_reg_slcor_port_add_pack(char *payload,
1434 u16 local_port, u16 lag_id,
1435 u8 port_index)
1436{
1437 mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1438 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT);
1439 mlxsw_reg_slcor_port_index_set(payload, port_index);
1440}
1441
1442static inline void mlxsw_reg_slcor_port_remove_pack(char *payload,
1443 u16 local_port, u16 lag_id)
1444{
1445 mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1446 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT);
1447}
1448
1449static inline void mlxsw_reg_slcor_col_enable_pack(char *payload,
1450 u16 local_port, u16 lag_id)
1451{
1452 mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1453 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED);
1454}
1455
1456static inline void mlxsw_reg_slcor_col_disable_pack(char *payload,
1457 u16 local_port, u16 lag_id)
1458{
1459 mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1460 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED);
1461}
1462
1463
1464
1465
1466
1467#define MLXSW_REG_SPMLR_ID 0x2018
1468#define MLXSW_REG_SPMLR_LEN 0x8
1469
1470MLXSW_REG_DEFINE(spmlr, MLXSW_REG_SPMLR_ID, MLXSW_REG_SPMLR_LEN);
1471
1472
1473
1474
1475
1476MLXSW_ITEM32_LP(reg, spmlr, 0x00, 16, 0x00, 12);
1477
1478
1479
1480
1481
1482
1483MLXSW_ITEM32(reg, spmlr, sub_port, 0x00, 8, 8);
1484
1485enum mlxsw_reg_spmlr_learn_mode {
1486 MLXSW_REG_SPMLR_LEARN_MODE_DISABLE = 0,
1487 MLXSW_REG_SPMLR_LEARN_MODE_ENABLE = 2,
1488 MLXSW_REG_SPMLR_LEARN_MODE_SEC = 3,
1489};
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502MLXSW_ITEM32(reg, spmlr, learn_mode, 0x04, 30, 2);
1503
1504static inline void mlxsw_reg_spmlr_pack(char *payload, u16 local_port,
1505 enum mlxsw_reg_spmlr_learn_mode mode)
1506{
1507 MLXSW_REG_ZERO(spmlr, payload);
1508 mlxsw_reg_spmlr_local_port_set(payload, local_port);
1509 mlxsw_reg_spmlr_sub_port_set(payload, 0);
1510 mlxsw_reg_spmlr_learn_mode_set(payload, mode);
1511}
1512
1513
1514
1515
1516
1517
1518#define MLXSW_REG_SVFA_ID 0x201C
1519#define MLXSW_REG_SVFA_LEN 0x10
1520
1521MLXSW_REG_DEFINE(svfa, MLXSW_REG_SVFA_ID, MLXSW_REG_SVFA_LEN);
1522
1523
1524
1525
1526
1527MLXSW_ITEM32(reg, svfa, swid, 0x00, 24, 8);
1528
1529
1530
1531
1532
1533
1534
1535MLXSW_ITEM32_LP(reg, svfa, 0x00, 16, 0x00, 12);
1536
1537enum mlxsw_reg_svfa_mt {
1538 MLXSW_REG_SVFA_MT_VID_TO_FID,
1539 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID,
1540};
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550MLXSW_ITEM32(reg, svfa, mapping_table, 0x00, 8, 3);
1551
1552
1553
1554
1555
1556
1557
1558
1559MLXSW_ITEM32(reg, svfa, v, 0x00, 0, 1);
1560
1561
1562
1563
1564
1565MLXSW_ITEM32(reg, svfa, fid, 0x04, 16, 16);
1566
1567
1568
1569
1570
1571MLXSW_ITEM32(reg, svfa, vid, 0x04, 0, 12);
1572
1573
1574
1575
1576
1577
1578
1579MLXSW_ITEM32(reg, svfa, counter_set_type, 0x08, 24, 8);
1580
1581
1582
1583
1584
1585
1586
1587MLXSW_ITEM32(reg, svfa, counter_index, 0x08, 0, 24);
1588
1589static inline void mlxsw_reg_svfa_pack(char *payload, u16 local_port,
1590 enum mlxsw_reg_svfa_mt mt, bool valid,
1591 u16 fid, u16 vid)
1592{
1593 MLXSW_REG_ZERO(svfa, payload);
1594 local_port = mt == MLXSW_REG_SVFA_MT_VID_TO_FID ? 0 : local_port;
1595 mlxsw_reg_svfa_swid_set(payload, 0);
1596 mlxsw_reg_svfa_local_port_set(payload, local_port);
1597 mlxsw_reg_svfa_mapping_table_set(payload, mt);
1598 mlxsw_reg_svfa_v_set(payload, valid);
1599 mlxsw_reg_svfa_fid_set(payload, fid);
1600 mlxsw_reg_svfa_vid_set(payload, vid);
1601}
1602
1603
1604
1605
1606
1607
1608#define MLXSW_REG_SPVTR_ID 0x201D
1609#define MLXSW_REG_SPVTR_LEN 0x10
1610
1611MLXSW_REG_DEFINE(spvtr, MLXSW_REG_SPVTR_ID, MLXSW_REG_SPVTR_LEN);
1612
1613
1614
1615
1616
1617
1618
1619MLXSW_ITEM32(reg, spvtr, tport, 0x00, 24, 1);
1620
1621
1622
1623
1624
1625
1626MLXSW_ITEM32_LP(reg, spvtr, 0x00, 16, 0x00, 12);
1627
1628
1629
1630
1631
1632
1633
1634MLXSW_ITEM32(reg, spvtr, ippe, 0x04, 31, 1);
1635
1636
1637
1638
1639
1640
1641
1642
1643MLXSW_ITEM32(reg, spvtr, ipve, 0x04, 30, 1);
1644
1645
1646
1647
1648
1649
1650
1651MLXSW_ITEM32(reg, spvtr, epve, 0x04, 29, 1);
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663MLXSW_ITEM32(reg, spvtr, ipprio_mode, 0x04, 20, 4);
1664
1665enum mlxsw_reg_spvtr_ipvid_mode {
1666
1667 MLXSW_REG_SPVTR_IPVID_MODE_IEEE_COMPLIANT_PVID,
1668
1669 MLXSW_REG_SPVTR_IPVID_MODE_PUSH_VLAN_FOR_UNTAGGED_PACKET,
1670
1671 MLXSW_REG_SPVTR_IPVID_MODE_ALWAYS_PUSH_VLAN,
1672};
1673
1674
1675
1676
1677
1678
1679MLXSW_ITEM32(reg, spvtr, ipvid_mode, 0x04, 16, 4);
1680
1681enum mlxsw_reg_spvtr_epvid_mode {
1682
1683 MLXSW_REG_SPVTR_EPVID_MODE_IEEE_COMPLIANT_VLAN_MEMBERSHIP,
1684
1685 MLXSW_REG_SPVTR_EPVID_MODE_POP_VLAN,
1686};
1687
1688
1689
1690
1691
1692
1693MLXSW_ITEM32(reg, spvtr, epvid_mode, 0x04, 0, 4);
1694
1695static inline void mlxsw_reg_spvtr_pack(char *payload, bool tport,
1696 u16 local_port,
1697 enum mlxsw_reg_spvtr_ipvid_mode ipvid_mode)
1698{
1699 MLXSW_REG_ZERO(spvtr, payload);
1700 mlxsw_reg_spvtr_tport_set(payload, tport);
1701 mlxsw_reg_spvtr_local_port_set(payload, local_port);
1702 mlxsw_reg_spvtr_ipvid_mode_set(payload, ipvid_mode);
1703 mlxsw_reg_spvtr_ipve_set(payload, true);
1704}
1705
1706
1707
1708
1709
1710#define MLXSW_REG_SVPE_ID 0x201E
1711#define MLXSW_REG_SVPE_LEN 0x4
1712
1713MLXSW_REG_DEFINE(svpe, MLXSW_REG_SVPE_ID, MLXSW_REG_SVPE_LEN);
1714
1715
1716
1717
1718
1719
1720
1721MLXSW_ITEM32_LP(reg, svpe, 0x00, 16, 0x00, 12);
1722
1723
1724
1725
1726
1727
1728
1729MLXSW_ITEM32(reg, svpe, vp_en, 0x00, 8, 1);
1730
1731static inline void mlxsw_reg_svpe_pack(char *payload, u16 local_port,
1732 bool enable)
1733{
1734 MLXSW_REG_ZERO(svpe, payload);
1735 mlxsw_reg_svpe_local_port_set(payload, local_port);
1736 mlxsw_reg_svpe_vp_en_set(payload, enable);
1737}
1738
1739
1740
1741
1742
1743#define MLXSW_REG_SFMR_ID 0x201F
1744#define MLXSW_REG_SFMR_LEN 0x18
1745
1746MLXSW_REG_DEFINE(sfmr, MLXSW_REG_SFMR_ID, MLXSW_REG_SFMR_LEN);
1747
1748enum mlxsw_reg_sfmr_op {
1749 MLXSW_REG_SFMR_OP_CREATE_FID,
1750 MLXSW_REG_SFMR_OP_DESTROY_FID,
1751};
1752
1753
1754
1755
1756
1757
1758
1759MLXSW_ITEM32(reg, sfmr, op, 0x00, 24, 4);
1760
1761
1762
1763
1764
1765MLXSW_ITEM32(reg, sfmr, fid, 0x00, 0, 16);
1766
1767
1768
1769
1770
1771
1772
1773MLXSW_ITEM32(reg, sfmr, fid_offset, 0x08, 0, 16);
1774
1775
1776
1777
1778
1779
1780
1781
1782MLXSW_ITEM32(reg, sfmr, vtfp, 0x0C, 31, 1);
1783
1784
1785
1786
1787
1788
1789
1790MLXSW_ITEM32(reg, sfmr, nve_tunnel_flood_ptr, 0x0C, 0, 24);
1791
1792
1793
1794
1795
1796
1797
1798
1799MLXSW_ITEM32(reg, sfmr, vv, 0x10, 31, 1);
1800
1801
1802
1803
1804
1805
1806
1807MLXSW_ITEM32(reg, sfmr, vni, 0x10, 0, 24);
1808
1809static inline void mlxsw_reg_sfmr_pack(char *payload,
1810 enum mlxsw_reg_sfmr_op op, u16 fid,
1811 u16 fid_offset)
1812{
1813 MLXSW_REG_ZERO(sfmr, payload);
1814 mlxsw_reg_sfmr_op_set(payload, op);
1815 mlxsw_reg_sfmr_fid_set(payload, fid);
1816 mlxsw_reg_sfmr_fid_offset_set(payload, fid_offset);
1817 mlxsw_reg_sfmr_vtfp_set(payload, false);
1818 mlxsw_reg_sfmr_vv_set(payload, false);
1819}
1820
1821
1822
1823
1824
1825#define MLXSW_REG_SPVMLR_ID 0x2020
1826#define MLXSW_REG_SPVMLR_BASE_LEN 0x04
1827#define MLXSW_REG_SPVMLR_REC_LEN 0x04
1828#define MLXSW_REG_SPVMLR_REC_MAX_COUNT 255
1829#define MLXSW_REG_SPVMLR_LEN (MLXSW_REG_SPVMLR_BASE_LEN + \
1830 MLXSW_REG_SPVMLR_REC_LEN * \
1831 MLXSW_REG_SPVMLR_REC_MAX_COUNT)
1832
1833MLXSW_REG_DEFINE(spvmlr, MLXSW_REG_SPVMLR_ID, MLXSW_REG_SPVMLR_LEN);
1834
1835
1836
1837
1838
1839
1840
1841MLXSW_ITEM32_LP(reg, spvmlr, 0x00, 16, 0x00, 12);
1842
1843
1844
1845
1846
1847MLXSW_ITEM32(reg, spvmlr, num_rec, 0x00, 0, 8);
1848
1849
1850
1851
1852
1853
1854MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_learn_enable, MLXSW_REG_SPVMLR_BASE_LEN,
1855 31, 1, MLXSW_REG_SPVMLR_REC_LEN, 0x00, false);
1856
1857
1858
1859
1860
1861MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_vid, MLXSW_REG_SPVMLR_BASE_LEN, 0, 12,
1862 MLXSW_REG_SPVMLR_REC_LEN, 0x00, false);
1863
1864static inline void mlxsw_reg_spvmlr_pack(char *payload, u16 local_port,
1865 u16 vid_begin, u16 vid_end,
1866 bool learn_enable)
1867{
1868 int num_rec = vid_end - vid_begin + 1;
1869 int i;
1870
1871 WARN_ON(num_rec < 1 || num_rec > MLXSW_REG_SPVMLR_REC_MAX_COUNT);
1872
1873 MLXSW_REG_ZERO(spvmlr, payload);
1874 mlxsw_reg_spvmlr_local_port_set(payload, local_port);
1875 mlxsw_reg_spvmlr_num_rec_set(payload, num_rec);
1876
1877 for (i = 0; i < num_rec; i++) {
1878 mlxsw_reg_spvmlr_rec_learn_enable_set(payload, i, learn_enable);
1879 mlxsw_reg_spvmlr_rec_vid_set(payload, i, vid_begin + i);
1880 }
1881}
1882
1883
1884
1885
1886
1887
1888
1889#define MLXSW_REG_SPVC_ID 0x2026
1890#define MLXSW_REG_SPVC_LEN 0x0C
1891
1892MLXSW_REG_DEFINE(spvc, MLXSW_REG_SPVC_ID, MLXSW_REG_SPVC_LEN);
1893
1894
1895
1896
1897
1898
1899
1900
1901
1902MLXSW_ITEM32_LP(reg, spvc, 0x00, 16, 0x00, 12);
1903
1904
1905
1906
1907
1908
1909
1910
1911
1912
1913MLXSW_ITEM32(reg, spvc, inner_et2, 0x08, 17, 1);
1914
1915
1916
1917
1918
1919
1920
1921
1922
1923MLXSW_ITEM32(reg, spvc, et2, 0x08, 16, 1);
1924
1925
1926
1927
1928
1929
1930
1931
1932
1933
1934MLXSW_ITEM32(reg, spvc, inner_et1, 0x08, 9, 1);
1935
1936
1937
1938
1939
1940
1941
1942
1943
1944MLXSW_ITEM32(reg, spvc, et1, 0x08, 8, 1);
1945
1946
1947
1948
1949
1950
1951
1952
1953
1954
1955MLXSW_ITEM32(reg, spvc, inner_et0, 0x08, 1, 1);
1956
1957
1958
1959
1960
1961
1962
1963
1964
1965MLXSW_ITEM32(reg, spvc, et0, 0x08, 0, 1);
1966
1967static inline void mlxsw_reg_spvc_pack(char *payload, u16 local_port, bool et1,
1968 bool et0)
1969{
1970 MLXSW_REG_ZERO(spvc, payload);
1971 mlxsw_reg_spvc_local_port_set(payload, local_port);
1972
1973
1974
1975 mlxsw_reg_spvc_inner_et1_set(payload, 1);
1976 mlxsw_reg_spvc_inner_et0_set(payload, 1);
1977 mlxsw_reg_spvc_et1_set(payload, et1);
1978 mlxsw_reg_spvc_et0_set(payload, et0);
1979}
1980
1981
1982
1983
1984
1985
1986
1987#define MLXSW_REG_SPEVET_ID 0x202A
1988#define MLXSW_REG_SPEVET_LEN 0x08
1989
1990MLXSW_REG_DEFINE(spevet, MLXSW_REG_SPEVET_ID, MLXSW_REG_SPEVET_LEN);
1991
1992
1993
1994
1995
1996
1997MLXSW_ITEM32_LP(reg, spevet, 0x00, 16, 0x00, 12);
1998
1999
2000
2001
2002
2003
2004
2005
2006MLXSW_ITEM32(reg, spevet, et_vlan, 0x04, 16, 2);
2007
2008static inline void mlxsw_reg_spevet_pack(char *payload, u16 local_port,
2009 u8 et_vlan)
2010{
2011 MLXSW_REG_ZERO(spevet, payload);
2012 mlxsw_reg_spevet_local_port_set(payload, local_port);
2013 mlxsw_reg_spevet_et_vlan_set(payload, et_vlan);
2014}
2015
2016
2017
2018
2019
2020
2021#define MLXSW_REG_SFTR2_ID 0x202F
2022#define MLXSW_REG_SFTR2_LEN 0x120
2023
2024MLXSW_REG_DEFINE(sftr2, MLXSW_REG_SFTR2_ID, MLXSW_REG_SFTR2_LEN);
2025
2026
2027
2028
2029
2030MLXSW_ITEM32(reg, sftr2, swid, 0x00, 24, 8);
2031
2032
2033
2034
2035
2036
2037MLXSW_ITEM32(reg, sftr2, flood_table, 0x00, 16, 6);
2038
2039
2040
2041
2042
2043
2044MLXSW_ITEM32(reg, sftr2, index, 0x00, 0, 16);
2045
2046
2047
2048
2049
2050MLXSW_ITEM32(reg, sftr2, table_type, 0x04, 16, 3);
2051
2052
2053
2054
2055
2056MLXSW_ITEM32(reg, sftr2, range, 0x04, 0, 16);
2057
2058
2059
2060
2061
2062MLXSW_ITEM_BIT_ARRAY(reg, sftr2, port, 0x20, 0x80, 1);
2063
2064
2065
2066
2067
2068MLXSW_ITEM_BIT_ARRAY(reg, sftr2, port_mask, 0xA0, 0x80, 1);
2069
2070static inline void mlxsw_reg_sftr2_pack(char *payload,
2071 unsigned int flood_table,
2072 unsigned int index,
2073 enum mlxsw_flood_table_type table_type,
2074 unsigned int range, u16 port, bool set)
2075{
2076 MLXSW_REG_ZERO(sftr2, payload);
2077 mlxsw_reg_sftr2_swid_set(payload, 0);
2078 mlxsw_reg_sftr2_flood_table_set(payload, flood_table);
2079 mlxsw_reg_sftr2_index_set(payload, index);
2080 mlxsw_reg_sftr2_table_type_set(payload, table_type);
2081 mlxsw_reg_sftr2_range_set(payload, range);
2082 mlxsw_reg_sftr2_port_set(payload, port, set);
2083 mlxsw_reg_sftr2_port_mask_set(payload, port, 1);
2084}
2085
2086
2087
2088
2089
2090
2091
2092#define MLXSW_REG_SMID2_ID 0x2034
2093#define MLXSW_REG_SMID2_LEN 0x120
2094
2095MLXSW_REG_DEFINE(smid2, MLXSW_REG_SMID2_ID, MLXSW_REG_SMID2_LEN);
2096
2097
2098
2099
2100
2101MLXSW_ITEM32(reg, smid2, swid, 0x00, 24, 8);
2102
2103
2104
2105
2106
2107
2108MLXSW_ITEM32(reg, smid2, mid, 0x00, 0, 16);
2109
2110
2111
2112
2113
2114MLXSW_ITEM_BIT_ARRAY(reg, smid2, port, 0x20, 0x80, 1);
2115
2116
2117
2118
2119
2120MLXSW_ITEM_BIT_ARRAY(reg, smid2, port_mask, 0xA0, 0x80, 1);
2121
2122static inline void mlxsw_reg_smid2_pack(char *payload, u16 mid, u16 port,
2123 bool set)
2124{
2125 MLXSW_REG_ZERO(smid2, payload);
2126 mlxsw_reg_smid2_swid_set(payload, 0);
2127 mlxsw_reg_smid2_mid_set(payload, mid);
2128 mlxsw_reg_smid2_port_set(payload, port, set);
2129 mlxsw_reg_smid2_port_mask_set(payload, port, 1);
2130}
2131
2132
2133
2134
2135
2136#define MLXSW_REG_CWTP_ID 0x2802
2137#define MLXSW_REG_CWTP_BASE_LEN 0x28
2138#define MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN 0x08
2139#define MLXSW_REG_CWTP_LEN 0x40
2140
2141MLXSW_REG_DEFINE(cwtp, MLXSW_REG_CWTP_ID, MLXSW_REG_CWTP_LEN);
2142
2143
2144
2145
2146
2147
2148MLXSW_ITEM32_LP(reg, cwtp, 0x00, 16, 0x00, 12);
2149
2150
2151
2152
2153
2154MLXSW_ITEM32(reg, cwtp, traffic_class, 32, 0, 8);
2155
2156
2157
2158
2159
2160MLXSW_ITEM32_INDEXED(reg, cwtp, profile_min, MLXSW_REG_CWTP_BASE_LEN,
2161 0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 0, false);
2162
2163
2164
2165
2166
2167
2168MLXSW_ITEM32_INDEXED(reg, cwtp, profile_percent, MLXSW_REG_CWTP_BASE_LEN,
2169 24, 7, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false);
2170
2171
2172
2173
2174
2175MLXSW_ITEM32_INDEXED(reg, cwtp, profile_max, MLXSW_REG_CWTP_BASE_LEN,
2176 0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false);
2177
2178#define MLXSW_REG_CWTP_MIN_VALUE 64
2179#define MLXSW_REG_CWTP_MAX_PROFILE 2
2180#define MLXSW_REG_CWTP_DEFAULT_PROFILE 1
2181
2182static inline void mlxsw_reg_cwtp_pack(char *payload, u16 local_port,
2183 u8 traffic_class)
2184{
2185 int i;
2186
2187 MLXSW_REG_ZERO(cwtp, payload);
2188 mlxsw_reg_cwtp_local_port_set(payload, local_port);
2189 mlxsw_reg_cwtp_traffic_class_set(payload, traffic_class);
2190
2191 for (i = 0; i <= MLXSW_REG_CWTP_MAX_PROFILE; i++) {
2192 mlxsw_reg_cwtp_profile_min_set(payload, i,
2193 MLXSW_REG_CWTP_MIN_VALUE);
2194 mlxsw_reg_cwtp_profile_max_set(payload, i,
2195 MLXSW_REG_CWTP_MIN_VALUE);
2196 }
2197}
2198
2199#define MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile) (profile - 1)
2200
2201static inline void
2202mlxsw_reg_cwtp_profile_pack(char *payload, u8 profile, u32 min, u32 max,
2203 u32 probability)
2204{
2205 u8 index = MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile);
2206
2207 mlxsw_reg_cwtp_profile_min_set(payload, index, min);
2208 mlxsw_reg_cwtp_profile_max_set(payload, index, max);
2209 mlxsw_reg_cwtp_profile_percent_set(payload, index, probability);
2210}
2211
2212
2213
2214
2215
2216#define MLXSW_REG_CWTPM_ID 0x2803
2217#define MLXSW_REG_CWTPM_LEN 0x44
2218
2219MLXSW_REG_DEFINE(cwtpm, MLXSW_REG_CWTPM_ID, MLXSW_REG_CWTPM_LEN);
2220
2221
2222
2223
2224
2225
2226MLXSW_ITEM32_LP(reg, cwtpm, 0x00, 16, 0x00, 12);
2227
2228
2229
2230
2231
2232MLXSW_ITEM32(reg, cwtpm, traffic_class, 32, 0, 8);
2233
2234
2235
2236
2237
2238
2239
2240MLXSW_ITEM32(reg, cwtpm, ew, 36, 1, 1);
2241
2242
2243
2244
2245
2246
2247
2248MLXSW_ITEM32(reg, cwtpm, ee, 36, 0, 1);
2249
2250
2251
2252
2253
2254
2255
2256MLXSW_ITEM32(reg, cwtpm, tcp_g, 52, 0, 2);
2257
2258
2259
2260
2261
2262
2263
2264MLXSW_ITEM32(reg, cwtpm, tcp_y, 56, 16, 2);
2265
2266
2267
2268
2269
2270
2271
2272MLXSW_ITEM32(reg, cwtpm, tcp_r, 56, 0, 2);
2273
2274
2275
2276
2277
2278
2279
2280MLXSW_ITEM32(reg, cwtpm, ntcp_g, 60, 0, 2);
2281
2282
2283
2284
2285
2286
2287
2288MLXSW_ITEM32(reg, cwtpm, ntcp_y, 64, 16, 2);
2289
2290
2291
2292
2293
2294
2295
2296MLXSW_ITEM32(reg, cwtpm, ntcp_r, 64, 0, 2);
2297
2298#define MLXSW_REG_CWTPM_RESET_PROFILE 0
2299
2300static inline void mlxsw_reg_cwtpm_pack(char *payload, u16 local_port,
2301 u8 traffic_class, u8 profile,
2302 bool wred, bool ecn)
2303{
2304 MLXSW_REG_ZERO(cwtpm, payload);
2305 mlxsw_reg_cwtpm_local_port_set(payload, local_port);
2306 mlxsw_reg_cwtpm_traffic_class_set(payload, traffic_class);
2307 mlxsw_reg_cwtpm_ew_set(payload, wred);
2308 mlxsw_reg_cwtpm_ee_set(payload, ecn);
2309 mlxsw_reg_cwtpm_tcp_g_set(payload, profile);
2310 mlxsw_reg_cwtpm_tcp_y_set(payload, profile);
2311 mlxsw_reg_cwtpm_tcp_r_set(payload, profile);
2312 mlxsw_reg_cwtpm_ntcp_g_set(payload, profile);
2313 mlxsw_reg_cwtpm_ntcp_y_set(payload, profile);
2314 mlxsw_reg_cwtpm_ntcp_r_set(payload, profile);
2315}
2316
2317
2318
2319
2320
2321#define MLXSW_REG_PGCR_ID 0x3001
2322#define MLXSW_REG_PGCR_LEN 0x20
2323
2324MLXSW_REG_DEFINE(pgcr, MLXSW_REG_PGCR_ID, MLXSW_REG_PGCR_LEN);
2325
2326
2327
2328
2329
2330
2331MLXSW_ITEM32(reg, pgcr, default_action_pointer_base, 0x1C, 0, 24);
2332
2333static inline void mlxsw_reg_pgcr_pack(char *payload, u32 pointer_base)
2334{
2335 MLXSW_REG_ZERO(pgcr, payload);
2336 mlxsw_reg_pgcr_default_action_pointer_base_set(payload, pointer_base);
2337}
2338
2339
2340
2341
2342
2343#define MLXSW_REG_PPBT_ID 0x3002
2344#define MLXSW_REG_PPBT_LEN 0x14
2345
2346MLXSW_REG_DEFINE(ppbt, MLXSW_REG_PPBT_ID, MLXSW_REG_PPBT_LEN);
2347
2348enum mlxsw_reg_pxbt_e {
2349 MLXSW_REG_PXBT_E_IACL,
2350 MLXSW_REG_PXBT_E_EACL,
2351};
2352
2353
2354
2355
2356MLXSW_ITEM32(reg, ppbt, e, 0x00, 31, 1);
2357
2358enum mlxsw_reg_pxbt_op {
2359 MLXSW_REG_PXBT_OP_BIND,
2360 MLXSW_REG_PXBT_OP_UNBIND,
2361};
2362
2363
2364
2365
2366MLXSW_ITEM32(reg, ppbt, op, 0x00, 28, 3);
2367
2368
2369
2370
2371
2372MLXSW_ITEM32_LP(reg, ppbt, 0x00, 16, 0x00, 12);
2373
2374
2375
2376
2377
2378
2379
2380MLXSW_ITEM32(reg, ppbt, g, 0x10, 31, 1);
2381
2382
2383
2384
2385
2386
2387MLXSW_ITEM32(reg, ppbt, acl_info, 0x10, 0, 16);
2388
2389static inline void mlxsw_reg_ppbt_pack(char *payload, enum mlxsw_reg_pxbt_e e,
2390 enum mlxsw_reg_pxbt_op op,
2391 u16 local_port, u16 acl_info)
2392{
2393 MLXSW_REG_ZERO(ppbt, payload);
2394 mlxsw_reg_ppbt_e_set(payload, e);
2395 mlxsw_reg_ppbt_op_set(payload, op);
2396 mlxsw_reg_ppbt_local_port_set(payload, local_port);
2397 mlxsw_reg_ppbt_g_set(payload, true);
2398 mlxsw_reg_ppbt_acl_info_set(payload, acl_info);
2399}
2400
2401
2402
2403
2404
2405#define MLXSW_REG_PACL_ID 0x3004
2406#define MLXSW_REG_PACL_LEN 0x70
2407
2408MLXSW_REG_DEFINE(pacl, MLXSW_REG_PACL_ID, MLXSW_REG_PACL_LEN);
2409
2410
2411
2412
2413
2414
2415MLXSW_ITEM32(reg, pacl, v, 0x00, 24, 1);
2416
2417
2418
2419
2420
2421
2422MLXSW_ITEM32(reg, pacl, acl_id, 0x08, 0, 16);
2423
2424#define MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN 16
2425
2426
2427
2428
2429
2430
2431MLXSW_ITEM_BUF(reg, pacl, tcam_region_info, 0x30,
2432 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2433
2434static inline void mlxsw_reg_pacl_pack(char *payload, u16 acl_id,
2435 bool valid, const char *tcam_region_info)
2436{
2437 MLXSW_REG_ZERO(pacl, payload);
2438 mlxsw_reg_pacl_acl_id_set(payload, acl_id);
2439 mlxsw_reg_pacl_v_set(payload, valid);
2440 mlxsw_reg_pacl_tcam_region_info_memcpy_to(payload, tcam_region_info);
2441}
2442
2443
2444
2445
2446
2447#define MLXSW_REG_PAGT_ID 0x3005
2448#define MLXSW_REG_PAGT_BASE_LEN 0x30
2449#define MLXSW_REG_PAGT_ACL_LEN 4
2450#define MLXSW_REG_PAGT_ACL_MAX_NUM 16
2451#define MLXSW_REG_PAGT_LEN (MLXSW_REG_PAGT_BASE_LEN + \
2452 MLXSW_REG_PAGT_ACL_MAX_NUM * MLXSW_REG_PAGT_ACL_LEN)
2453
2454MLXSW_REG_DEFINE(pagt, MLXSW_REG_PAGT_ID, MLXSW_REG_PAGT_LEN);
2455
2456
2457
2458
2459
2460
2461
2462
2463
2464
2465MLXSW_ITEM32(reg, pagt, size, 0x00, 0, 8);
2466
2467
2468
2469
2470
2471
2472MLXSW_ITEM32(reg, pagt, acl_group_id, 0x08, 0, 16);
2473
2474
2475
2476
2477
2478
2479
2480MLXSW_ITEM32_INDEXED(reg, pagt, multi, 0x30, 31, 1, 0x04, 0x00, false);
2481
2482
2483
2484
2485
2486MLXSW_ITEM32_INDEXED(reg, pagt, acl_id, 0x30, 0, 16, 0x04, 0x00, false);
2487
2488static inline void mlxsw_reg_pagt_pack(char *payload, u16 acl_group_id)
2489{
2490 MLXSW_REG_ZERO(pagt, payload);
2491 mlxsw_reg_pagt_acl_group_id_set(payload, acl_group_id);
2492}
2493
2494static inline void mlxsw_reg_pagt_acl_id_pack(char *payload, int index,
2495 u16 acl_id, bool multi)
2496{
2497 u8 size = mlxsw_reg_pagt_size_get(payload);
2498
2499 if (index >= size)
2500 mlxsw_reg_pagt_size_set(payload, index + 1);
2501 mlxsw_reg_pagt_multi_set(payload, index, multi);
2502 mlxsw_reg_pagt_acl_id_set(payload, index, acl_id);
2503}
2504
2505
2506
2507
2508
2509
2510#define MLXSW_REG_PTAR_ID 0x3006
2511#define MLXSW_REG_PTAR_BASE_LEN 0x20
2512#define MLXSW_REG_PTAR_KEY_ID_LEN 1
2513#define MLXSW_REG_PTAR_KEY_ID_MAX_NUM 16
2514#define MLXSW_REG_PTAR_LEN (MLXSW_REG_PTAR_BASE_LEN + \
2515 MLXSW_REG_PTAR_KEY_ID_MAX_NUM * MLXSW_REG_PTAR_KEY_ID_LEN)
2516
2517MLXSW_REG_DEFINE(ptar, MLXSW_REG_PTAR_ID, MLXSW_REG_PTAR_LEN);
2518
2519enum mlxsw_reg_ptar_op {
2520
2521 MLXSW_REG_PTAR_OP_ALLOC,
2522
2523 MLXSW_REG_PTAR_OP_RESIZE,
2524
2525 MLXSW_REG_PTAR_OP_FREE,
2526
2527 MLXSW_REG_PTAR_OP_TEST,
2528};
2529
2530
2531
2532
2533MLXSW_ITEM32(reg, ptar, op, 0x00, 28, 4);
2534
2535
2536
2537
2538
2539
2540MLXSW_ITEM32(reg, ptar, action_set_type, 0x00, 16, 8);
2541
2542enum mlxsw_reg_ptar_key_type {
2543 MLXSW_REG_PTAR_KEY_TYPE_FLEX = 0x50,
2544 MLXSW_REG_PTAR_KEY_TYPE_FLEX2 = 0x51,
2545};
2546
2547
2548
2549
2550
2551MLXSW_ITEM32(reg, ptar, key_type, 0x00, 0, 8);
2552
2553
2554
2555
2556
2557
2558
2559
2560
2561MLXSW_ITEM32(reg, ptar, region_size, 0x04, 0, 16);
2562
2563
2564
2565
2566
2567
2568MLXSW_ITEM32(reg, ptar, region_id, 0x08, 0, 16);
2569
2570
2571
2572
2573
2574
2575
2576MLXSW_ITEM_BUF(reg, ptar, tcam_region_info, 0x10,
2577 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2578
2579
2580
2581
2582
2583
2584
2585
2586
2587MLXSW_ITEM8_INDEXED(reg, ptar, flexible_key_id, 0x20, 0, 8,
2588 MLXSW_REG_PTAR_KEY_ID_LEN, 0x00, false);
2589
2590static inline void mlxsw_reg_ptar_pack(char *payload, enum mlxsw_reg_ptar_op op,
2591 enum mlxsw_reg_ptar_key_type key_type,
2592 u16 region_size, u16 region_id,
2593 const char *tcam_region_info)
2594{
2595 MLXSW_REG_ZERO(ptar, payload);
2596 mlxsw_reg_ptar_op_set(payload, op);
2597 mlxsw_reg_ptar_action_set_type_set(payload, 2);
2598 mlxsw_reg_ptar_key_type_set(payload, key_type);
2599 mlxsw_reg_ptar_region_size_set(payload, region_size);
2600 mlxsw_reg_ptar_region_id_set(payload, region_id);
2601 mlxsw_reg_ptar_tcam_region_info_memcpy_to(payload, tcam_region_info);
2602}
2603
2604static inline void mlxsw_reg_ptar_key_id_pack(char *payload, int index,
2605 u16 key_id)
2606{
2607 mlxsw_reg_ptar_flexible_key_id_set(payload, index, key_id);
2608}
2609
2610static inline void mlxsw_reg_ptar_unpack(char *payload, char *tcam_region_info)
2611{
2612 mlxsw_reg_ptar_tcam_region_info_memcpy_from(payload, tcam_region_info);
2613}
2614
2615
2616
2617
2618
2619#define MLXSW_REG_PPBS_ID 0x300C
2620#define MLXSW_REG_PPBS_LEN 0x14
2621
2622MLXSW_REG_DEFINE(ppbs, MLXSW_REG_PPBS_ID, MLXSW_REG_PPBS_LEN);
2623
2624
2625
2626
2627
2628
2629MLXSW_ITEM32(reg, ppbs, pbs_ptr, 0x08, 0, 24);
2630
2631
2632
2633
2634
2635MLXSW_ITEM32(reg, ppbs, system_port, 0x10, 0, 16);
2636
2637static inline void mlxsw_reg_ppbs_pack(char *payload, u32 pbs_ptr,
2638 u16 system_port)
2639{
2640 MLXSW_REG_ZERO(ppbs, payload);
2641 mlxsw_reg_ppbs_pbs_ptr_set(payload, pbs_ptr);
2642 mlxsw_reg_ppbs_system_port_set(payload, system_port);
2643}
2644
2645
2646
2647
2648
2649#define MLXSW_REG_PRCR_ID 0x300D
2650#define MLXSW_REG_PRCR_LEN 0x40
2651
2652MLXSW_REG_DEFINE(prcr, MLXSW_REG_PRCR_ID, MLXSW_REG_PRCR_LEN);
2653
2654enum mlxsw_reg_prcr_op {
2655
2656
2657
2658
2659 MLXSW_REG_PRCR_OP_MOVE,
2660
2661
2662
2663
2664 MLXSW_REG_PRCR_OP_COPY,
2665};
2666
2667
2668
2669
2670MLXSW_ITEM32(reg, prcr, op, 0x00, 28, 4);
2671
2672
2673
2674
2675
2676MLXSW_ITEM32(reg, prcr, offset, 0x00, 0, 16);
2677
2678
2679
2680
2681
2682MLXSW_ITEM32(reg, prcr, size, 0x04, 0, 16);
2683
2684
2685
2686
2687
2688MLXSW_ITEM_BUF(reg, prcr, tcam_region_info, 0x10,
2689 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2690
2691
2692
2693
2694
2695MLXSW_ITEM32(reg, prcr, dest_offset, 0x20, 0, 16);
2696
2697
2698
2699
2700
2701MLXSW_ITEM_BUF(reg, prcr, dest_tcam_region_info, 0x30,
2702 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2703
2704static inline void mlxsw_reg_prcr_pack(char *payload, enum mlxsw_reg_prcr_op op,
2705 const char *src_tcam_region_info,
2706 u16 src_offset,
2707 const char *dest_tcam_region_info,
2708 u16 dest_offset, u16 size)
2709{
2710 MLXSW_REG_ZERO(prcr, payload);
2711 mlxsw_reg_prcr_op_set(payload, op);
2712 mlxsw_reg_prcr_offset_set(payload, src_offset);
2713 mlxsw_reg_prcr_size_set(payload, size);
2714 mlxsw_reg_prcr_tcam_region_info_memcpy_to(payload,
2715 src_tcam_region_info);
2716 mlxsw_reg_prcr_dest_offset_set(payload, dest_offset);
2717 mlxsw_reg_prcr_dest_tcam_region_info_memcpy_to(payload,
2718 dest_tcam_region_info);
2719}
2720
2721
2722
2723
2724
2725
2726#define MLXSW_REG_PEFA_ID 0x300F
2727#define MLXSW_REG_PEFA_LEN 0xB0
2728
2729MLXSW_REG_DEFINE(pefa, MLXSW_REG_PEFA_ID, MLXSW_REG_PEFA_LEN);
2730
2731
2732
2733
2734
2735MLXSW_ITEM32(reg, pefa, index, 0x00, 0, 24);
2736
2737
2738
2739
2740
2741
2742
2743
2744MLXSW_ITEM32(reg, pefa, a, 0x04, 29, 1);
2745
2746
2747
2748
2749
2750
2751
2752MLXSW_ITEM32(reg, pefa, ca, 0x04, 24, 1);
2753
2754#define MLXSW_REG_FLEX_ACTION_SET_LEN 0xA8
2755
2756
2757
2758
2759
2760
2761MLXSW_ITEM_BUF(reg, pefa, flex_action_set, 0x08, MLXSW_REG_FLEX_ACTION_SET_LEN);
2762
2763static inline void mlxsw_reg_pefa_pack(char *payload, u32 index, bool ca,
2764 const char *flex_action_set)
2765{
2766 MLXSW_REG_ZERO(pefa, payload);
2767 mlxsw_reg_pefa_index_set(payload, index);
2768 mlxsw_reg_pefa_ca_set(payload, ca);
2769 if (flex_action_set)
2770 mlxsw_reg_pefa_flex_action_set_memcpy_to(payload,
2771 flex_action_set);
2772}
2773
2774static inline void mlxsw_reg_pefa_unpack(char *payload, bool *p_a)
2775{
2776 *p_a = mlxsw_reg_pefa_a_get(payload);
2777}
2778
2779
2780
2781
2782
2783
2784
2785#define MLXSW_REG_PEMRBT_ID 0x3014
2786#define MLXSW_REG_PEMRBT_LEN 0x14
2787
2788MLXSW_REG_DEFINE(pemrbt, MLXSW_REG_PEMRBT_ID, MLXSW_REG_PEMRBT_LEN);
2789
2790enum mlxsw_reg_pemrbt_protocol {
2791 MLXSW_REG_PEMRBT_PROTO_IPV4,
2792 MLXSW_REG_PEMRBT_PROTO_IPV6,
2793};
2794
2795
2796
2797
2798MLXSW_ITEM32(reg, pemrbt, protocol, 0x00, 0, 1);
2799
2800
2801
2802
2803
2804
2805MLXSW_ITEM32(reg, pemrbt, group_id, 0x10, 0, 16);
2806
2807static inline void
2808mlxsw_reg_pemrbt_pack(char *payload, enum mlxsw_reg_pemrbt_protocol protocol,
2809 u16 group_id)
2810{
2811 MLXSW_REG_ZERO(pemrbt, payload);
2812 mlxsw_reg_pemrbt_protocol_set(payload, protocol);
2813 mlxsw_reg_pemrbt_group_id_set(payload, group_id);
2814}
2815
2816
2817
2818
2819
2820
2821
2822
2823#define MLXSW_REG_PTCE2_ID 0x3017
2824#define MLXSW_REG_PTCE2_LEN 0x1D8
2825
2826MLXSW_REG_DEFINE(ptce2, MLXSW_REG_PTCE2_ID, MLXSW_REG_PTCE2_LEN);
2827
2828
2829
2830
2831
2832MLXSW_ITEM32(reg, ptce2, v, 0x00, 31, 1);
2833
2834
2835
2836
2837
2838
2839MLXSW_ITEM32(reg, ptce2, a, 0x00, 30, 1);
2840
2841enum mlxsw_reg_ptce2_op {
2842
2843 MLXSW_REG_PTCE2_OP_QUERY_READ = 0,
2844
2845
2846
2847 MLXSW_REG_PTCE2_OP_QUERY_CLEAR_ON_READ = 1,
2848
2849
2850
2851
2852 MLXSW_REG_PTCE2_OP_WRITE_WRITE = 0,
2853
2854 MLXSW_REG_PTCE2_OP_WRITE_UPDATE = 1,
2855
2856 MLXSW_REG_PTCE2_OP_WRITE_CLEAR_ACTIVITY = 2,
2857};
2858
2859
2860
2861
2862MLXSW_ITEM32(reg, ptce2, op, 0x00, 20, 3);
2863
2864
2865
2866
2867MLXSW_ITEM32(reg, ptce2, offset, 0x00, 0, 16);
2868
2869
2870
2871
2872
2873
2874
2875
2876MLXSW_ITEM32(reg, ptce2, priority, 0x04, 0, 24);
2877
2878
2879
2880
2881
2882MLXSW_ITEM_BUF(reg, ptce2, tcam_region_info, 0x10,
2883 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2884
2885#define MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN 96
2886
2887
2888
2889
2890
2891MLXSW_ITEM_BUF(reg, ptce2, flex_key_blocks, 0x20,
2892 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN);
2893
2894
2895
2896
2897
2898
2899
2900MLXSW_ITEM_BUF(reg, ptce2, mask, 0x80,
2901 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN);
2902
2903
2904
2905
2906
2907MLXSW_ITEM_BUF(reg, ptce2, flex_action_set, 0xE0,
2908 MLXSW_REG_FLEX_ACTION_SET_LEN);
2909
2910static inline void mlxsw_reg_ptce2_pack(char *payload, bool valid,
2911 enum mlxsw_reg_ptce2_op op,
2912 const char *tcam_region_info,
2913 u16 offset, u32 priority)
2914{
2915 MLXSW_REG_ZERO(ptce2, payload);
2916 mlxsw_reg_ptce2_v_set(payload, valid);
2917 mlxsw_reg_ptce2_op_set(payload, op);
2918 mlxsw_reg_ptce2_offset_set(payload, offset);
2919 mlxsw_reg_ptce2_priority_set(payload, priority);
2920 mlxsw_reg_ptce2_tcam_region_info_memcpy_to(payload, tcam_region_info);
2921}
2922
2923
2924
2925
2926
2927#define MLXSW_REG_PERPT_ID 0x3021
2928#define MLXSW_REG_PERPT_LEN 0x80
2929
2930MLXSW_REG_DEFINE(perpt, MLXSW_REG_PERPT_ID, MLXSW_REG_PERPT_LEN);
2931
2932
2933
2934
2935
2936
2937MLXSW_ITEM32(reg, perpt, erpt_bank, 0x00, 16, 4);
2938
2939
2940
2941
2942
2943
2944MLXSW_ITEM32(reg, perpt, erpt_index, 0x00, 0, 8);
2945
2946enum mlxsw_reg_perpt_key_size {
2947 MLXSW_REG_PERPT_KEY_SIZE_2KB,
2948 MLXSW_REG_PERPT_KEY_SIZE_4KB,
2949 MLXSW_REG_PERPT_KEY_SIZE_8KB,
2950 MLXSW_REG_PERPT_KEY_SIZE_12KB,
2951};
2952
2953
2954
2955
2956MLXSW_ITEM32(reg, perpt, key_size, 0x04, 0, 4);
2957
2958
2959
2960
2961
2962
2963
2964
2965MLXSW_ITEM32(reg, perpt, bf_bypass, 0x08, 8, 1);
2966
2967
2968
2969
2970
2971MLXSW_ITEM32(reg, perpt, erp_id, 0x08, 0, 4);
2972
2973
2974
2975
2976
2977
2978MLXSW_ITEM32(reg, perpt, erpt_base_bank, 0x0C, 16, 4);
2979
2980
2981
2982
2983
2984
2985MLXSW_ITEM32(reg, perpt, erpt_base_index, 0x0C, 0, 8);
2986
2987
2988
2989
2990
2991MLXSW_ITEM32(reg, perpt, erp_index_in_vector, 0x10, 0, 4);
2992
2993
2994
2995
2996
2997MLXSW_ITEM_BIT_ARRAY(reg, perpt, erp_vector, 0x14, 4, 1);
2998
2999
3000
3001
3002
3003
3004
3005MLXSW_ITEM_BUF(reg, perpt, mask, 0x20, MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN);
3006
3007static inline void mlxsw_reg_perpt_erp_vector_pack(char *payload,
3008 unsigned long *erp_vector,
3009 unsigned long size)
3010{
3011 unsigned long bit;
3012
3013 for_each_set_bit(bit, erp_vector, size)
3014 mlxsw_reg_perpt_erp_vector_set(payload, bit, true);
3015}
3016
3017static inline void
3018mlxsw_reg_perpt_pack(char *payload, u8 erpt_bank, u8 erpt_index,
3019 enum mlxsw_reg_perpt_key_size key_size, u8 erp_id,
3020 u8 erpt_base_bank, u8 erpt_base_index, u8 erp_index,
3021 char *mask)
3022{
3023 MLXSW_REG_ZERO(perpt, payload);
3024 mlxsw_reg_perpt_erpt_bank_set(payload, erpt_bank);
3025 mlxsw_reg_perpt_erpt_index_set(payload, erpt_index);
3026 mlxsw_reg_perpt_key_size_set(payload, key_size);
3027 mlxsw_reg_perpt_bf_bypass_set(payload, false);
3028 mlxsw_reg_perpt_erp_id_set(payload, erp_id);
3029 mlxsw_reg_perpt_erpt_base_bank_set(payload, erpt_base_bank);
3030 mlxsw_reg_perpt_erpt_base_index_set(payload, erpt_base_index);
3031 mlxsw_reg_perpt_erp_index_in_vector_set(payload, erp_index);
3032 mlxsw_reg_perpt_mask_memcpy_to(payload, mask);
3033}
3034
3035
3036
3037
3038
3039
3040#define MLXSW_REG_PERAR_ID 0x3026
3041#define MLXSW_REG_PERAR_LEN 0x08
3042
3043MLXSW_REG_DEFINE(perar, MLXSW_REG_PERAR_ID, MLXSW_REG_PERAR_LEN);
3044
3045
3046
3047
3048
3049
3050MLXSW_ITEM32(reg, perar, region_id, 0x00, 0, 16);
3051
3052static inline unsigned int
3053mlxsw_reg_perar_hw_regions_needed(unsigned int block_num)
3054{
3055 return DIV_ROUND_UP(block_num, 4);
3056}
3057
3058
3059
3060
3061
3062
3063
3064
3065
3066MLXSW_ITEM32(reg, perar, hw_region, 0x04, 0, 16);
3067
3068static inline void mlxsw_reg_perar_pack(char *payload, u16 region_id,
3069 u16 hw_region)
3070{
3071 MLXSW_REG_ZERO(perar, payload);
3072 mlxsw_reg_perar_region_id_set(payload, region_id);
3073 mlxsw_reg_perar_hw_region_set(payload, hw_region);
3074}
3075
3076
3077
3078
3079
3080
3081#define MLXSW_REG_PTCE3_ID 0x3027
3082#define MLXSW_REG_PTCE3_LEN 0xF0
3083
3084MLXSW_REG_DEFINE(ptce3, MLXSW_REG_PTCE3_ID, MLXSW_REG_PTCE3_LEN);
3085
3086
3087
3088
3089
3090MLXSW_ITEM32(reg, ptce3, v, 0x00, 31, 1);
3091
3092enum mlxsw_reg_ptce3_op {
3093
3094
3095
3096
3097
3098 MLXSW_REG_PTCE3_OP_WRITE_WRITE = 0,
3099
3100 MLXSW_REG_PTCE3_OP_WRITE_UPDATE = 1,
3101
3102 MLXSW_REG_PTCE3_OP_QUERY_READ = 0,
3103};
3104
3105
3106
3107
3108MLXSW_ITEM32(reg, ptce3, op, 0x00, 20, 3);
3109
3110
3111
3112
3113
3114
3115
3116MLXSW_ITEM32(reg, ptce3, priority, 0x04, 0, 24);
3117
3118
3119
3120
3121
3122MLXSW_ITEM_BUF(reg, ptce3, tcam_region_info, 0x10,
3123 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
3124
3125
3126
3127
3128
3129
3130MLXSW_ITEM_BUF(reg, ptce3, flex2_key_blocks, 0x20,
3131 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN);
3132
3133
3134
3135
3136
3137MLXSW_ITEM32(reg, ptce3, erp_id, 0x80, 0, 4);
3138
3139
3140
3141
3142
3143
3144MLXSW_ITEM32(reg, ptce3, delta_start, 0x84, 0, 10);
3145
3146
3147
3148
3149
3150
3151
3152
3153
3154
3155MLXSW_ITEM32(reg, ptce3, delta_mask, 0x88, 16, 8);
3156
3157
3158
3159
3160
3161
3162MLXSW_ITEM32(reg, ptce3, delta_value, 0x88, 0, 8);
3163
3164
3165
3166
3167
3168
3169
3170
3171
3172
3173
3174MLXSW_ITEM_BIT_ARRAY(reg, ptce3, prune_vector, 0x90, 4, 1);
3175
3176
3177
3178
3179
3180
3181
3182MLXSW_ITEM32(reg, ptce3, prune_ctcam, 0x94, 31, 1);
3183
3184
3185
3186
3187
3188
3189
3190
3191
3192
3193
3194
3195MLXSW_ITEM32(reg, ptce3, large_exists, 0x98, 31, 1);
3196
3197
3198
3199
3200
3201
3202
3203
3204
3205MLXSW_ITEM32(reg, ptce3, large_entry_key_id, 0x98, 0, 24);
3206
3207
3208
3209
3210
3211
3212MLXSW_ITEM32(reg, ptce3, action_pointer, 0xA0, 0, 24);
3213
3214static inline void mlxsw_reg_ptce3_pack(char *payload, bool valid,
3215 enum mlxsw_reg_ptce3_op op,
3216 u32 priority,
3217 const char *tcam_region_info,
3218 const char *key, u8 erp_id,
3219 u16 delta_start, u8 delta_mask,
3220 u8 delta_value, bool large_exists,
3221 u32 lkey_id, u32 action_pointer)
3222{
3223 MLXSW_REG_ZERO(ptce3, payload);
3224 mlxsw_reg_ptce3_v_set(payload, valid);
3225 mlxsw_reg_ptce3_op_set(payload, op);
3226 mlxsw_reg_ptce3_priority_set(payload, priority);
3227 mlxsw_reg_ptce3_tcam_region_info_memcpy_to(payload, tcam_region_info);
3228 mlxsw_reg_ptce3_flex2_key_blocks_memcpy_to(payload, key);
3229 mlxsw_reg_ptce3_erp_id_set(payload, erp_id);
3230 mlxsw_reg_ptce3_delta_start_set(payload, delta_start);
3231 mlxsw_reg_ptce3_delta_mask_set(payload, delta_mask);
3232 mlxsw_reg_ptce3_delta_value_set(payload, delta_value);
3233 mlxsw_reg_ptce3_large_exists_set(payload, large_exists);
3234 mlxsw_reg_ptce3_large_entry_key_id_set(payload, lkey_id);
3235 mlxsw_reg_ptce3_action_pointer_set(payload, action_pointer);
3236}
3237
3238
3239
3240
3241
3242
3243#define MLXSW_REG_PERCR_ID 0x302A
3244#define MLXSW_REG_PERCR_LEN 0x80
3245
3246MLXSW_REG_DEFINE(percr, MLXSW_REG_PERCR_ID, MLXSW_REG_PERCR_LEN);
3247
3248
3249
3250
3251
3252
3253MLXSW_ITEM32(reg, percr, region_id, 0x00, 0, 16);
3254
3255
3256
3257
3258
3259MLXSW_ITEM32(reg, percr, atcam_ignore_prune, 0x04, 25, 1);
3260
3261
3262
3263
3264
3265MLXSW_ITEM32(reg, percr, ctcam_ignore_prune, 0x04, 24, 1);
3266
3267
3268
3269
3270
3271
3272
3273
3274MLXSW_ITEM32(reg, percr, bf_bypass, 0x04, 16, 1);
3275
3276
3277
3278
3279
3280
3281
3282MLXSW_ITEM_BUF(reg, percr, master_mask, 0x20, 96);
3283
3284static inline void mlxsw_reg_percr_pack(char *payload, u16 region_id)
3285{
3286 MLXSW_REG_ZERO(percr, payload);
3287 mlxsw_reg_percr_region_id_set(payload, region_id);
3288 mlxsw_reg_percr_atcam_ignore_prune_set(payload, false);
3289 mlxsw_reg_percr_ctcam_ignore_prune_set(payload, false);
3290 mlxsw_reg_percr_bf_bypass_set(payload, false);
3291}
3292
3293
3294
3295
3296
3297
3298#define MLXSW_REG_PERERP_ID 0x302B
3299#define MLXSW_REG_PERERP_LEN 0x1C
3300
3301MLXSW_REG_DEFINE(pererp, MLXSW_REG_PERERP_ID, MLXSW_REG_PERERP_LEN);
3302
3303
3304
3305
3306
3307
3308MLXSW_ITEM32(reg, pererp, region_id, 0x00, 0, 16);
3309
3310
3311
3312
3313
3314MLXSW_ITEM32(reg, pererp, ctcam_le, 0x04, 28, 1);
3315
3316
3317
3318
3319
3320MLXSW_ITEM32(reg, pererp, erpt_pointer_valid, 0x10, 31, 1);
3321
3322
3323
3324
3325
3326
3327MLXSW_ITEM32(reg, pererp, erpt_bank_pointer, 0x10, 16, 4);
3328
3329
3330
3331
3332
3333
3334
3335
3336MLXSW_ITEM32(reg, pererp, erpt_pointer, 0x10, 0, 8);
3337
3338
3339
3340
3341
3342
3343
3344
3345MLXSW_ITEM_BIT_ARRAY(reg, pererp, erpt_vector, 0x14, 4, 1);
3346
3347
3348
3349
3350
3351
3352
3353MLXSW_ITEM32(reg, pererp, master_rp_id, 0x18, 0, 4);
3354
3355static inline void mlxsw_reg_pererp_erp_vector_pack(char *payload,
3356 unsigned long *erp_vector,
3357 unsigned long size)
3358{
3359 unsigned long bit;
3360
3361 for_each_set_bit(bit, erp_vector, size)
3362 mlxsw_reg_pererp_erpt_vector_set(payload, bit, true);
3363}
3364
3365static inline void mlxsw_reg_pererp_pack(char *payload, u16 region_id,
3366 bool ctcam_le, bool erpt_pointer_valid,
3367 u8 erpt_bank_pointer, u8 erpt_pointer,
3368 u8 master_rp_id)
3369{
3370 MLXSW_REG_ZERO(pererp, payload);
3371 mlxsw_reg_pererp_region_id_set(payload, region_id);
3372 mlxsw_reg_pererp_ctcam_le_set(payload, ctcam_le);
3373 mlxsw_reg_pererp_erpt_pointer_valid_set(payload, erpt_pointer_valid);
3374 mlxsw_reg_pererp_erpt_bank_pointer_set(payload, erpt_bank_pointer);
3375 mlxsw_reg_pererp_erpt_pointer_set(payload, erpt_pointer);
3376 mlxsw_reg_pererp_master_rp_id_set(payload, master_rp_id);
3377}
3378
3379
3380
3381
3382
3383#define MLXSW_REG_PEABFE_ID 0x3022
3384#define MLXSW_REG_PEABFE_BASE_LEN 0x10
3385#define MLXSW_REG_PEABFE_BF_REC_LEN 0x4
3386#define MLXSW_REG_PEABFE_BF_REC_MAX_COUNT 256
3387#define MLXSW_REG_PEABFE_LEN (MLXSW_REG_PEABFE_BASE_LEN + \
3388 MLXSW_REG_PEABFE_BF_REC_LEN * \
3389 MLXSW_REG_PEABFE_BF_REC_MAX_COUNT)
3390
3391MLXSW_REG_DEFINE(peabfe, MLXSW_REG_PEABFE_ID, MLXSW_REG_PEABFE_LEN);
3392
3393
3394
3395
3396
3397
3398MLXSW_ITEM32(reg, peabfe, size, 0x00, 0, 9);
3399
3400
3401
3402
3403
3404
3405
3406MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_state,
3407 MLXSW_REG_PEABFE_BASE_LEN, 31, 1,
3408 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false);
3409
3410
3411
3412
3413
3414
3415MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_bank,
3416 MLXSW_REG_PEABFE_BASE_LEN, 24, 4,
3417 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false);
3418
3419
3420
3421
3422
3423
3424MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_index,
3425 MLXSW_REG_PEABFE_BASE_LEN, 0, 24,
3426 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false);
3427
3428static inline void mlxsw_reg_peabfe_pack(char *payload)
3429{
3430 MLXSW_REG_ZERO(peabfe, payload);
3431}
3432
3433static inline void mlxsw_reg_peabfe_rec_pack(char *payload, int rec_index,
3434 u8 state, u8 bank, u32 bf_index)
3435{
3436 u8 num_rec = mlxsw_reg_peabfe_size_get(payload);
3437
3438 if (rec_index >= num_rec)
3439 mlxsw_reg_peabfe_size_set(payload, rec_index + 1);
3440 mlxsw_reg_peabfe_bf_entry_state_set(payload, rec_index, state);
3441 mlxsw_reg_peabfe_bf_entry_bank_set(payload, rec_index, bank);
3442 mlxsw_reg_peabfe_bf_entry_index_set(payload, rec_index, bf_index);
3443}
3444
3445
3446
3447
3448
3449
3450
3451#define MLXSW_REG_IEDR_ID 0x3804
3452#define MLXSW_REG_IEDR_BASE_LEN 0x10
3453#define MLXSW_REG_IEDR_REC_LEN 0x8
3454#define MLXSW_REG_IEDR_REC_MAX_COUNT 64
3455#define MLXSW_REG_IEDR_LEN (MLXSW_REG_IEDR_BASE_LEN + \
3456 MLXSW_REG_IEDR_REC_LEN * \
3457 MLXSW_REG_IEDR_REC_MAX_COUNT)
3458
3459MLXSW_REG_DEFINE(iedr, MLXSW_REG_IEDR_ID, MLXSW_REG_IEDR_LEN);
3460
3461
3462
3463
3464
3465MLXSW_ITEM32(reg, iedr, num_rec, 0x00, 0, 8);
3466
3467
3468
3469
3470
3471MLXSW_ITEM32_INDEXED(reg, iedr, rec_type, MLXSW_REG_IEDR_BASE_LEN, 24, 8,
3472 MLXSW_REG_IEDR_REC_LEN, 0x00, false);
3473
3474
3475
3476
3477
3478MLXSW_ITEM32_INDEXED(reg, iedr, rec_size, MLXSW_REG_IEDR_BASE_LEN, 0, 13,
3479 MLXSW_REG_IEDR_REC_LEN, 0x00, false);
3480
3481
3482
3483
3484
3485MLXSW_ITEM32_INDEXED(reg, iedr, rec_index_start, MLXSW_REG_IEDR_BASE_LEN, 0, 24,
3486 MLXSW_REG_IEDR_REC_LEN, 0x04, false);
3487
3488static inline void mlxsw_reg_iedr_pack(char *payload)
3489{
3490 MLXSW_REG_ZERO(iedr, payload);
3491}
3492
3493static inline void mlxsw_reg_iedr_rec_pack(char *payload, int rec_index,
3494 u8 rec_type, u16 rec_size,
3495 u32 rec_index_start)
3496{
3497 u8 num_rec = mlxsw_reg_iedr_num_rec_get(payload);
3498
3499 if (rec_index >= num_rec)
3500 mlxsw_reg_iedr_num_rec_set(payload, rec_index + 1);
3501 mlxsw_reg_iedr_rec_type_set(payload, rec_index, rec_type);
3502 mlxsw_reg_iedr_rec_size_set(payload, rec_index, rec_size);
3503 mlxsw_reg_iedr_rec_index_start_set(payload, rec_index, rec_index_start);
3504}
3505
3506
3507
3508
3509
3510
3511#define MLXSW_REG_QPTS_ID 0x4002
3512#define MLXSW_REG_QPTS_LEN 0x8
3513
3514MLXSW_REG_DEFINE(qpts, MLXSW_REG_QPTS_ID, MLXSW_REG_QPTS_LEN);
3515
3516
3517
3518
3519
3520
3521
3522MLXSW_ITEM32_LP(reg, qpts, 0x00, 16, 0x00, 12);
3523
3524enum mlxsw_reg_qpts_trust_state {
3525 MLXSW_REG_QPTS_TRUST_STATE_PCP = 1,
3526 MLXSW_REG_QPTS_TRUST_STATE_DSCP = 2,
3527};
3528
3529
3530
3531
3532
3533MLXSW_ITEM32(reg, qpts, trust_state, 0x04, 0, 3);
3534
3535static inline void mlxsw_reg_qpts_pack(char *payload, u16 local_port,
3536 enum mlxsw_reg_qpts_trust_state ts)
3537{
3538 MLXSW_REG_ZERO(qpts, payload);
3539
3540 mlxsw_reg_qpts_local_port_set(payload, local_port);
3541 mlxsw_reg_qpts_trust_state_set(payload, ts);
3542}
3543
3544
3545
3546
3547
3548
3549#define MLXSW_REG_QPCR_ID 0x4004
3550#define MLXSW_REG_QPCR_LEN 0x28
3551
3552MLXSW_REG_DEFINE(qpcr, MLXSW_REG_QPCR_ID, MLXSW_REG_QPCR_LEN);
3553
3554enum mlxsw_reg_qpcr_g {
3555 MLXSW_REG_QPCR_G_GLOBAL = 2,
3556 MLXSW_REG_QPCR_G_STORM_CONTROL = 3,
3557};
3558
3559
3560
3561
3562
3563MLXSW_ITEM32(reg, qpcr, g, 0x00, 14, 2);
3564
3565
3566
3567
3568
3569MLXSW_ITEM32(reg, qpcr, pid, 0x00, 0, 14);
3570
3571
3572
3573
3574
3575MLXSW_ITEM32(reg, qpcr, clear_counter, 0x04, 31, 1);
3576
3577
3578
3579
3580
3581
3582MLXSW_ITEM32(reg, qpcr, color_aware, 0x04, 15, 1);
3583
3584
3585
3586
3587
3588
3589
3590MLXSW_ITEM32(reg, qpcr, bytes, 0x04, 14, 1);
3591
3592enum mlxsw_reg_qpcr_ir_units {
3593 MLXSW_REG_QPCR_IR_UNITS_M,
3594 MLXSW_REG_QPCR_IR_UNITS_K,
3595};
3596
3597
3598
3599
3600
3601
3602
3603MLXSW_ITEM32(reg, qpcr, ir_units, 0x04, 12, 1);
3604
3605enum mlxsw_reg_qpcr_rate_type {
3606 MLXSW_REG_QPCR_RATE_TYPE_SINGLE = 1,
3607 MLXSW_REG_QPCR_RATE_TYPE_DOUBLE = 2,
3608};
3609
3610
3611
3612
3613
3614
3615
3616MLXSW_ITEM32(reg, qpcr, rate_type, 0x04, 8, 2);
3617
3618
3619
3620
3621
3622
3623
3624
3625
3626
3627
3628
3629MLXSW_ITEM32(reg, qpcr, cbs, 0x08, 24, 6);
3630
3631
3632
3633
3634
3635
3636
3637
3638MLXSW_ITEM32(reg, qpcr, cir, 0x0C, 0, 32);
3639
3640
3641
3642
3643
3644
3645
3646
3647
3648MLXSW_ITEM32(reg, qpcr, eir, 0x10, 0, 32);
3649
3650#define MLXSW_REG_QPCR_DOUBLE_RATE_ACTION 2
3651
3652
3653
3654
3655
3656MLXSW_ITEM32(reg, qpcr, exceed_action, 0x14, 0, 4);
3657
3658enum mlxsw_reg_qpcr_action {
3659
3660 MLXSW_REG_QPCR_ACTION_DISCARD = 1,
3661
3662
3663
3664 MLXSW_REG_QPCR_ACTION_FORWARD = 2,
3665};
3666
3667
3668
3669
3670
3671
3672MLXSW_ITEM32(reg, qpcr, violate_action, 0x18, 0, 4);
3673
3674
3675
3676
3677
3678MLXSW_ITEM64(reg, qpcr, violate_count, 0x20, 0, 64);
3679
3680
3681#define MLXSW_REG_QPCR_LOWEST_CIR 1
3682#define MLXSW_REG_QPCR_HIGHEST_CIR (2 * 1000 * 1000 * 1000)
3683#define MLXSW_REG_QPCR_LOWEST_CBS 4
3684#define MLXSW_REG_QPCR_HIGHEST_CBS 24
3685
3686
3687#define MLXSW_REG_QPCR_LOWEST_CIR_BITS 1024
3688#define MLXSW_REG_QPCR_HIGHEST_CIR_BITS 2000000000000ULL
3689#define MLXSW_REG_QPCR_LOWEST_CBS_BITS_SP1 4
3690#define MLXSW_REG_QPCR_LOWEST_CBS_BITS_SP2 4
3691#define MLXSW_REG_QPCR_HIGHEST_CBS_BITS_SP1 25
3692#define MLXSW_REG_QPCR_HIGHEST_CBS_BITS_SP2 31
3693
3694static inline void mlxsw_reg_qpcr_pack(char *payload, u16 pid,
3695 enum mlxsw_reg_qpcr_ir_units ir_units,
3696 bool bytes, u32 cir, u16 cbs)
3697{
3698 MLXSW_REG_ZERO(qpcr, payload);
3699 mlxsw_reg_qpcr_pid_set(payload, pid);
3700 mlxsw_reg_qpcr_g_set(payload, MLXSW_REG_QPCR_G_GLOBAL);
3701 mlxsw_reg_qpcr_rate_type_set(payload, MLXSW_REG_QPCR_RATE_TYPE_SINGLE);
3702 mlxsw_reg_qpcr_violate_action_set(payload,
3703 MLXSW_REG_QPCR_ACTION_DISCARD);
3704 mlxsw_reg_qpcr_cir_set(payload, cir);
3705 mlxsw_reg_qpcr_ir_units_set(payload, ir_units);
3706 mlxsw_reg_qpcr_bytes_set(payload, bytes);
3707 mlxsw_reg_qpcr_cbs_set(payload, cbs);
3708}
3709
3710
3711
3712
3713
3714
3715#define MLXSW_REG_QTCT_ID 0x400A
3716#define MLXSW_REG_QTCT_LEN 0x08
3717
3718MLXSW_REG_DEFINE(qtct, MLXSW_REG_QTCT_ID, MLXSW_REG_QTCT_LEN);
3719
3720
3721
3722
3723
3724
3725
3726MLXSW_ITEM32_LP(reg, qtct, 0x00, 16, 0x00, 12);
3727
3728
3729
3730
3731
3732
3733MLXSW_ITEM32(reg, qtct, sub_port, 0x00, 8, 8);
3734
3735
3736
3737
3738
3739MLXSW_ITEM32(reg, qtct, switch_prio, 0x00, 0, 4);
3740
3741
3742
3743
3744
3745
3746
3747
3748
3749MLXSW_ITEM32(reg, qtct, tclass, 0x04, 0, 4);
3750
3751static inline void mlxsw_reg_qtct_pack(char *payload, u16 local_port,
3752 u8 switch_prio, u8 tclass)
3753{
3754 MLXSW_REG_ZERO(qtct, payload);
3755 mlxsw_reg_qtct_local_port_set(payload, local_port);
3756 mlxsw_reg_qtct_switch_prio_set(payload, switch_prio);
3757 mlxsw_reg_qtct_tclass_set(payload, tclass);
3758}
3759
3760
3761
3762
3763
3764#define MLXSW_REG_QEEC_ID 0x400D
3765#define MLXSW_REG_QEEC_LEN 0x20
3766
3767MLXSW_REG_DEFINE(qeec, MLXSW_REG_QEEC_ID, MLXSW_REG_QEEC_LEN);
3768
3769
3770
3771
3772
3773
3774
3775MLXSW_ITEM32_LP(reg, qeec, 0x00, 16, 0x00, 12);
3776
3777enum mlxsw_reg_qeec_hr {
3778 MLXSW_REG_QEEC_HR_PORT,
3779 MLXSW_REG_QEEC_HR_GROUP,
3780 MLXSW_REG_QEEC_HR_SUBGROUP,
3781 MLXSW_REG_QEEC_HR_TC,
3782};
3783
3784
3785
3786
3787
3788
3789
3790
3791MLXSW_ITEM32(reg, qeec, element_hierarchy, 0x04, 16, 4);
3792
3793
3794
3795
3796
3797MLXSW_ITEM32(reg, qeec, element_index, 0x04, 0, 8);
3798
3799
3800
3801
3802
3803
3804
3805MLXSW_ITEM32(reg, qeec, next_element_index, 0x08, 0, 8);
3806
3807
3808
3809
3810
3811
3812
3813
3814MLXSW_ITEM32(reg, qeec, mise, 0x0C, 31, 1);
3815
3816
3817
3818
3819
3820
3821
3822
3823
3824
3825
3826MLXSW_ITEM32(reg, qeec, ptps, 0x0C, 29, 1);
3827
3828enum {
3829 MLXSW_REG_QEEC_BYTES_MODE,
3830 MLXSW_REG_QEEC_PACKETS_MODE,
3831};
3832
3833
3834
3835
3836
3837
3838
3839
3840
3841
3842MLXSW_ITEM32(reg, qeec, pb, 0x0C, 28, 1);
3843
3844
3845#define MLXSW_REG_QEEC_MIS_MIN 200000
3846
3847
3848
3849
3850
3851
3852
3853MLXSW_ITEM32(reg, qeec, min_shaper_rate, 0x0C, 0, 28);
3854
3855
3856
3857
3858
3859
3860
3861
3862MLXSW_ITEM32(reg, qeec, mase, 0x10, 31, 1);
3863
3864
3865#define MLXSW_REG_QEEC_MAS_DIS ((1u << 31) - 1)
3866
3867
3868
3869
3870
3871
3872
3873MLXSW_ITEM32(reg, qeec, max_shaper_rate, 0x10, 0, 31);
3874
3875
3876
3877
3878
3879
3880
3881
3882MLXSW_ITEM32(reg, qeec, de, 0x18, 31, 1);
3883
3884
3885
3886
3887
3888
3889
3890
3891MLXSW_ITEM32(reg, qeec, dwrr, 0x18, 15, 1);
3892
3893
3894
3895
3896
3897
3898
3899
3900
3901MLXSW_ITEM32(reg, qeec, dwrr_weight, 0x18, 0, 8);
3902
3903
3904
3905
3906
3907
3908
3909
3910
3911MLXSW_ITEM32(reg, qeec, max_shaper_bs, 0x1C, 0, 6);
3912
3913#define MLXSW_REG_QEEC_HIGHEST_SHAPER_BS 25
3914#define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP1 5
3915#define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP2 11
3916#define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP3 11
3917#define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP4 11
3918
3919static inline void mlxsw_reg_qeec_pack(char *payload, u16 local_port,
3920 enum mlxsw_reg_qeec_hr hr, u8 index,
3921 u8 next_index)
3922{
3923 MLXSW_REG_ZERO(qeec, payload);
3924 mlxsw_reg_qeec_local_port_set(payload, local_port);
3925 mlxsw_reg_qeec_element_hierarchy_set(payload, hr);
3926 mlxsw_reg_qeec_element_index_set(payload, index);
3927 mlxsw_reg_qeec_next_element_index_set(payload, next_index);
3928}
3929
3930static inline void mlxsw_reg_qeec_ptps_pack(char *payload, u16 local_port,
3931 bool ptps)
3932{
3933 MLXSW_REG_ZERO(qeec, payload);
3934 mlxsw_reg_qeec_local_port_set(payload, local_port);
3935 mlxsw_reg_qeec_element_hierarchy_set(payload, MLXSW_REG_QEEC_HR_PORT);
3936 mlxsw_reg_qeec_ptps_set(payload, ptps);
3937}
3938
3939
3940
3941
3942
3943#define MLXSW_REG_QRWE_ID 0x400F
3944#define MLXSW_REG_QRWE_LEN 0x08
3945
3946MLXSW_REG_DEFINE(qrwe, MLXSW_REG_QRWE_ID, MLXSW_REG_QRWE_LEN);
3947
3948
3949
3950
3951
3952
3953
3954MLXSW_ITEM32_LP(reg, qrwe, 0x00, 16, 0x00, 12);
3955
3956
3957
3958
3959
3960MLXSW_ITEM32(reg, qrwe, dscp, 0x04, 1, 1);
3961
3962
3963
3964
3965
3966MLXSW_ITEM32(reg, qrwe, pcp, 0x04, 0, 1);
3967
3968static inline void mlxsw_reg_qrwe_pack(char *payload, u16 local_port,
3969 bool rewrite_pcp, bool rewrite_dscp)
3970{
3971 MLXSW_REG_ZERO(qrwe, payload);
3972 mlxsw_reg_qrwe_local_port_set(payload, local_port);
3973 mlxsw_reg_qrwe_pcp_set(payload, rewrite_pcp);
3974 mlxsw_reg_qrwe_dscp_set(payload, rewrite_dscp);
3975}
3976
3977
3978
3979
3980
3981#define MLXSW_REG_QPDSM_ID 0x4011
3982#define MLXSW_REG_QPDSM_BASE_LEN 0x04
3983#define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN 0x4
3984#define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT 16
3985#define MLXSW_REG_QPDSM_LEN (MLXSW_REG_QPDSM_BASE_LEN + \
3986 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN * \
3987 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT)
3988
3989MLXSW_REG_DEFINE(qpdsm, MLXSW_REG_QPDSM_ID, MLXSW_REG_QPDSM_LEN);
3990
3991
3992
3993
3994
3995MLXSW_ITEM32_LP(reg, qpdsm, 0x00, 16, 0x00, 12);
3996
3997
3998
3999
4000
4001MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_e,
4002 MLXSW_REG_QPDSM_BASE_LEN, 31, 1,
4003 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
4004
4005
4006
4007
4008
4009
4010MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_dscp,
4011 MLXSW_REG_QPDSM_BASE_LEN, 24, 6,
4012 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
4013
4014
4015
4016
4017
4018MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_e,
4019 MLXSW_REG_QPDSM_BASE_LEN, 23, 1,
4020 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
4021
4022
4023
4024
4025
4026
4027MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_dscp,
4028 MLXSW_REG_QPDSM_BASE_LEN, 16, 6,
4029 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
4030
4031
4032
4033
4034
4035MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_e,
4036 MLXSW_REG_QPDSM_BASE_LEN, 15, 1,
4037 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
4038
4039
4040
4041
4042
4043
4044MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_dscp,
4045 MLXSW_REG_QPDSM_BASE_LEN, 8, 6,
4046 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
4047
4048static inline void mlxsw_reg_qpdsm_pack(char *payload, u16 local_port)
4049{
4050 MLXSW_REG_ZERO(qpdsm, payload);
4051 mlxsw_reg_qpdsm_local_port_set(payload, local_port);
4052}
4053
4054static inline void
4055mlxsw_reg_qpdsm_prio_pack(char *payload, unsigned short prio, u8 dscp)
4056{
4057 mlxsw_reg_qpdsm_prio_entry_color0_e_set(payload, prio, 1);
4058 mlxsw_reg_qpdsm_prio_entry_color0_dscp_set(payload, prio, dscp);
4059 mlxsw_reg_qpdsm_prio_entry_color1_e_set(payload, prio, 1);
4060 mlxsw_reg_qpdsm_prio_entry_color1_dscp_set(payload, prio, dscp);
4061 mlxsw_reg_qpdsm_prio_entry_color2_e_set(payload, prio, 1);
4062 mlxsw_reg_qpdsm_prio_entry_color2_dscp_set(payload, prio, dscp);
4063}
4064
4065
4066
4067
4068
4069
4070
4071
4072#define MLXSW_REG_QPDP_ID 0x4007
4073#define MLXSW_REG_QPDP_LEN 0x8
4074
4075MLXSW_REG_DEFINE(qpdp, MLXSW_REG_QPDP_ID, MLXSW_REG_QPDP_LEN);
4076
4077
4078
4079
4080
4081MLXSW_ITEM32_LP(reg, qpdp, 0x00, 16, 0x00, 12);
4082
4083
4084
4085
4086
4087MLXSW_ITEM32(reg, qpdp, switch_prio, 0x04, 0, 4);
4088
4089static inline void mlxsw_reg_qpdp_pack(char *payload, u16 local_port,
4090 u8 switch_prio)
4091{
4092 MLXSW_REG_ZERO(qpdp, payload);
4093 mlxsw_reg_qpdp_local_port_set(payload, local_port);
4094 mlxsw_reg_qpdp_switch_prio_set(payload, switch_prio);
4095}
4096
4097
4098
4099
4100
4101
4102#define MLXSW_REG_QPDPM_ID 0x4013
4103#define MLXSW_REG_QPDPM_BASE_LEN 0x4
4104#define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN 0x2
4105#define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT 64
4106#define MLXSW_REG_QPDPM_LEN (MLXSW_REG_QPDPM_BASE_LEN + \
4107 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN * \
4108 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT)
4109
4110MLXSW_REG_DEFINE(qpdpm, MLXSW_REG_QPDPM_ID, MLXSW_REG_QPDPM_LEN);
4111
4112
4113
4114
4115
4116MLXSW_ITEM32_LP(reg, qpdpm, 0x00, 16, 0x00, 12);
4117
4118
4119
4120
4121
4122
4123
4124MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_e, MLXSW_REG_QPDPM_BASE_LEN, 15, 1,
4125 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false);
4126
4127
4128
4129
4130
4131MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_prio,
4132 MLXSW_REG_QPDPM_BASE_LEN, 0, 4,
4133 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false);
4134
4135static inline void mlxsw_reg_qpdpm_pack(char *payload, u16 local_port)
4136{
4137 MLXSW_REG_ZERO(qpdpm, payload);
4138 mlxsw_reg_qpdpm_local_port_set(payload, local_port);
4139}
4140
4141static inline void
4142mlxsw_reg_qpdpm_dscp_pack(char *payload, unsigned short dscp, u8 prio)
4143{
4144 mlxsw_reg_qpdpm_dscp_entry_e_set(payload, dscp, 1);
4145 mlxsw_reg_qpdpm_dscp_entry_prio_set(payload, dscp, prio);
4146}
4147
4148
4149
4150
4151
4152
4153
4154
4155
4156
4157#define MLXSW_REG_QTCTM_ID 0x401A
4158#define MLXSW_REG_QTCTM_LEN 0x08
4159
4160MLXSW_REG_DEFINE(qtctm, MLXSW_REG_QTCTM_ID, MLXSW_REG_QTCTM_LEN);
4161
4162
4163
4164
4165
4166
4167MLXSW_ITEM32_LP(reg, qtctm, 0x00, 16, 0x00, 12);
4168
4169
4170
4171
4172
4173
4174MLXSW_ITEM32(reg, qtctm, mc, 0x04, 0, 1);
4175
4176static inline void
4177mlxsw_reg_qtctm_pack(char *payload, u16 local_port, bool mc)
4178{
4179 MLXSW_REG_ZERO(qtctm, payload);
4180 mlxsw_reg_qtctm_local_port_set(payload, local_port);
4181 mlxsw_reg_qtctm_mc_set(payload, mc);
4182}
4183
4184
4185
4186
4187
4188
4189#define MLXSW_REG_QPSC_ID 0x401B
4190#define MLXSW_REG_QPSC_LEN 0x28
4191
4192MLXSW_REG_DEFINE(qpsc, MLXSW_REG_QPSC_ID, MLXSW_REG_QPSC_LEN);
4193
4194enum mlxsw_reg_qpsc_port_speed {
4195 MLXSW_REG_QPSC_PORT_SPEED_100M,
4196 MLXSW_REG_QPSC_PORT_SPEED_1G,
4197 MLXSW_REG_QPSC_PORT_SPEED_10G,
4198 MLXSW_REG_QPSC_PORT_SPEED_25G,
4199};
4200
4201
4202
4203
4204
4205MLXSW_ITEM32(reg, qpsc, port_speed, 0x00, 0, 4);
4206
4207
4208
4209
4210
4211
4212
4213MLXSW_ITEM32(reg, qpsc, shaper_time_exp, 0x04, 16, 4);
4214
4215
4216
4217
4218
4219
4220
4221MLXSW_ITEM32(reg, qpsc, shaper_time_mantissa, 0x04, 0, 5);
4222
4223
4224
4225
4226
4227
4228MLXSW_ITEM32(reg, qpsc, shaper_inc, 0x08, 0, 5);
4229
4230
4231
4232
4233
4234
4235
4236MLXSW_ITEM32(reg, qpsc, shaper_bs, 0x0C, 0, 6);
4237
4238
4239
4240
4241
4242MLXSW_ITEM32(reg, qpsc, ptsc_we, 0x10, 31, 1);
4243
4244
4245
4246
4247
4248
4249
4250MLXSW_ITEM32(reg, qpsc, port_to_shaper_credits, 0x10, 0, 8);
4251
4252
4253
4254
4255
4256
4257
4258
4259
4260MLXSW_ITEM32(reg, qpsc, ing_timestamp_inc, 0x20, 0, 32);
4261
4262
4263
4264
4265
4266
4267
4268
4269
4270MLXSW_ITEM32(reg, qpsc, egr_timestamp_inc, 0x24, 0, 32);
4271
4272static inline void
4273mlxsw_reg_qpsc_pack(char *payload, enum mlxsw_reg_qpsc_port_speed port_speed,
4274 u8 shaper_time_exp, u8 shaper_time_mantissa, u8 shaper_inc,
4275 u8 shaper_bs, u8 port_to_shaper_credits,
4276 int ing_timestamp_inc, int egr_timestamp_inc)
4277{
4278 MLXSW_REG_ZERO(qpsc, payload);
4279 mlxsw_reg_qpsc_port_speed_set(payload, port_speed);
4280 mlxsw_reg_qpsc_shaper_time_exp_set(payload, shaper_time_exp);
4281 mlxsw_reg_qpsc_shaper_time_mantissa_set(payload, shaper_time_mantissa);
4282 mlxsw_reg_qpsc_shaper_inc_set(payload, shaper_inc);
4283 mlxsw_reg_qpsc_shaper_bs_set(payload, shaper_bs);
4284 mlxsw_reg_qpsc_ptsc_we_set(payload, true);
4285 mlxsw_reg_qpsc_port_to_shaper_credits_set(payload, port_to_shaper_credits);
4286 mlxsw_reg_qpsc_ing_timestamp_inc_set(payload, ing_timestamp_inc);
4287 mlxsw_reg_qpsc_egr_timestamp_inc_set(payload, egr_timestamp_inc);
4288}
4289
4290
4291
4292
4293
4294#define MLXSW_REG_PMLP_ID 0x5002
4295#define MLXSW_REG_PMLP_LEN 0x40
4296
4297MLXSW_REG_DEFINE(pmlp, MLXSW_REG_PMLP_ID, MLXSW_REG_PMLP_LEN);
4298
4299
4300
4301
4302
4303
4304MLXSW_ITEM32(reg, pmlp, rxtx, 0x00, 31, 1);
4305
4306
4307
4308
4309
4310MLXSW_ITEM32_LP(reg, pmlp, 0x00, 16, 0x00, 12);
4311
4312
4313
4314
4315
4316
4317
4318
4319
4320MLXSW_ITEM32(reg, pmlp, width, 0x00, 0, 8);
4321
4322
4323
4324
4325
4326MLXSW_ITEM32_INDEXED(reg, pmlp, module, 0x04, 0, 8, 0x04, 0x00, false);
4327
4328
4329
4330
4331
4332MLXSW_ITEM32_INDEXED(reg, pmlp, tx_lane, 0x04, 16, 4, 0x04, 0x00, false);
4333
4334
4335
4336
4337
4338
4339MLXSW_ITEM32_INDEXED(reg, pmlp, rx_lane, 0x04, 24, 4, 0x04, 0x00, false);
4340
4341static inline void mlxsw_reg_pmlp_pack(char *payload, u16 local_port)
4342{
4343 MLXSW_REG_ZERO(pmlp, payload);
4344 mlxsw_reg_pmlp_local_port_set(payload, local_port);
4345}
4346
4347
4348
4349
4350
4351#define MLXSW_REG_PMTU_ID 0x5003
4352#define MLXSW_REG_PMTU_LEN 0x10
4353
4354MLXSW_REG_DEFINE(pmtu, MLXSW_REG_PMTU_ID, MLXSW_REG_PMTU_LEN);
4355
4356
4357
4358
4359
4360MLXSW_ITEM32_LP(reg, pmtu, 0x00, 16, 0x00, 12);
4361
4362
4363
4364
4365
4366
4367
4368
4369MLXSW_ITEM32(reg, pmtu, max_mtu, 0x04, 16, 16);
4370
4371
4372
4373
4374
4375
4376
4377MLXSW_ITEM32(reg, pmtu, admin_mtu, 0x08, 16, 16);
4378
4379
4380
4381
4382
4383
4384
4385
4386MLXSW_ITEM32(reg, pmtu, oper_mtu, 0x0C, 16, 16);
4387
4388static inline void mlxsw_reg_pmtu_pack(char *payload, u16 local_port,
4389 u16 new_mtu)
4390{
4391 MLXSW_REG_ZERO(pmtu, payload);
4392 mlxsw_reg_pmtu_local_port_set(payload, local_port);
4393 mlxsw_reg_pmtu_max_mtu_set(payload, 0);
4394 mlxsw_reg_pmtu_admin_mtu_set(payload, new_mtu);
4395 mlxsw_reg_pmtu_oper_mtu_set(payload, 0);
4396}
4397
4398
4399
4400
4401
4402
4403
4404
4405#define MLXSW_REG_PTYS_ID 0x5004
4406#define MLXSW_REG_PTYS_LEN 0x40
4407
4408MLXSW_REG_DEFINE(ptys, MLXSW_REG_PTYS_ID, MLXSW_REG_PTYS_LEN);
4409
4410
4411
4412
4413
4414
4415
4416MLXSW_ITEM32(reg, ptys, an_disable_admin, 0x00, 30, 1);
4417
4418
4419
4420
4421
4422MLXSW_ITEM32_LP(reg, ptys, 0x00, 16, 0x00, 12);
4423
4424#define MLXSW_REG_PTYS_PROTO_MASK_IB BIT(0)
4425#define MLXSW_REG_PTYS_PROTO_MASK_ETH BIT(2)
4426
4427
4428
4429
4430
4431
4432
4433
4434MLXSW_ITEM32(reg, ptys, proto_mask, 0x00, 0, 3);
4435
4436enum {
4437 MLXSW_REG_PTYS_AN_STATUS_NA,
4438 MLXSW_REG_PTYS_AN_STATUS_OK,
4439 MLXSW_REG_PTYS_AN_STATUS_FAIL,
4440};
4441
4442
4443
4444
4445
4446MLXSW_ITEM32(reg, ptys, an_status, 0x04, 28, 4);
4447
4448#define MLXSW_REG_PTYS_EXT_ETH_SPEED_SGMII_100M BIT(0)
4449#define MLXSW_REG_PTYS_EXT_ETH_SPEED_1000BASE_X_SGMII BIT(1)
4450#define MLXSW_REG_PTYS_EXT_ETH_SPEED_5GBASE_R BIT(3)
4451#define MLXSW_REG_PTYS_EXT_ETH_SPEED_XFI_XAUI_1_10G BIT(4)
4452#define MLXSW_REG_PTYS_EXT_ETH_SPEED_XLAUI_4_XLPPI_4_40G BIT(5)
4453#define MLXSW_REG_PTYS_EXT_ETH_SPEED_25GAUI_1_25GBASE_CR_KR BIT(6)
4454#define MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_2_LAUI_2_50GBASE_CR2_KR2 BIT(7)
4455#define MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_1_LAUI_1_50GBASE_CR_KR BIT(8)
4456#define MLXSW_REG_PTYS_EXT_ETH_SPEED_CAUI_4_100GBASE_CR4_KR4 BIT(9)
4457#define MLXSW_REG_PTYS_EXT_ETH_SPEED_100GAUI_2_100GBASE_CR2_KR2 BIT(10)
4458#define MLXSW_REG_PTYS_EXT_ETH_SPEED_200GAUI_4_200GBASE_CR4_KR4 BIT(12)
4459#define MLXSW_REG_PTYS_EXT_ETH_SPEED_400GAUI_8 BIT(15)
4460
4461
4462
4463
4464
4465MLXSW_ITEM32(reg, ptys, ext_eth_proto_cap, 0x08, 0, 32);
4466
4467#define MLXSW_REG_PTYS_ETH_SPEED_SGMII BIT(0)
4468#define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX BIT(1)
4469#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 BIT(2)
4470#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 BIT(3)
4471#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR BIT(4)
4472#define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 BIT(6)
4473#define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 BIT(7)
4474#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR BIT(12)
4475#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR BIT(13)
4476#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR BIT(14)
4477#define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 BIT(15)
4478#define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4 BIT(16)
4479#define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2 BIT(18)
4480#define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 BIT(19)
4481#define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 BIT(20)
4482#define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 BIT(21)
4483#define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 BIT(22)
4484#define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4 BIT(23)
4485#define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR BIT(27)
4486#define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR BIT(28)
4487#define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR BIT(29)
4488#define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 BIT(30)
4489#define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2 BIT(31)
4490
4491
4492
4493
4494
4495MLXSW_ITEM32(reg, ptys, eth_proto_cap, 0x0C, 0, 32);
4496
4497
4498
4499
4500
4501MLXSW_ITEM32(reg, ptys, ib_link_width_cap, 0x10, 16, 16);
4502
4503#define MLXSW_REG_PTYS_IB_SPEED_SDR BIT(0)
4504#define MLXSW_REG_PTYS_IB_SPEED_DDR BIT(1)
4505#define MLXSW_REG_PTYS_IB_SPEED_QDR BIT(2)
4506#define MLXSW_REG_PTYS_IB_SPEED_FDR10 BIT(3)
4507#define MLXSW_REG_PTYS_IB_SPEED_FDR BIT(4)
4508#define MLXSW_REG_PTYS_IB_SPEED_EDR BIT(5)
4509
4510
4511
4512
4513
4514MLXSW_ITEM32(reg, ptys, ib_proto_cap, 0x10, 0, 16);
4515
4516
4517
4518
4519
4520MLXSW_ITEM32(reg, ptys, ext_eth_proto_admin, 0x14, 0, 32);
4521
4522
4523
4524
4525
4526MLXSW_ITEM32(reg, ptys, eth_proto_admin, 0x18, 0, 32);
4527
4528
4529
4530
4531
4532MLXSW_ITEM32(reg, ptys, ib_link_width_admin, 0x1C, 16, 16);
4533
4534
4535
4536
4537
4538MLXSW_ITEM32(reg, ptys, ib_proto_admin, 0x1C, 0, 16);
4539
4540
4541
4542
4543
4544MLXSW_ITEM32(reg, ptys, ext_eth_proto_oper, 0x20, 0, 32);
4545
4546
4547
4548
4549
4550MLXSW_ITEM32(reg, ptys, eth_proto_oper, 0x24, 0, 32);
4551
4552
4553
4554
4555
4556MLXSW_ITEM32(reg, ptys, ib_link_width_oper, 0x28, 16, 16);
4557
4558
4559
4560
4561
4562MLXSW_ITEM32(reg, ptys, ib_proto_oper, 0x28, 0, 16);
4563
4564enum mlxsw_reg_ptys_connector_type {
4565 MLXSW_REG_PTYS_CONNECTOR_TYPE_UNKNOWN_OR_NO_CONNECTOR,
4566 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_NONE,
4567 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_TP,
4568 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_AUI,
4569 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_BNC,
4570 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_MII,
4571 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_FIBRE,
4572 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_DA,
4573 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_OTHER,
4574};
4575
4576
4577
4578
4579
4580MLXSW_ITEM32(reg, ptys, connector_type, 0x2C, 0, 4);
4581
4582static inline void mlxsw_reg_ptys_eth_pack(char *payload, u16 local_port,
4583 u32 proto_admin, bool autoneg)
4584{
4585 MLXSW_REG_ZERO(ptys, payload);
4586 mlxsw_reg_ptys_local_port_set(payload, local_port);
4587 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH);
4588 mlxsw_reg_ptys_eth_proto_admin_set(payload, proto_admin);
4589 mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg);
4590}
4591
4592static inline void mlxsw_reg_ptys_ext_eth_pack(char *payload, u16 local_port,
4593 u32 proto_admin, bool autoneg)
4594{
4595 MLXSW_REG_ZERO(ptys, payload);
4596 mlxsw_reg_ptys_local_port_set(payload, local_port);
4597 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH);
4598 mlxsw_reg_ptys_ext_eth_proto_admin_set(payload, proto_admin);
4599 mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg);
4600}
4601
4602static inline void mlxsw_reg_ptys_eth_unpack(char *payload,
4603 u32 *p_eth_proto_cap,
4604 u32 *p_eth_proto_admin,
4605 u32 *p_eth_proto_oper)
4606{
4607 if (p_eth_proto_cap)
4608 *p_eth_proto_cap =
4609 mlxsw_reg_ptys_eth_proto_cap_get(payload);
4610 if (p_eth_proto_admin)
4611 *p_eth_proto_admin =
4612 mlxsw_reg_ptys_eth_proto_admin_get(payload);
4613 if (p_eth_proto_oper)
4614 *p_eth_proto_oper =
4615 mlxsw_reg_ptys_eth_proto_oper_get(payload);
4616}
4617
4618static inline void mlxsw_reg_ptys_ext_eth_unpack(char *payload,
4619 u32 *p_eth_proto_cap,
4620 u32 *p_eth_proto_admin,
4621 u32 *p_eth_proto_oper)
4622{
4623 if (p_eth_proto_cap)
4624 *p_eth_proto_cap =
4625 mlxsw_reg_ptys_ext_eth_proto_cap_get(payload);
4626 if (p_eth_proto_admin)
4627 *p_eth_proto_admin =
4628 mlxsw_reg_ptys_ext_eth_proto_admin_get(payload);
4629 if (p_eth_proto_oper)
4630 *p_eth_proto_oper =
4631 mlxsw_reg_ptys_ext_eth_proto_oper_get(payload);
4632}
4633
4634static inline void mlxsw_reg_ptys_ib_pack(char *payload, u16 local_port,
4635 u16 proto_admin, u16 link_width)
4636{
4637 MLXSW_REG_ZERO(ptys, payload);
4638 mlxsw_reg_ptys_local_port_set(payload, local_port);
4639 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_IB);
4640 mlxsw_reg_ptys_ib_proto_admin_set(payload, proto_admin);
4641 mlxsw_reg_ptys_ib_link_width_admin_set(payload, link_width);
4642}
4643
4644static inline void mlxsw_reg_ptys_ib_unpack(char *payload, u16 *p_ib_proto_cap,
4645 u16 *p_ib_link_width_cap,
4646 u16 *p_ib_proto_oper,
4647 u16 *p_ib_link_width_oper)
4648{
4649 if (p_ib_proto_cap)
4650 *p_ib_proto_cap = mlxsw_reg_ptys_ib_proto_cap_get(payload);
4651 if (p_ib_link_width_cap)
4652 *p_ib_link_width_cap =
4653 mlxsw_reg_ptys_ib_link_width_cap_get(payload);
4654 if (p_ib_proto_oper)
4655 *p_ib_proto_oper = mlxsw_reg_ptys_ib_proto_oper_get(payload);
4656 if (p_ib_link_width_oper)
4657 *p_ib_link_width_oper =
4658 mlxsw_reg_ptys_ib_link_width_oper_get(payload);
4659}
4660
4661
4662
4663
4664
4665#define MLXSW_REG_PPAD_ID 0x5005
4666#define MLXSW_REG_PPAD_LEN 0x10
4667
4668MLXSW_REG_DEFINE(ppad, MLXSW_REG_PPAD_ID, MLXSW_REG_PPAD_LEN);
4669
4670
4671
4672
4673
4674
4675
4676MLXSW_ITEM32(reg, ppad, single_base_mac, 0x00, 28, 1);
4677
4678
4679
4680
4681
4682MLXSW_ITEM32_LP(reg, ppad, 0x00, 16, 0x00, 24);
4683
4684
4685
4686
4687
4688
4689MLXSW_ITEM_BUF(reg, ppad, mac, 0x02, 6);
4690
4691static inline void mlxsw_reg_ppad_pack(char *payload, bool single_base_mac,
4692 u16 local_port)
4693{
4694 MLXSW_REG_ZERO(ppad, payload);
4695 mlxsw_reg_ppad_single_base_mac_set(payload, !!single_base_mac);
4696 mlxsw_reg_ppad_local_port_set(payload, local_port);
4697}
4698
4699
4700
4701
4702
4703#define MLXSW_REG_PAOS_ID 0x5006
4704#define MLXSW_REG_PAOS_LEN 0x10
4705
4706MLXSW_REG_DEFINE(paos, MLXSW_REG_PAOS_ID, MLXSW_REG_PAOS_LEN);
4707
4708
4709
4710
4711
4712
4713
4714
4715MLXSW_ITEM32(reg, paos, swid, 0x00, 24, 8);
4716
4717
4718
4719
4720
4721MLXSW_ITEM32_LP(reg, paos, 0x00, 16, 0x00, 12);
4722
4723
4724
4725
4726
4727
4728
4729
4730
4731
4732MLXSW_ITEM32(reg, paos, admin_status, 0x00, 8, 4);
4733
4734
4735
4736
4737
4738
4739
4740
4741
4742MLXSW_ITEM32(reg, paos, oper_status, 0x00, 0, 4);
4743
4744
4745
4746
4747
4748MLXSW_ITEM32(reg, paos, ase, 0x04, 31, 1);
4749
4750
4751
4752
4753
4754
4755MLXSW_ITEM32(reg, paos, ee, 0x04, 30, 1);
4756
4757
4758
4759
4760
4761
4762
4763
4764MLXSW_ITEM32(reg, paos, e, 0x04, 0, 2);
4765
4766static inline void mlxsw_reg_paos_pack(char *payload, u16 local_port,
4767 enum mlxsw_port_admin_status status)
4768{
4769 MLXSW_REG_ZERO(paos, payload);
4770 mlxsw_reg_paos_swid_set(payload, 0);
4771 mlxsw_reg_paos_local_port_set(payload, local_port);
4772 mlxsw_reg_paos_admin_status_set(payload, status);
4773 mlxsw_reg_paos_oper_status_set(payload, 0);
4774 mlxsw_reg_paos_ase_set(payload, 1);
4775 mlxsw_reg_paos_ee_set(payload, 1);
4776 mlxsw_reg_paos_e_set(payload, 1);
4777}
4778
4779
4780
4781
4782
4783#define MLXSW_REG_PFCC_ID 0x5007
4784#define MLXSW_REG_PFCC_LEN 0x20
4785
4786MLXSW_REG_DEFINE(pfcc, MLXSW_REG_PFCC_ID, MLXSW_REG_PFCC_LEN);
4787
4788
4789
4790
4791
4792MLXSW_ITEM32_LP(reg, pfcc, 0x00, 16, 0x00, 12);
4793
4794
4795
4796
4797
4798
4799
4800MLXSW_ITEM32(reg, pfcc, pnat, 0x00, 14, 2);
4801
4802
4803
4804
4805
4806
4807
4808
4809MLXSW_ITEM32(reg, pfcc, shl_cap, 0x00, 1, 1);
4810
4811
4812
4813
4814
4815
4816
4817
4818MLXSW_ITEM32(reg, pfcc, shl_opr, 0x00, 0, 1);
4819
4820
4821
4822
4823
4824
4825
4826
4827
4828
4829
4830MLXSW_ITEM32(reg, pfcc, ppan, 0x04, 28, 4);
4831
4832
4833
4834
4835
4836
4837MLXSW_ITEM32(reg, pfcc, prio_mask_tx, 0x04, 16, 8);
4838
4839
4840
4841
4842
4843
4844MLXSW_ITEM32(reg, pfcc, prio_mask_rx, 0x04, 0, 8);
4845
4846
4847
4848
4849
4850
4851
4852MLXSW_ITEM32(reg, pfcc, pptx, 0x08, 31, 1);
4853
4854
4855
4856
4857
4858
4859
4860MLXSW_ITEM32(reg, pfcc, aptx, 0x08, 30, 1);
4861
4862
4863
4864
4865
4866
4867
4868
4869
4870
4871
4872MLXSW_ITEM32(reg, pfcc, pfctx, 0x08, 16, 8);
4873
4874
4875
4876
4877
4878
4879
4880MLXSW_ITEM32(reg, pfcc, pprx, 0x0C, 31, 1);
4881
4882
4883
4884
4885
4886
4887
4888MLXSW_ITEM32(reg, pfcc, aprx, 0x0C, 30, 1);
4889
4890
4891
4892
4893
4894
4895
4896
4897MLXSW_ITEM32(reg, pfcc, pfcrx, 0x0C, 16, 8);
4898
4899#define MLXSW_REG_PFCC_ALL_PRIO 0xFF
4900
4901static inline void mlxsw_reg_pfcc_prio_pack(char *payload, u8 pfc_en)
4902{
4903 mlxsw_reg_pfcc_prio_mask_tx_set(payload, MLXSW_REG_PFCC_ALL_PRIO);
4904 mlxsw_reg_pfcc_prio_mask_rx_set(payload, MLXSW_REG_PFCC_ALL_PRIO);
4905 mlxsw_reg_pfcc_pfctx_set(payload, pfc_en);
4906 mlxsw_reg_pfcc_pfcrx_set(payload, pfc_en);
4907}
4908
4909static inline void mlxsw_reg_pfcc_pack(char *payload, u16 local_port)
4910{
4911 MLXSW_REG_ZERO(pfcc, payload);
4912 mlxsw_reg_pfcc_local_port_set(payload, local_port);
4913}
4914
4915
4916
4917
4918
4919#define MLXSW_REG_PPCNT_ID 0x5008
4920#define MLXSW_REG_PPCNT_LEN 0x100
4921#define MLXSW_REG_PPCNT_COUNTERS_OFFSET 0x08
4922
4923MLXSW_REG_DEFINE(ppcnt, MLXSW_REG_PPCNT_ID, MLXSW_REG_PPCNT_LEN);
4924
4925
4926
4927
4928
4929
4930
4931
4932
4933
4934MLXSW_ITEM32(reg, ppcnt, swid, 0x00, 24, 8);
4935
4936
4937
4938
4939
4940MLXSW_ITEM32_LP(reg, ppcnt, 0x00, 16, 0x00, 12);
4941
4942
4943
4944
4945
4946
4947
4948MLXSW_ITEM32(reg, ppcnt, pnat, 0x00, 14, 2);
4949
4950enum mlxsw_reg_ppcnt_grp {
4951 MLXSW_REG_PPCNT_IEEE_8023_CNT = 0x0,
4952 MLXSW_REG_PPCNT_RFC_2863_CNT = 0x1,
4953 MLXSW_REG_PPCNT_RFC_2819_CNT = 0x2,
4954 MLXSW_REG_PPCNT_RFC_3635_CNT = 0x3,
4955 MLXSW_REG_PPCNT_EXT_CNT = 0x5,
4956 MLXSW_REG_PPCNT_DISCARD_CNT = 0x6,
4957 MLXSW_REG_PPCNT_PRIO_CNT = 0x10,
4958 MLXSW_REG_PPCNT_TC_CNT = 0x11,
4959 MLXSW_REG_PPCNT_TC_CONG_CNT = 0x13,
4960};
4961
4962
4963
4964
4965
4966
4967
4968
4969
4970
4971
4972
4973
4974
4975
4976
4977
4978
4979MLXSW_ITEM32(reg, ppcnt, grp, 0x00, 0, 6);
4980
4981
4982
4983
4984
4985
4986
4987MLXSW_ITEM32(reg, ppcnt, clr, 0x04, 31, 1);
4988
4989
4990
4991
4992
4993
4994
4995MLXSW_ITEM32(reg, ppcnt, lp_gl, 0x04, 30, 1);
4996
4997
4998
4999
5000
5001
5002
5003
5004
5005MLXSW_ITEM32(reg, ppcnt, prio_tc, 0x04, 0, 5);
5006
5007
5008
5009
5010
5011
5012MLXSW_ITEM64(reg, ppcnt, a_frames_transmitted_ok,
5013 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64);
5014
5015
5016
5017
5018MLXSW_ITEM64(reg, ppcnt, a_frames_received_ok,
5019 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64);
5020
5021
5022
5023
5024MLXSW_ITEM64(reg, ppcnt, a_frame_check_sequence_errors,
5025 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64);
5026
5027
5028
5029
5030MLXSW_ITEM64(reg, ppcnt, a_alignment_errors,
5031 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64);
5032
5033
5034
5035
5036MLXSW_ITEM64(reg, ppcnt, a_octets_transmitted_ok,
5037 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64);
5038
5039
5040
5041
5042MLXSW_ITEM64(reg, ppcnt, a_octets_received_ok,
5043 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64);
5044
5045
5046
5047
5048MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_xmitted_ok,
5049 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64);
5050
5051
5052
5053
5054MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_xmitted_ok,
5055 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64);
5056
5057
5058
5059
5060MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_received_ok,
5061 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64);
5062
5063
5064
5065
5066MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_received_ok,
5067 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64);
5068
5069
5070
5071
5072MLXSW_ITEM64(reg, ppcnt, a_in_range_length_errors,
5073 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64);
5074
5075
5076
5077
5078MLXSW_ITEM64(reg, ppcnt, a_out_of_range_length_field,
5079 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64);
5080
5081
5082
5083
5084MLXSW_ITEM64(reg, ppcnt, a_frame_too_long_errors,
5085 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64);
5086
5087
5088
5089
5090MLXSW_ITEM64(reg, ppcnt, a_symbol_error_during_carrier,
5091 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64);
5092
5093
5094
5095
5096MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_transmitted,
5097 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64);
5098
5099
5100
5101
5102MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_received,
5103 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64);
5104
5105
5106
5107
5108MLXSW_ITEM64(reg, ppcnt, a_unsupported_opcodes_received,
5109 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64);
5110
5111
5112
5113
5114MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_received,
5115 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64);
5116
5117
5118
5119
5120MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_transmitted,
5121 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64);
5122
5123
5124
5125
5126
5127
5128MLXSW_ITEM64(reg, ppcnt, if_in_discards,
5129 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64);
5130
5131
5132
5133
5134MLXSW_ITEM64(reg, ppcnt, if_out_discards,
5135 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64);
5136
5137
5138
5139
5140MLXSW_ITEM64(reg, ppcnt, if_out_errors,
5141 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64);
5142
5143
5144
5145
5146
5147
5148MLXSW_ITEM64(reg, ppcnt, ether_stats_undersize_pkts,
5149 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64);
5150
5151
5152
5153
5154MLXSW_ITEM64(reg, ppcnt, ether_stats_oversize_pkts,
5155 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64);
5156
5157
5158
5159
5160MLXSW_ITEM64(reg, ppcnt, ether_stats_fragments,
5161 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64);
5162
5163
5164
5165
5166MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts64octets,
5167 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64);
5168
5169
5170
5171
5172MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts65to127octets,
5173 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64);
5174
5175
5176
5177
5178MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts128to255octets,
5179 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64);
5180
5181
5182
5183
5184MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts256to511octets,
5185 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64);
5186
5187
5188
5189
5190MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts512to1023octets,
5191 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64);
5192
5193
5194
5195
5196MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1024to1518octets,
5197 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64);
5198
5199
5200
5201
5202MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1519to2047octets,
5203 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64);
5204
5205
5206
5207
5208MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts2048to4095octets,
5209 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64);
5210
5211
5212
5213
5214MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts4096to8191octets,
5215 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x98, 0, 64);
5216
5217
5218
5219
5220MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts8192to10239octets,
5221 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0xA0, 0, 64);
5222
5223
5224
5225
5226
5227
5228MLXSW_ITEM64(reg, ppcnt, dot3stats_fcs_errors,
5229 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64);
5230
5231
5232
5233
5234MLXSW_ITEM64(reg, ppcnt, dot3stats_symbol_errors,
5235 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64);
5236
5237
5238
5239
5240MLXSW_ITEM64(reg, ppcnt, dot3control_in_unknown_opcodes,
5241 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64);
5242
5243
5244
5245
5246MLXSW_ITEM64(reg, ppcnt, dot3in_pause_frames,
5247 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64);
5248
5249
5250
5251
5252
5253
5254MLXSW_ITEM64(reg, ppcnt, ecn_marked,
5255 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64);
5256
5257
5258
5259
5260
5261
5262MLXSW_ITEM64(reg, ppcnt, ingress_general,
5263 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64);
5264
5265
5266
5267
5268MLXSW_ITEM64(reg, ppcnt, ingress_policy_engine,
5269 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64);
5270
5271
5272
5273
5274MLXSW_ITEM64(reg, ppcnt, ingress_vlan_membership,
5275 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64);
5276
5277
5278
5279
5280MLXSW_ITEM64(reg, ppcnt, ingress_tag_frame_type,
5281 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64);
5282
5283
5284
5285
5286MLXSW_ITEM64(reg, ppcnt, egress_vlan_membership,
5287 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64);
5288
5289
5290
5291
5292MLXSW_ITEM64(reg, ppcnt, loopback_filter,
5293 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64);
5294
5295
5296
5297
5298MLXSW_ITEM64(reg, ppcnt, egress_general,
5299 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64);
5300
5301
5302
5303
5304MLXSW_ITEM64(reg, ppcnt, egress_hoq,
5305 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64);
5306
5307
5308
5309
5310MLXSW_ITEM64(reg, ppcnt, egress_policy_engine,
5311 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64);
5312
5313
5314
5315
5316MLXSW_ITEM64(reg, ppcnt, ingress_tx_link_down,
5317 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64);
5318
5319
5320
5321
5322MLXSW_ITEM64(reg, ppcnt, egress_stp_filter,
5323 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64);
5324
5325
5326
5327
5328MLXSW_ITEM64(reg, ppcnt, egress_sll,
5329 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64);
5330
5331
5332
5333
5334
5335
5336MLXSW_ITEM64(reg, ppcnt, rx_octets,
5337 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64);
5338
5339
5340
5341
5342MLXSW_ITEM64(reg, ppcnt, rx_frames,
5343 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64);
5344
5345
5346
5347
5348MLXSW_ITEM64(reg, ppcnt, tx_octets,
5349 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64);
5350
5351
5352
5353
5354MLXSW_ITEM64(reg, ppcnt, tx_frames,
5355 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64);
5356
5357
5358
5359
5360MLXSW_ITEM64(reg, ppcnt, rx_pause,
5361 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64);
5362
5363
5364
5365
5366MLXSW_ITEM64(reg, ppcnt, rx_pause_duration,
5367 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64);
5368
5369
5370
5371
5372MLXSW_ITEM64(reg, ppcnt, tx_pause,
5373 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64);
5374
5375
5376
5377
5378MLXSW_ITEM64(reg, ppcnt, tx_pause_duration,
5379 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64);
5380
5381
5382
5383
5384MLXSW_ITEM64(reg, ppcnt, tx_pause_transition,
5385 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64);
5386
5387
5388
5389
5390
5391
5392
5393
5394
5395MLXSW_ITEM64(reg, ppcnt, tc_transmit_queue,
5396 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64);
5397
5398
5399
5400
5401
5402
5403MLXSW_ITEM64(reg, ppcnt, tc_no_buffer_discard_uc,
5404 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64);
5405
5406
5407
5408
5409
5410
5411MLXSW_ITEM64(reg, ppcnt, wred_discard,
5412 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64);
5413
5414
5415
5416
5417MLXSW_ITEM64(reg, ppcnt, ecn_marked_tc,
5418 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64);
5419
5420static inline void mlxsw_reg_ppcnt_pack(char *payload, u16 local_port,
5421 enum mlxsw_reg_ppcnt_grp grp,
5422 u8 prio_tc)
5423{
5424 MLXSW_REG_ZERO(ppcnt, payload);
5425 mlxsw_reg_ppcnt_swid_set(payload, 0);
5426 mlxsw_reg_ppcnt_local_port_set(payload, local_port);
5427 mlxsw_reg_ppcnt_pnat_set(payload, 0);
5428 mlxsw_reg_ppcnt_grp_set(payload, grp);
5429 mlxsw_reg_ppcnt_clr_set(payload, 0);
5430 mlxsw_reg_ppcnt_lp_gl_set(payload, 1);
5431 mlxsw_reg_ppcnt_prio_tc_set(payload, prio_tc);
5432}
5433
5434
5435
5436
5437
5438#define MLXSW_REG_PLIB_ID 0x500A
5439#define MLXSW_REG_PLIB_LEN 0x10
5440
5441MLXSW_REG_DEFINE(plib, MLXSW_REG_PLIB_ID, MLXSW_REG_PLIB_LEN);
5442
5443
5444
5445
5446
5447MLXSW_ITEM32_LP(reg, plib, 0x00, 16, 0x00, 12);
5448
5449
5450
5451
5452
5453MLXSW_ITEM32(reg, plib, ib_port, 0x00, 0, 8);
5454
5455
5456
5457
5458
5459#define MLXSW_REG_PPTB_ID 0x500B
5460#define MLXSW_REG_PPTB_LEN 0x10
5461
5462MLXSW_REG_DEFINE(pptb, MLXSW_REG_PPTB_ID, MLXSW_REG_PPTB_LEN);
5463
5464enum {
5465 MLXSW_REG_PPTB_MM_UM,
5466 MLXSW_REG_PPTB_MM_UNICAST,
5467 MLXSW_REG_PPTB_MM_MULTICAST,
5468};
5469
5470
5471
5472
5473
5474
5475
5476
5477
5478
5479MLXSW_ITEM32(reg, pptb, mm, 0x00, 28, 2);
5480
5481
5482
5483
5484
5485MLXSW_ITEM32_LP(reg, pptb, 0x00, 16, 0x00, 12);
5486
5487
5488
5489
5490
5491MLXSW_ITEM32(reg, pptb, um, 0x00, 8, 1);
5492
5493
5494
5495
5496
5497
5498MLXSW_ITEM32(reg, pptb, pm, 0x00, 0, 8);
5499
5500
5501
5502
5503
5504
5505MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff, 0x04, 0x04, 4);
5506
5507
5508
5509
5510
5511
5512MLXSW_ITEM32(reg, pptb, pm_msb, 0x08, 24, 8);
5513
5514
5515
5516
5517
5518
5519
5520
5521MLXSW_ITEM32(reg, pptb, untagged_buff, 0x08, 0, 4);
5522
5523
5524
5525
5526
5527
5528MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff_msb, 0x0C, 0x04, 4);
5529
5530#define MLXSW_REG_PPTB_ALL_PRIO 0xFF
5531
5532static inline void mlxsw_reg_pptb_pack(char *payload, u16 local_port)
5533{
5534 MLXSW_REG_ZERO(pptb, payload);
5535 mlxsw_reg_pptb_mm_set(payload, MLXSW_REG_PPTB_MM_UM);
5536 mlxsw_reg_pptb_local_port_set(payload, local_port);
5537 mlxsw_reg_pptb_pm_set(payload, MLXSW_REG_PPTB_ALL_PRIO);
5538 mlxsw_reg_pptb_pm_msb_set(payload, MLXSW_REG_PPTB_ALL_PRIO);
5539}
5540
5541static inline void mlxsw_reg_pptb_prio_to_buff_pack(char *payload, u8 prio,
5542 u8 buff)
5543{
5544 mlxsw_reg_pptb_prio_to_buff_set(payload, prio, buff);
5545 mlxsw_reg_pptb_prio_to_buff_msb_set(payload, prio, buff);
5546}
5547
5548
5549
5550
5551
5552
5553#define MLXSW_REG_PBMC_ID 0x500C
5554#define MLXSW_REG_PBMC_LEN 0x6C
5555
5556MLXSW_REG_DEFINE(pbmc, MLXSW_REG_PBMC_ID, MLXSW_REG_PBMC_LEN);
5557
5558
5559
5560
5561
5562MLXSW_ITEM32_LP(reg, pbmc, 0x00, 16, 0x00, 12);
5563
5564
5565
5566
5567
5568
5569MLXSW_ITEM32(reg, pbmc, xoff_timer_value, 0x04, 16, 16);
5570
5571
5572
5573
5574
5575
5576
5577MLXSW_ITEM32(reg, pbmc, xoff_refresh, 0x04, 0, 16);
5578
5579#define MLXSW_REG_PBMC_PORT_SHARED_BUF_IDX 11
5580
5581
5582
5583
5584
5585
5586
5587MLXSW_ITEM32_INDEXED(reg, pbmc, buf_lossy, 0x0C, 25, 1, 0x08, 0x00, false);
5588
5589
5590
5591
5592
5593
5594
5595
5596MLXSW_ITEM32_INDEXED(reg, pbmc, buf_epsb, 0x0C, 24, 1, 0x08, 0x00, false);
5597
5598
5599
5600
5601
5602
5603MLXSW_ITEM32_INDEXED(reg, pbmc, buf_size, 0x0C, 0, 16, 0x08, 0x00, false);
5604
5605
5606
5607
5608
5609
5610
5611
5612
5613
5614MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xoff_threshold, 0x0C, 16, 16,
5615 0x08, 0x04, false);
5616
5617
5618
5619
5620
5621
5622
5623
5624
5625
5626MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xon_threshold, 0x0C, 0, 16,
5627 0x08, 0x04, false);
5628
5629static inline void mlxsw_reg_pbmc_pack(char *payload, u16 local_port,
5630 u16 xoff_timer_value, u16 xoff_refresh)
5631{
5632 MLXSW_REG_ZERO(pbmc, payload);
5633 mlxsw_reg_pbmc_local_port_set(payload, local_port);
5634 mlxsw_reg_pbmc_xoff_timer_value_set(payload, xoff_timer_value);
5635 mlxsw_reg_pbmc_xoff_refresh_set(payload, xoff_refresh);
5636}
5637
5638static inline void mlxsw_reg_pbmc_lossy_buffer_pack(char *payload,
5639 int buf_index,
5640 u16 size)
5641{
5642 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 1);
5643 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0);
5644 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size);
5645}
5646
5647static inline void mlxsw_reg_pbmc_lossless_buffer_pack(char *payload,
5648 int buf_index, u16 size,
5649 u16 threshold)
5650{
5651 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 0);
5652 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0);
5653 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size);
5654 mlxsw_reg_pbmc_buf_xoff_threshold_set(payload, buf_index, threshold);
5655 mlxsw_reg_pbmc_buf_xon_threshold_set(payload, buf_index, threshold);
5656}
5657
5658
5659
5660
5661
5662
5663#define MLXSW_REG_PSPA_ID 0x500D
5664#define MLXSW_REG_PSPA_LEN 0x8
5665
5666MLXSW_REG_DEFINE(pspa, MLXSW_REG_PSPA_ID, MLXSW_REG_PSPA_LEN);
5667
5668
5669
5670
5671
5672MLXSW_ITEM32(reg, pspa, swid, 0x00, 24, 8);
5673
5674
5675
5676
5677
5678MLXSW_ITEM32_LP(reg, pspa, 0x00, 16, 0x00, 0);
5679
5680
5681
5682
5683
5684
5685MLXSW_ITEM32(reg, pspa, sub_port, 0x00, 8, 8);
5686
5687static inline void mlxsw_reg_pspa_pack(char *payload, u8 swid, u16 local_port)
5688{
5689 MLXSW_REG_ZERO(pspa, payload);
5690 mlxsw_reg_pspa_swid_set(payload, swid);
5691 mlxsw_reg_pspa_local_port_set(payload, local_port);
5692 mlxsw_reg_pspa_sub_port_set(payload, 0);
5693}
5694
5695
5696
5697
5698
5699#define MLXSW_REG_PMAOS_ID 0x5012
5700#define MLXSW_REG_PMAOS_LEN 0x10
5701
5702MLXSW_REG_DEFINE(pmaos, MLXSW_REG_PMAOS_ID, MLXSW_REG_PMAOS_LEN);
5703
5704
5705
5706
5707
5708
5709
5710MLXSW_ITEM32(reg, pmaos, rst, 0x00, 31, 1);
5711
5712
5713
5714
5715
5716MLXSW_ITEM32(reg, pmaos, slot_index, 0x00, 24, 4);
5717
5718
5719
5720
5721
5722MLXSW_ITEM32(reg, pmaos, module, 0x00, 16, 8);
5723
5724enum mlxsw_reg_pmaos_admin_status {
5725 MLXSW_REG_PMAOS_ADMIN_STATUS_ENABLED = 1,
5726 MLXSW_REG_PMAOS_ADMIN_STATUS_DISABLED = 2,
5727
5728
5729
5730
5731 MLXSW_REG_PMAOS_ADMIN_STATUS_ENABLED_ONCE = 3,
5732};
5733
5734
5735
5736
5737
5738
5739
5740MLXSW_ITEM32(reg, pmaos, admin_status, 0x00, 8, 4);
5741
5742
5743
5744
5745
5746
5747
5748MLXSW_ITEM32(reg, pmaos, ase, 0x04, 31, 1);
5749
5750
5751
5752
5753
5754
5755
5756MLXSW_ITEM32(reg, pmaos, ee, 0x04, 30, 1);
5757
5758enum mlxsw_reg_pmaos_e {
5759 MLXSW_REG_PMAOS_E_DO_NOT_GENERATE_EVENT,
5760 MLXSW_REG_PMAOS_E_GENERATE_EVENT,
5761 MLXSW_REG_PMAOS_E_GENERATE_SINGLE_EVENT,
5762};
5763
5764
5765
5766
5767
5768MLXSW_ITEM32(reg, pmaos, e, 0x04, 0, 2);
5769
5770static inline void mlxsw_reg_pmaos_pack(char *payload, u8 module)
5771{
5772 MLXSW_REG_ZERO(pmaos, payload);
5773 mlxsw_reg_pmaos_module_set(payload, module);
5774}
5775
5776
5777
5778
5779
5780#define MLXSW_REG_PPLR_ID 0x5018
5781#define MLXSW_REG_PPLR_LEN 0x8
5782
5783MLXSW_REG_DEFINE(pplr, MLXSW_REG_PPLR_ID, MLXSW_REG_PPLR_LEN);
5784
5785
5786
5787
5788
5789MLXSW_ITEM32_LP(reg, pplr, 0x00, 16, 0x00, 12);
5790
5791
5792
5793
5794#define MLXSW_REG_PPLR_LB_TYPE_BIT_PHY_LOCAL BIT(1)
5795
5796
5797
5798
5799
5800MLXSW_ITEM32(reg, pplr, lb_en, 0x04, 0, 8);
5801
5802static inline void mlxsw_reg_pplr_pack(char *payload, u16 local_port,
5803 bool phy_local)
5804{
5805 MLXSW_REG_ZERO(pplr, payload);
5806 mlxsw_reg_pplr_local_port_set(payload, local_port);
5807 mlxsw_reg_pplr_lb_en_set(payload,
5808 phy_local ?
5809 MLXSW_REG_PPLR_LB_TYPE_BIT_PHY_LOCAL : 0);
5810}
5811
5812
5813
5814
5815
5816
5817
5818#define MLXSW_REG_PMTDB_ID 0x501A
5819#define MLXSW_REG_PMTDB_LEN 0x40
5820
5821MLXSW_REG_DEFINE(pmtdb, MLXSW_REG_PMTDB_ID, MLXSW_REG_PMTDB_LEN);
5822
5823
5824
5825
5826
5827MLXSW_ITEM32(reg, pmtdb, slot_index, 0x00, 24, 4);
5828
5829
5830
5831
5832
5833MLXSW_ITEM32(reg, pmtdb, module, 0x00, 16, 8);
5834
5835
5836
5837
5838
5839MLXSW_ITEM32(reg, pmtdb, ports_width, 0x00, 12, 4);
5840
5841
5842
5843
5844
5845MLXSW_ITEM32(reg, pmtdb, num_ports, 0x00, 8, 4);
5846
5847enum mlxsw_reg_pmtdb_status {
5848 MLXSW_REG_PMTDB_STATUS_SUCCESS,
5849};
5850
5851
5852
5853
5854
5855MLXSW_ITEM32(reg, pmtdb, status, 0x00, 0, 4);
5856
5857
5858
5859
5860
5861
5862
5863MLXSW_ITEM16_INDEXED(reg, pmtdb, port_num, 0x04, 0, 10, 0x02, 0x00, false);
5864
5865static inline void mlxsw_reg_pmtdb_pack(char *payload, u8 slot_index, u8 module,
5866 u8 ports_width, u8 num_ports)
5867{
5868 MLXSW_REG_ZERO(pmtdb, payload);
5869 mlxsw_reg_pmtdb_slot_index_set(payload, slot_index);
5870 mlxsw_reg_pmtdb_module_set(payload, module);
5871 mlxsw_reg_pmtdb_ports_width_set(payload, ports_width);
5872 mlxsw_reg_pmtdb_num_ports_set(payload, num_ports);
5873}
5874
5875
5876
5877
5878
5879
5880
5881
5882
5883#define MLXSW_REG_PMPE_ID 0x5024
5884#define MLXSW_REG_PMPE_LEN 0x10
5885
5886MLXSW_REG_DEFINE(pmpe, MLXSW_REG_PMPE_ID, MLXSW_REG_PMPE_LEN);
5887
5888
5889
5890
5891
5892MLXSW_ITEM32(reg, pmpe, slot_index, 0x00, 24, 4);
5893
5894
5895
5896
5897
5898MLXSW_ITEM32(reg, pmpe, module, 0x00, 16, 8);
5899
5900enum mlxsw_reg_pmpe_module_status {
5901 MLXSW_REG_PMPE_MODULE_STATUS_PLUGGED_ENABLED = 1,
5902 MLXSW_REG_PMPE_MODULE_STATUS_UNPLUGGED,
5903 MLXSW_REG_PMPE_MODULE_STATUS_PLUGGED_ERROR,
5904 MLXSW_REG_PMPE_MODULE_STATUS_PLUGGED_DISABLED,
5905};
5906
5907
5908
5909
5910
5911MLXSW_ITEM32(reg, pmpe, module_status, 0x00, 0, 4);
5912
5913
5914
5915
5916
5917MLXSW_ITEM32(reg, pmpe, error_type, 0x04, 8, 4);
5918
5919
5920
5921
5922
5923#define MLXSW_REG_PDDR_ID 0x5031
5924#define MLXSW_REG_PDDR_LEN 0x100
5925
5926MLXSW_REG_DEFINE(pddr, MLXSW_REG_PDDR_ID, MLXSW_REG_PDDR_LEN);
5927
5928
5929
5930
5931
5932MLXSW_ITEM32_LP(reg, pddr, 0x00, 16, 0x00, 12);
5933
5934enum mlxsw_reg_pddr_page_select {
5935 MLXSW_REG_PDDR_PAGE_SELECT_TROUBLESHOOTING_INFO = 1,
5936};
5937
5938
5939
5940
5941
5942MLXSW_ITEM32(reg, pddr, page_select, 0x04, 0, 8);
5943
5944enum mlxsw_reg_pddr_trblsh_group_opcode {
5945
5946 MLXSW_REG_PDDR_TRBLSH_GROUP_OPCODE_MONITOR,
5947};
5948
5949
5950
5951
5952
5953MLXSW_ITEM32(reg, pddr, trblsh_group_opcode, 0x08, 0, 16);
5954
5955
5956
5957
5958
5959MLXSW_ITEM32(reg, pddr, trblsh_status_opcode, 0x0C, 0, 16);
5960
5961static inline void mlxsw_reg_pddr_pack(char *payload, u16 local_port,
5962 u8 page_select)
5963{
5964 MLXSW_REG_ZERO(pddr, payload);
5965 mlxsw_reg_pddr_local_port_set(payload, local_port);
5966 mlxsw_reg_pddr_page_select_set(payload, page_select);
5967}
5968
5969
5970
5971
5972
5973
5974#define MLXSW_REG_PMMP_ID 0x5044
5975#define MLXSW_REG_PMMP_LEN 0x2C
5976
5977MLXSW_REG_DEFINE(pmmp, MLXSW_REG_PMMP_ID, MLXSW_REG_PMMP_LEN);
5978
5979
5980
5981
5982
5983MLXSW_ITEM32(reg, pmmp, module, 0x00, 16, 8);
5984
5985
5986
5987
5988
5989MLXSW_ITEM32(reg, pmmp, sticky, 0x00, 0, 1);
5990
5991
5992
5993
5994
5995
5996
5997
5998
5999MLXSW_ITEM32(reg, pmmp, eeprom_override_mask, 0x04, 16, 16);
6000
6001enum {
6002
6003 MLXSW_REG_PMMP_EEPROM_OVERRIDE_LOW_POWER_MASK = BIT(8),
6004};
6005
6006
6007
6008
6009
6010MLXSW_ITEM32(reg, pmmp, eeprom_override, 0x04, 0, 16);
6011
6012static inline void mlxsw_reg_pmmp_pack(char *payload, u8 module)
6013{
6014 MLXSW_REG_ZERO(pmmp, payload);
6015 mlxsw_reg_pmmp_module_set(payload, module);
6016}
6017
6018
6019
6020
6021
6022#define MLXSW_REG_PLLP_ID 0x504A
6023#define MLXSW_REG_PLLP_LEN 0x10
6024
6025MLXSW_REG_DEFINE(pllp, MLXSW_REG_PLLP_ID, MLXSW_REG_PLLP_LEN);
6026
6027
6028
6029
6030
6031MLXSW_ITEM32_LP(reg, pllp, 0x00, 16, 0x00, 12);
6032
6033
6034
6035
6036
6037MLXSW_ITEM32(reg, pllp, label_port, 0x00, 0, 8);
6038
6039
6040
6041
6042
6043MLXSW_ITEM32(reg, pllp, split_num, 0x04, 0, 4);
6044
6045
6046
6047
6048
6049MLXSW_ITEM32(reg, pllp, slot_index, 0x08, 0, 4);
6050
6051static inline void mlxsw_reg_pllp_pack(char *payload, u16 local_port)
6052{
6053 MLXSW_REG_ZERO(pllp, payload);
6054 mlxsw_reg_pllp_local_port_set(payload, local_port);
6055}
6056
6057static inline void mlxsw_reg_pllp_unpack(char *payload, u8 *label_port,
6058 u8 *split_num, u8 *slot_index)
6059{
6060 *label_port = mlxsw_reg_pllp_label_port_get(payload);
6061 *split_num = mlxsw_reg_pllp_split_num_get(payload);
6062 *slot_index = mlxsw_reg_pllp_slot_index_get(payload);
6063}
6064
6065
6066
6067
6068
6069#define MLXSW_REG_HTGT_ID 0x7002
6070#define MLXSW_REG_HTGT_LEN 0x20
6071
6072MLXSW_REG_DEFINE(htgt, MLXSW_REG_HTGT_ID, MLXSW_REG_HTGT_LEN);
6073
6074
6075
6076
6077
6078MLXSW_ITEM32(reg, htgt, swid, 0x00, 24, 8);
6079
6080#define MLXSW_REG_HTGT_PATH_TYPE_LOCAL 0x0
6081
6082
6083
6084
6085
6086MLXSW_ITEM32(reg, htgt, type, 0x00, 8, 4);
6087
6088enum mlxsw_reg_htgt_trap_group {
6089 MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
6090 MLXSW_REG_HTGT_TRAP_GROUP_MFDE,
6091 MLXSW_REG_HTGT_TRAP_GROUP_MTWE,
6092 MLXSW_REG_HTGT_TRAP_GROUP_PMPE,
6093 MLXSW_REG_HTGT_TRAP_GROUP_SP_STP,
6094 MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP,
6095 MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP,
6096 MLXSW_REG_HTGT_TRAP_GROUP_SP_MC_SNOOPING,
6097 MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP,
6098 MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF,
6099 MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM,
6100 MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST,
6101 MLXSW_REG_HTGT_TRAP_GROUP_SP_NEIGH_DISCOVERY,
6102 MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP,
6103 MLXSW_REG_HTGT_TRAP_GROUP_SP_EXTERNAL_ROUTE,
6104 MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME,
6105 MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP,
6106 MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT,
6107 MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6,
6108 MLXSW_REG_HTGT_TRAP_GROUP_SP_LBERROR,
6109 MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP0,
6110 MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP1,
6111 MLXSW_REG_HTGT_TRAP_GROUP_SP_VRRP,
6112 MLXSW_REG_HTGT_TRAP_GROUP_SP_PKT_SAMPLE,
6113 MLXSW_REG_HTGT_TRAP_GROUP_SP_FLOW_LOGGING,
6114 MLXSW_REG_HTGT_TRAP_GROUP_SP_FID_MISS,
6115 MLXSW_REG_HTGT_TRAP_GROUP_SP_BFD,
6116 MLXSW_REG_HTGT_TRAP_GROUP_SP_DUMMY,
6117 MLXSW_REG_HTGT_TRAP_GROUP_SP_L2_DISCARDS,
6118 MLXSW_REG_HTGT_TRAP_GROUP_SP_L3_DISCARDS,
6119 MLXSW_REG_HTGT_TRAP_GROUP_SP_L3_EXCEPTIONS,
6120 MLXSW_REG_HTGT_TRAP_GROUP_SP_TUNNEL_DISCARDS,
6121 MLXSW_REG_HTGT_TRAP_GROUP_SP_ACL_DISCARDS,
6122 MLXSW_REG_HTGT_TRAP_GROUP_SP_BUFFER_DISCARDS,
6123
6124 __MLXSW_REG_HTGT_TRAP_GROUP_MAX,
6125 MLXSW_REG_HTGT_TRAP_GROUP_MAX = __MLXSW_REG_HTGT_TRAP_GROUP_MAX - 1
6126};
6127
6128
6129
6130
6131
6132
6133
6134MLXSW_ITEM32(reg, htgt, trap_group, 0x00, 0, 8);
6135
6136enum {
6137 MLXSW_REG_HTGT_POLICER_DISABLE,
6138 MLXSW_REG_HTGT_POLICER_ENABLE,
6139};
6140
6141
6142
6143
6144
6145MLXSW_ITEM32(reg, htgt, pide, 0x04, 15, 1);
6146
6147#define MLXSW_REG_HTGT_INVALID_POLICER 0xff
6148
6149
6150
6151
6152
6153MLXSW_ITEM32(reg, htgt, pid, 0x04, 0, 8);
6154
6155#define MLXSW_REG_HTGT_TRAP_TO_CPU 0x0
6156
6157
6158
6159
6160
6161
6162
6163
6164
6165
6166MLXSW_ITEM32(reg, htgt, mirror_action, 0x08, 8, 2);
6167
6168
6169
6170
6171
6172MLXSW_ITEM32(reg, htgt, mirroring_agent, 0x08, 0, 3);
6173
6174#define MLXSW_REG_HTGT_DEFAULT_PRIORITY 0
6175
6176
6177
6178
6179
6180
6181
6182
6183
6184
6185
6186
6187MLXSW_ITEM32(reg, htgt, priority, 0x0C, 0, 4);
6188
6189#define MLXSW_REG_HTGT_DEFAULT_TC 7
6190
6191
6192
6193
6194
6195MLXSW_ITEM32(reg, htgt, local_path_cpu_tclass, 0x10, 16, 6);
6196
6197enum mlxsw_reg_htgt_local_path_rdq {
6198 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_CTRL = 0x13,
6199 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_RX = 0x14,
6200 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_EMAD = 0x15,
6201 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SIB_EMAD = 0x15,
6202};
6203
6204
6205
6206
6207MLXSW_ITEM32(reg, htgt, local_path_rdq, 0x10, 0, 6);
6208
6209static inline void mlxsw_reg_htgt_pack(char *payload, u8 group, u8 policer_id,
6210 u8 priority, u8 tc)
6211{
6212 MLXSW_REG_ZERO(htgt, payload);
6213
6214 if (policer_id == MLXSW_REG_HTGT_INVALID_POLICER) {
6215 mlxsw_reg_htgt_pide_set(payload,
6216 MLXSW_REG_HTGT_POLICER_DISABLE);
6217 } else {
6218 mlxsw_reg_htgt_pide_set(payload,
6219 MLXSW_REG_HTGT_POLICER_ENABLE);
6220 mlxsw_reg_htgt_pid_set(payload, policer_id);
6221 }
6222
6223 mlxsw_reg_htgt_type_set(payload, MLXSW_REG_HTGT_PATH_TYPE_LOCAL);
6224 mlxsw_reg_htgt_trap_group_set(payload, group);
6225 mlxsw_reg_htgt_mirror_action_set(payload, MLXSW_REG_HTGT_TRAP_TO_CPU);
6226 mlxsw_reg_htgt_mirroring_agent_set(payload, 0);
6227 mlxsw_reg_htgt_priority_set(payload, priority);
6228 mlxsw_reg_htgt_local_path_cpu_tclass_set(payload, tc);
6229 mlxsw_reg_htgt_local_path_rdq_set(payload, group);
6230}
6231
6232
6233
6234
6235
6236#define MLXSW_REG_HPKT_ID 0x7003
6237#define MLXSW_REG_HPKT_LEN 0x10
6238
6239MLXSW_REG_DEFINE(hpkt, MLXSW_REG_HPKT_ID, MLXSW_REG_HPKT_LEN);
6240
6241enum {
6242 MLXSW_REG_HPKT_ACK_NOT_REQUIRED,
6243 MLXSW_REG_HPKT_ACK_REQUIRED,
6244};
6245
6246
6247
6248
6249
6250
6251
6252
6253
6254MLXSW_ITEM32(reg, hpkt, ack, 0x00, 24, 1);
6255
6256enum mlxsw_reg_hpkt_action {
6257 MLXSW_REG_HPKT_ACTION_FORWARD,
6258 MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU,
6259 MLXSW_REG_HPKT_ACTION_MIRROR_TO_CPU,
6260 MLXSW_REG_HPKT_ACTION_DISCARD,
6261 MLXSW_REG_HPKT_ACTION_SOFT_DISCARD,
6262 MLXSW_REG_HPKT_ACTION_TRAP_AND_SOFT_DISCARD,
6263 MLXSW_REG_HPKT_ACTION_TRAP_EXCEPTION_TO_CPU,
6264 MLXSW_REG_HPKT_ACTION_SET_FW_DEFAULT = 15,
6265};
6266
6267
6268
6269
6270
6271
6272
6273
6274
6275
6276
6277
6278
6279
6280
6281
6282MLXSW_ITEM32(reg, hpkt, action, 0x00, 20, 3);
6283
6284
6285
6286
6287
6288MLXSW_ITEM32(reg, hpkt, trap_group, 0x00, 12, 6);
6289
6290
6291
6292
6293
6294
6295
6296
6297MLXSW_ITEM32(reg, hpkt, trap_id, 0x00, 0, 10);
6298
6299enum {
6300 MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT,
6301 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER,
6302 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER,
6303};
6304
6305
6306
6307
6308
6309
6310
6311
6312
6313MLXSW_ITEM32(reg, hpkt, ctrl, 0x04, 16, 2);
6314
6315static inline void mlxsw_reg_hpkt_pack(char *payload, u8 action, u16 trap_id,
6316 enum mlxsw_reg_htgt_trap_group trap_group,
6317 bool is_ctrl)
6318{
6319 MLXSW_REG_ZERO(hpkt, payload);
6320 mlxsw_reg_hpkt_ack_set(payload, MLXSW_REG_HPKT_ACK_NOT_REQUIRED);
6321 mlxsw_reg_hpkt_action_set(payload, action);
6322 mlxsw_reg_hpkt_trap_group_set(payload, trap_group);
6323 mlxsw_reg_hpkt_trap_id_set(payload, trap_id);
6324 mlxsw_reg_hpkt_ctrl_set(payload, is_ctrl ?
6325 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER :
6326 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER);
6327}
6328
6329
6330
6331
6332
6333#define MLXSW_REG_RGCR_ID 0x8001
6334#define MLXSW_REG_RGCR_LEN 0x28
6335
6336MLXSW_REG_DEFINE(rgcr, MLXSW_REG_RGCR_ID, MLXSW_REG_RGCR_LEN);
6337
6338
6339
6340
6341
6342MLXSW_ITEM32(reg, rgcr, ipv4_en, 0x00, 31, 1);
6343
6344
6345
6346
6347
6348MLXSW_ITEM32(reg, rgcr, ipv6_en, 0x00, 30, 1);
6349
6350
6351
6352
6353
6354
6355MLXSW_ITEM32(reg, rgcr, max_router_interfaces, 0x10, 0, 16);
6356
6357
6358
6359
6360
6361
6362
6363
6364
6365MLXSW_ITEM32(reg, rgcr, usp, 0x18, 20, 1);
6366
6367
6368
6369
6370
6371
6372
6373
6374
6375
6376MLXSW_ITEM32(reg, rgcr, pcp_rw, 0x18, 16, 2);
6377
6378
6379
6380
6381
6382
6383
6384
6385
6386
6387
6388
6389
6390
6391
6392MLXSW_ITEM32(reg, rgcr, activity_dis, 0x20, 0, 8);
6393
6394static inline void mlxsw_reg_rgcr_pack(char *payload, bool ipv4_en,
6395 bool ipv6_en)
6396{
6397 MLXSW_REG_ZERO(rgcr, payload);
6398 mlxsw_reg_rgcr_ipv4_en_set(payload, ipv4_en);
6399 mlxsw_reg_rgcr_ipv6_en_set(payload, ipv6_en);
6400}
6401
6402
6403
6404
6405
6406#define MLXSW_REG_RITR_ID 0x8002
6407#define MLXSW_REG_RITR_LEN 0x40
6408
6409MLXSW_REG_DEFINE(ritr, MLXSW_REG_RITR_ID, MLXSW_REG_RITR_LEN);
6410
6411
6412
6413
6414
6415MLXSW_ITEM32(reg, ritr, enable, 0x00, 31, 1);
6416
6417
6418
6419
6420
6421
6422MLXSW_ITEM32(reg, ritr, ipv4, 0x00, 29, 1);
6423
6424
6425
6426
6427
6428
6429MLXSW_ITEM32(reg, ritr, ipv6, 0x00, 28, 1);
6430
6431
6432
6433
6434
6435MLXSW_ITEM32(reg, ritr, ipv4_mc, 0x00, 27, 1);
6436
6437
6438
6439
6440
6441MLXSW_ITEM32(reg, ritr, ipv6_mc, 0x00, 26, 1);
6442
6443enum mlxsw_reg_ritr_if_type {
6444
6445 MLXSW_REG_RITR_VLAN_IF,
6446
6447 MLXSW_REG_RITR_FID_IF,
6448
6449 MLXSW_REG_RITR_SP_IF,
6450
6451 MLXSW_REG_RITR_LOOPBACK_IF,
6452};
6453
6454
6455
6456
6457
6458MLXSW_ITEM32(reg, ritr, type, 0x00, 23, 3);
6459
6460enum {
6461 MLXSW_REG_RITR_RIF_CREATE,
6462 MLXSW_REG_RITR_RIF_DEL,
6463};
6464
6465
6466
6467
6468
6469
6470
6471
6472
6473
6474MLXSW_ITEM32(reg, ritr, op, 0x00, 20, 2);
6475
6476
6477
6478
6479
6480MLXSW_ITEM32(reg, ritr, rif, 0x00, 0, 16);
6481
6482
6483
6484
6485
6486
6487
6488
6489MLXSW_ITEM32(reg, ritr, ipv4_fe, 0x04, 29, 1);
6490
6491
6492
6493
6494
6495
6496
6497
6498MLXSW_ITEM32(reg, ritr, ipv6_fe, 0x04, 28, 1);
6499
6500
6501
6502
6503
6504
6505
6506MLXSW_ITEM32(reg, ritr, ipv4_mc_fe, 0x04, 27, 1);
6507
6508
6509
6510
6511
6512
6513
6514MLXSW_ITEM32(reg, ritr, ipv6_mc_fe, 0x04, 26, 1);
6515
6516
6517
6518
6519
6520
6521
6522
6523MLXSW_ITEM32(reg, ritr, lb_en, 0x04, 24, 1);
6524
6525
6526
6527
6528
6529MLXSW_ITEM32(reg, ritr, virtual_router, 0x04, 0, 16);
6530
6531
6532
6533
6534
6535MLXSW_ITEM32(reg, ritr, mtu, 0x34, 0, 16);
6536
6537
6538
6539
6540
6541MLXSW_ITEM32(reg, ritr, if_swid, 0x08, 24, 8);
6542
6543
6544
6545
6546
6547MLXSW_ITEM32(reg, ritr, if_mac_profile_id, 0x10, 16, 4);
6548
6549
6550
6551
6552
6553
6554MLXSW_ITEM_BUF(reg, ritr, if_mac, 0x12, 6);
6555
6556
6557
6558
6559
6560
6561MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv6, 0x1C, 8, 8);
6562
6563
6564
6565
6566
6567
6568MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv4, 0x1C, 0, 8);
6569
6570
6571
6572
6573
6574
6575
6576MLXSW_ITEM32(reg, ritr, vlan_if_vid, 0x08, 0, 12);
6577
6578
6579
6580
6581
6582
6583
6584
6585MLXSW_ITEM32(reg, ritr, fid_if_fid, 0x08, 0, 16);
6586
6587static inline void mlxsw_reg_ritr_fid_set(char *payload,
6588 enum mlxsw_reg_ritr_if_type rif_type,
6589 u16 fid)
6590{
6591 if (rif_type == MLXSW_REG_RITR_FID_IF)
6592 mlxsw_reg_ritr_fid_if_fid_set(payload, fid);
6593 else
6594 mlxsw_reg_ritr_vlan_if_vid_set(payload, fid);
6595}
6596
6597
6598
6599
6600
6601
6602
6603
6604MLXSW_ITEM32(reg, ritr, sp_if_lag, 0x08, 24, 1);
6605
6606
6607
6608
6609
6610
6611MLXSW_ITEM32(reg, ritr, sp_if_system_port, 0x08, 0, 16);
6612
6613
6614
6615
6616
6617MLXSW_ITEM32(reg, ritr, sp_if_vid, 0x18, 0, 12);
6618
6619
6620
6621enum mlxsw_reg_ritr_loopback_protocol {
6622
6623 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4,
6624
6625 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV6,
6626
6627 MLXSW_REG_RITR_LOOPBACK_GENERIC,
6628};
6629
6630
6631
6632
6633MLXSW_ITEM32(reg, ritr, loopback_protocol, 0x08, 28, 4);
6634
6635enum mlxsw_reg_ritr_loopback_ipip_type {
6636
6637 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_IP,
6638
6639 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_IN_IP,
6640
6641 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_KEY_IN_IP,
6642};
6643
6644
6645
6646
6647
6648MLXSW_ITEM32(reg, ritr, loopback_ipip_type, 0x10, 24, 4);
6649
6650enum mlxsw_reg_ritr_loopback_ipip_options {
6651
6652 MLXSW_REG_RITR_LOOPBACK_IPIP_OPTIONS_GRE_KEY_PRESET,
6653};
6654
6655
6656
6657
6658MLXSW_ITEM32(reg, ritr, loopback_ipip_options, 0x10, 20, 4);
6659
6660
6661
6662
6663
6664
6665
6666MLXSW_ITEM32(reg, ritr, loopback_ipip_uvr, 0x10, 0, 16);
6667
6668
6669
6670
6671
6672
6673MLXSW_ITEM32(reg, ritr, loopback_ipip_underlay_rif, 0x14, 0, 16);
6674
6675
6676
6677
6678
6679MLXSW_ITEM_BUF(reg, ritr, loopback_ipip_usip6, 0x18, 16);
6680MLXSW_ITEM32(reg, ritr, loopback_ipip_usip4, 0x24, 0, 32);
6681
6682
6683
6684
6685
6686
6687MLXSW_ITEM32(reg, ritr, loopback_ipip_gre_key, 0x28, 0, 32);
6688
6689
6690enum mlxsw_reg_ritr_counter_set_type {
6691
6692 MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT = 0x0,
6693
6694
6695
6696
6697
6698
6699 MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC = 0x9,
6700};
6701
6702
6703
6704
6705
6706MLXSW_ITEM32(reg, ritr, ingress_counter_index, 0x38, 0, 24);
6707
6708
6709
6710
6711
6712MLXSW_ITEM32(reg, ritr, ingress_counter_set_type, 0x38, 24, 8);
6713
6714
6715
6716
6717
6718MLXSW_ITEM32(reg, ritr, egress_counter_index, 0x3C, 0, 24);
6719
6720
6721
6722
6723
6724MLXSW_ITEM32(reg, ritr, egress_counter_set_type, 0x3C, 24, 8);
6725
6726static inline void mlxsw_reg_ritr_counter_pack(char *payload, u32 index,
6727 bool enable, bool egress)
6728{
6729 enum mlxsw_reg_ritr_counter_set_type set_type;
6730
6731 if (enable)
6732 set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC;
6733 else
6734 set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT;
6735 mlxsw_reg_ritr_egress_counter_set_type_set(payload, set_type);
6736
6737 if (egress)
6738 mlxsw_reg_ritr_egress_counter_index_set(payload, index);
6739 else
6740 mlxsw_reg_ritr_ingress_counter_index_set(payload, index);
6741}
6742
6743static inline void mlxsw_reg_ritr_rif_pack(char *payload, u16 rif)
6744{
6745 MLXSW_REG_ZERO(ritr, payload);
6746 mlxsw_reg_ritr_rif_set(payload, rif);
6747}
6748
6749static inline void mlxsw_reg_ritr_sp_if_pack(char *payload, bool lag,
6750 u16 system_port, u16 vid)
6751{
6752 mlxsw_reg_ritr_sp_if_lag_set(payload, lag);
6753 mlxsw_reg_ritr_sp_if_system_port_set(payload, system_port);
6754 mlxsw_reg_ritr_sp_if_vid_set(payload, vid);
6755}
6756
6757static inline void mlxsw_reg_ritr_pack(char *payload, bool enable,
6758 enum mlxsw_reg_ritr_if_type type,
6759 u16 rif, u16 vr_id, u16 mtu)
6760{
6761 bool op = enable ? MLXSW_REG_RITR_RIF_CREATE : MLXSW_REG_RITR_RIF_DEL;
6762
6763 MLXSW_REG_ZERO(ritr, payload);
6764 mlxsw_reg_ritr_enable_set(payload, enable);
6765 mlxsw_reg_ritr_ipv4_set(payload, 1);
6766 mlxsw_reg_ritr_ipv6_set(payload, 1);
6767 mlxsw_reg_ritr_ipv4_mc_set(payload, 1);
6768 mlxsw_reg_ritr_ipv6_mc_set(payload, 1);
6769 mlxsw_reg_ritr_type_set(payload, type);
6770 mlxsw_reg_ritr_op_set(payload, op);
6771 mlxsw_reg_ritr_rif_set(payload, rif);
6772 mlxsw_reg_ritr_ipv4_fe_set(payload, 1);
6773 mlxsw_reg_ritr_ipv6_fe_set(payload, 1);
6774 mlxsw_reg_ritr_ipv4_mc_fe_set(payload, 1);
6775 mlxsw_reg_ritr_ipv6_mc_fe_set(payload, 1);
6776 mlxsw_reg_ritr_lb_en_set(payload, 1);
6777 mlxsw_reg_ritr_virtual_router_set(payload, vr_id);
6778 mlxsw_reg_ritr_mtu_set(payload, mtu);
6779}
6780
6781static inline void mlxsw_reg_ritr_mac_pack(char *payload, const char *mac)
6782{
6783 mlxsw_reg_ritr_if_mac_memcpy_to(payload, mac);
6784}
6785
6786static inline void
6787mlxsw_reg_ritr_loopback_ipip_common_pack(char *payload,
6788 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type,
6789 enum mlxsw_reg_ritr_loopback_ipip_options options,
6790 u16 uvr_id, u16 underlay_rif, u32 gre_key)
6791{
6792 mlxsw_reg_ritr_loopback_ipip_type_set(payload, ipip_type);
6793 mlxsw_reg_ritr_loopback_ipip_options_set(payload, options);
6794 mlxsw_reg_ritr_loopback_ipip_uvr_set(payload, uvr_id);
6795 mlxsw_reg_ritr_loopback_ipip_underlay_rif_set(payload, underlay_rif);
6796 mlxsw_reg_ritr_loopback_ipip_gre_key_set(payload, gre_key);
6797}
6798
6799static inline void
6800mlxsw_reg_ritr_loopback_ipip4_pack(char *payload,
6801 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type,
6802 enum mlxsw_reg_ritr_loopback_ipip_options options,
6803 u16 uvr_id, u16 underlay_rif, u32 usip, u32 gre_key)
6804{
6805 mlxsw_reg_ritr_loopback_protocol_set(payload,
6806 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4);
6807 mlxsw_reg_ritr_loopback_ipip_common_pack(payload, ipip_type, options,
6808 uvr_id, underlay_rif, gre_key);
6809 mlxsw_reg_ritr_loopback_ipip_usip4_set(payload, usip);
6810}
6811
6812static inline void
6813mlxsw_reg_ritr_loopback_ipip6_pack(char *payload,
6814 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type,
6815 enum mlxsw_reg_ritr_loopback_ipip_options options,
6816 u16 uvr_id, u16 underlay_rif,
6817 const struct in6_addr *usip, u32 gre_key)
6818{
6819 enum mlxsw_reg_ritr_loopback_protocol protocol =
6820 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV6;
6821
6822 mlxsw_reg_ritr_loopback_protocol_set(payload, protocol);
6823 mlxsw_reg_ritr_loopback_ipip_common_pack(payload, ipip_type, options,
6824 uvr_id, underlay_rif, gre_key);
6825 mlxsw_reg_ritr_loopback_ipip_usip6_memcpy_to(payload,
6826 (const char *)usip);
6827}
6828
6829
6830
6831
6832
6833#define MLXSW_REG_RTAR_ID 0x8004
6834#define MLXSW_REG_RTAR_LEN 0x20
6835
6836MLXSW_REG_DEFINE(rtar, MLXSW_REG_RTAR_ID, MLXSW_REG_RTAR_LEN);
6837
6838enum mlxsw_reg_rtar_op {
6839 MLXSW_REG_RTAR_OP_ALLOCATE,
6840 MLXSW_REG_RTAR_OP_RESIZE,
6841 MLXSW_REG_RTAR_OP_DEALLOCATE,
6842};
6843
6844
6845
6846
6847MLXSW_ITEM32(reg, rtar, op, 0x00, 28, 4);
6848
6849enum mlxsw_reg_rtar_key_type {
6850 MLXSW_REG_RTAR_KEY_TYPE_IPV4_MULTICAST = 1,
6851 MLXSW_REG_RTAR_KEY_TYPE_IPV6_MULTICAST = 3
6852};
6853
6854
6855
6856
6857
6858MLXSW_ITEM32(reg, rtar, key_type, 0x00, 0, 8);
6859
6860
6861
6862
6863
6864
6865
6866
6867MLXSW_ITEM32(reg, rtar, region_size, 0x04, 0, 16);
6868
6869static inline void mlxsw_reg_rtar_pack(char *payload,
6870 enum mlxsw_reg_rtar_op op,
6871 enum mlxsw_reg_rtar_key_type key_type,
6872 u16 region_size)
6873{
6874 MLXSW_REG_ZERO(rtar, payload);
6875 mlxsw_reg_rtar_op_set(payload, op);
6876 mlxsw_reg_rtar_key_type_set(payload, key_type);
6877 mlxsw_reg_rtar_region_size_set(payload, region_size);
6878}
6879
6880
6881
6882
6883
6884
6885#define MLXSW_REG_RATR_ID 0x8008
6886#define MLXSW_REG_RATR_LEN 0x2C
6887
6888MLXSW_REG_DEFINE(ratr, MLXSW_REG_RATR_ID, MLXSW_REG_RATR_LEN);
6889
6890enum mlxsw_reg_ratr_op {
6891
6892 MLXSW_REG_RATR_OP_QUERY_READ = 0,
6893
6894 MLXSW_REG_RATR_OP_QUERY_READ_CLEAR = 2,
6895
6896 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY = 1,
6897
6898
6899
6900
6901
6902
6903 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY_ON_ACTIVITY = 3,
6904};
6905
6906
6907
6908
6909
6910
6911
6912MLXSW_ITEM32(reg, ratr, op, 0x00, 28, 4);
6913
6914
6915
6916
6917
6918
6919
6920
6921
6922
6923
6924
6925
6926MLXSW_ITEM32(reg, ratr, v, 0x00, 24, 1);
6927
6928
6929
6930
6931
6932
6933MLXSW_ITEM32(reg, ratr, a, 0x00, 16, 1);
6934
6935enum mlxsw_reg_ratr_type {
6936
6937 MLXSW_REG_RATR_TYPE_ETHERNET,
6938
6939
6940
6941 MLXSW_REG_RATR_TYPE_IPOIB_UC,
6942
6943
6944
6945
6946 MLXSW_REG_RATR_TYPE_IPOIB_UC_W_GRH,
6947
6948
6949
6950 MLXSW_REG_RATR_TYPE_IPOIB_MC,
6951
6952
6953
6954 MLXSW_REG_RATR_TYPE_MPLS,
6955
6956
6957
6958 MLXSW_REG_RATR_TYPE_IPIP,
6959};
6960
6961
6962
6963
6964
6965MLXSW_ITEM32(reg, ratr, type, 0x04, 28, 4);
6966
6967
6968
6969
6970
6971
6972
6973
6974MLXSW_ITEM32(reg, ratr, adjacency_index_low, 0x04, 0, 16);
6975
6976
6977
6978
6979
6980MLXSW_ITEM32(reg, ratr, egress_router_interface, 0x08, 0, 16);
6981
6982enum mlxsw_reg_ratr_trap_action {
6983 MLXSW_REG_RATR_TRAP_ACTION_NOP,
6984 MLXSW_REG_RATR_TRAP_ACTION_TRAP,
6985 MLXSW_REG_RATR_TRAP_ACTION_MIRROR_TO_CPU,
6986 MLXSW_REG_RATR_TRAP_ACTION_MIRROR,
6987 MLXSW_REG_RATR_TRAP_ACTION_DISCARD_ERRORS,
6988};
6989
6990
6991
6992
6993
6994MLXSW_ITEM32(reg, ratr, trap_action, 0x0C, 28, 4);
6995
6996
6997
6998
6999
7000MLXSW_ITEM32(reg, ratr, adjacency_index_high, 0x0C, 16, 8);
7001
7002enum mlxsw_reg_ratr_trap_id {
7003 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS0,
7004 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS1,
7005};
7006
7007
7008
7009
7010
7011
7012
7013MLXSW_ITEM32(reg, ratr, trap_id, 0x0C, 0, 8);
7014
7015
7016
7017
7018
7019MLXSW_ITEM_BUF(reg, ratr, eth_destination_mac, 0x12, 6);
7020
7021enum mlxsw_reg_ratr_ipip_type {
7022
7023 MLXSW_REG_RATR_IPIP_TYPE_IPV4,
7024
7025 MLXSW_REG_RATR_IPIP_TYPE_IPV6,
7026};
7027
7028
7029
7030
7031
7032
7033MLXSW_ITEM32(reg, ratr, ipip_type, 0x10, 16, 4);
7034
7035
7036
7037
7038
7039
7040MLXSW_ITEM32(reg, ratr, ipip_ipv4_udip, 0x18, 0, 32);
7041
7042
7043
7044
7045
7046
7047MLXSW_ITEM32(reg, ratr, ipip_ipv6_ptr, 0x1C, 0, 24);
7048
7049enum mlxsw_reg_flow_counter_set_type {
7050
7051 MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT = 0x00,
7052
7053 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES = 0x03,
7054
7055 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS = 0x05,
7056};
7057
7058
7059
7060
7061
7062MLXSW_ITEM32(reg, ratr, counter_set_type, 0x28, 24, 8);
7063
7064
7065
7066
7067
7068MLXSW_ITEM32(reg, ratr, counter_index, 0x28, 0, 24);
7069
7070static inline void
7071mlxsw_reg_ratr_pack(char *payload,
7072 enum mlxsw_reg_ratr_op op, bool valid,
7073 enum mlxsw_reg_ratr_type type,
7074 u32 adjacency_index, u16 egress_rif)
7075{
7076 MLXSW_REG_ZERO(ratr, payload);
7077 mlxsw_reg_ratr_op_set(payload, op);
7078 mlxsw_reg_ratr_v_set(payload, valid);
7079 mlxsw_reg_ratr_type_set(payload, type);
7080 mlxsw_reg_ratr_adjacency_index_low_set(payload, adjacency_index);
7081 mlxsw_reg_ratr_adjacency_index_high_set(payload, adjacency_index >> 16);
7082 mlxsw_reg_ratr_egress_router_interface_set(payload, egress_rif);
7083}
7084
7085static inline void mlxsw_reg_ratr_eth_entry_pack(char *payload,
7086 const char *dest_mac)
7087{
7088 mlxsw_reg_ratr_eth_destination_mac_memcpy_to(payload, dest_mac);
7089}
7090
7091static inline void mlxsw_reg_ratr_ipip4_entry_pack(char *payload, u32 ipv4_udip)
7092{
7093 mlxsw_reg_ratr_ipip_type_set(payload, MLXSW_REG_RATR_IPIP_TYPE_IPV4);
7094 mlxsw_reg_ratr_ipip_ipv4_udip_set(payload, ipv4_udip);
7095}
7096
7097static inline void mlxsw_reg_ratr_ipip6_entry_pack(char *payload, u32 ipv6_ptr)
7098{
7099 mlxsw_reg_ratr_ipip_type_set(payload, MLXSW_REG_RATR_IPIP_TYPE_IPV6);
7100 mlxsw_reg_ratr_ipip_ipv6_ptr_set(payload, ipv6_ptr);
7101}
7102
7103static inline void mlxsw_reg_ratr_counter_pack(char *payload, u64 counter_index,
7104 bool counter_enable)
7105{
7106 enum mlxsw_reg_flow_counter_set_type set_type;
7107
7108 if (counter_enable)
7109 set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES;
7110 else
7111 set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT;
7112
7113 mlxsw_reg_ratr_counter_index_set(payload, counter_index);
7114 mlxsw_reg_ratr_counter_set_type_set(payload, set_type);
7115}
7116
7117
7118
7119
7120
7121#define MLXSW_REG_RDPM_ID 0x8009
7122#define MLXSW_REG_RDPM_BASE_LEN 0x00
7123#define MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN 0x01
7124#define MLXSW_REG_RDPM_DSCP_ENTRY_REC_MAX_COUNT 64
7125#define MLXSW_REG_RDPM_LEN 0x40
7126#define MLXSW_REG_RDPM_LAST_ENTRY (MLXSW_REG_RDPM_BASE_LEN + \
7127 MLXSW_REG_RDPM_LEN - \
7128 MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN)
7129
7130MLXSW_REG_DEFINE(rdpm, MLXSW_REG_RDPM_ID, MLXSW_REG_RDPM_LEN);
7131
7132
7133
7134
7135
7136MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_e, MLXSW_REG_RDPM_LAST_ENTRY, 7, 1,
7137 -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false);
7138
7139
7140
7141
7142
7143MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_prio, MLXSW_REG_RDPM_LAST_ENTRY, 0, 4,
7144 -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false);
7145
7146static inline void mlxsw_reg_rdpm_pack(char *payload, unsigned short index,
7147 u8 prio)
7148{
7149 mlxsw_reg_rdpm_dscp_entry_e_set(payload, index, 1);
7150 mlxsw_reg_rdpm_dscp_entry_prio_set(payload, index, prio);
7151}
7152
7153
7154
7155
7156
7157#define MLXSW_REG_RICNT_ID 0x800B
7158#define MLXSW_REG_RICNT_LEN 0x100
7159
7160MLXSW_REG_DEFINE(ricnt, MLXSW_REG_RICNT_ID, MLXSW_REG_RICNT_LEN);
7161
7162
7163
7164
7165
7166MLXSW_ITEM32(reg, ricnt, counter_index, 0x04, 0, 24);
7167
7168enum mlxsw_reg_ricnt_counter_set_type {
7169
7170 MLXSW_REG_RICNT_COUNTER_SET_TYPE_NO_COUNT = 0x00,
7171
7172
7173
7174
7175
7176
7177 MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC = 0x09,
7178};
7179
7180
7181
7182
7183
7184MLXSW_ITEM32(reg, ricnt, counter_set_type, 0x04, 24, 8);
7185
7186enum mlxsw_reg_ricnt_opcode {
7187
7188 MLXSW_REG_RICNT_OPCODE_NOP = 0x00,
7189
7190
7191
7192 MLXSW_REG_RICNT_OPCODE_CLEAR = 0x08,
7193};
7194
7195
7196
7197
7198
7199MLXSW_ITEM32(reg, ricnt, op, 0x00, 28, 4);
7200
7201
7202
7203
7204
7205MLXSW_ITEM64(reg, ricnt, good_unicast_packets, 0x08, 0, 64);
7206
7207
7208
7209
7210
7211MLXSW_ITEM64(reg, ricnt, good_multicast_packets, 0x10, 0, 64);
7212
7213
7214
7215
7216
7217MLXSW_ITEM64(reg, ricnt, good_broadcast_packets, 0x18, 0, 64);
7218
7219
7220
7221
7222
7223
7224MLXSW_ITEM64(reg, ricnt, good_unicast_bytes, 0x20, 0, 64);
7225
7226
7227
7228
7229
7230
7231MLXSW_ITEM64(reg, ricnt, good_multicast_bytes, 0x28, 0, 64);
7232
7233
7234
7235
7236
7237
7238MLXSW_ITEM64(reg, ricnt, good_broadcast_bytes, 0x30, 0, 64);
7239
7240
7241
7242
7243
7244MLXSW_ITEM64(reg, ricnt, error_packets, 0x38, 0, 64);
7245
7246
7247
7248
7249
7250MLXSW_ITEM64(reg, ricnt, discard_packets, 0x40, 0, 64);
7251
7252
7253
7254
7255
7256
7257MLXSW_ITEM64(reg, ricnt, error_bytes, 0x48, 0, 64);
7258
7259
7260
7261
7262
7263
7264MLXSW_ITEM64(reg, ricnt, discard_bytes, 0x50, 0, 64);
7265
7266static inline void mlxsw_reg_ricnt_pack(char *payload, u32 index,
7267 enum mlxsw_reg_ricnt_opcode op)
7268{
7269 MLXSW_REG_ZERO(ricnt, payload);
7270 mlxsw_reg_ricnt_op_set(payload, op);
7271 mlxsw_reg_ricnt_counter_index_set(payload, index);
7272 mlxsw_reg_ricnt_counter_set_type_set(payload,
7273 MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC);
7274}
7275
7276
7277
7278
7279
7280#define MLXSW_REG_RRCR_ID 0x800F
7281#define MLXSW_REG_RRCR_LEN 0x24
7282
7283MLXSW_REG_DEFINE(rrcr, MLXSW_REG_RRCR_ID, MLXSW_REG_RRCR_LEN);
7284
7285enum mlxsw_reg_rrcr_op {
7286
7287 MLXSW_REG_RRCR_OP_MOVE,
7288
7289 MLXSW_REG_RRCR_OP_COPY,
7290};
7291
7292
7293
7294
7295MLXSW_ITEM32(reg, rrcr, op, 0x00, 28, 4);
7296
7297
7298
7299
7300
7301MLXSW_ITEM32(reg, rrcr, offset, 0x00, 0, 16);
7302
7303
7304
7305
7306
7307MLXSW_ITEM32(reg, rrcr, size, 0x04, 0, 16);
7308
7309
7310
7311
7312
7313
7314MLXSW_ITEM32(reg, rrcr, table_id, 0x10, 0, 4);
7315
7316
7317
7318
7319
7320MLXSW_ITEM32(reg, rrcr, dest_offset, 0x20, 0, 16);
7321
7322static inline void mlxsw_reg_rrcr_pack(char *payload, enum mlxsw_reg_rrcr_op op,
7323 u16 offset, u16 size,
7324 enum mlxsw_reg_rtar_key_type table_id,
7325 u16 dest_offset)
7326{
7327 MLXSW_REG_ZERO(rrcr, payload);
7328 mlxsw_reg_rrcr_op_set(payload, op);
7329 mlxsw_reg_rrcr_offset_set(payload, offset);
7330 mlxsw_reg_rrcr_size_set(payload, size);
7331 mlxsw_reg_rrcr_table_id_set(payload, table_id);
7332 mlxsw_reg_rrcr_dest_offset_set(payload, dest_offset);
7333}
7334
7335
7336
7337
7338
7339#define MLXSW_REG_RALTA_ID 0x8010
7340#define MLXSW_REG_RALTA_LEN 0x04
7341
7342MLXSW_REG_DEFINE(ralta, MLXSW_REG_RALTA_ID, MLXSW_REG_RALTA_LEN);
7343
7344
7345
7346
7347
7348
7349
7350MLXSW_ITEM32(reg, ralta, op, 0x00, 28, 2);
7351
7352enum mlxsw_reg_ralxx_protocol {
7353 MLXSW_REG_RALXX_PROTOCOL_IPV4,
7354 MLXSW_REG_RALXX_PROTOCOL_IPV6,
7355};
7356
7357
7358
7359
7360
7361
7362MLXSW_ITEM32(reg, ralta, protocol, 0x00, 24, 4);
7363
7364
7365
7366
7367
7368
7369
7370MLXSW_ITEM32(reg, ralta, tree_id, 0x00, 0, 8);
7371
7372static inline void mlxsw_reg_ralta_pack(char *payload, bool alloc,
7373 enum mlxsw_reg_ralxx_protocol protocol,
7374 u8 tree_id)
7375{
7376 MLXSW_REG_ZERO(ralta, payload);
7377 mlxsw_reg_ralta_op_set(payload, !alloc);
7378 mlxsw_reg_ralta_protocol_set(payload, protocol);
7379 mlxsw_reg_ralta_tree_id_set(payload, tree_id);
7380}
7381
7382
7383
7384
7385
7386
7387
7388
7389
7390
7391#define MLXSW_REG_RALST_ID 0x8011
7392#define MLXSW_REG_RALST_LEN 0x104
7393
7394MLXSW_REG_DEFINE(ralst, MLXSW_REG_RALST_ID, MLXSW_REG_RALST_LEN);
7395
7396
7397
7398
7399
7400
7401
7402MLXSW_ITEM32(reg, ralst, root_bin, 0x00, 16, 8);
7403
7404
7405
7406
7407
7408MLXSW_ITEM32(reg, ralst, tree_id, 0x00, 0, 8);
7409
7410#define MLXSW_REG_RALST_BIN_NO_CHILD 0xff
7411#define MLXSW_REG_RALST_BIN_OFFSET 0x04
7412#define MLXSW_REG_RALST_BIN_COUNT 128
7413
7414
7415
7416
7417
7418
7419
7420MLXSW_ITEM16_INDEXED(reg, ralst, left_child_bin, 0x04, 8, 8, 0x02, 0x00, false);
7421
7422
7423
7424
7425
7426
7427
7428MLXSW_ITEM16_INDEXED(reg, ralst, right_child_bin, 0x04, 0, 8, 0x02, 0x00,
7429 false);
7430
7431static inline void mlxsw_reg_ralst_pack(char *payload, u8 root_bin, u8 tree_id)
7432{
7433 MLXSW_REG_ZERO(ralst, payload);
7434
7435
7436 memset(payload + MLXSW_REG_RALST_BIN_OFFSET,
7437 MLXSW_REG_RALST_BIN_NO_CHILD, MLXSW_REG_RALST_BIN_COUNT * 2);
7438
7439 mlxsw_reg_ralst_root_bin_set(payload, root_bin);
7440 mlxsw_reg_ralst_tree_id_set(payload, tree_id);
7441}
7442
7443static inline void mlxsw_reg_ralst_bin_pack(char *payload, u8 bin_number,
7444 u8 left_child_bin,
7445 u8 right_child_bin)
7446{
7447 int bin_index = bin_number - 1;
7448
7449 mlxsw_reg_ralst_left_child_bin_set(payload, bin_index, left_child_bin);
7450 mlxsw_reg_ralst_right_child_bin_set(payload, bin_index,
7451 right_child_bin);
7452}
7453
7454
7455
7456
7457
7458#define MLXSW_REG_RALTB_ID 0x8012
7459#define MLXSW_REG_RALTB_LEN 0x04
7460
7461MLXSW_REG_DEFINE(raltb, MLXSW_REG_RALTB_ID, MLXSW_REG_RALTB_LEN);
7462
7463
7464
7465
7466
7467
7468MLXSW_ITEM32(reg, raltb, virtual_router, 0x00, 16, 16);
7469
7470
7471
7472
7473
7474MLXSW_ITEM32(reg, raltb, protocol, 0x00, 12, 4);
7475
7476
7477
7478
7479
7480
7481
7482MLXSW_ITEM32(reg, raltb, tree_id, 0x00, 0, 8);
7483
7484static inline void mlxsw_reg_raltb_pack(char *payload, u16 virtual_router,
7485 enum mlxsw_reg_ralxx_protocol protocol,
7486 u8 tree_id)
7487{
7488 MLXSW_REG_ZERO(raltb, payload);
7489 mlxsw_reg_raltb_virtual_router_set(payload, virtual_router);
7490 mlxsw_reg_raltb_protocol_set(payload, protocol);
7491 mlxsw_reg_raltb_tree_id_set(payload, tree_id);
7492}
7493
7494
7495
7496
7497
7498
7499#define MLXSW_REG_RALUE_ID 0x8013
7500#define MLXSW_REG_RALUE_LEN 0x38
7501
7502MLXSW_REG_DEFINE(ralue, MLXSW_REG_RALUE_ID, MLXSW_REG_RALUE_LEN);
7503
7504
7505
7506
7507
7508MLXSW_ITEM32(reg, ralue, protocol, 0x00, 24, 4);
7509
7510enum mlxsw_reg_ralue_op {
7511
7512 MLXSW_REG_RALUE_OP_QUERY_READ = 0,
7513
7514
7515
7516 MLXSW_REG_RALUE_OP_QUERY_CLEAR = 1,
7517
7518
7519
7520
7521 MLXSW_REG_RALUE_OP_WRITE_WRITE = 0,
7522
7523
7524
7525
7526 MLXSW_REG_RALUE_OP_WRITE_UPDATE = 1,
7527
7528
7529
7530 MLXSW_REG_RALUE_OP_WRITE_CLEAR = 2,
7531
7532
7533
7534 MLXSW_REG_RALUE_OP_WRITE_DELETE = 3,
7535};
7536
7537
7538
7539
7540
7541MLXSW_ITEM32(reg, ralue, op, 0x00, 20, 3);
7542
7543
7544
7545
7546
7547
7548
7549
7550MLXSW_ITEM32(reg, ralue, a, 0x00, 16, 1);
7551
7552
7553
7554
7555
7556
7557MLXSW_ITEM32(reg, ralue, virtual_router, 0x04, 16, 16);
7558
7559#define MLXSW_REG_RALUE_OP_U_MASK_ENTRY_TYPE BIT(0)
7560#define MLXSW_REG_RALUE_OP_U_MASK_BMP_LEN BIT(1)
7561#define MLXSW_REG_RALUE_OP_U_MASK_ACTION BIT(2)
7562
7563
7564
7565
7566
7567
7568
7569
7570MLXSW_ITEM32(reg, ralue, op_u_mask, 0x04, 8, 3);
7571
7572
7573
7574
7575
7576
7577
7578MLXSW_ITEM32(reg, ralue, prefix_len, 0x08, 0, 8);
7579
7580
7581
7582
7583
7584
7585
7586
7587
7588MLXSW_ITEM32(reg, ralue, dip4, 0x18, 0, 32);
7589MLXSW_ITEM_BUF(reg, ralue, dip6, 0x0C, 16);
7590
7591enum mlxsw_reg_ralue_entry_type {
7592 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_ENTRY = 1,
7593 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY = 2,
7594 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_AND_ROUTE_ENTRY = 3,
7595};
7596
7597
7598
7599
7600
7601
7602MLXSW_ITEM32(reg, ralue, entry_type, 0x1C, 30, 2);
7603
7604
7605
7606
7607
7608
7609
7610
7611
7612MLXSW_ITEM32(reg, ralue, bmp_len, 0x1C, 16, 8);
7613
7614enum mlxsw_reg_ralue_action_type {
7615 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE,
7616 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL,
7617 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME,
7618};
7619
7620
7621
7622
7623
7624
7625
7626
7627
7628
7629MLXSW_ITEM32(reg, ralue, action_type, 0x1C, 0, 2);
7630
7631enum mlxsw_reg_ralue_trap_action {
7632 MLXSW_REG_RALUE_TRAP_ACTION_NOP,
7633 MLXSW_REG_RALUE_TRAP_ACTION_TRAP,
7634 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR_TO_CPU,
7635 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR,
7636 MLXSW_REG_RALUE_TRAP_ACTION_DISCARD_ERROR,
7637};
7638
7639
7640
7641
7642
7643
7644MLXSW_ITEM32(reg, ralue, trap_action, 0x20, 28, 4);
7645
7646
7647
7648
7649
7650
7651
7652MLXSW_ITEM32(reg, ralue, trap_id, 0x20, 0, 9);
7653
7654
7655
7656
7657
7658
7659MLXSW_ITEM32(reg, ralue, adjacency_index, 0x24, 0, 24);
7660
7661
7662
7663
7664
7665
7666
7667
7668
7669MLXSW_ITEM32(reg, ralue, ecmp_size, 0x28, 0, 13);
7670
7671
7672
7673
7674
7675
7676MLXSW_ITEM32(reg, ralue, local_erif, 0x24, 0, 16);
7677
7678
7679
7680
7681
7682
7683
7684
7685
7686
7687
7688MLXSW_ITEM32(reg, ralue, ip2me_v, 0x24, 31, 1);
7689
7690
7691
7692
7693
7694
7695
7696MLXSW_ITEM32(reg, ralue, ip2me_tunnel_ptr, 0x24, 0, 24);
7697
7698static inline void mlxsw_reg_ralue_pack(char *payload,
7699 enum mlxsw_reg_ralxx_protocol protocol,
7700 enum mlxsw_reg_ralue_op op,
7701 u16 virtual_router, u8 prefix_len)
7702{
7703 MLXSW_REG_ZERO(ralue, payload);
7704 mlxsw_reg_ralue_protocol_set(payload, protocol);
7705 mlxsw_reg_ralue_op_set(payload, op);
7706 mlxsw_reg_ralue_virtual_router_set(payload, virtual_router);
7707 mlxsw_reg_ralue_prefix_len_set(payload, prefix_len);
7708 mlxsw_reg_ralue_entry_type_set(payload,
7709 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY);
7710 mlxsw_reg_ralue_bmp_len_set(payload, prefix_len);
7711}
7712
7713static inline void mlxsw_reg_ralue_pack4(char *payload,
7714 enum mlxsw_reg_ralxx_protocol protocol,
7715 enum mlxsw_reg_ralue_op op,
7716 u16 virtual_router, u8 prefix_len,
7717 u32 *dip)
7718{
7719 mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len);
7720 if (dip)
7721 mlxsw_reg_ralue_dip4_set(payload, *dip);
7722}
7723
7724static inline void mlxsw_reg_ralue_pack6(char *payload,
7725 enum mlxsw_reg_ralxx_protocol protocol,
7726 enum mlxsw_reg_ralue_op op,
7727 u16 virtual_router, u8 prefix_len,
7728 const void *dip)
7729{
7730 mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len);
7731 if (dip)
7732 mlxsw_reg_ralue_dip6_memcpy_to(payload, dip);
7733}
7734
7735static inline void
7736mlxsw_reg_ralue_act_remote_pack(char *payload,
7737 enum mlxsw_reg_ralue_trap_action trap_action,
7738 u16 trap_id, u32 adjacency_index, u16 ecmp_size)
7739{
7740 mlxsw_reg_ralue_action_type_set(payload,
7741 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE);
7742 mlxsw_reg_ralue_trap_action_set(payload, trap_action);
7743 mlxsw_reg_ralue_trap_id_set(payload, trap_id);
7744 mlxsw_reg_ralue_adjacency_index_set(payload, adjacency_index);
7745 mlxsw_reg_ralue_ecmp_size_set(payload, ecmp_size);
7746}
7747
7748static inline void
7749mlxsw_reg_ralue_act_local_pack(char *payload,
7750 enum mlxsw_reg_ralue_trap_action trap_action,
7751 u16 trap_id, u16 local_erif)
7752{
7753 mlxsw_reg_ralue_action_type_set(payload,
7754 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL);
7755 mlxsw_reg_ralue_trap_action_set(payload, trap_action);
7756 mlxsw_reg_ralue_trap_id_set(payload, trap_id);
7757 mlxsw_reg_ralue_local_erif_set(payload, local_erif);
7758}
7759
7760static inline void
7761mlxsw_reg_ralue_act_ip2me_pack(char *payload)
7762{
7763 mlxsw_reg_ralue_action_type_set(payload,
7764 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME);
7765}
7766
7767static inline void
7768mlxsw_reg_ralue_act_ip2me_tun_pack(char *payload, u32 tunnel_ptr)
7769{
7770 mlxsw_reg_ralue_action_type_set(payload,
7771 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME);
7772 mlxsw_reg_ralue_ip2me_v_set(payload, 1);
7773 mlxsw_reg_ralue_ip2me_tunnel_ptr_set(payload, tunnel_ptr);
7774}
7775
7776
7777
7778
7779
7780
7781#define MLXSW_REG_RAUHT_ID 0x8014
7782#define MLXSW_REG_RAUHT_LEN 0x74
7783
7784MLXSW_REG_DEFINE(rauht, MLXSW_REG_RAUHT_ID, MLXSW_REG_RAUHT_LEN);
7785
7786enum mlxsw_reg_rauht_type {
7787 MLXSW_REG_RAUHT_TYPE_IPV4,
7788 MLXSW_REG_RAUHT_TYPE_IPV6,
7789};
7790
7791
7792
7793
7794MLXSW_ITEM32(reg, rauht, type, 0x00, 24, 2);
7795
7796enum mlxsw_reg_rauht_op {
7797 MLXSW_REG_RAUHT_OP_QUERY_READ = 0,
7798
7799 MLXSW_REG_RAUHT_OP_QUERY_CLEAR_ON_READ = 1,
7800
7801
7802
7803 MLXSW_REG_RAUHT_OP_WRITE_ADD = 0,
7804
7805
7806
7807 MLXSW_REG_RAUHT_OP_WRITE_UPDATE = 1,
7808
7809
7810
7811
7812 MLXSW_REG_RAUHT_OP_WRITE_CLEAR_ACTIVITY = 2,
7813
7814 MLXSW_REG_RAUHT_OP_WRITE_DELETE = 3,
7815
7816 MLXSW_REG_RAUHT_OP_WRITE_DELETE_ALL = 4,
7817
7818
7819
7820};
7821
7822
7823
7824
7825MLXSW_ITEM32(reg, rauht, op, 0x00, 20, 3);
7826
7827
7828
7829
7830
7831
7832
7833
7834MLXSW_ITEM32(reg, rauht, a, 0x00, 16, 1);
7835
7836
7837
7838
7839
7840MLXSW_ITEM32(reg, rauht, rif, 0x00, 0, 16);
7841
7842
7843
7844
7845
7846MLXSW_ITEM32(reg, rauht, dip4, 0x1C, 0x0, 32);
7847MLXSW_ITEM_BUF(reg, rauht, dip6, 0x10, 16);
7848
7849enum mlxsw_reg_rauht_trap_action {
7850 MLXSW_REG_RAUHT_TRAP_ACTION_NOP,
7851 MLXSW_REG_RAUHT_TRAP_ACTION_TRAP,
7852 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR_TO_CPU,
7853 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR,
7854 MLXSW_REG_RAUHT_TRAP_ACTION_DISCARD_ERRORS,
7855};
7856
7857
7858
7859
7860MLXSW_ITEM32(reg, rauht, trap_action, 0x60, 28, 4);
7861
7862enum mlxsw_reg_rauht_trap_id {
7863 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS0,
7864 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS1,
7865};
7866
7867
7868
7869
7870
7871
7872
7873
7874MLXSW_ITEM32(reg, rauht, trap_id, 0x60, 0, 9);
7875
7876
7877
7878
7879
7880MLXSW_ITEM32(reg, rauht, counter_set_type, 0x68, 24, 8);
7881
7882
7883
7884
7885
7886MLXSW_ITEM32(reg, rauht, counter_index, 0x68, 0, 24);
7887
7888
7889
7890
7891
7892MLXSW_ITEM_BUF(reg, rauht, mac, 0x6E, 6);
7893
7894static inline void mlxsw_reg_rauht_pack(char *payload,
7895 enum mlxsw_reg_rauht_op op, u16 rif,
7896 const char *mac)
7897{
7898 MLXSW_REG_ZERO(rauht, payload);
7899 mlxsw_reg_rauht_op_set(payload, op);
7900 mlxsw_reg_rauht_rif_set(payload, rif);
7901 mlxsw_reg_rauht_mac_memcpy_to(payload, mac);
7902}
7903
7904static inline void mlxsw_reg_rauht_pack4(char *payload,
7905 enum mlxsw_reg_rauht_op op, u16 rif,
7906 const char *mac, u32 dip)
7907{
7908 mlxsw_reg_rauht_pack(payload, op, rif, mac);
7909 mlxsw_reg_rauht_dip4_set(payload, dip);
7910}
7911
7912static inline void mlxsw_reg_rauht_pack6(char *payload,
7913 enum mlxsw_reg_rauht_op op, u16 rif,
7914 const char *mac, const char *dip)
7915{
7916 mlxsw_reg_rauht_pack(payload, op, rif, mac);
7917 mlxsw_reg_rauht_type_set(payload, MLXSW_REG_RAUHT_TYPE_IPV6);
7918 mlxsw_reg_rauht_dip6_memcpy_to(payload, dip);
7919}
7920
7921static inline void mlxsw_reg_rauht_pack_counter(char *payload,
7922 u64 counter_index)
7923{
7924 mlxsw_reg_rauht_counter_index_set(payload, counter_index);
7925 mlxsw_reg_rauht_counter_set_type_set(payload,
7926 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
7927}
7928
7929
7930
7931
7932
7933
7934
7935#define MLXSW_REG_RALEU_ID 0x8015
7936#define MLXSW_REG_RALEU_LEN 0x28
7937
7938MLXSW_REG_DEFINE(raleu, MLXSW_REG_RALEU_ID, MLXSW_REG_RALEU_LEN);
7939
7940
7941
7942
7943
7944MLXSW_ITEM32(reg, raleu, protocol, 0x00, 24, 4);
7945
7946
7947
7948
7949
7950
7951MLXSW_ITEM32(reg, raleu, virtual_router, 0x00, 0, 16);
7952
7953
7954
7955
7956
7957MLXSW_ITEM32(reg, raleu, adjacency_index, 0x10, 0, 24);
7958
7959
7960
7961
7962
7963MLXSW_ITEM32(reg, raleu, ecmp_size, 0x14, 0, 13);
7964
7965
7966
7967
7968
7969MLXSW_ITEM32(reg, raleu, new_adjacency_index, 0x20, 0, 24);
7970
7971
7972
7973
7974
7975MLXSW_ITEM32(reg, raleu, new_ecmp_size, 0x24, 0, 13);
7976
7977static inline void mlxsw_reg_raleu_pack(char *payload,
7978 enum mlxsw_reg_ralxx_protocol protocol,
7979 u16 virtual_router,
7980 u32 adjacency_index, u16 ecmp_size,
7981 u32 new_adjacency_index,
7982 u16 new_ecmp_size)
7983{
7984 MLXSW_REG_ZERO(raleu, payload);
7985 mlxsw_reg_raleu_protocol_set(payload, protocol);
7986 mlxsw_reg_raleu_virtual_router_set(payload, virtual_router);
7987 mlxsw_reg_raleu_adjacency_index_set(payload, adjacency_index);
7988 mlxsw_reg_raleu_ecmp_size_set(payload, ecmp_size);
7989 mlxsw_reg_raleu_new_adjacency_index_set(payload, new_adjacency_index);
7990 mlxsw_reg_raleu_new_ecmp_size_set(payload, new_ecmp_size);
7991}
7992
7993
7994
7995
7996
7997
7998
7999
8000
8001
8002#define MLXSW_REG_RAUHTD_ID 0x8018
8003#define MLXSW_REG_RAUHTD_BASE_LEN 0x20
8004#define MLXSW_REG_RAUHTD_REC_LEN 0x20
8005#define MLXSW_REG_RAUHTD_REC_MAX_NUM 32
8006#define MLXSW_REG_RAUHTD_LEN (MLXSW_REG_RAUHTD_BASE_LEN + \
8007 MLXSW_REG_RAUHTD_REC_MAX_NUM * MLXSW_REG_RAUHTD_REC_LEN)
8008#define MLXSW_REG_RAUHTD_IPV4_ENT_PER_REC 4
8009
8010MLXSW_REG_DEFINE(rauhtd, MLXSW_REG_RAUHTD_ID, MLXSW_REG_RAUHTD_LEN);
8011
8012#define MLXSW_REG_RAUHTD_FILTER_A BIT(0)
8013#define MLXSW_REG_RAUHTD_FILTER_RIF BIT(3)
8014
8015
8016
8017
8018
8019
8020
8021
8022MLXSW_ITEM32(reg, rauhtd, filter_fields, 0x00, 0, 8);
8023
8024enum mlxsw_reg_rauhtd_op {
8025 MLXSW_REG_RAUHTD_OP_DUMP,
8026 MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR,
8027};
8028
8029
8030
8031
8032MLXSW_ITEM32(reg, rauhtd, op, 0x04, 24, 2);
8033
8034
8035
8036
8037
8038
8039
8040
8041
8042MLXSW_ITEM32(reg, rauhtd, num_rec, 0x04, 0, 8);
8043
8044
8045
8046
8047
8048
8049MLXSW_ITEM32(reg, rauhtd, entry_a, 0x08, 16, 1);
8050
8051enum mlxsw_reg_rauhtd_type {
8052 MLXSW_REG_RAUHTD_TYPE_IPV4,
8053 MLXSW_REG_RAUHTD_TYPE_IPV6,
8054};
8055
8056
8057
8058
8059
8060
8061
8062MLXSW_ITEM32(reg, rauhtd, type, 0x08, 0, 4);
8063
8064
8065
8066
8067
8068
8069MLXSW_ITEM32(reg, rauhtd, entry_rif, 0x0C, 0, 16);
8070
8071static inline void mlxsw_reg_rauhtd_pack(char *payload,
8072 enum mlxsw_reg_rauhtd_type type)
8073{
8074 MLXSW_REG_ZERO(rauhtd, payload);
8075 mlxsw_reg_rauhtd_filter_fields_set(payload, MLXSW_REG_RAUHTD_FILTER_A);
8076 mlxsw_reg_rauhtd_op_set(payload, MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR);
8077 mlxsw_reg_rauhtd_num_rec_set(payload, MLXSW_REG_RAUHTD_REC_MAX_NUM);
8078 mlxsw_reg_rauhtd_entry_a_set(payload, 1);
8079 mlxsw_reg_rauhtd_type_set(payload, type);
8080}
8081
8082
8083
8084
8085
8086
8087
8088
8089
8090MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_rec_num_entries,
8091 MLXSW_REG_RAUHTD_BASE_LEN, 28, 2,
8092 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false);
8093
8094
8095
8096
8097
8098
8099
8100MLXSW_ITEM32_INDEXED(reg, rauhtd, rec_type, MLXSW_REG_RAUHTD_BASE_LEN, 24, 2,
8101 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false);
8102
8103#define MLXSW_REG_RAUHTD_IPV4_ENT_LEN 0x8
8104
8105
8106
8107
8108
8109
8110MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1,
8111 MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false);
8112
8113
8114
8115
8116
8117MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0,
8118 16, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false);
8119
8120
8121
8122
8123
8124MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 0,
8125 32, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x04, false);
8126
8127#define MLXSW_REG_RAUHTD_IPV6_ENT_LEN 0x20
8128
8129
8130
8131
8132
8133
8134MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1,
8135 MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false);
8136
8137
8138
8139
8140
8141MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0,
8142 16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false);
8143
8144
8145
8146
8147
8148MLXSW_ITEM_BUF_INDEXED(reg, rauhtd, ipv6_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN,
8149 16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x10);
8150
8151static inline void mlxsw_reg_rauhtd_ent_ipv4_unpack(char *payload,
8152 int ent_index, u16 *p_rif,
8153 u32 *p_dip)
8154{
8155 *p_rif = mlxsw_reg_rauhtd_ipv4_ent_rif_get(payload, ent_index);
8156 *p_dip = mlxsw_reg_rauhtd_ipv4_ent_dip_get(payload, ent_index);
8157}
8158
8159static inline void mlxsw_reg_rauhtd_ent_ipv6_unpack(char *payload,
8160 int rec_index, u16 *p_rif,
8161 char *p_dip)
8162{
8163 *p_rif = mlxsw_reg_rauhtd_ipv6_ent_rif_get(payload, rec_index);
8164 mlxsw_reg_rauhtd_ipv6_ent_dip_memcpy_from(payload, rec_index, p_dip);
8165}
8166
8167
8168
8169
8170
8171
8172#define MLXSW_REG_RTDP_ID 0x8020
8173#define MLXSW_REG_RTDP_LEN 0x44
8174
8175MLXSW_REG_DEFINE(rtdp, MLXSW_REG_RTDP_ID, MLXSW_REG_RTDP_LEN);
8176
8177enum mlxsw_reg_rtdp_type {
8178 MLXSW_REG_RTDP_TYPE_NVE,
8179 MLXSW_REG_RTDP_TYPE_IPIP,
8180};
8181
8182
8183
8184
8185
8186MLXSW_ITEM32(reg, rtdp, type, 0x00, 28, 4);
8187
8188
8189
8190
8191
8192
8193MLXSW_ITEM32(reg, rtdp, tunnel_index, 0x00, 0, 24);
8194
8195
8196
8197
8198
8199
8200MLXSW_ITEM32(reg, rtdp, egress_router_interface, 0x40, 0, 16);
8201
8202
8203
8204
8205
8206
8207
8208MLXSW_ITEM32(reg, rtdp, ipip_irif, 0x04, 16, 16);
8209
8210enum mlxsw_reg_rtdp_ipip_sip_check {
8211
8212 MLXSW_REG_RTDP_IPIP_SIP_CHECK_NO,
8213
8214
8215
8216 MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV4,
8217
8218
8219
8220 MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6 = 3,
8221};
8222
8223
8224
8225
8226
8227
8228MLXSW_ITEM32(reg, rtdp, ipip_sip_check, 0x04, 0, 3);
8229
8230
8231#define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_IPIP BIT(0)
8232
8233#define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE BIT(1)
8234
8235#define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE_KEY BIT(2)
8236
8237
8238
8239
8240
8241
8242MLXSW_ITEM32(reg, rtdp, ipip_type_check, 0x08, 24, 3);
8243
8244
8245
8246
8247
8248
8249
8250
8251
8252
8253MLXSW_ITEM32(reg, rtdp, ipip_gre_key_check, 0x08, 23, 1);
8254
8255
8256
8257
8258
8259
8260MLXSW_ITEM32(reg, rtdp, ipip_ipv4_usip, 0x0C, 0, 32);
8261
8262
8263
8264
8265
8266
8267
8268
8269MLXSW_ITEM32(reg, rtdp, ipip_ipv6_usip_ptr, 0x10, 0, 24);
8270
8271
8272
8273
8274
8275
8276MLXSW_ITEM32(reg, rtdp, ipip_expected_gre_key, 0x14, 0, 32);
8277
8278static inline void mlxsw_reg_rtdp_pack(char *payload,
8279 enum mlxsw_reg_rtdp_type type,
8280 u32 tunnel_index)
8281{
8282 MLXSW_REG_ZERO(rtdp, payload);
8283 mlxsw_reg_rtdp_type_set(payload, type);
8284 mlxsw_reg_rtdp_tunnel_index_set(payload, tunnel_index);
8285}
8286
8287static inline void
8288mlxsw_reg_rtdp_ipip_pack(char *payload, u16 irif,
8289 enum mlxsw_reg_rtdp_ipip_sip_check sip_check,
8290 unsigned int type_check, bool gre_key_check,
8291 u32 expected_gre_key)
8292{
8293 mlxsw_reg_rtdp_ipip_irif_set(payload, irif);
8294 mlxsw_reg_rtdp_ipip_sip_check_set(payload, sip_check);
8295 mlxsw_reg_rtdp_ipip_type_check_set(payload, type_check);
8296 mlxsw_reg_rtdp_ipip_gre_key_check_set(payload, gre_key_check);
8297 mlxsw_reg_rtdp_ipip_expected_gre_key_set(payload, expected_gre_key);
8298}
8299
8300static inline void
8301mlxsw_reg_rtdp_ipip4_pack(char *payload, u16 irif,
8302 enum mlxsw_reg_rtdp_ipip_sip_check sip_check,
8303 unsigned int type_check, bool gre_key_check,
8304 u32 ipv4_usip, u32 expected_gre_key)
8305{
8306 mlxsw_reg_rtdp_ipip_pack(payload, irif, sip_check, type_check,
8307 gre_key_check, expected_gre_key);
8308 mlxsw_reg_rtdp_ipip_ipv4_usip_set(payload, ipv4_usip);
8309}
8310
8311static inline void
8312mlxsw_reg_rtdp_ipip6_pack(char *payload, u16 irif,
8313 enum mlxsw_reg_rtdp_ipip_sip_check sip_check,
8314 unsigned int type_check, bool gre_key_check,
8315 u32 ipv6_usip_ptr, u32 expected_gre_key)
8316{
8317 mlxsw_reg_rtdp_ipip_pack(payload, irif, sip_check, type_check,
8318 gre_key_check, expected_gre_key);
8319 mlxsw_reg_rtdp_ipip_ipv6_usip_ptr_set(payload, ipv6_usip_ptr);
8320}
8321
8322
8323
8324
8325
8326
8327#define MLXSW_REG_RIPS_ID 0x8021
8328#define MLXSW_REG_RIPS_LEN 0x14
8329
8330MLXSW_REG_DEFINE(rips, MLXSW_REG_RIPS_ID, MLXSW_REG_RIPS_LEN);
8331
8332
8333
8334
8335
8336
8337MLXSW_ITEM32(reg, rips, index, 0x00, 0, 24);
8338
8339
8340
8341
8342
8343MLXSW_ITEM_BUF(reg, rips, ipv6, 0x04, 16);
8344
8345static inline void mlxsw_reg_rips_pack(char *payload, u32 index,
8346 const struct in6_addr *ipv6)
8347{
8348 MLXSW_REG_ZERO(rips, payload);
8349 mlxsw_reg_rips_index_set(payload, index);
8350 mlxsw_reg_rips_ipv6_memcpy_to(payload, (const char *)ipv6);
8351}
8352
8353
8354
8355
8356
8357
8358#define MLXSW_REG_RATRAD_ID 0x8022
8359#define MLXSW_REG_RATRAD_LEN 0x210
8360
8361MLXSW_REG_DEFINE(ratrad, MLXSW_REG_RATRAD_ID, MLXSW_REG_RATRAD_LEN);
8362
8363enum {
8364
8365 MLXSW_REG_RATRAD_OP_READ_ACTIVITY,
8366
8367 MLXSW_REG_RATRAD_OP_READ_CLEAR_ACTIVITY,
8368};
8369
8370
8371
8372
8373MLXSW_ITEM32(reg, ratrad, op, 0x00, 30, 2);
8374
8375
8376
8377
8378
8379
8380
8381
8382MLXSW_ITEM32(reg, ratrad, ecmp_size, 0x00, 0, 13);
8383
8384
8385
8386
8387
8388MLXSW_ITEM32(reg, ratrad, adjacency_index, 0x04, 0, 24);
8389
8390
8391
8392
8393
8394
8395MLXSW_ITEM_BIT_ARRAY(reg, ratrad, activity_vector, 0x10, 0x200, 1);
8396
8397static inline void mlxsw_reg_ratrad_pack(char *payload, u32 adjacency_index,
8398 u16 ecmp_size)
8399{
8400 MLXSW_REG_ZERO(ratrad, payload);
8401 mlxsw_reg_ratrad_op_set(payload,
8402 MLXSW_REG_RATRAD_OP_READ_CLEAR_ACTIVITY);
8403 mlxsw_reg_ratrad_ecmp_size_set(payload, ecmp_size);
8404 mlxsw_reg_ratrad_adjacency_index_set(payload, adjacency_index);
8405}
8406
8407
8408
8409
8410
8411
8412#define MLXSW_REG_RIGR2_ID 0x8023
8413#define MLXSW_REG_RIGR2_LEN 0xB0
8414
8415#define MLXSW_REG_RIGR2_MAX_ERIFS 32
8416
8417MLXSW_REG_DEFINE(rigr2, MLXSW_REG_RIGR2_ID, MLXSW_REG_RIGR2_LEN);
8418
8419
8420
8421
8422
8423MLXSW_ITEM32(reg, rigr2, rigr_index, 0x04, 0, 24);
8424
8425
8426
8427
8428
8429MLXSW_ITEM32(reg, rigr2, vnext, 0x08, 31, 1);
8430
8431
8432
8433
8434
8435
8436MLXSW_ITEM32(reg, rigr2, next_rigr_index, 0x08, 0, 24);
8437
8438
8439
8440
8441
8442MLXSW_ITEM32(reg, rigr2, vrmid, 0x20, 31, 1);
8443
8444
8445
8446
8447
8448
8449
8450
8451MLXSW_ITEM32(reg, rigr2, rmid_index, 0x20, 0, 16);
8452
8453
8454
8455
8456
8457
8458
8459
8460
8461MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_v, 0x24, 31, 1, 4, 0, false);
8462
8463
8464
8465
8466
8467
8468
8469MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_erif, 0x24, 0, 16, 4, 0, false);
8470
8471static inline void mlxsw_reg_rigr2_pack(char *payload, u32 rigr_index,
8472 bool vnext, u32 next_rigr_index)
8473{
8474 MLXSW_REG_ZERO(rigr2, payload);
8475 mlxsw_reg_rigr2_rigr_index_set(payload, rigr_index);
8476 mlxsw_reg_rigr2_vnext_set(payload, vnext);
8477 mlxsw_reg_rigr2_next_rigr_index_set(payload, next_rigr_index);
8478 mlxsw_reg_rigr2_vrmid_set(payload, 0);
8479 mlxsw_reg_rigr2_rmid_index_set(payload, 0);
8480}
8481
8482static inline void mlxsw_reg_rigr2_erif_entry_pack(char *payload, int index,
8483 bool v, u16 erif)
8484{
8485 mlxsw_reg_rigr2_erif_entry_v_set(payload, index, v);
8486 mlxsw_reg_rigr2_erif_entry_erif_set(payload, index, erif);
8487}
8488
8489
8490
8491
8492#define MLXSW_REG_RECR2_ID 0x8025
8493#define MLXSW_REG_RECR2_LEN 0x38
8494
8495MLXSW_REG_DEFINE(recr2, MLXSW_REG_RECR2_ID, MLXSW_REG_RECR2_LEN);
8496
8497
8498
8499
8500
8501MLXSW_ITEM32(reg, recr2, pp, 0x00, 24, 1);
8502
8503
8504
8505
8506
8507MLXSW_ITEM32(reg, recr2, sh, 0x00, 8, 1);
8508
8509
8510
8511
8512
8513MLXSW_ITEM32(reg, recr2, seed, 0x08, 0, 32);
8514
8515enum {
8516
8517 MLXSW_REG_RECR2_IPV4_EN_NOT_TCP_NOT_UDP = 3,
8518
8519 MLXSW_REG_RECR2_IPV4_EN_TCP_UDP = 4,
8520
8521 MLXSW_REG_RECR2_IPV6_EN_NOT_TCP_NOT_UDP = 5,
8522
8523 MLXSW_REG_RECR2_IPV6_EN_TCP_UDP = 6,
8524
8525 MLXSW_REG_RECR2_TCP_UDP_EN_IPV4 = 7,
8526
8527 MLXSW_REG_RECR2_TCP_UDP_EN_IPV6 = 8,
8528
8529 __MLXSW_REG_RECR2_HEADER_CNT,
8530};
8531
8532
8533
8534
8535
8536
8537MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_enables, 0x10, 0x04, 1);
8538
8539enum {
8540
8541 MLXSW_REG_RECR2_IPV4_SIP0 = 9,
8542 MLXSW_REG_RECR2_IPV4_SIP3 = 12,
8543
8544 MLXSW_REG_RECR2_IPV4_DIP0 = 13,
8545 MLXSW_REG_RECR2_IPV4_DIP3 = 16,
8546
8547 MLXSW_REG_RECR2_IPV4_PROTOCOL = 17,
8548
8549 MLXSW_REG_RECR2_IPV6_SIP0_7 = 21,
8550 MLXSW_REG_RECR2_IPV6_SIP8 = 29,
8551 MLXSW_REG_RECR2_IPV6_SIP15 = 36,
8552
8553 MLXSW_REG_RECR2_IPV6_DIP0_7 = 37,
8554 MLXSW_REG_RECR2_IPV6_DIP8 = 45,
8555 MLXSW_REG_RECR2_IPV6_DIP15 = 52,
8556
8557 MLXSW_REG_RECR2_IPV6_NEXT_HEADER = 53,
8558
8559 MLXSW_REG_RECR2_IPV6_FLOW_LABEL = 57,
8560
8561 MLXSW_REG_RECR2_TCP_UDP_SPORT = 74,
8562
8563 MLXSW_REG_RECR2_TCP_UDP_DPORT = 75,
8564
8565 __MLXSW_REG_RECR2_FIELD_CNT,
8566};
8567
8568
8569
8570
8571
8572MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_fields_enable, 0x14, 0x14, 1);
8573
8574
8575
8576
8577
8578
8579MLXSW_ITEM_BIT_ARRAY(reg, recr2, inner_header_enables, 0x2C, 0x04, 1);
8580
8581enum {
8582
8583 MLXSW_REG_RECR2_INNER_IPV4_SIP0 = 3,
8584 MLXSW_REG_RECR2_INNER_IPV4_SIP3 = 6,
8585
8586 MLXSW_REG_RECR2_INNER_IPV4_DIP0 = 7,
8587 MLXSW_REG_RECR2_INNER_IPV4_DIP3 = 10,
8588
8589 MLXSW_REG_RECR2_INNER_IPV4_PROTOCOL = 11,
8590
8591 MLXSW_REG_RECR2_INNER_IPV6_SIP0_7 = 12,
8592 MLXSW_REG_RECR2_INNER_IPV6_SIP8 = 20,
8593 MLXSW_REG_RECR2_INNER_IPV6_SIP15 = 27,
8594
8595 MLXSW_REG_RECR2_INNER_IPV6_DIP0_7 = 28,
8596 MLXSW_REG_RECR2_INNER_IPV6_DIP8 = 36,
8597 MLXSW_REG_RECR2_INNER_IPV6_DIP15 = 43,
8598
8599 MLXSW_REG_RECR2_INNER_IPV6_NEXT_HEADER = 44,
8600
8601 MLXSW_REG_RECR2_INNER_IPV6_FLOW_LABEL = 45,
8602
8603 MLXSW_REG_RECR2_INNER_TCP_UDP_SPORT = 46,
8604
8605 MLXSW_REG_RECR2_INNER_TCP_UDP_DPORT = 47,
8606
8607 __MLXSW_REG_RECR2_INNER_FIELD_CNT,
8608};
8609
8610
8611
8612
8613
8614MLXSW_ITEM_BIT_ARRAY(reg, recr2, inner_header_fields_enable, 0x30, 0x08, 1);
8615
8616static inline void mlxsw_reg_recr2_pack(char *payload, u32 seed)
8617{
8618 MLXSW_REG_ZERO(recr2, payload);
8619 mlxsw_reg_recr2_pp_set(payload, false);
8620 mlxsw_reg_recr2_sh_set(payload, true);
8621 mlxsw_reg_recr2_seed_set(payload, seed);
8622}
8623
8624
8625
8626
8627
8628#define MLXSW_REG_RMFT2_ID 0x8027
8629#define MLXSW_REG_RMFT2_LEN 0x174
8630
8631MLXSW_REG_DEFINE(rmft2, MLXSW_REG_RMFT2_ID, MLXSW_REG_RMFT2_LEN);
8632
8633
8634
8635
8636
8637MLXSW_ITEM32(reg, rmft2, v, 0x00, 31, 1);
8638
8639enum mlxsw_reg_rmft2_type {
8640 MLXSW_REG_RMFT2_TYPE_IPV4,
8641 MLXSW_REG_RMFT2_TYPE_IPV6
8642};
8643
8644
8645
8646
8647MLXSW_ITEM32(reg, rmft2, type, 0x00, 28, 2);
8648
8649enum mlxsw_sp_reg_rmft2_op {
8650
8651
8652
8653
8654
8655
8656
8657 MLXSW_REG_RMFT2_OP_READ_WRITE,
8658};
8659
8660
8661
8662
8663
8664MLXSW_ITEM32(reg, rmft2, op, 0x00, 20, 2);
8665
8666
8667
8668
8669
8670
8671MLXSW_ITEM32(reg, rmft2, a, 0x00, 16, 1);
8672
8673
8674
8675
8676
8677MLXSW_ITEM32(reg, rmft2, offset, 0x00, 0, 16);
8678
8679
8680
8681
8682
8683MLXSW_ITEM32(reg, rmft2, virtual_router, 0x04, 0, 16);
8684
8685enum mlxsw_reg_rmft2_irif_mask {
8686 MLXSW_REG_RMFT2_IRIF_MASK_IGNORE,
8687 MLXSW_REG_RMFT2_IRIF_MASK_COMPARE
8688};
8689
8690
8691
8692
8693
8694MLXSW_ITEM32(reg, rmft2, irif_mask, 0x08, 24, 1);
8695
8696
8697
8698
8699
8700MLXSW_ITEM32(reg, rmft2, irif, 0x08, 0, 16);
8701
8702
8703
8704
8705
8706MLXSW_ITEM_BUF(reg, rmft2, dip6, 0x10, 16);
8707MLXSW_ITEM32(reg, rmft2, dip4, 0x1C, 0, 32);
8708
8709
8710
8711
8712
8713
8714MLXSW_ITEM_BUF(reg, rmft2, dip6_mask, 0x20, 16);
8715MLXSW_ITEM32(reg, rmft2, dip4_mask, 0x2C, 0, 32);
8716
8717
8718
8719
8720
8721MLXSW_ITEM_BUF(reg, rmft2, sip6, 0x30, 16);
8722MLXSW_ITEM32(reg, rmft2, sip4, 0x3C, 0, 32);
8723
8724
8725
8726
8727
8728
8729MLXSW_ITEM_BUF(reg, rmft2, sip6_mask, 0x40, 16);
8730MLXSW_ITEM32(reg, rmft2, sip4_mask, 0x4C, 0, 32);
8731
8732
8733
8734
8735
8736
8737
8738
8739
8740
8741
8742
8743MLXSW_ITEM_BUF(reg, rmft2, flexible_action_set, 0x80,
8744 MLXSW_REG_FLEX_ACTION_SET_LEN);
8745
8746static inline void
8747mlxsw_reg_rmft2_common_pack(char *payload, bool v, u16 offset,
8748 u16 virtual_router,
8749 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif,
8750 const char *flex_action_set)
8751{
8752 MLXSW_REG_ZERO(rmft2, payload);
8753 mlxsw_reg_rmft2_v_set(payload, v);
8754 mlxsw_reg_rmft2_op_set(payload, MLXSW_REG_RMFT2_OP_READ_WRITE);
8755 mlxsw_reg_rmft2_offset_set(payload, offset);
8756 mlxsw_reg_rmft2_virtual_router_set(payload, virtual_router);
8757 mlxsw_reg_rmft2_irif_mask_set(payload, irif_mask);
8758 mlxsw_reg_rmft2_irif_set(payload, irif);
8759 if (flex_action_set)
8760 mlxsw_reg_rmft2_flexible_action_set_memcpy_to(payload,
8761 flex_action_set);
8762}
8763
8764static inline void
8765mlxsw_reg_rmft2_ipv4_pack(char *payload, bool v, u16 offset, u16 virtual_router,
8766 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif,
8767 u32 dip4, u32 dip4_mask, u32 sip4, u32 sip4_mask,
8768 const char *flexible_action_set)
8769{
8770 mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router,
8771 irif_mask, irif, flexible_action_set);
8772 mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV4);
8773 mlxsw_reg_rmft2_dip4_set(payload, dip4);
8774 mlxsw_reg_rmft2_dip4_mask_set(payload, dip4_mask);
8775 mlxsw_reg_rmft2_sip4_set(payload, sip4);
8776 mlxsw_reg_rmft2_sip4_mask_set(payload, sip4_mask);
8777}
8778
8779static inline void
8780mlxsw_reg_rmft2_ipv6_pack(char *payload, bool v, u16 offset, u16 virtual_router,
8781 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif,
8782 struct in6_addr dip6, struct in6_addr dip6_mask,
8783 struct in6_addr sip6, struct in6_addr sip6_mask,
8784 const char *flexible_action_set)
8785{
8786 mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router,
8787 irif_mask, irif, flexible_action_set);
8788 mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV6);
8789 mlxsw_reg_rmft2_dip6_memcpy_to(payload, (void *)&dip6);
8790 mlxsw_reg_rmft2_dip6_mask_memcpy_to(payload, (void *)&dip6_mask);
8791 mlxsw_reg_rmft2_sip6_memcpy_to(payload, (void *)&sip6);
8792 mlxsw_reg_rmft2_sip6_mask_memcpy_to(payload, (void *)&sip6_mask);
8793}
8794
8795
8796
8797
8798
8799
8800
8801#define MLXSW_REG_RXLTE_ID 0x8050
8802#define MLXSW_REG_RXLTE_LEN 0x0C
8803
8804MLXSW_REG_DEFINE(rxlte, MLXSW_REG_RXLTE_ID, MLXSW_REG_RXLTE_LEN);
8805
8806
8807
8808
8809
8810
8811MLXSW_ITEM32(reg, rxlte, virtual_router, 0x00, 0, 16);
8812
8813enum mlxsw_reg_rxlte_protocol {
8814 MLXSW_REG_RXLTE_PROTOCOL_IPV4,
8815 MLXSW_REG_RXLTE_PROTOCOL_IPV6,
8816};
8817
8818
8819
8820
8821MLXSW_ITEM32(reg, rxlte, protocol, 0x04, 0, 4);
8822
8823
8824
8825
8826MLXSW_ITEM32(reg, rxlte, lpm_xlt_en, 0x08, 0, 1);
8827
8828static inline void mlxsw_reg_rxlte_pack(char *payload, u16 virtual_router,
8829 enum mlxsw_reg_rxlte_protocol protocol,
8830 bool lpm_xlt_en)
8831{
8832 MLXSW_REG_ZERO(rxlte, payload);
8833 mlxsw_reg_rxlte_virtual_router_set(payload, virtual_router);
8834 mlxsw_reg_rxlte_protocol_set(payload, protocol);
8835 mlxsw_reg_rxlte_lpm_xlt_en_set(payload, lpm_xlt_en);
8836}
8837
8838
8839
8840
8841
8842
8843#define MLXSW_REG_RXLTM_ID 0x8051
8844#define MLXSW_REG_RXLTM_LEN 0x14
8845
8846MLXSW_REG_DEFINE(rxltm, MLXSW_REG_RXLTM_ID, MLXSW_REG_RXLTM_LEN);
8847
8848
8849
8850
8851
8852
8853MLXSW_ITEM32(reg, rxltm, m0_val_v6, 0x10, 16, 8);
8854
8855
8856
8857
8858
8859
8860MLXSW_ITEM32(reg, rxltm, m0_val_v4, 0x10, 0, 6);
8861
8862static inline void mlxsw_reg_rxltm_pack(char *payload, u8 m0_val_v4, u8 m0_val_v6)
8863{
8864 MLXSW_REG_ZERO(rxltm, payload);
8865 mlxsw_reg_rxltm_m0_val_v6_set(payload, m0_val_v6);
8866 mlxsw_reg_rxltm_m0_val_v4_set(payload, m0_val_v4);
8867}
8868
8869
8870
8871
8872
8873
8874
8875
8876#define MLXSW_REG_RLCMLD_ID 0x8055
8877#define MLXSW_REG_RLCMLD_LEN 0x30
8878
8879MLXSW_REG_DEFINE(rlcmld, MLXSW_REG_RLCMLD_ID, MLXSW_REG_RLCMLD_LEN);
8880
8881enum mlxsw_reg_rlcmld_select {
8882 MLXSW_REG_RLCMLD_SELECT_ML_ENTRIES,
8883 MLXSW_REG_RLCMLD_SELECT_M_ENTRIES,
8884 MLXSW_REG_RLCMLD_SELECT_M_AND_ML_ENTRIES,
8885};
8886
8887
8888
8889
8890
8891MLXSW_ITEM32(reg, rlcmld, select, 0x00, 16, 2);
8892
8893enum mlxsw_reg_rlcmld_filter_fields {
8894 MLXSW_REG_RLCMLD_FILTER_FIELDS_BY_PROTOCOL = 0x04,
8895 MLXSW_REG_RLCMLD_FILTER_FIELDS_BY_VIRTUAL_ROUTER = 0x08,
8896 MLXSW_REG_RLCMLD_FILTER_FIELDS_BY_DIP = 0x10,
8897};
8898
8899
8900
8901
8902
8903MLXSW_ITEM32(reg, rlcmld, filter_fields, 0x00, 0, 8);
8904
8905enum mlxsw_reg_rlcmld_protocol {
8906 MLXSW_REG_RLCMLD_PROTOCOL_UC_IPV4,
8907 MLXSW_REG_RLCMLD_PROTOCOL_UC_IPV6,
8908};
8909
8910
8911
8912
8913MLXSW_ITEM32(reg, rlcmld, protocol, 0x08, 0, 4);
8914
8915
8916
8917
8918
8919
8920MLXSW_ITEM32(reg, rlcmld, virtual_router, 0x0C, 0, 16);
8921
8922
8923
8924
8925
8926
8927MLXSW_ITEM32(reg, rlcmld, dip4, 0x1C, 0, 32);
8928MLXSW_ITEM_BUF(reg, rlcmld, dip6, 0x10, 16);
8929
8930
8931
8932
8933
8934
8935
8936MLXSW_ITEM32(reg, rlcmld, dip_mask4, 0x2C, 0, 32);
8937MLXSW_ITEM_BUF(reg, rlcmld, dip_mask6, 0x20, 16);
8938
8939static inline void __mlxsw_reg_rlcmld_pack(char *payload,
8940 enum mlxsw_reg_rlcmld_select select,
8941 enum mlxsw_reg_rlcmld_protocol protocol,
8942 u16 virtual_router)
8943{
8944 u8 filter_fields = MLXSW_REG_RLCMLD_FILTER_FIELDS_BY_PROTOCOL |
8945 MLXSW_REG_RLCMLD_FILTER_FIELDS_BY_VIRTUAL_ROUTER |
8946 MLXSW_REG_RLCMLD_FILTER_FIELDS_BY_DIP;
8947
8948 MLXSW_REG_ZERO(rlcmld, payload);
8949 mlxsw_reg_rlcmld_select_set(payload, select);
8950 mlxsw_reg_rlcmld_filter_fields_set(payload, filter_fields);
8951 mlxsw_reg_rlcmld_protocol_set(payload, protocol);
8952 mlxsw_reg_rlcmld_virtual_router_set(payload, virtual_router);
8953}
8954
8955static inline void mlxsw_reg_rlcmld_pack4(char *payload,
8956 enum mlxsw_reg_rlcmld_select select,
8957 u16 virtual_router,
8958 u32 dip, u32 dip_mask)
8959{
8960 __mlxsw_reg_rlcmld_pack(payload, select,
8961 MLXSW_REG_RLCMLD_PROTOCOL_UC_IPV4,
8962 virtual_router);
8963 mlxsw_reg_rlcmld_dip4_set(payload, dip);
8964 mlxsw_reg_rlcmld_dip_mask4_set(payload, dip_mask);
8965}
8966
8967static inline void mlxsw_reg_rlcmld_pack6(char *payload,
8968 enum mlxsw_reg_rlcmld_select select,
8969 u16 virtual_router,
8970 const void *dip, const void *dip_mask)
8971{
8972 __mlxsw_reg_rlcmld_pack(payload, select,
8973 MLXSW_REG_RLCMLD_PROTOCOL_UC_IPV6,
8974 virtual_router);
8975 mlxsw_reg_rlcmld_dip6_memcpy_to(payload, dip);
8976 mlxsw_reg_rlcmld_dip_mask6_memcpy_to(payload, dip_mask);
8977}
8978
8979
8980
8981
8982
8983
8984#define MLXSW_REG_RLPMCE_ID 0x8056
8985#define MLXSW_REG_RLPMCE_LEN 0x4
8986
8987MLXSW_REG_DEFINE(rlpmce, MLXSW_REG_RLPMCE_ID, MLXSW_REG_RLPMCE_LEN);
8988
8989
8990
8991
8992
8993
8994
8995MLXSW_ITEM32(reg, rlpmce, flush, 0x00, 4, 1);
8996
8997
8998
8999
9000
9001
9002
9003MLXSW_ITEM32(reg, rlpmce, disable, 0x00, 0, 1);
9004
9005static inline void mlxsw_reg_rlpmce_pack(char *payload, bool flush,
9006 bool disable)
9007{
9008 MLXSW_REG_ZERO(rlpmce, payload);
9009 mlxsw_reg_rlpmce_flush_set(payload, flush);
9010 mlxsw_reg_rlpmce_disable_set(payload, disable);
9011}
9012
9013
9014
9015
9016
9017
9018
9019
9020
9021
9022
9023#define MLXSW_REG_XLTQ_ID 0x7802
9024#define MLXSW_REG_XLTQ_LEN 0x2C
9025
9026MLXSW_REG_DEFINE(xltq, MLXSW_REG_XLTQ_ID, MLXSW_REG_XLTQ_LEN);
9027
9028enum mlxsw_reg_xltq_xm_device_id {
9029 MLXSW_REG_XLTQ_XM_DEVICE_ID_UNKNOWN,
9030 MLXSW_REG_XLTQ_XM_DEVICE_ID_XLT = 0xCF71,
9031};
9032
9033
9034
9035
9036
9037MLXSW_ITEM32(reg, xltq, xm_device_id, 0x04, 0, 16);
9038
9039
9040
9041
9042MLXSW_ITEM32(reg, xltq, xlt_cap_ipv4_lpm, 0x10, 0, 1);
9043
9044
9045
9046
9047MLXSW_ITEM32(reg, xltq, xlt_cap_ipv6_lpm, 0x10, 1, 1);
9048
9049
9050
9051
9052
9053
9054MLXSW_ITEM32(reg, xltq, cap_xlt_entries, 0x20, 0, 32);
9055
9056
9057
9058
9059
9060MLXSW_ITEM32(reg, xltq, cap_xlt_mtable, 0x24, 0, 32);
9061
9062static inline void mlxsw_reg_xltq_pack(char *payload)
9063{
9064 MLXSW_REG_ZERO(xltq, payload);
9065}
9066
9067static inline void mlxsw_reg_xltq_unpack(char *payload, u16 *xm_device_id, bool *xlt_cap_ipv4_lpm,
9068 bool *xlt_cap_ipv6_lpm, u32 *cap_xlt_entries,
9069 u32 *cap_xlt_mtable)
9070{
9071 *xm_device_id = mlxsw_reg_xltq_xm_device_id_get(payload);
9072 *xlt_cap_ipv4_lpm = mlxsw_reg_xltq_xlt_cap_ipv4_lpm_get(payload);
9073 *xlt_cap_ipv6_lpm = mlxsw_reg_xltq_xlt_cap_ipv6_lpm_get(payload);
9074 *cap_xlt_entries = mlxsw_reg_xltq_cap_xlt_entries_get(payload);
9075 *cap_xlt_mtable = mlxsw_reg_xltq_cap_xlt_mtable_get(payload);
9076}
9077
9078
9079
9080
9081
9082
9083
9084#define MLXSW_REG_XMDR_ID 0x7803
9085#define MLXSW_REG_XMDR_BASE_LEN 0x20
9086#define MLXSW_REG_XMDR_TRANS_LEN 0x80
9087#define MLXSW_REG_XMDR_LEN (MLXSW_REG_XMDR_BASE_LEN + \
9088 MLXSW_REG_XMDR_TRANS_LEN)
9089
9090MLXSW_REG_DEFINE(xmdr, MLXSW_REG_XMDR_ID, MLXSW_REG_XMDR_LEN);
9091
9092
9093
9094
9095
9096
9097
9098MLXSW_ITEM32(reg, xmdr, bulk_entry, 0x04, 8, 1);
9099
9100
9101
9102
9103
9104
9105
9106
9107MLXSW_ITEM32(reg, xmdr, num_rec, 0x04, 0, 4);
9108
9109
9110
9111
9112
9113
9114
9115
9116
9117
9118
9119MLXSW_ITEM_BIT_ARRAY(reg, xmdr, reply_vect, 0x08, 4, 1);
9120
9121static inline void mlxsw_reg_xmdr_pack(char *payload, bool bulk_entry)
9122{
9123 MLXSW_REG_ZERO(xmdr, payload);
9124 mlxsw_reg_xmdr_bulk_entry_set(payload, bulk_entry);
9125}
9126
9127enum mlxsw_reg_xmdr_c_cmd_id {
9128 MLXSW_REG_XMDR_C_CMD_ID_LT_ROUTE_V4 = 0x30,
9129 MLXSW_REG_XMDR_C_CMD_ID_LT_ROUTE_V6 = 0x31,
9130};
9131
9132#define MLXSW_REG_XMDR_C_LT_ROUTE_V4_LEN 32
9133#define MLXSW_REG_XMDR_C_LT_ROUTE_V6_LEN 48
9134
9135
9136
9137MLXSW_ITEM32(reg, xmdr_c, cmd_id, 0x00, 24, 8);
9138
9139
9140
9141MLXSW_ITEM32(reg, xmdr_c, seq_number, 0x00, 12, 12);
9142
9143enum mlxsw_reg_xmdr_c_ltr_op {
9144
9145 MLXSW_REG_XMDR_C_LTR_OP_WRITE = 0,
9146
9147 MLXSW_REG_XMDR_C_LTR_OP_UPDATE = 1,
9148 MLXSW_REG_XMDR_C_LTR_OP_DELETE = 2,
9149};
9150
9151
9152
9153
9154MLXSW_ITEM32(reg, xmdr_c, ltr_op, 0x04, 24, 8);
9155
9156
9157
9158
9159
9160MLXSW_ITEM32(reg, xmdr_c, ltr_trap_action, 0x04, 20, 4);
9161
9162enum mlxsw_reg_xmdr_c_ltr_trap_id_num {
9163 MLXSW_REG_XMDR_C_LTR_TRAP_ID_NUM_RTR_INGRESS0,
9164 MLXSW_REG_XMDR_C_LTR_TRAP_ID_NUM_RTR_INGRESS1,
9165 MLXSW_REG_XMDR_C_LTR_TRAP_ID_NUM_RTR_INGRESS2,
9166 MLXSW_REG_XMDR_C_LTR_TRAP_ID_NUM_RTR_INGRESS3,
9167};
9168
9169
9170
9171
9172MLXSW_ITEM32(reg, xmdr_c, ltr_trap_id_num, 0x04, 16, 4);
9173
9174
9175
9176
9177
9178MLXSW_ITEM32(reg, xmdr_c, ltr_virtual_router, 0x04, 0, 16);
9179
9180
9181
9182
9183MLXSW_ITEM32(reg, xmdr_c, ltr_prefix_len, 0x08, 24, 8);
9184
9185
9186
9187
9188
9189
9190MLXSW_ITEM32(reg, xmdr_c, ltr_bmp_len, 0x08, 16, 8);
9191
9192
9193
9194
9195
9196MLXSW_ITEM32(reg, xmdr_c, ltr_entry_type, 0x08, 4, 4);
9197
9198enum mlxsw_reg_xmdr_c_ltr_action_type {
9199 MLXSW_REG_XMDR_C_LTR_ACTION_TYPE_LOCAL,
9200 MLXSW_REG_XMDR_C_LTR_ACTION_TYPE_REMOTE,
9201 MLXSW_REG_XMDR_C_LTR_ACTION_TYPE_IP2ME,
9202};
9203
9204
9205
9206
9207MLXSW_ITEM32(reg, xmdr_c, ltr_action_type, 0x08, 0, 4);
9208
9209
9210
9211
9212
9213MLXSW_ITEM32(reg, xmdr_c, ltr_erif, 0x10, 0, 16);
9214
9215
9216
9217
9218
9219MLXSW_ITEM32(reg, xmdr_c, ltr_adjacency_index, 0x10, 0, 24);
9220
9221#define MLXSW_REG_XMDR_C_LTR_POINTER_TO_TUNNEL_DISABLED_MAGIC 0xFFFFFF
9222
9223
9224
9225
9226MLXSW_ITEM32(reg, xmdr_c, ltr_pointer_to_tunnel, 0x10, 0, 24);
9227
9228
9229
9230
9231
9232
9233
9234MLXSW_ITEM32(reg, xmdr_c, ltr_ecmp_size, 0x14, 0, 32);
9235
9236
9237
9238
9239
9240
9241
9242MLXSW_ITEM32(reg, xmdr_c, ltr_dip4, 0x1C, 0, 32);
9243MLXSW_ITEM_BUF(reg, xmdr_c, ltr_dip6, 0x1C, 16);
9244
9245static inline void
9246mlxsw_reg_xmdr_c_ltr_pack(char *xmdr_payload, unsigned int trans_offset,
9247 enum mlxsw_reg_xmdr_c_cmd_id cmd_id, u16 seq_number,
9248 enum mlxsw_reg_xmdr_c_ltr_op op, u16 virtual_router,
9249 u8 prefix_len)
9250{
9251 char *payload = xmdr_payload + MLXSW_REG_XMDR_BASE_LEN + trans_offset;
9252 u8 num_rec = mlxsw_reg_xmdr_num_rec_get(xmdr_payload);
9253
9254 mlxsw_reg_xmdr_num_rec_set(xmdr_payload, num_rec + 1);
9255
9256 mlxsw_reg_xmdr_c_cmd_id_set(payload, cmd_id);
9257 mlxsw_reg_xmdr_c_seq_number_set(payload, seq_number);
9258 mlxsw_reg_xmdr_c_ltr_op_set(payload, op);
9259 mlxsw_reg_xmdr_c_ltr_virtual_router_set(payload, virtual_router);
9260 mlxsw_reg_xmdr_c_ltr_prefix_len_set(payload, prefix_len);
9261 mlxsw_reg_xmdr_c_ltr_entry_type_set(payload,
9262 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY);
9263 mlxsw_reg_xmdr_c_ltr_bmp_len_set(payload, prefix_len);
9264}
9265
9266static inline unsigned int
9267mlxsw_reg_xmdr_c_ltr_pack4(char *xmdr_payload, unsigned int trans_offset,
9268 u16 seq_number, enum mlxsw_reg_xmdr_c_ltr_op op,
9269 u16 virtual_router, u8 prefix_len, u32 *dip)
9270{
9271 char *payload = xmdr_payload + MLXSW_REG_XMDR_BASE_LEN + trans_offset;
9272
9273 mlxsw_reg_xmdr_c_ltr_pack(xmdr_payload, trans_offset,
9274 MLXSW_REG_XMDR_C_CMD_ID_LT_ROUTE_V4,
9275 seq_number, op, virtual_router, prefix_len);
9276 if (dip)
9277 mlxsw_reg_xmdr_c_ltr_dip4_set(payload, *dip);
9278 return MLXSW_REG_XMDR_C_LT_ROUTE_V4_LEN;
9279}
9280
9281static inline unsigned int
9282mlxsw_reg_xmdr_c_ltr_pack6(char *xmdr_payload, unsigned int trans_offset,
9283 u16 seq_number, enum mlxsw_reg_xmdr_c_ltr_op op,
9284 u16 virtual_router, u8 prefix_len, const void *dip)
9285{
9286 char *payload = xmdr_payload + MLXSW_REG_XMDR_BASE_LEN + trans_offset;
9287
9288 mlxsw_reg_xmdr_c_ltr_pack(xmdr_payload, trans_offset,
9289 MLXSW_REG_XMDR_C_CMD_ID_LT_ROUTE_V6,
9290 seq_number, op, virtual_router, prefix_len);
9291 if (dip)
9292 mlxsw_reg_xmdr_c_ltr_dip6_memcpy_to(payload, dip);
9293 return MLXSW_REG_XMDR_C_LT_ROUTE_V6_LEN;
9294}
9295
9296static inline void
9297mlxsw_reg_xmdr_c_ltr_act_remote_pack(char *xmdr_payload, unsigned int trans_offset,
9298 enum mlxsw_reg_ralue_trap_action trap_action,
9299 enum mlxsw_reg_xmdr_c_ltr_trap_id_num trap_id_num,
9300 u32 adjacency_index, u16 ecmp_size)
9301{
9302 char *payload = xmdr_payload + MLXSW_REG_XMDR_BASE_LEN + trans_offset;
9303
9304 mlxsw_reg_xmdr_c_ltr_action_type_set(payload, MLXSW_REG_XMDR_C_LTR_ACTION_TYPE_REMOTE);
9305 mlxsw_reg_xmdr_c_ltr_trap_action_set(payload, trap_action);
9306 mlxsw_reg_xmdr_c_ltr_trap_id_num_set(payload, trap_id_num);
9307 mlxsw_reg_xmdr_c_ltr_adjacency_index_set(payload, adjacency_index);
9308 mlxsw_reg_xmdr_c_ltr_ecmp_size_set(payload, ecmp_size);
9309}
9310
9311static inline void
9312mlxsw_reg_xmdr_c_ltr_act_local_pack(char *xmdr_payload, unsigned int trans_offset,
9313 enum mlxsw_reg_ralue_trap_action trap_action,
9314 enum mlxsw_reg_xmdr_c_ltr_trap_id_num trap_id_num, u16 erif)
9315{
9316 char *payload = xmdr_payload + MLXSW_REG_XMDR_BASE_LEN + trans_offset;
9317
9318 mlxsw_reg_xmdr_c_ltr_action_type_set(payload, MLXSW_REG_XMDR_C_LTR_ACTION_TYPE_LOCAL);
9319 mlxsw_reg_xmdr_c_ltr_trap_action_set(payload, trap_action);
9320 mlxsw_reg_xmdr_c_ltr_trap_id_num_set(payload, trap_id_num);
9321 mlxsw_reg_xmdr_c_ltr_erif_set(payload, erif);
9322}
9323
9324static inline void mlxsw_reg_xmdr_c_ltr_act_ip2me_pack(char *xmdr_payload,
9325 unsigned int trans_offset)
9326{
9327 char *payload = xmdr_payload + MLXSW_REG_XMDR_BASE_LEN + trans_offset;
9328
9329 mlxsw_reg_xmdr_c_ltr_action_type_set(payload, MLXSW_REG_XMDR_C_LTR_ACTION_TYPE_IP2ME);
9330 mlxsw_reg_xmdr_c_ltr_pointer_to_tunnel_set(payload,
9331 MLXSW_REG_XMDR_C_LTR_POINTER_TO_TUNNEL_DISABLED_MAGIC);
9332}
9333
9334static inline void mlxsw_reg_xmdr_c_ltr_act_ip2me_tun_pack(char *xmdr_payload,
9335 unsigned int trans_offset,
9336 u32 pointer_to_tunnel)
9337{
9338 char *payload = xmdr_payload + MLXSW_REG_XMDR_BASE_LEN + trans_offset;
9339
9340 mlxsw_reg_xmdr_c_ltr_action_type_set(payload, MLXSW_REG_XMDR_C_LTR_ACTION_TYPE_IP2ME);
9341 mlxsw_reg_xmdr_c_ltr_pointer_to_tunnel_set(payload, pointer_to_tunnel);
9342}
9343
9344
9345
9346
9347
9348#define MLXSW_REG_XRMT_ID 0x7810
9349#define MLXSW_REG_XRMT_LEN 0x14
9350
9351MLXSW_REG_DEFINE(xrmt, MLXSW_REG_XRMT_ID, MLXSW_REG_XRMT_LEN);
9352
9353
9354
9355
9356
9357
9358MLXSW_ITEM32(reg, xrmt, index, 0x04, 0, 20);
9359
9360
9361
9362
9363MLXSW_ITEM32(reg, xrmt, l0_val, 0x10, 24, 8);
9364
9365static inline void mlxsw_reg_xrmt_pack(char *payload, u32 index, u8 l0_val)
9366{
9367 MLXSW_REG_ZERO(xrmt, payload);
9368 mlxsw_reg_xrmt_index_set(payload, index);
9369 mlxsw_reg_xrmt_l0_val_set(payload, l0_val);
9370}
9371
9372
9373
9374
9375
9376
9377
9378#define MLXSW_REG_XRALTA_ID 0x7811
9379#define MLXSW_REG_XRALTA_LEN 0x08
9380#define MLXSW_REG_XRALTA_RALTA_OFFSET 0x04
9381
9382MLXSW_REG_DEFINE(xralta, MLXSW_REG_XRALTA_ID, MLXSW_REG_XRALTA_LEN);
9383
9384static inline void mlxsw_reg_xralta_pack(char *payload, bool alloc,
9385 enum mlxsw_reg_ralxx_protocol protocol,
9386 u8 tree_id)
9387{
9388 char *ralta_payload = payload + MLXSW_REG_XRALTA_RALTA_OFFSET;
9389
9390 MLXSW_REG_ZERO(xralta, payload);
9391 mlxsw_reg_ralta_pack(ralta_payload, alloc, protocol, tree_id);
9392}
9393
9394
9395
9396
9397
9398
9399
9400#define MLXSW_REG_XRALST_ID 0x7812
9401#define MLXSW_REG_XRALST_LEN 0x108
9402#define MLXSW_REG_XRALST_RALST_OFFSET 0x04
9403
9404MLXSW_REG_DEFINE(xralst, MLXSW_REG_XRALST_ID, MLXSW_REG_XRALST_LEN);
9405
9406static inline void mlxsw_reg_xralst_pack(char *payload, u8 root_bin, u8 tree_id)
9407{
9408 char *ralst_payload = payload + MLXSW_REG_XRALST_RALST_OFFSET;
9409
9410 MLXSW_REG_ZERO(xralst, payload);
9411 mlxsw_reg_ralst_pack(ralst_payload, root_bin, tree_id);
9412}
9413
9414static inline void mlxsw_reg_xralst_bin_pack(char *payload, u8 bin_number,
9415 u8 left_child_bin,
9416 u8 right_child_bin)
9417{
9418 char *ralst_payload = payload + MLXSW_REG_XRALST_RALST_OFFSET;
9419
9420 mlxsw_reg_ralst_bin_pack(ralst_payload, bin_number, left_child_bin,
9421 right_child_bin);
9422}
9423
9424
9425
9426
9427
9428
9429
9430
9431#define MLXSW_REG_XRALTB_ID 0x7813
9432#define MLXSW_REG_XRALTB_LEN 0x08
9433#define MLXSW_REG_XRALTB_RALTB_OFFSET 0x04
9434
9435MLXSW_REG_DEFINE(xraltb, MLXSW_REG_XRALTB_ID, MLXSW_REG_XRALTB_LEN);
9436
9437static inline void mlxsw_reg_xraltb_pack(char *payload, u16 virtual_router,
9438 enum mlxsw_reg_ralxx_protocol protocol,
9439 u8 tree_id)
9440{
9441 char *raltb_payload = payload + MLXSW_REG_XRALTB_RALTB_OFFSET;
9442
9443 MLXSW_REG_ZERO(xraltb, payload);
9444 mlxsw_reg_raltb_pack(raltb_payload, virtual_router, protocol, tree_id);
9445}
9446
9447
9448
9449
9450
9451#define MLXSW_REG_MFCR_ID 0x9001
9452#define MLXSW_REG_MFCR_LEN 0x08
9453
9454MLXSW_REG_DEFINE(mfcr, MLXSW_REG_MFCR_ID, MLXSW_REG_MFCR_LEN);
9455
9456enum mlxsw_reg_mfcr_pwm_frequency {
9457 MLXSW_REG_MFCR_PWM_FEQ_11HZ = 0x00,
9458 MLXSW_REG_MFCR_PWM_FEQ_14_7HZ = 0x01,
9459 MLXSW_REG_MFCR_PWM_FEQ_22_1HZ = 0x02,
9460 MLXSW_REG_MFCR_PWM_FEQ_1_4KHZ = 0x40,
9461 MLXSW_REG_MFCR_PWM_FEQ_5KHZ = 0x41,
9462 MLXSW_REG_MFCR_PWM_FEQ_20KHZ = 0x42,
9463 MLXSW_REG_MFCR_PWM_FEQ_22_5KHZ = 0x43,
9464 MLXSW_REG_MFCR_PWM_FEQ_25KHZ = 0x44,
9465};
9466
9467
9468
9469
9470
9471MLXSW_ITEM32(reg, mfcr, pwm_frequency, 0x00, 0, 7);
9472
9473#define MLXSW_MFCR_TACHOS_MAX 10
9474
9475
9476
9477
9478
9479MLXSW_ITEM32(reg, mfcr, tacho_active, 0x04, 16, MLXSW_MFCR_TACHOS_MAX);
9480
9481#define MLXSW_MFCR_PWMS_MAX 5
9482
9483
9484
9485
9486
9487MLXSW_ITEM32(reg, mfcr, pwm_active, 0x04, 0, MLXSW_MFCR_PWMS_MAX);
9488
9489static inline void
9490mlxsw_reg_mfcr_pack(char *payload,
9491 enum mlxsw_reg_mfcr_pwm_frequency pwm_frequency)
9492{
9493 MLXSW_REG_ZERO(mfcr, payload);
9494 mlxsw_reg_mfcr_pwm_frequency_set(payload, pwm_frequency);
9495}
9496
9497static inline void
9498mlxsw_reg_mfcr_unpack(char *payload,
9499 enum mlxsw_reg_mfcr_pwm_frequency *p_pwm_frequency,
9500 u16 *p_tacho_active, u8 *p_pwm_active)
9501{
9502 *p_pwm_frequency = mlxsw_reg_mfcr_pwm_frequency_get(payload);
9503 *p_tacho_active = mlxsw_reg_mfcr_tacho_active_get(payload);
9504 *p_pwm_active = mlxsw_reg_mfcr_pwm_active_get(payload);
9505}
9506
9507
9508
9509
9510
9511#define MLXSW_REG_MFSC_ID 0x9002
9512#define MLXSW_REG_MFSC_LEN 0x08
9513
9514MLXSW_REG_DEFINE(mfsc, MLXSW_REG_MFSC_ID, MLXSW_REG_MFSC_LEN);
9515
9516
9517
9518
9519
9520MLXSW_ITEM32(reg, mfsc, pwm, 0x00, 24, 3);
9521
9522
9523
9524
9525
9526
9527MLXSW_ITEM32(reg, mfsc, pwm_duty_cycle, 0x04, 0, 8);
9528
9529static inline void mlxsw_reg_mfsc_pack(char *payload, u8 pwm,
9530 u8 pwm_duty_cycle)
9531{
9532 MLXSW_REG_ZERO(mfsc, payload);
9533 mlxsw_reg_mfsc_pwm_set(payload, pwm);
9534 mlxsw_reg_mfsc_pwm_duty_cycle_set(payload, pwm_duty_cycle);
9535}
9536
9537
9538
9539
9540
9541
9542#define MLXSW_REG_MFSM_ID 0x9003
9543#define MLXSW_REG_MFSM_LEN 0x08
9544
9545MLXSW_REG_DEFINE(mfsm, MLXSW_REG_MFSM_ID, MLXSW_REG_MFSM_LEN);
9546
9547
9548
9549
9550
9551MLXSW_ITEM32(reg, mfsm, tacho, 0x00, 24, 4);
9552
9553
9554
9555
9556
9557MLXSW_ITEM32(reg, mfsm, rpm, 0x04, 0, 16);
9558
9559static inline void mlxsw_reg_mfsm_pack(char *payload, u8 tacho)
9560{
9561 MLXSW_REG_ZERO(mfsm, payload);
9562 mlxsw_reg_mfsm_tacho_set(payload, tacho);
9563}
9564
9565
9566
9567
9568
9569
9570
9571#define MLXSW_REG_MFSL_ID 0x9004
9572#define MLXSW_REG_MFSL_LEN 0x0C
9573
9574MLXSW_REG_DEFINE(mfsl, MLXSW_REG_MFSL_ID, MLXSW_REG_MFSL_LEN);
9575
9576
9577
9578
9579
9580MLXSW_ITEM32(reg, mfsl, tacho, 0x00, 24, 4);
9581
9582
9583
9584
9585
9586MLXSW_ITEM32(reg, mfsl, tach_min, 0x04, 0, 16);
9587
9588
9589
9590
9591
9592MLXSW_ITEM32(reg, mfsl, tach_max, 0x08, 0, 16);
9593
9594static inline void mlxsw_reg_mfsl_pack(char *payload, u8 tacho,
9595 u16 tach_min, u16 tach_max)
9596{
9597 MLXSW_REG_ZERO(mfsl, payload);
9598 mlxsw_reg_mfsl_tacho_set(payload, tacho);
9599 mlxsw_reg_mfsl_tach_min_set(payload, tach_min);
9600 mlxsw_reg_mfsl_tach_max_set(payload, tach_max);
9601}
9602
9603static inline void mlxsw_reg_mfsl_unpack(char *payload, u8 tacho,
9604 u16 *p_tach_min, u16 *p_tach_max)
9605{
9606 if (p_tach_min)
9607 *p_tach_min = mlxsw_reg_mfsl_tach_min_get(payload);
9608
9609 if (p_tach_max)
9610 *p_tach_max = mlxsw_reg_mfsl_tach_max_get(payload);
9611}
9612
9613
9614
9615
9616
9617
9618#define MLXSW_REG_FORE_ID 0x9007
9619#define MLXSW_REG_FORE_LEN 0x0C
9620
9621MLXSW_REG_DEFINE(fore, MLXSW_REG_FORE_ID, MLXSW_REG_FORE_LEN);
9622
9623
9624
9625
9626
9627
9628
9629MLXSW_ITEM32(reg, fore, fan_under_limit, 0x00, 16, 10);
9630
9631static inline void mlxsw_reg_fore_unpack(char *payload, u8 tacho,
9632 bool *fault)
9633{
9634 u16 limit;
9635
9636 if (fault) {
9637 limit = mlxsw_reg_fore_fan_under_limit_get(payload);
9638 *fault = limit & BIT(tacho);
9639 }
9640}
9641
9642
9643
9644
9645
9646
9647#define MLXSW_REG_MTCAP_ID 0x9009
9648#define MLXSW_REG_MTCAP_LEN 0x08
9649
9650MLXSW_REG_DEFINE(mtcap, MLXSW_REG_MTCAP_ID, MLXSW_REG_MTCAP_LEN);
9651
9652
9653
9654
9655
9656
9657MLXSW_ITEM32(reg, mtcap, sensor_count, 0x00, 0, 7);
9658
9659
9660
9661
9662
9663
9664
9665#define MLXSW_REG_MTMP_ID 0x900A
9666#define MLXSW_REG_MTMP_LEN 0x20
9667
9668MLXSW_REG_DEFINE(mtmp, MLXSW_REG_MTMP_ID, MLXSW_REG_MTMP_LEN);
9669
9670#define MLXSW_REG_MTMP_MODULE_INDEX_MIN 64
9671#define MLXSW_REG_MTMP_GBOX_INDEX_MIN 256
9672
9673
9674
9675
9676
9677
9678MLXSW_ITEM32(reg, mtmp, sensor_index, 0x00, 0, 12);
9679
9680
9681#define MLXSW_REG_MTMP_TEMP_TO_MC(val) ({ typeof(val) v_ = (val); \
9682 ((v_) >= 0) ? ((v_) * 125) : \
9683 ((s16)((GENMASK(15, 0) + (v_) + 1) \
9684 * 125)); })
9685
9686
9687
9688
9689
9690
9691
9692MLXSW_ITEM32(reg, mtmp, max_operational_temperature, 0x04, 16, 16);
9693
9694
9695
9696
9697
9698
9699MLXSW_ITEM32(reg, mtmp, temperature, 0x04, 0, 16);
9700
9701
9702
9703
9704
9705MLXSW_ITEM32(reg, mtmp, mte, 0x08, 31, 1);
9706
9707
9708
9709
9710
9711MLXSW_ITEM32(reg, mtmp, mtr, 0x08, 30, 1);
9712
9713
9714
9715
9716
9717
9718MLXSW_ITEM32(reg, mtmp, max_temperature, 0x08, 0, 16);
9719
9720
9721
9722
9723
9724
9725
9726
9727
9728enum mlxsw_reg_mtmp_tee {
9729 MLXSW_REG_MTMP_TEE_NO_EVENT,
9730 MLXSW_REG_MTMP_TEE_GENERATE_EVENT,
9731 MLXSW_REG_MTMP_TEE_GENERATE_SINGLE_EVENT,
9732};
9733
9734MLXSW_ITEM32(reg, mtmp, tee, 0x0C, 30, 2);
9735
9736#define MLXSW_REG_MTMP_THRESH_HI 0x348
9737
9738
9739
9740
9741
9742MLXSW_ITEM32(reg, mtmp, temperature_threshold_hi, 0x0C, 0, 16);
9743
9744#define MLXSW_REG_MTMP_HYSTERESIS_TEMP 0x28
9745
9746
9747
9748
9749MLXSW_ITEM32(reg, mtmp, temperature_threshold_lo, 0x10, 0, 16);
9750
9751#define MLXSW_REG_MTMP_SENSOR_NAME_SIZE 8
9752
9753
9754
9755
9756
9757MLXSW_ITEM_BUF(reg, mtmp, sensor_name, 0x18, MLXSW_REG_MTMP_SENSOR_NAME_SIZE);
9758
9759static inline void mlxsw_reg_mtmp_pack(char *payload, u16 sensor_index,
9760 bool max_temp_enable,
9761 bool max_temp_reset)
9762{
9763 MLXSW_REG_ZERO(mtmp, payload);
9764 mlxsw_reg_mtmp_sensor_index_set(payload, sensor_index);
9765 mlxsw_reg_mtmp_mte_set(payload, max_temp_enable);
9766 mlxsw_reg_mtmp_mtr_set(payload, max_temp_reset);
9767 mlxsw_reg_mtmp_temperature_threshold_hi_set(payload,
9768 MLXSW_REG_MTMP_THRESH_HI);
9769}
9770
9771static inline void mlxsw_reg_mtmp_unpack(char *payload, int *p_temp,
9772 int *p_max_temp, int *p_temp_hi,
9773 int *p_max_oper_temp,
9774 char *sensor_name)
9775{
9776 s16 temp;
9777
9778 if (p_temp) {
9779 temp = mlxsw_reg_mtmp_temperature_get(payload);
9780 *p_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp);
9781 }
9782 if (p_max_temp) {
9783 temp = mlxsw_reg_mtmp_max_temperature_get(payload);
9784 *p_max_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp);
9785 }
9786 if (p_temp_hi) {
9787 temp = mlxsw_reg_mtmp_temperature_threshold_hi_get(payload);
9788 *p_temp_hi = MLXSW_REG_MTMP_TEMP_TO_MC(temp);
9789 }
9790 if (p_max_oper_temp) {
9791 temp = mlxsw_reg_mtmp_max_operational_temperature_get(payload);
9792 *p_max_oper_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp);
9793 }
9794 if (sensor_name)
9795 mlxsw_reg_mtmp_sensor_name_memcpy_from(payload, sensor_name);
9796}
9797
9798
9799
9800
9801
9802#define MLXSW_REG_MTWE_ID 0x900B
9803#define MLXSW_REG_MTWE_LEN 0x10
9804
9805MLXSW_REG_DEFINE(mtwe, MLXSW_REG_MTWE_ID, MLXSW_REG_MTWE_LEN);
9806
9807
9808
9809
9810
9811
9812
9813MLXSW_ITEM_BIT_ARRAY(reg, mtwe, sensor_warning, 0x0, 0x10, 1);
9814
9815
9816
9817
9818
9819#define MLXSW_REG_MTBR_ID 0x900F
9820#define MLXSW_REG_MTBR_BASE_LEN 0x10
9821#define MLXSW_REG_MTBR_REC_LEN 0x04
9822#define MLXSW_REG_MTBR_REC_MAX_COUNT 47
9823#define MLXSW_REG_MTBR_LEN (MLXSW_REG_MTBR_BASE_LEN + \
9824 MLXSW_REG_MTBR_REC_LEN * \
9825 MLXSW_REG_MTBR_REC_MAX_COUNT)
9826
9827MLXSW_REG_DEFINE(mtbr, MLXSW_REG_MTBR_ID, MLXSW_REG_MTBR_LEN);
9828
9829
9830
9831
9832
9833
9834MLXSW_ITEM32(reg, mtbr, base_sensor_index, 0x00, 0, 12);
9835
9836
9837
9838
9839
9840
9841
9842
9843MLXSW_ITEM32(reg, mtbr, num_rec, 0x04, 0, 8);
9844
9845
9846
9847
9848
9849
9850MLXSW_ITEM32_INDEXED(reg, mtbr, rec_max_temp, MLXSW_REG_MTBR_BASE_LEN, 16,
9851 16, MLXSW_REG_MTBR_REC_LEN, 0x00, false);
9852
9853
9854
9855
9856
9857
9858MLXSW_ITEM32_INDEXED(reg, mtbr, rec_temp, MLXSW_REG_MTBR_BASE_LEN, 0, 16,
9859 MLXSW_REG_MTBR_REC_LEN, 0x00, false);
9860
9861static inline void mlxsw_reg_mtbr_pack(char *payload, u16 base_sensor_index,
9862 u8 num_rec)
9863{
9864 MLXSW_REG_ZERO(mtbr, payload);
9865 mlxsw_reg_mtbr_base_sensor_index_set(payload, base_sensor_index);
9866 mlxsw_reg_mtbr_num_rec_set(payload, num_rec);
9867}
9868
9869
9870enum mlxsw_reg_mtbr_temp_status {
9871 MLXSW_REG_MTBR_NO_CONN = 0x8000,
9872 MLXSW_REG_MTBR_NO_TEMP_SENS = 0x8001,
9873 MLXSW_REG_MTBR_INDEX_NA = 0x8002,
9874 MLXSW_REG_MTBR_BAD_SENS_INFO = 0x8003,
9875};
9876
9877
9878#define MLXSW_REG_MTBR_BASE_MODULE_INDEX 64
9879
9880static inline void mlxsw_reg_mtbr_temp_unpack(char *payload, int rec_ind,
9881 u16 *p_temp, u16 *p_max_temp)
9882{
9883 if (p_temp)
9884 *p_temp = mlxsw_reg_mtbr_rec_temp_get(payload, rec_ind);
9885 if (p_max_temp)
9886 *p_max_temp = mlxsw_reg_mtbr_rec_max_temp_get(payload, rec_ind);
9887}
9888
9889
9890
9891
9892
9893
9894#define MLXSW_REG_MCIA_ID 0x9014
9895#define MLXSW_REG_MCIA_LEN 0x40
9896
9897MLXSW_REG_DEFINE(mcia, MLXSW_REG_MCIA_ID, MLXSW_REG_MCIA_LEN);
9898
9899
9900
9901
9902
9903
9904
9905MLXSW_ITEM32(reg, mcia, l, 0x00, 31, 1);
9906
9907
9908
9909
9910
9911MLXSW_ITEM32(reg, mcia, module, 0x00, 16, 8);
9912
9913enum {
9914 MLXSW_REG_MCIA_STATUS_GOOD = 0,
9915
9916 MLXSW_REG_MCIA_STATUS_NO_EEPROM_MODULE = 1,
9917
9918 MLXSW_REG_MCIA_STATUS_MODULE_NOT_SUPPORTED = 2,
9919
9920 MLXSW_REG_MCIA_STATUS_MODULE_NOT_CONNECTED = 3,
9921
9922 MLXSW_REG_MCIA_STATUS_I2C_ERROR = 9,
9923
9924 MLXSW_REG_MCIA_STATUS_MODULE_DISABLED = 16,
9925};
9926
9927
9928
9929
9930
9931MLXSW_ITEM32(reg, mcia, status, 0x00, 0, 8);
9932
9933
9934
9935
9936
9937MLXSW_ITEM32(reg, mcia, i2c_device_address, 0x04, 24, 8);
9938
9939
9940
9941
9942
9943MLXSW_ITEM32(reg, mcia, page_number, 0x04, 16, 8);
9944
9945
9946
9947
9948
9949MLXSW_ITEM32(reg, mcia, device_address, 0x04, 0, 16);
9950
9951
9952
9953
9954
9955MLXSW_ITEM32(reg, mcia, bank_number, 0x08, 16, 8);
9956
9957
9958
9959
9960
9961MLXSW_ITEM32(reg, mcia, size, 0x08, 0, 16);
9962
9963#define MLXSW_REG_MCIA_EEPROM_PAGE_LENGTH 256
9964#define MLXSW_REG_MCIA_EEPROM_UP_PAGE_LENGTH 128
9965#define MLXSW_REG_MCIA_EEPROM_SIZE 48
9966#define MLXSW_REG_MCIA_I2C_ADDR_LOW 0x50
9967#define MLXSW_REG_MCIA_I2C_ADDR_HIGH 0x51
9968#define MLXSW_REG_MCIA_PAGE0_LO_OFF 0xa0
9969#define MLXSW_REG_MCIA_TH_ITEM_SIZE 2
9970#define MLXSW_REG_MCIA_TH_PAGE_NUM 3
9971#define MLXSW_REG_MCIA_TH_PAGE_CMIS_NUM 2
9972#define MLXSW_REG_MCIA_PAGE0_LO 0
9973#define MLXSW_REG_MCIA_TH_PAGE_OFF 0x80
9974#define MLXSW_REG_MCIA_EEPROM_CMIS_FLAT_MEMORY BIT(7)
9975
9976enum mlxsw_reg_mcia_eeprom_module_info_rev_id {
9977 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_UNSPC = 0x00,
9978 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_8436 = 0x01,
9979 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_8636 = 0x03,
9980};
9981
9982enum mlxsw_reg_mcia_eeprom_module_info_id {
9983 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_SFP = 0x03,
9984 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP = 0x0C,
9985 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP_PLUS = 0x0D,
9986 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP28 = 0x11,
9987 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP_DD = 0x18,
9988};
9989
9990enum mlxsw_reg_mcia_eeprom_module_info {
9991 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID,
9992 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID,
9993 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_TYPE_ID,
9994 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_SIZE,
9995};
9996
9997
9998
9999
10000
10001MLXSW_ITEM_BUF(reg, mcia, eeprom, 0x10, MLXSW_REG_MCIA_EEPROM_SIZE);
10002
10003
10004
10005
10006
10007#define MLXSW_REG_MCIA_PAGE_GET(off) (((off) - \
10008 MLXSW_REG_MCIA_EEPROM_PAGE_LENGTH) / \
10009 MLXSW_REG_MCIA_EEPROM_UP_PAGE_LENGTH + 1)
10010
10011static inline void mlxsw_reg_mcia_pack(char *payload, u8 module, u8 lock,
10012 u8 page_number, u16 device_addr,
10013 u8 size, u8 i2c_device_addr)
10014{
10015 MLXSW_REG_ZERO(mcia, payload);
10016 mlxsw_reg_mcia_module_set(payload, module);
10017 mlxsw_reg_mcia_l_set(payload, lock);
10018 mlxsw_reg_mcia_page_number_set(payload, page_number);
10019 mlxsw_reg_mcia_device_address_set(payload, device_addr);
10020 mlxsw_reg_mcia_size_set(payload, size);
10021 mlxsw_reg_mcia_i2c_device_address_set(payload, i2c_device_addr);
10022}
10023
10024
10025
10026
10027
10028
10029#define MLXSW_REG_MPAT_ID 0x901A
10030#define MLXSW_REG_MPAT_LEN 0x78
10031
10032MLXSW_REG_DEFINE(mpat, MLXSW_REG_MPAT_ID, MLXSW_REG_MPAT_LEN);
10033
10034
10035
10036
10037
10038MLXSW_ITEM32(reg, mpat, pa_id, 0x00, 28, 4);
10039
10040
10041
10042
10043
10044
10045MLXSW_ITEM32(reg, mpat, session_id, 0x00, 24, 4);
10046
10047
10048
10049
10050
10051MLXSW_ITEM32(reg, mpat, system_port, 0x00, 0, 16);
10052
10053
10054
10055
10056
10057MLXSW_ITEM32(reg, mpat, e, 0x04, 31, 1);
10058
10059
10060
10061
10062
10063
10064
10065
10066
10067
10068MLXSW_ITEM32(reg, mpat, qos, 0x04, 26, 1);
10069
10070
10071
10072
10073
10074
10075
10076
10077
10078MLXSW_ITEM32(reg, mpat, be, 0x04, 25, 1);
10079
10080enum mlxsw_reg_mpat_span_type {
10081
10082
10083
10084 MLXSW_REG_MPAT_SPAN_TYPE_LOCAL_ETH = 0x0,
10085
10086
10087
10088
10089
10090 MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH = 0x1,
10091
10092
10093
10094
10095 MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH_L3 = 0x3,
10096};
10097
10098
10099
10100
10101
10102MLXSW_ITEM32(reg, mpat, span_type, 0x04, 0, 4);
10103
10104
10105
10106
10107
10108MLXSW_ITEM32(reg, mpat, pide, 0x0C, 15, 1);
10109
10110
10111
10112
10113
10114MLXSW_ITEM32(reg, mpat, pid, 0x0C, 0, 14);
10115
10116
10117
10118
10119
10120
10121
10122
10123
10124MLXSW_ITEM32(reg, mpat, eth_rspan_vid, 0x18, 0, 12);
10125
10126
10127
10128
10129
10130enum mlxsw_reg_mpat_eth_rspan_version {
10131 MLXSW_REG_MPAT_ETH_RSPAN_VERSION_NO_HEADER = 15,
10132};
10133
10134
10135
10136
10137
10138MLXSW_ITEM32(reg, mpat, eth_rspan_version, 0x10, 18, 4);
10139
10140
10141
10142
10143
10144MLXSW_ITEM_BUF(reg, mpat, eth_rspan_mac, 0x12, 6);
10145
10146
10147
10148
10149
10150MLXSW_ITEM32(reg, mpat, eth_rspan_tp, 0x18, 16, 1);
10151
10152
10153
10154
10155
10156enum mlxsw_reg_mpat_eth_rspan_protocol {
10157 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4,
10158 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6,
10159};
10160
10161
10162
10163
10164
10165MLXSW_ITEM32(reg, mpat, eth_rspan_protocol, 0x18, 24, 4);
10166
10167
10168
10169
10170
10171MLXSW_ITEM32(reg, mpat, eth_rspan_ttl, 0x1C, 4, 8);
10172
10173
10174
10175
10176
10177MLXSW_ITEM_BUF(reg, mpat, eth_rspan_smac, 0x22, 6);
10178
10179
10180
10181
10182
10183MLXSW_ITEM32(reg, mpat, eth_rspan_dip4, 0x4C, 0, 32);
10184MLXSW_ITEM_BUF(reg, mpat, eth_rspan_dip6, 0x40, 16);
10185
10186
10187
10188
10189
10190MLXSW_ITEM32(reg, mpat, eth_rspan_sip4, 0x5C, 0, 32);
10191MLXSW_ITEM_BUF(reg, mpat, eth_rspan_sip6, 0x50, 16);
10192
10193static inline void mlxsw_reg_mpat_pack(char *payload, u8 pa_id,
10194 u16 system_port, bool e,
10195 enum mlxsw_reg_mpat_span_type span_type)
10196{
10197 MLXSW_REG_ZERO(mpat, payload);
10198 mlxsw_reg_mpat_pa_id_set(payload, pa_id);
10199 mlxsw_reg_mpat_system_port_set(payload, system_port);
10200 mlxsw_reg_mpat_e_set(payload, e);
10201 mlxsw_reg_mpat_qos_set(payload, 1);
10202 mlxsw_reg_mpat_be_set(payload, 1);
10203 mlxsw_reg_mpat_span_type_set(payload, span_type);
10204}
10205
10206static inline void mlxsw_reg_mpat_eth_rspan_pack(char *payload, u16 vid)
10207{
10208 mlxsw_reg_mpat_eth_rspan_vid_set(payload, vid);
10209}
10210
10211static inline void
10212mlxsw_reg_mpat_eth_rspan_l2_pack(char *payload,
10213 enum mlxsw_reg_mpat_eth_rspan_version version,
10214 const char *mac,
10215 bool tp)
10216{
10217 mlxsw_reg_mpat_eth_rspan_version_set(payload, version);
10218 mlxsw_reg_mpat_eth_rspan_mac_memcpy_to(payload, mac);
10219 mlxsw_reg_mpat_eth_rspan_tp_set(payload, tp);
10220}
10221
10222static inline void
10223mlxsw_reg_mpat_eth_rspan_l3_ipv4_pack(char *payload, u8 ttl,
10224 const char *smac,
10225 u32 sip, u32 dip)
10226{
10227 mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl);
10228 mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac);
10229 mlxsw_reg_mpat_eth_rspan_protocol_set(payload,
10230 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4);
10231 mlxsw_reg_mpat_eth_rspan_sip4_set(payload, sip);
10232 mlxsw_reg_mpat_eth_rspan_dip4_set(payload, dip);
10233}
10234
10235static inline void
10236mlxsw_reg_mpat_eth_rspan_l3_ipv6_pack(char *payload, u8 ttl,
10237 const char *smac,
10238 struct in6_addr sip, struct in6_addr dip)
10239{
10240 mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl);
10241 mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac);
10242 mlxsw_reg_mpat_eth_rspan_protocol_set(payload,
10243 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6);
10244 mlxsw_reg_mpat_eth_rspan_sip6_memcpy_to(payload, (void *)&sip);
10245 mlxsw_reg_mpat_eth_rspan_dip6_memcpy_to(payload, (void *)&dip);
10246}
10247
10248
10249
10250
10251
10252
10253#define MLXSW_REG_MPAR_ID 0x901B
10254#define MLXSW_REG_MPAR_LEN 0x0C
10255
10256MLXSW_REG_DEFINE(mpar, MLXSW_REG_MPAR_ID, MLXSW_REG_MPAR_LEN);
10257
10258
10259
10260
10261
10262MLXSW_ITEM32_LP(reg, mpar, 0x00, 16, 0x00, 4);
10263
10264enum mlxsw_reg_mpar_i_e {
10265 MLXSW_REG_MPAR_TYPE_EGRESS,
10266 MLXSW_REG_MPAR_TYPE_INGRESS,
10267};
10268
10269
10270
10271
10272
10273MLXSW_ITEM32(reg, mpar, i_e, 0x00, 0, 4);
10274
10275
10276
10277
10278
10279
10280MLXSW_ITEM32(reg, mpar, enable, 0x04, 31, 1);
10281
10282
10283
10284
10285
10286MLXSW_ITEM32(reg, mpar, pa_id, 0x04, 0, 4);
10287
10288#define MLXSW_REG_MPAR_RATE_MAX 3500000000UL
10289
10290
10291
10292
10293
10294
10295
10296
10297MLXSW_ITEM32(reg, mpar, probability_rate, 0x08, 0, 32);
10298
10299static inline void mlxsw_reg_mpar_pack(char *payload, u16 local_port,
10300 enum mlxsw_reg_mpar_i_e i_e,
10301 bool enable, u8 pa_id,
10302 u32 probability_rate)
10303{
10304 MLXSW_REG_ZERO(mpar, payload);
10305 mlxsw_reg_mpar_local_port_set(payload, local_port);
10306 mlxsw_reg_mpar_enable_set(payload, enable);
10307 mlxsw_reg_mpar_i_e_set(payload, i_e);
10308 mlxsw_reg_mpar_pa_id_set(payload, pa_id);
10309 mlxsw_reg_mpar_probability_rate_set(payload, probability_rate);
10310}
10311
10312
10313
10314
10315
10316
10317#define MLXSW_REG_MGIR_ID 0x9020
10318#define MLXSW_REG_MGIR_LEN 0x9C
10319
10320MLXSW_REG_DEFINE(mgir, MLXSW_REG_MGIR_ID, MLXSW_REG_MGIR_LEN);
10321
10322
10323
10324
10325MLXSW_ITEM32(reg, mgir, hw_info_device_hw_revision, 0x0, 16, 16);
10326
10327#define MLXSW_REG_MGIR_FW_INFO_PSID_SIZE 16
10328
10329
10330
10331
10332
10333MLXSW_ITEM_BUF(reg, mgir, fw_info_psid, 0x30, MLXSW_REG_MGIR_FW_INFO_PSID_SIZE);
10334
10335
10336
10337
10338MLXSW_ITEM32(reg, mgir, fw_info_extended_major, 0x44, 0, 32);
10339
10340
10341
10342
10343MLXSW_ITEM32(reg, mgir, fw_info_extended_minor, 0x48, 0, 32);
10344
10345
10346
10347
10348MLXSW_ITEM32(reg, mgir, fw_info_extended_sub_minor, 0x4C, 0, 32);
10349
10350static inline void mlxsw_reg_mgir_pack(char *payload)
10351{
10352 MLXSW_REG_ZERO(mgir, payload);
10353}
10354
10355static inline void
10356mlxsw_reg_mgir_unpack(char *payload, u32 *hw_rev, char *fw_info_psid,
10357 u32 *fw_major, u32 *fw_minor, u32 *fw_sub_minor)
10358{
10359 *hw_rev = mlxsw_reg_mgir_hw_info_device_hw_revision_get(payload);
10360 mlxsw_reg_mgir_fw_info_psid_memcpy_from(payload, fw_info_psid);
10361 *fw_major = mlxsw_reg_mgir_fw_info_extended_major_get(payload);
10362 *fw_minor = mlxsw_reg_mgir_fw_info_extended_minor_get(payload);
10363 *fw_sub_minor = mlxsw_reg_mgir_fw_info_extended_sub_minor_get(payload);
10364}
10365
10366
10367
10368
10369
10370
10371#define MLXSW_REG_MRSR_ID 0x9023
10372#define MLXSW_REG_MRSR_LEN 0x08
10373
10374MLXSW_REG_DEFINE(mrsr, MLXSW_REG_MRSR_ID, MLXSW_REG_MRSR_LEN);
10375
10376
10377
10378
10379
10380
10381
10382MLXSW_ITEM32(reg, mrsr, command, 0x00, 0, 4);
10383
10384static inline void mlxsw_reg_mrsr_pack(char *payload)
10385{
10386 MLXSW_REG_ZERO(mrsr, payload);
10387 mlxsw_reg_mrsr_command_set(payload, 1);
10388}
10389
10390
10391
10392
10393
10394#define MLXSW_REG_MLCR_ID 0x902B
10395#define MLXSW_REG_MLCR_LEN 0x0C
10396
10397MLXSW_REG_DEFINE(mlcr, MLXSW_REG_MLCR_ID, MLXSW_REG_MLCR_LEN);
10398
10399
10400
10401
10402
10403MLXSW_ITEM32_LP(reg, mlcr, 0x00, 16, 0x00, 24);
10404
10405#define MLXSW_REG_MLCR_DURATION_MAX 0xFFFF
10406
10407
10408
10409
10410
10411
10412
10413MLXSW_ITEM32(reg, mlcr, beacon_duration, 0x04, 0, 16);
10414
10415
10416
10417
10418
10419
10420MLXSW_ITEM32(reg, mlcr, beacon_remain, 0x08, 0, 16);
10421
10422static inline void mlxsw_reg_mlcr_pack(char *payload, u16 local_port,
10423 bool active)
10424{
10425 MLXSW_REG_ZERO(mlcr, payload);
10426 mlxsw_reg_mlcr_local_port_set(payload, local_port);
10427 mlxsw_reg_mlcr_beacon_duration_set(payload, active ?
10428 MLXSW_REG_MLCR_DURATION_MAX : 0);
10429}
10430
10431
10432
10433
10434
10435
10436#define MLXSW_REG_MCION_ID 0x9052
10437#define MLXSW_REG_MCION_LEN 0x18
10438
10439MLXSW_REG_DEFINE(mcion, MLXSW_REG_MCION_ID, MLXSW_REG_MCION_LEN);
10440
10441
10442
10443
10444
10445MLXSW_ITEM32(reg, mcion, module, 0x00, 16, 8);
10446
10447enum {
10448 MLXSW_REG_MCION_MODULE_STATUS_BITS_PRESENT_MASK = BIT(0),
10449 MLXSW_REG_MCION_MODULE_STATUS_BITS_LOW_POWER_MASK = BIT(8),
10450};
10451
10452
10453
10454
10455
10456MLXSW_ITEM32(reg, mcion, module_status_bits, 0x04, 0, 16);
10457
10458static inline void mlxsw_reg_mcion_pack(char *payload, u8 module)
10459{
10460 MLXSW_REG_ZERO(mcion, payload);
10461 mlxsw_reg_mcion_module_set(payload, module);
10462}
10463
10464
10465
10466
10467
10468
10469#define MLXSW_REG_MTPPS_ID 0x9053
10470#define MLXSW_REG_MTPPS_LEN 0x3C
10471
10472MLXSW_REG_DEFINE(mtpps, MLXSW_REG_MTPPS_ID, MLXSW_REG_MTPPS_LEN);
10473
10474
10475
10476
10477
10478
10479MLXSW_ITEM32(reg, mtpps, enable, 0x20, 31, 1);
10480
10481enum mlxsw_reg_mtpps_pin_mode {
10482 MLXSW_REG_MTPPS_PIN_MODE_VIRTUAL_PIN = 0x2,
10483};
10484
10485
10486
10487
10488
10489
10490MLXSW_ITEM32(reg, mtpps, pin_mode, 0x20, 8, 4);
10491
10492#define MLXSW_REG_MTPPS_PIN_SP_VIRTUAL_PIN 7
10493
10494
10495
10496
10497
10498MLXSW_ITEM32(reg, mtpps, pin, 0x20, 0, 8);
10499
10500
10501
10502
10503
10504
10505
10506
10507
10508MLXSW_ITEM64(reg, mtpps, time_stamp, 0x28, 0, 64);
10509
10510static inline void
10511mlxsw_reg_mtpps_vpin_pack(char *payload, u64 time_stamp)
10512{
10513 MLXSW_REG_ZERO(mtpps, payload);
10514 mlxsw_reg_mtpps_pin_set(payload, MLXSW_REG_MTPPS_PIN_SP_VIRTUAL_PIN);
10515 mlxsw_reg_mtpps_pin_mode_set(payload,
10516 MLXSW_REG_MTPPS_PIN_MODE_VIRTUAL_PIN);
10517 mlxsw_reg_mtpps_enable_set(payload, true);
10518 mlxsw_reg_mtpps_time_stamp_set(payload, time_stamp);
10519}
10520
10521
10522
10523
10524
10525#define MLXSW_REG_MTUTC_ID 0x9055
10526#define MLXSW_REG_MTUTC_LEN 0x1C
10527
10528MLXSW_REG_DEFINE(mtutc, MLXSW_REG_MTUTC_ID, MLXSW_REG_MTUTC_LEN);
10529
10530enum mlxsw_reg_mtutc_operation {
10531 MLXSW_REG_MTUTC_OPERATION_SET_TIME_AT_NEXT_SEC = 0,
10532 MLXSW_REG_MTUTC_OPERATION_ADJUST_FREQ = 3,
10533};
10534
10535
10536
10537
10538
10539MLXSW_ITEM32(reg, mtutc, operation, 0x00, 0, 4);
10540
10541
10542
10543
10544
10545
10546
10547MLXSW_ITEM32(reg, mtutc, freq_adjustment, 0x04, 0, 32);
10548
10549
10550
10551
10552
10553MLXSW_ITEM32(reg, mtutc, utc_sec, 0x10, 0, 32);
10554
10555static inline void
10556mlxsw_reg_mtutc_pack(char *payload, enum mlxsw_reg_mtutc_operation oper,
10557 u32 freq_adj, u32 utc_sec)
10558{
10559 MLXSW_REG_ZERO(mtutc, payload);
10560 mlxsw_reg_mtutc_operation_set(payload, oper);
10561 mlxsw_reg_mtutc_freq_adjustment_set(payload, freq_adj);
10562 mlxsw_reg_mtutc_utc_sec_set(payload, utc_sec);
10563}
10564
10565
10566
10567
10568
10569#define MLXSW_REG_MCQI_ID 0x9061
10570#define MLXSW_REG_MCQI_BASE_LEN 0x18
10571#define MLXSW_REG_MCQI_CAP_LEN 0x14
10572#define MLXSW_REG_MCQI_LEN (MLXSW_REG_MCQI_BASE_LEN + MLXSW_REG_MCQI_CAP_LEN)
10573
10574MLXSW_REG_DEFINE(mcqi, MLXSW_REG_MCQI_ID, MLXSW_REG_MCQI_LEN);
10575
10576
10577
10578
10579
10580MLXSW_ITEM32(reg, mcqi, component_index, 0x00, 0, 16);
10581
10582enum mlxfw_reg_mcqi_info_type {
10583 MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES,
10584};
10585
10586
10587
10588
10589
10590MLXSW_ITEM32(reg, mcqi, info_type, 0x08, 0, 5);
10591
10592
10593
10594
10595
10596
10597MLXSW_ITEM32(reg, mcqi, offset, 0x10, 0, 32);
10598
10599
10600
10601
10602
10603
10604MLXSW_ITEM32(reg, mcqi, data_size, 0x14, 0, 16);
10605
10606
10607
10608
10609
10610MLXSW_ITEM32(reg, mcqi, cap_max_component_size, 0x20, 0, 32);
10611
10612
10613
10614
10615
10616
10617MLXSW_ITEM32(reg, mcqi, cap_log_mcda_word_size, 0x24, 28, 4);
10618
10619
10620
10621
10622
10623MLXSW_ITEM32(reg, mcqi, cap_mcda_max_write_size, 0x24, 0, 16);
10624
10625static inline void mlxsw_reg_mcqi_pack(char *payload, u16 component_index)
10626{
10627 MLXSW_REG_ZERO(mcqi, payload);
10628 mlxsw_reg_mcqi_component_index_set(payload, component_index);
10629 mlxsw_reg_mcqi_info_type_set(payload,
10630 MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES);
10631 mlxsw_reg_mcqi_offset_set(payload, 0);
10632 mlxsw_reg_mcqi_data_size_set(payload, MLXSW_REG_MCQI_CAP_LEN);
10633}
10634
10635static inline void mlxsw_reg_mcqi_unpack(char *payload,
10636 u32 *p_cap_max_component_size,
10637 u8 *p_cap_log_mcda_word_size,
10638 u16 *p_cap_mcda_max_write_size)
10639{
10640 *p_cap_max_component_size =
10641 mlxsw_reg_mcqi_cap_max_component_size_get(payload);
10642 *p_cap_log_mcda_word_size =
10643 mlxsw_reg_mcqi_cap_log_mcda_word_size_get(payload);
10644 *p_cap_mcda_max_write_size =
10645 mlxsw_reg_mcqi_cap_mcda_max_write_size_get(payload);
10646}
10647
10648
10649
10650
10651
10652#define MLXSW_REG_MCC_ID 0x9062
10653#define MLXSW_REG_MCC_LEN 0x1C
10654
10655MLXSW_REG_DEFINE(mcc, MLXSW_REG_MCC_ID, MLXSW_REG_MCC_LEN);
10656
10657enum mlxsw_reg_mcc_instruction {
10658 MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE = 0x01,
10659 MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE = 0x02,
10660 MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT = 0x03,
10661 MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT = 0x04,
10662 MLXSW_REG_MCC_INSTRUCTION_ACTIVATE = 0x06,
10663 MLXSW_REG_MCC_INSTRUCTION_CANCEL = 0x08,
10664};
10665
10666
10667
10668
10669
10670
10671MLXSW_ITEM32(reg, mcc, instruction, 0x00, 0, 8);
10672
10673
10674
10675
10676
10677
10678MLXSW_ITEM32(reg, mcc, component_index, 0x04, 0, 16);
10679
10680
10681
10682
10683
10684MLXSW_ITEM32(reg, mcc, update_handle, 0x08, 0, 24);
10685
10686
10687
10688
10689
10690
10691MLXSW_ITEM32(reg, mcc, error_code, 0x0C, 8, 8);
10692
10693
10694
10695
10696
10697MLXSW_ITEM32(reg, mcc, control_state, 0x0C, 0, 4);
10698
10699
10700
10701
10702
10703
10704
10705MLXSW_ITEM32(reg, mcc, component_size, 0x10, 0, 32);
10706
10707static inline void mlxsw_reg_mcc_pack(char *payload,
10708 enum mlxsw_reg_mcc_instruction instr,
10709 u16 component_index, u32 update_handle,
10710 u32 component_size)
10711{
10712 MLXSW_REG_ZERO(mcc, payload);
10713 mlxsw_reg_mcc_instruction_set(payload, instr);
10714 mlxsw_reg_mcc_component_index_set(payload, component_index);
10715 mlxsw_reg_mcc_update_handle_set(payload, update_handle);
10716 mlxsw_reg_mcc_component_size_set(payload, component_size);
10717}
10718
10719static inline void mlxsw_reg_mcc_unpack(char *payload, u32 *p_update_handle,
10720 u8 *p_error_code, u8 *p_control_state)
10721{
10722 if (p_update_handle)
10723 *p_update_handle = mlxsw_reg_mcc_update_handle_get(payload);
10724 if (p_error_code)
10725 *p_error_code = mlxsw_reg_mcc_error_code_get(payload);
10726 if (p_control_state)
10727 *p_control_state = mlxsw_reg_mcc_control_state_get(payload);
10728}
10729
10730
10731
10732
10733
10734#define MLXSW_REG_MCDA_ID 0x9063
10735#define MLXSW_REG_MCDA_BASE_LEN 0x10
10736#define MLXSW_REG_MCDA_MAX_DATA_LEN 0x80
10737#define MLXSW_REG_MCDA_LEN \
10738 (MLXSW_REG_MCDA_BASE_LEN + MLXSW_REG_MCDA_MAX_DATA_LEN)
10739
10740MLXSW_REG_DEFINE(mcda, MLXSW_REG_MCDA_ID, MLXSW_REG_MCDA_LEN);
10741
10742
10743
10744
10745
10746MLXSW_ITEM32(reg, mcda, update_handle, 0x00, 0, 24);
10747
10748
10749
10750
10751
10752
10753MLXSW_ITEM32(reg, mcda, offset, 0x04, 0, 32);
10754
10755
10756
10757
10758
10759MLXSW_ITEM32(reg, mcda, size, 0x08, 0, 16);
10760
10761
10762
10763
10764
10765MLXSW_ITEM32_INDEXED(reg, mcda, data, 0x10, 0, 32, 4, 0, false);
10766
10767static inline void mlxsw_reg_mcda_pack(char *payload, u32 update_handle,
10768 u32 offset, u16 size, u8 *data)
10769{
10770 int i;
10771
10772 MLXSW_REG_ZERO(mcda, payload);
10773 mlxsw_reg_mcda_update_handle_set(payload, update_handle);
10774 mlxsw_reg_mcda_offset_set(payload, offset);
10775 mlxsw_reg_mcda_size_set(payload, size);
10776
10777 for (i = 0; i < size / 4; i++)
10778 mlxsw_reg_mcda_data_set(payload, i, *(u32 *) &data[i * 4]);
10779}
10780
10781
10782
10783
10784
10785#define MLXSW_REG_MPSC_ID 0x9080
10786#define MLXSW_REG_MPSC_LEN 0x1C
10787
10788MLXSW_REG_DEFINE(mpsc, MLXSW_REG_MPSC_ID, MLXSW_REG_MPSC_LEN);
10789
10790
10791
10792
10793
10794
10795MLXSW_ITEM32_LP(reg, mpsc, 0x00, 16, 0x00, 12);
10796
10797
10798
10799
10800
10801MLXSW_ITEM32(reg, mpsc, e, 0x04, 30, 1);
10802
10803#define MLXSW_REG_MPSC_RATE_MAX 3500000000UL
10804
10805
10806
10807
10808
10809
10810MLXSW_ITEM32(reg, mpsc, rate, 0x08, 0, 32);
10811
10812static inline void mlxsw_reg_mpsc_pack(char *payload, u16 local_port, bool e,
10813 u32 rate)
10814{
10815 MLXSW_REG_ZERO(mpsc, payload);
10816 mlxsw_reg_mpsc_local_port_set(payload, local_port);
10817 mlxsw_reg_mpsc_e_set(payload, e);
10818 mlxsw_reg_mpsc_rate_set(payload, rate);
10819}
10820
10821
10822
10823
10824#define MLXSW_REG_MGPC_ID 0x9081
10825#define MLXSW_REG_MGPC_LEN 0x18
10826
10827MLXSW_REG_DEFINE(mgpc, MLXSW_REG_MGPC_ID, MLXSW_REG_MGPC_LEN);
10828
10829
10830
10831
10832
10833MLXSW_ITEM32(reg, mgpc, counter_set_type, 0x00, 24, 8);
10834
10835
10836
10837
10838
10839MLXSW_ITEM32(reg, mgpc, counter_index, 0x00, 0, 24);
10840
10841enum mlxsw_reg_mgpc_opcode {
10842
10843 MLXSW_REG_MGPC_OPCODE_NOP = 0x00,
10844
10845 MLXSW_REG_MGPC_OPCODE_CLEAR = 0x08,
10846};
10847
10848
10849
10850
10851
10852MLXSW_ITEM32(reg, mgpc, opcode, 0x04, 28, 4);
10853
10854
10855
10856
10857
10858MLXSW_ITEM64(reg, mgpc, byte_counter, 0x08, 0, 64);
10859
10860
10861
10862
10863
10864MLXSW_ITEM64(reg, mgpc, packet_counter, 0x10, 0, 64);
10865
10866static inline void mlxsw_reg_mgpc_pack(char *payload, u32 counter_index,
10867 enum mlxsw_reg_mgpc_opcode opcode,
10868 enum mlxsw_reg_flow_counter_set_type set_type)
10869{
10870 MLXSW_REG_ZERO(mgpc, payload);
10871 mlxsw_reg_mgpc_counter_index_set(payload, counter_index);
10872 mlxsw_reg_mgpc_counter_set_type_set(payload, set_type);
10873 mlxsw_reg_mgpc_opcode_set(payload, opcode);
10874}
10875
10876
10877
10878
10879
10880
10881#define MLXSW_REG_MPRS_ID 0x9083
10882#define MLXSW_REG_MPRS_LEN 0x14
10883
10884MLXSW_REG_DEFINE(mprs, MLXSW_REG_MPRS_ID, MLXSW_REG_MPRS_LEN);
10885
10886
10887
10888
10889
10890
10891
10892MLXSW_ITEM32(reg, mprs, parsing_depth, 0x00, 0, 16);
10893
10894
10895
10896
10897
10898
10899
10900MLXSW_ITEM32(reg, mprs, parsing_en, 0x04, 0, 16);
10901
10902
10903
10904
10905
10906
10907
10908MLXSW_ITEM32(reg, mprs, vxlan_udp_dport, 0x10, 0, 16);
10909
10910static inline void mlxsw_reg_mprs_pack(char *payload, u16 parsing_depth,
10911 u16 vxlan_udp_dport)
10912{
10913 MLXSW_REG_ZERO(mprs, payload);
10914 mlxsw_reg_mprs_parsing_depth_set(payload, parsing_depth);
10915 mlxsw_reg_mprs_parsing_en_set(payload, true);
10916 mlxsw_reg_mprs_vxlan_udp_dport_set(payload, vxlan_udp_dport);
10917}
10918
10919
10920
10921
10922#define MLXSW_REG_MOGCR_ID 0x9086
10923#define MLXSW_REG_MOGCR_LEN 0x20
10924
10925MLXSW_REG_DEFINE(mogcr, MLXSW_REG_MOGCR_ID, MLXSW_REG_MOGCR_LEN);
10926
10927
10928
10929
10930
10931
10932
10933
10934MLXSW_ITEM32(reg, mogcr, ptp_iftc, 0x00, 1, 1);
10935
10936
10937
10938
10939
10940
10941
10942
10943MLXSW_ITEM32(reg, mogcr, ptp_eftc, 0x00, 0, 1);
10944
10945
10946
10947
10948
10949
10950
10951MLXSW_ITEM32(reg, mogcr, mirroring_pid_base, 0x0C, 0, 14);
10952
10953
10954
10955
10956
10957
10958#define MLXSW_REG_MPAGR_ID 0x9089
10959#define MLXSW_REG_MPAGR_LEN 0x0C
10960
10961MLXSW_REG_DEFINE(mpagr, MLXSW_REG_MPAGR_ID, MLXSW_REG_MPAGR_LEN);
10962
10963enum mlxsw_reg_mpagr_trigger {
10964 MLXSW_REG_MPAGR_TRIGGER_EGRESS,
10965 MLXSW_REG_MPAGR_TRIGGER_INGRESS,
10966 MLXSW_REG_MPAGR_TRIGGER_INGRESS_WRED,
10967 MLXSW_REG_MPAGR_TRIGGER_INGRESS_SHARED_BUFFER,
10968 MLXSW_REG_MPAGR_TRIGGER_INGRESS_ING_CONG,
10969 MLXSW_REG_MPAGR_TRIGGER_INGRESS_EGR_CONG,
10970 MLXSW_REG_MPAGR_TRIGGER_EGRESS_ECN,
10971 MLXSW_REG_MPAGR_TRIGGER_EGRESS_HIGH_LATENCY,
10972};
10973
10974
10975
10976
10977
10978MLXSW_ITEM32(reg, mpagr, trigger, 0x00, 0, 4);
10979
10980
10981
10982
10983
10984MLXSW_ITEM32(reg, mpagr, pa_id, 0x04, 0, 4);
10985
10986#define MLXSW_REG_MPAGR_RATE_MAX 3500000000UL
10987
10988
10989
10990
10991
10992
10993
10994MLXSW_ITEM32(reg, mpagr, probability_rate, 0x08, 0, 32);
10995
10996static inline void mlxsw_reg_mpagr_pack(char *payload,
10997 enum mlxsw_reg_mpagr_trigger trigger,
10998 u8 pa_id, u32 probability_rate)
10999{
11000 MLXSW_REG_ZERO(mpagr, payload);
11001 mlxsw_reg_mpagr_trigger_set(payload, trigger);
11002 mlxsw_reg_mpagr_pa_id_set(payload, pa_id);
11003 mlxsw_reg_mpagr_probability_rate_set(payload, probability_rate);
11004}
11005
11006
11007
11008
11009
11010
11011#define MLXSW_REG_MOMTE_ID 0x908D
11012#define MLXSW_REG_MOMTE_LEN 0x10
11013
11014MLXSW_REG_DEFINE(momte, MLXSW_REG_MOMTE_ID, MLXSW_REG_MOMTE_LEN);
11015
11016
11017
11018
11019
11020MLXSW_ITEM32_LP(reg, momte, 0x00, 16, 0x00, 12);
11021
11022enum mlxsw_reg_momte_type {
11023 MLXSW_REG_MOMTE_TYPE_WRED = 0x20,
11024 MLXSW_REG_MOMTE_TYPE_SHARED_BUFFER_TCLASS = 0x31,
11025 MLXSW_REG_MOMTE_TYPE_SHARED_BUFFER_TCLASS_DESCRIPTORS = 0x32,
11026 MLXSW_REG_MOMTE_TYPE_SHARED_BUFFER_EGRESS_PORT = 0x33,
11027 MLXSW_REG_MOMTE_TYPE_ING_CONG = 0x40,
11028 MLXSW_REG_MOMTE_TYPE_EGR_CONG = 0x50,
11029 MLXSW_REG_MOMTE_TYPE_ECN = 0x60,
11030 MLXSW_REG_MOMTE_TYPE_HIGH_LATENCY = 0x70,
11031};
11032
11033
11034
11035
11036
11037MLXSW_ITEM32(reg, momte, type, 0x04, 0, 8);
11038
11039
11040
11041
11042
11043
11044
11045MLXSW_ITEM_BIT_ARRAY(reg, momte, tclass_en, 0x08, 0x08, 1);
11046
11047static inline void mlxsw_reg_momte_pack(char *payload, u16 local_port,
11048 enum mlxsw_reg_momte_type type)
11049{
11050 MLXSW_REG_ZERO(momte, payload);
11051 mlxsw_reg_momte_local_port_set(payload, local_port);
11052 mlxsw_reg_momte_type_set(payload, type);
11053}
11054
11055
11056
11057
11058
11059
11060
11061
11062#define MLXSW_REG_MTPPPC_ID 0x9090
11063#define MLXSW_REG_MTPPPC_LEN 0x28
11064
11065MLXSW_REG_DEFINE(mtpppc, MLXSW_REG_MTPPPC_ID, MLXSW_REG_MTPPPC_LEN);
11066
11067
11068
11069
11070
11071
11072
11073
11074MLXSW_ITEM32(reg, mtpppc, ing_timestamp_message_type, 0x08, 0, 16);
11075
11076
11077
11078
11079
11080
11081
11082
11083MLXSW_ITEM32(reg, mtpppc, egr_timestamp_message_type, 0x0C, 0, 16);
11084
11085static inline void mlxsw_reg_mtpppc_pack(char *payload, u16 ing, u16 egr)
11086{
11087 MLXSW_REG_ZERO(mtpppc, payload);
11088 mlxsw_reg_mtpppc_ing_timestamp_message_type_set(payload, ing);
11089 mlxsw_reg_mtpppc_egr_timestamp_message_type_set(payload, egr);
11090}
11091
11092
11093
11094
11095
11096
11097
11098
11099
11100
11101
11102#define MLXSW_REG_MTPPTR_ID 0x9091
11103#define MLXSW_REG_MTPPTR_BASE_LEN 0x10
11104#define MLXSW_REG_MTPPTR_REC_LEN 0x10
11105#define MLXSW_REG_MTPPTR_REC_MAX_COUNT 4
11106#define MLXSW_REG_MTPPTR_LEN (MLXSW_REG_MTPPTR_BASE_LEN + \
11107 MLXSW_REG_MTPPTR_REC_LEN * MLXSW_REG_MTPPTR_REC_MAX_COUNT)
11108
11109MLXSW_REG_DEFINE(mtpptr, MLXSW_REG_MTPPTR_ID, MLXSW_REG_MTPPTR_LEN);
11110
11111
11112
11113
11114
11115MLXSW_ITEM32_LP(reg, mtpptr, 0x00, 16, 0x00, 12);
11116
11117enum mlxsw_reg_mtpptr_dir {
11118 MLXSW_REG_MTPPTR_DIR_INGRESS,
11119 MLXSW_REG_MTPPTR_DIR_EGRESS,
11120};
11121
11122
11123
11124
11125
11126MLXSW_ITEM32(reg, mtpptr, dir, 0x00, 0, 1);
11127
11128
11129
11130
11131
11132MLXSW_ITEM32(reg, mtpptr, clr, 0x04, 31, 1);
11133
11134
11135
11136
11137
11138
11139MLXSW_ITEM32(reg, mtpptr, num_rec, 0x08, 0, 4);
11140
11141
11142
11143
11144
11145
11146MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_message_type,
11147 MLXSW_REG_MTPPTR_BASE_LEN, 8, 4,
11148 MLXSW_REG_MTPPTR_REC_LEN, 0, false);
11149
11150
11151
11152
11153
11154MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_domain_number,
11155 MLXSW_REG_MTPPTR_BASE_LEN, 0, 8,
11156 MLXSW_REG_MTPPTR_REC_LEN, 0, false);
11157
11158
11159
11160
11161
11162MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_sequence_id,
11163 MLXSW_REG_MTPPTR_BASE_LEN, 0, 16,
11164 MLXSW_REG_MTPPTR_REC_LEN, 0x4, false);
11165
11166
11167
11168
11169
11170
11171
11172MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_timestamp_high,
11173 MLXSW_REG_MTPPTR_BASE_LEN, 0, 32,
11174 MLXSW_REG_MTPPTR_REC_LEN, 0x8, false);
11175
11176
11177
11178
11179
11180MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_timestamp_low,
11181 MLXSW_REG_MTPPTR_BASE_LEN, 0, 32,
11182 MLXSW_REG_MTPPTR_REC_LEN, 0xC, false);
11183
11184static inline void mlxsw_reg_mtpptr_unpack(const char *payload,
11185 unsigned int rec,
11186 u8 *p_message_type,
11187 u8 *p_domain_number,
11188 u16 *p_sequence_id,
11189 u64 *p_timestamp)
11190{
11191 u32 timestamp_high, timestamp_low;
11192
11193 *p_message_type = mlxsw_reg_mtpptr_rec_message_type_get(payload, rec);
11194 *p_domain_number = mlxsw_reg_mtpptr_rec_domain_number_get(payload, rec);
11195 *p_sequence_id = mlxsw_reg_mtpptr_rec_sequence_id_get(payload, rec);
11196 timestamp_high = mlxsw_reg_mtpptr_rec_timestamp_high_get(payload, rec);
11197 timestamp_low = mlxsw_reg_mtpptr_rec_timestamp_low_get(payload, rec);
11198 *p_timestamp = (u64)timestamp_high << 32 | timestamp_low;
11199}
11200
11201
11202
11203
11204
11205
11206#define MLXSW_REG_MTPTPT_ID 0x9092
11207#define MLXSW_REG_MTPTPT_LEN 0x08
11208
11209MLXSW_REG_DEFINE(mtptpt, MLXSW_REG_MTPTPT_ID, MLXSW_REG_MTPTPT_LEN);
11210
11211enum mlxsw_reg_mtptpt_trap_id {
11212 MLXSW_REG_MTPTPT_TRAP_ID_PTP0,
11213 MLXSW_REG_MTPTPT_TRAP_ID_PTP1,
11214};
11215
11216
11217
11218
11219
11220MLXSW_ITEM32(reg, mtptpt, trap_id, 0x00, 0, 4);
11221
11222
11223
11224
11225
11226
11227
11228MLXSW_ITEM32(reg, mtptpt, message_type, 0x04, 0, 16);
11229
11230static inline void mlxsw_reg_mtptptp_pack(char *payload,
11231 enum mlxsw_reg_mtptpt_trap_id trap_id,
11232 u16 message_type)
11233{
11234 MLXSW_REG_ZERO(mtptpt, payload);
11235 mlxsw_reg_mtptpt_trap_id_set(payload, trap_id);
11236 mlxsw_reg_mtptpt_message_type_set(payload, message_type);
11237}
11238
11239
11240
11241
11242#define MLXSW_REG_MFGD_ID 0x90F0
11243#define MLXSW_REG_MFGD_LEN 0x0C
11244
11245MLXSW_REG_DEFINE(mfgd, MLXSW_REG_MFGD_ID, MLXSW_REG_MFGD_LEN);
11246
11247
11248
11249
11250
11251
11252MLXSW_ITEM32(reg, mfgd, fatal_event_mode, 0x00, 9, 2);
11253
11254
11255
11256
11257MLXSW_ITEM32(reg, mfgd, trigger_test, 0x00, 11, 1);
11258
11259
11260
11261
11262
11263
11264#define MLXSW_REG_MGPIR_ID 0x9100
11265#define MLXSW_REG_MGPIR_LEN 0xA0
11266
11267MLXSW_REG_DEFINE(mgpir, MLXSW_REG_MGPIR_ID, MLXSW_REG_MGPIR_LEN);
11268
11269enum mlxsw_reg_mgpir_device_type {
11270 MLXSW_REG_MGPIR_DEVICE_TYPE_NONE,
11271 MLXSW_REG_MGPIR_DEVICE_TYPE_GEARBOX_DIE,
11272};
11273
11274
11275
11276
11277MLXSW_ITEM32(reg, mgpir, device_type, 0x00, 24, 4);
11278
11279
11280
11281
11282
11283MLXSW_ITEM32(reg, mgpir, devices_per_flash, 0x00, 16, 8);
11284
11285
11286
11287
11288
11289MLXSW_ITEM32(reg, mgpir, num_of_devices, 0x00, 0, 8);
11290
11291
11292
11293
11294
11295MLXSW_ITEM32(reg, mgpir, num_of_modules, 0x04, 0, 8);
11296
11297static inline void mlxsw_reg_mgpir_pack(char *payload)
11298{
11299 MLXSW_REG_ZERO(mgpir, payload);
11300}
11301
11302static inline void
11303mlxsw_reg_mgpir_unpack(char *payload, u8 *num_of_devices,
11304 enum mlxsw_reg_mgpir_device_type *device_type,
11305 u8 *devices_per_flash, u8 *num_of_modules)
11306{
11307 if (num_of_devices)
11308 *num_of_devices = mlxsw_reg_mgpir_num_of_devices_get(payload);
11309 if (device_type)
11310 *device_type = mlxsw_reg_mgpir_device_type_get(payload);
11311 if (devices_per_flash)
11312 *devices_per_flash =
11313 mlxsw_reg_mgpir_devices_per_flash_get(payload);
11314 if (num_of_modules)
11315 *num_of_modules = mlxsw_reg_mgpir_num_of_modules_get(payload);
11316}
11317
11318
11319
11320
11321#define MLXSW_REG_MFDE_ID 0x9200
11322#define MLXSW_REG_MFDE_LEN 0x30
11323
11324MLXSW_REG_DEFINE(mfde, MLXSW_REG_MFDE_ID, MLXSW_REG_MFDE_LEN);
11325
11326
11327
11328
11329
11330MLXSW_ITEM32(reg, mfde, irisc_id, 0x00, 24, 8);
11331
11332enum mlxsw_reg_mfde_severity {
11333
11334 MLXSW_REG_MFDE_SEVERITY_FATL = 2,
11335
11336 MLXSW_REG_MFDE_SEVERITY_NRML = 3,
11337
11338 MLXSW_REG_MFDE_SEVERITY_INTR = 5,
11339};
11340
11341
11342
11343
11344
11345MLXSW_ITEM32(reg, mfde, severity, 0x00, 16, 8);
11346
11347enum mlxsw_reg_mfde_event_id {
11348
11349 MLXSW_REG_MFDE_EVENT_ID_CRSPACE_TO = 1,
11350
11351 MLXSW_REG_MFDE_EVENT_ID_KVD_IM_STOP,
11352
11353 MLXSW_REG_MFDE_EVENT_ID_TEST,
11354
11355 MLXSW_REG_MFDE_EVENT_ID_FW_ASSERT,
11356
11357 MLXSW_REG_MFDE_EVENT_ID_FATAL_CAUSE,
11358};
11359
11360
11361
11362
11363MLXSW_ITEM32(reg, mfde, event_id, 0x00, 0, 16);
11364
11365enum mlxsw_reg_mfde_method {
11366 MLXSW_REG_MFDE_METHOD_QUERY,
11367 MLXSW_REG_MFDE_METHOD_WRITE,
11368};
11369
11370
11371
11372
11373MLXSW_ITEM32(reg, mfde, method, 0x04, 29, 1);
11374
11375
11376
11377
11378
11379MLXSW_ITEM32(reg, mfde, long_process, 0x04, 28, 1);
11380
11381enum mlxsw_reg_mfde_command_type {
11382 MLXSW_REG_MFDE_COMMAND_TYPE_MAD,
11383 MLXSW_REG_MFDE_COMMAND_TYPE_EMAD,
11384 MLXSW_REG_MFDE_COMMAND_TYPE_CMDIF,
11385};
11386
11387
11388
11389
11390MLXSW_ITEM32(reg, mfde, command_type, 0x04, 24, 2);
11391
11392
11393
11394
11395
11396MLXSW_ITEM32(reg, mfde, reg_attr_id, 0x04, 0, 16);
11397
11398
11399
11400
11401
11402MLXSW_ITEM32(reg, mfde, crspace_to_log_address, 0x10, 0, 32);
11403
11404
11405
11406
11407
11408
11409MLXSW_ITEM32(reg, mfde, crspace_to_oe, 0x14, 24, 1);
11410
11411
11412
11413
11414
11415MLXSW_ITEM32(reg, mfde, crspace_to_log_id, 0x14, 0, 4);
11416
11417
11418
11419
11420
11421MLXSW_ITEM64(reg, mfde, crspace_to_log_ip, 0x18, 0, 64);
11422
11423
11424
11425
11426
11427
11428MLXSW_ITEM32(reg, mfde, kvd_im_stop_oe, 0x10, 24, 1);
11429
11430
11431
11432
11433
11434MLXSW_ITEM32(reg, mfde, kvd_im_stop_pipes_mask, 0x10, 0, 16);
11435
11436
11437
11438
11439
11440MLXSW_ITEM32(reg, mfde, fw_assert_var0, 0x10, 0, 32);
11441MLXSW_ITEM32(reg, mfde, fw_assert_var1, 0x14, 0, 32);
11442MLXSW_ITEM32(reg, mfde, fw_assert_var2, 0x18, 0, 32);
11443MLXSW_ITEM32(reg, mfde, fw_assert_var3, 0x1C, 0, 32);
11444MLXSW_ITEM32(reg, mfde, fw_assert_var4, 0x20, 0, 32);
11445
11446
11447
11448
11449
11450MLXSW_ITEM32(reg, mfde, fw_assert_existptr, 0x24, 0, 32);
11451
11452
11453
11454
11455
11456MLXSW_ITEM32(reg, mfde, fw_assert_callra, 0x28, 0, 32);
11457
11458
11459
11460
11461
11462
11463MLXSW_ITEM32(reg, mfde, fw_assert_oe, 0x2C, 24, 1);
11464
11465
11466
11467
11468
11469
11470MLXSW_ITEM32(reg, mfde, fw_assert_tile_v, 0x2C, 23, 1);
11471
11472
11473
11474
11475
11476MLXSW_ITEM32(reg, mfde, fw_assert_tile_index, 0x2C, 16, 6);
11477
11478
11479
11480
11481
11482MLXSW_ITEM32(reg, mfde, fw_assert_ext_synd, 0x2C, 0, 16);
11483
11484
11485
11486
11487
11488MLXSW_ITEM32(reg, mfde, fatal_cause_id, 0x10, 0, 18);
11489
11490
11491
11492
11493
11494
11495MLXSW_ITEM32(reg, mfde, fatal_cause_tile_v, 0x14, 23, 1);
11496
11497
11498
11499
11500
11501MLXSW_ITEM32(reg, mfde, fatal_cause_tile_index, 0x14, 16, 6);
11502
11503
11504
11505
11506
11507#define MLXSW_REG_TNGCR_ID 0xA001
11508#define MLXSW_REG_TNGCR_LEN 0x44
11509
11510MLXSW_REG_DEFINE(tngcr, MLXSW_REG_TNGCR_ID, MLXSW_REG_TNGCR_LEN);
11511
11512enum mlxsw_reg_tngcr_type {
11513 MLXSW_REG_TNGCR_TYPE_VXLAN,
11514 MLXSW_REG_TNGCR_TYPE_VXLAN_GPE,
11515 MLXSW_REG_TNGCR_TYPE_GENEVE,
11516 MLXSW_REG_TNGCR_TYPE_NVGRE,
11517};
11518
11519
11520
11521
11522
11523
11524
11525MLXSW_ITEM32(reg, tngcr, type, 0x00, 0, 4);
11526
11527
11528
11529
11530
11531MLXSW_ITEM32(reg, tngcr, nve_valid, 0x04, 31, 1);
11532
11533
11534
11535
11536
11537MLXSW_ITEM32(reg, tngcr, nve_ttl_uc, 0x04, 0, 8);
11538
11539
11540
11541
11542
11543MLXSW_ITEM32(reg, tngcr, nve_ttl_mc, 0x08, 0, 8);
11544
11545enum {
11546
11547 MLXSW_REG_TNGCR_FL_NO_COPY,
11548
11549
11550
11551
11552 MLXSW_REG_TNGCR_FL_COPY,
11553};
11554
11555
11556
11557
11558
11559MLXSW_ITEM32(reg, tngcr, nve_flc, 0x0C, 25, 1);
11560
11561enum {
11562
11563
11564
11565 MLXSW_REG_TNGCR_FL_NO_HASH,
11566
11567
11568
11569 MLXSW_REG_TNGCR_FL_HASH,
11570};
11571
11572
11573
11574
11575
11576MLXSW_ITEM32(reg, tngcr, nve_flh, 0x0C, 24, 1);
11577
11578
11579
11580
11581
11582MLXSW_ITEM32(reg, tngcr, nve_fl_prefix, 0x0C, 8, 12);
11583
11584
11585
11586
11587
11588
11589MLXSW_ITEM32(reg, tngcr, nve_fl_suffix, 0x0C, 0, 8);
11590
11591enum {
11592
11593 MLXSW_REG_TNGCR_UDP_SPORT_NO_HASH,
11594
11595 MLXSW_REG_TNGCR_UDP_SPORT_HASH,
11596};
11597
11598
11599
11600
11601
11602
11603
11604
11605
11606MLXSW_ITEM32(reg, tngcr, nve_udp_sport_type, 0x10, 24, 1);
11607
11608
11609
11610
11611
11612
11613MLXSW_ITEM32(reg, tngcr, nve_udp_sport_prefix, 0x10, 8, 8);
11614
11615
11616
11617
11618
11619
11620
11621
11622
11623MLXSW_ITEM32(reg, tngcr, nve_group_size_mc, 0x18, 0, 8);
11624
11625
11626
11627
11628
11629
11630
11631
11632
11633MLXSW_ITEM32(reg, tngcr, nve_group_size_flood, 0x1C, 0, 8);
11634
11635
11636
11637
11638
11639
11640MLXSW_ITEM32(reg, tngcr, learn_enable, 0x20, 31, 1);
11641
11642
11643
11644
11645
11646
11647MLXSW_ITEM32(reg, tngcr, underlay_virtual_router, 0x20, 0, 16);
11648
11649
11650
11651
11652
11653
11654MLXSW_ITEM32(reg, tngcr, underlay_rif, 0x24, 0, 16);
11655
11656
11657
11658
11659
11660MLXSW_ITEM32(reg, tngcr, usipv4, 0x28, 0, 32);
11661
11662
11663
11664
11665
11666
11667MLXSW_ITEM_BUF(reg, tngcr, usipv6, 0x30, 16);
11668
11669static inline void mlxsw_reg_tngcr_pack(char *payload,
11670 enum mlxsw_reg_tngcr_type type,
11671 bool valid, u8 ttl)
11672{
11673 MLXSW_REG_ZERO(tngcr, payload);
11674 mlxsw_reg_tngcr_type_set(payload, type);
11675 mlxsw_reg_tngcr_nve_valid_set(payload, valid);
11676 mlxsw_reg_tngcr_nve_ttl_uc_set(payload, ttl);
11677 mlxsw_reg_tngcr_nve_ttl_mc_set(payload, ttl);
11678 mlxsw_reg_tngcr_nve_flc_set(payload, MLXSW_REG_TNGCR_FL_NO_COPY);
11679 mlxsw_reg_tngcr_nve_flh_set(payload, 0);
11680 mlxsw_reg_tngcr_nve_udp_sport_type_set(payload,
11681 MLXSW_REG_TNGCR_UDP_SPORT_HASH);
11682 mlxsw_reg_tngcr_nve_udp_sport_prefix_set(payload, 0);
11683 mlxsw_reg_tngcr_nve_group_size_mc_set(payload, 1);
11684 mlxsw_reg_tngcr_nve_group_size_flood_set(payload, 1);
11685}
11686
11687
11688
11689
11690
11691
11692#define MLXSW_REG_TNUMT_ID 0xA003
11693#define MLXSW_REG_TNUMT_LEN 0x20
11694
11695MLXSW_REG_DEFINE(tnumt, MLXSW_REG_TNUMT_ID, MLXSW_REG_TNUMT_LEN);
11696
11697enum mlxsw_reg_tnumt_record_type {
11698 MLXSW_REG_TNUMT_RECORD_TYPE_IPV4,
11699 MLXSW_REG_TNUMT_RECORD_TYPE_IPV6,
11700 MLXSW_REG_TNUMT_RECORD_TYPE_LABEL,
11701};
11702
11703
11704
11705
11706
11707MLXSW_ITEM32(reg, tnumt, record_type, 0x00, 28, 4);
11708
11709
11710
11711
11712
11713MLXSW_ITEM32(reg, tnumt, tunnel_port, 0x00, 24, 4);
11714
11715
11716
11717
11718
11719
11720MLXSW_ITEM32(reg, tnumt, underlay_mc_ptr, 0x00, 0, 24);
11721
11722
11723
11724
11725
11726MLXSW_ITEM32(reg, tnumt, vnext, 0x04, 31, 1);
11727
11728
11729
11730
11731
11732MLXSW_ITEM32(reg, tnumt, next_underlay_mc_ptr, 0x04, 0, 24);
11733
11734
11735
11736
11737
11738
11739MLXSW_ITEM32(reg, tnumt, record_size, 0x08, 0, 3);
11740
11741
11742
11743
11744
11745MLXSW_ITEM32_INDEXED(reg, tnumt, udip, 0x0C, 0, 32, 0x04, 0x00, false);
11746
11747
11748
11749
11750
11751
11752MLXSW_ITEM32_INDEXED(reg, tnumt, udip_ptr, 0x0C, 0, 24, 0x04, 0x00, false);
11753
11754static inline void mlxsw_reg_tnumt_pack(char *payload,
11755 enum mlxsw_reg_tnumt_record_type type,
11756 enum mlxsw_reg_tunnel_port tport,
11757 u32 underlay_mc_ptr, bool vnext,
11758 u32 next_underlay_mc_ptr,
11759 u8 record_size)
11760{
11761 MLXSW_REG_ZERO(tnumt, payload);
11762 mlxsw_reg_tnumt_record_type_set(payload, type);
11763 mlxsw_reg_tnumt_tunnel_port_set(payload, tport);
11764 mlxsw_reg_tnumt_underlay_mc_ptr_set(payload, underlay_mc_ptr);
11765 mlxsw_reg_tnumt_vnext_set(payload, vnext);
11766 mlxsw_reg_tnumt_next_underlay_mc_ptr_set(payload, next_underlay_mc_ptr);
11767 mlxsw_reg_tnumt_record_size_set(payload, record_size);
11768}
11769
11770
11771
11772
11773
11774
11775#define MLXSW_REG_TNQCR_ID 0xA010
11776#define MLXSW_REG_TNQCR_LEN 0x0C
11777
11778MLXSW_REG_DEFINE(tnqcr, MLXSW_REG_TNQCR_ID, MLXSW_REG_TNQCR_LEN);
11779
11780
11781
11782
11783
11784
11785
11786
11787MLXSW_ITEM32(reg, tnqcr, enc_set_dscp, 0x04, 28, 1);
11788
11789static inline void mlxsw_reg_tnqcr_pack(char *payload)
11790{
11791 MLXSW_REG_ZERO(tnqcr, payload);
11792 mlxsw_reg_tnqcr_enc_set_dscp_set(payload, 0);
11793}
11794
11795
11796
11797
11798
11799
11800#define MLXSW_REG_TNQDR_ID 0xA011
11801#define MLXSW_REG_TNQDR_LEN 0x08
11802
11803MLXSW_REG_DEFINE(tnqdr, MLXSW_REG_TNQDR_ID, MLXSW_REG_TNQDR_LEN);
11804
11805
11806
11807
11808
11809MLXSW_ITEM32_LP(reg, tnqdr, 0x00, 16, 0x00, 12);
11810
11811
11812
11813
11814
11815MLXSW_ITEM32(reg, tnqdr, dscp, 0x04, 0, 6);
11816
11817static inline void mlxsw_reg_tnqdr_pack(char *payload, u16 local_port)
11818{
11819 MLXSW_REG_ZERO(tnqdr, payload);
11820 mlxsw_reg_tnqdr_local_port_set(payload, local_port);
11821 mlxsw_reg_tnqdr_dscp_set(payload, 0);
11822}
11823
11824
11825
11826
11827
11828
11829#define MLXSW_REG_TNEEM_ID 0xA012
11830#define MLXSW_REG_TNEEM_LEN 0x0C
11831
11832MLXSW_REG_DEFINE(tneem, MLXSW_REG_TNEEM_ID, MLXSW_REG_TNEEM_LEN);
11833
11834
11835
11836
11837
11838MLXSW_ITEM32(reg, tneem, overlay_ecn, 0x04, 24, 2);
11839
11840
11841
11842
11843
11844MLXSW_ITEM32(reg, tneem, underlay_ecn, 0x04, 16, 2);
11845
11846static inline void mlxsw_reg_tneem_pack(char *payload, u8 overlay_ecn,
11847 u8 underlay_ecn)
11848{
11849 MLXSW_REG_ZERO(tneem, payload);
11850 mlxsw_reg_tneem_overlay_ecn_set(payload, overlay_ecn);
11851 mlxsw_reg_tneem_underlay_ecn_set(payload, underlay_ecn);
11852}
11853
11854
11855
11856
11857
11858
11859#define MLXSW_REG_TNDEM_ID 0xA013
11860#define MLXSW_REG_TNDEM_LEN 0x0C
11861
11862MLXSW_REG_DEFINE(tndem, MLXSW_REG_TNDEM_ID, MLXSW_REG_TNDEM_LEN);
11863
11864
11865
11866
11867
11868MLXSW_ITEM32(reg, tndem, underlay_ecn, 0x04, 24, 2);
11869
11870
11871
11872
11873
11874MLXSW_ITEM32(reg, tndem, overlay_ecn, 0x04, 16, 2);
11875
11876
11877
11878
11879
11880
11881MLXSW_ITEM32(reg, tndem, eip_ecn, 0x04, 8, 2);
11882
11883
11884
11885
11886
11887
11888
11889MLXSW_ITEM32(reg, tndem, trap_en, 0x08, 28, 4);
11890
11891
11892
11893
11894
11895
11896MLXSW_ITEM32(reg, tndem, trap_id, 0x08, 0, 9);
11897
11898static inline void mlxsw_reg_tndem_pack(char *payload, u8 underlay_ecn,
11899 u8 overlay_ecn, u8 ecn, bool trap_en,
11900 u16 trap_id)
11901{
11902 MLXSW_REG_ZERO(tndem, payload);
11903 mlxsw_reg_tndem_underlay_ecn_set(payload, underlay_ecn);
11904 mlxsw_reg_tndem_overlay_ecn_set(payload, overlay_ecn);
11905 mlxsw_reg_tndem_eip_ecn_set(payload, ecn);
11906 mlxsw_reg_tndem_trap_en_set(payload, trap_en);
11907 mlxsw_reg_tndem_trap_id_set(payload, trap_id);
11908}
11909
11910
11911
11912
11913
11914
11915#define MLXSW_REG_TNPC_ID 0xA020
11916#define MLXSW_REG_TNPC_LEN 0x18
11917
11918MLXSW_REG_DEFINE(tnpc, MLXSW_REG_TNPC_ID, MLXSW_REG_TNPC_LEN);
11919
11920
11921
11922
11923
11924MLXSW_ITEM32(reg, tnpc, tunnel_port, 0x00, 0, 4);
11925
11926
11927
11928
11929
11930MLXSW_ITEM32(reg, tnpc, learn_enable_v6, 0x04, 1, 1);
11931
11932
11933
11934
11935
11936MLXSW_ITEM32(reg, tnpc, learn_enable_v4, 0x04, 0, 1);
11937
11938static inline void mlxsw_reg_tnpc_pack(char *payload,
11939 enum mlxsw_reg_tunnel_port tport,
11940 bool learn_enable)
11941{
11942 MLXSW_REG_ZERO(tnpc, payload);
11943 mlxsw_reg_tnpc_tunnel_port_set(payload, tport);
11944 mlxsw_reg_tnpc_learn_enable_v4_set(payload, learn_enable);
11945 mlxsw_reg_tnpc_learn_enable_v6_set(payload, learn_enable);
11946}
11947
11948
11949
11950
11951
11952#define MLXSW_REG_TIGCR_ID 0xA801
11953#define MLXSW_REG_TIGCR_LEN 0x10
11954
11955MLXSW_REG_DEFINE(tigcr, MLXSW_REG_TIGCR_ID, MLXSW_REG_TIGCR_LEN);
11956
11957
11958
11959
11960
11961
11962MLXSW_ITEM32(reg, tigcr, ttlc, 0x04, 8, 1);
11963
11964
11965
11966
11967
11968
11969MLXSW_ITEM32(reg, tigcr, ttl_uc, 0x04, 0, 8);
11970
11971static inline void mlxsw_reg_tigcr_pack(char *payload, bool ttlc, u8 ttl_uc)
11972{
11973 MLXSW_REG_ZERO(tigcr, payload);
11974 mlxsw_reg_tigcr_ttlc_set(payload, ttlc);
11975 mlxsw_reg_tigcr_ttl_uc_set(payload, ttl_uc);
11976}
11977
11978
11979
11980
11981
11982
11983#define MLXSW_REG_TIEEM_ID 0xA812
11984#define MLXSW_REG_TIEEM_LEN 0x0C
11985
11986MLXSW_REG_DEFINE(tieem, MLXSW_REG_TIEEM_ID, MLXSW_REG_TIEEM_LEN);
11987
11988
11989
11990
11991
11992MLXSW_ITEM32(reg, tieem, overlay_ecn, 0x04, 24, 2);
11993
11994
11995
11996
11997
11998MLXSW_ITEM32(reg, tieem, underlay_ecn, 0x04, 16, 2);
11999
12000static inline void mlxsw_reg_tieem_pack(char *payload, u8 overlay_ecn,
12001 u8 underlay_ecn)
12002{
12003 MLXSW_REG_ZERO(tieem, payload);
12004 mlxsw_reg_tieem_overlay_ecn_set(payload, overlay_ecn);
12005 mlxsw_reg_tieem_underlay_ecn_set(payload, underlay_ecn);
12006}
12007
12008
12009
12010
12011
12012
12013#define MLXSW_REG_TIDEM_ID 0xA813
12014#define MLXSW_REG_TIDEM_LEN 0x0C
12015
12016MLXSW_REG_DEFINE(tidem, MLXSW_REG_TIDEM_ID, MLXSW_REG_TIDEM_LEN);
12017
12018
12019
12020
12021
12022MLXSW_ITEM32(reg, tidem, underlay_ecn, 0x04, 24, 2);
12023
12024
12025
12026
12027
12028MLXSW_ITEM32(reg, tidem, overlay_ecn, 0x04, 16, 2);
12029
12030
12031
12032
12033
12034
12035MLXSW_ITEM32(reg, tidem, eip_ecn, 0x04, 8, 2);
12036
12037
12038
12039
12040
12041
12042
12043MLXSW_ITEM32(reg, tidem, trap_en, 0x08, 28, 4);
12044
12045
12046
12047
12048
12049
12050MLXSW_ITEM32(reg, tidem, trap_id, 0x08, 0, 9);
12051
12052static inline void mlxsw_reg_tidem_pack(char *payload, u8 underlay_ecn,
12053 u8 overlay_ecn, u8 eip_ecn,
12054 bool trap_en, u16 trap_id)
12055{
12056 MLXSW_REG_ZERO(tidem, payload);
12057 mlxsw_reg_tidem_underlay_ecn_set(payload, underlay_ecn);
12058 mlxsw_reg_tidem_overlay_ecn_set(payload, overlay_ecn);
12059 mlxsw_reg_tidem_eip_ecn_set(payload, eip_ecn);
12060 mlxsw_reg_tidem_trap_en_set(payload, trap_en);
12061 mlxsw_reg_tidem_trap_id_set(payload, trap_id);
12062}
12063
12064
12065
12066
12067
12068#define MLXSW_REG_SBPR_ID 0xB001
12069#define MLXSW_REG_SBPR_LEN 0x14
12070
12071MLXSW_REG_DEFINE(sbpr, MLXSW_REG_SBPR_ID, MLXSW_REG_SBPR_LEN);
12072
12073
12074enum mlxsw_reg_sbxx_dir {
12075 MLXSW_REG_SBXX_DIR_INGRESS,
12076 MLXSW_REG_SBXX_DIR_EGRESS,
12077};
12078
12079
12080
12081
12082
12083MLXSW_ITEM32(reg, sbpr, dir, 0x00, 24, 2);
12084
12085
12086
12087
12088
12089MLXSW_ITEM32(reg, sbpr, pool, 0x00, 0, 4);
12090
12091
12092
12093
12094
12095MLXSW_ITEM32(reg, sbpr, infi_size, 0x04, 31, 1);
12096
12097
12098
12099
12100
12101
12102MLXSW_ITEM32(reg, sbpr, size, 0x04, 0, 24);
12103
12104enum mlxsw_reg_sbpr_mode {
12105 MLXSW_REG_SBPR_MODE_STATIC,
12106 MLXSW_REG_SBPR_MODE_DYNAMIC,
12107};
12108
12109
12110
12111
12112
12113MLXSW_ITEM32(reg, sbpr, mode, 0x08, 0, 4);
12114
12115static inline void mlxsw_reg_sbpr_pack(char *payload, u8 pool,
12116 enum mlxsw_reg_sbxx_dir dir,
12117 enum mlxsw_reg_sbpr_mode mode, u32 size,
12118 bool infi_size)
12119{
12120 MLXSW_REG_ZERO(sbpr, payload);
12121 mlxsw_reg_sbpr_pool_set(payload, pool);
12122 mlxsw_reg_sbpr_dir_set(payload, dir);
12123 mlxsw_reg_sbpr_mode_set(payload, mode);
12124 mlxsw_reg_sbpr_size_set(payload, size);
12125 mlxsw_reg_sbpr_infi_size_set(payload, infi_size);
12126}
12127
12128
12129
12130
12131
12132
12133
12134#define MLXSW_REG_SBCM_ID 0xB002
12135#define MLXSW_REG_SBCM_LEN 0x28
12136
12137MLXSW_REG_DEFINE(sbcm, MLXSW_REG_SBCM_ID, MLXSW_REG_SBCM_LEN);
12138
12139
12140
12141
12142
12143
12144
12145MLXSW_ITEM32_LP(reg, sbcm, 0x00, 16, 0x00, 4);
12146
12147
12148
12149
12150
12151
12152
12153
12154
12155MLXSW_ITEM32(reg, sbcm, pg_buff, 0x00, 8, 6);
12156
12157
12158
12159
12160
12161MLXSW_ITEM32(reg, sbcm, dir, 0x00, 0, 2);
12162
12163
12164
12165
12166
12167MLXSW_ITEM32(reg, sbcm, min_buff, 0x18, 0, 24);
12168
12169
12170#define MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN 1
12171#define MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX 14
12172
12173
12174
12175
12176
12177MLXSW_ITEM32(reg, sbcm, infi_max, 0x1C, 31, 1);
12178
12179
12180
12181
12182
12183
12184
12185
12186
12187
12188
12189
12190
12191MLXSW_ITEM32(reg, sbcm, max_buff, 0x1C, 0, 24);
12192
12193
12194
12195
12196
12197MLXSW_ITEM32(reg, sbcm, pool, 0x24, 0, 4);
12198
12199static inline void mlxsw_reg_sbcm_pack(char *payload, u16 local_port, u8 pg_buff,
12200 enum mlxsw_reg_sbxx_dir dir,
12201 u32 min_buff, u32 max_buff,
12202 bool infi_max, u8 pool)
12203{
12204 MLXSW_REG_ZERO(sbcm, payload);
12205 mlxsw_reg_sbcm_local_port_set(payload, local_port);
12206 mlxsw_reg_sbcm_pg_buff_set(payload, pg_buff);
12207 mlxsw_reg_sbcm_dir_set(payload, dir);
12208 mlxsw_reg_sbcm_min_buff_set(payload, min_buff);
12209 mlxsw_reg_sbcm_max_buff_set(payload, max_buff);
12210 mlxsw_reg_sbcm_infi_max_set(payload, infi_max);
12211 mlxsw_reg_sbcm_pool_set(payload, pool);
12212}
12213
12214
12215
12216
12217
12218
12219
12220#define MLXSW_REG_SBPM_ID 0xB003
12221#define MLXSW_REG_SBPM_LEN 0x28
12222
12223MLXSW_REG_DEFINE(sbpm, MLXSW_REG_SBPM_ID, MLXSW_REG_SBPM_LEN);
12224
12225
12226
12227
12228
12229
12230
12231MLXSW_ITEM32_LP(reg, sbpm, 0x00, 16, 0x00, 12);
12232
12233
12234
12235
12236
12237MLXSW_ITEM32(reg, sbpm, pool, 0x00, 8, 4);
12238
12239
12240
12241
12242
12243MLXSW_ITEM32(reg, sbpm, dir, 0x00, 0, 2);
12244
12245
12246
12247
12248
12249MLXSW_ITEM32(reg, sbpm, buff_occupancy, 0x10, 0, 24);
12250
12251
12252
12253
12254
12255
12256
12257MLXSW_ITEM32(reg, sbpm, clr, 0x14, 31, 1);
12258
12259
12260
12261
12262
12263
12264MLXSW_ITEM32(reg, sbpm, max_buff_occupancy, 0x14, 0, 24);
12265
12266
12267
12268
12269
12270MLXSW_ITEM32(reg, sbpm, min_buff, 0x18, 0, 24);
12271
12272
12273
12274
12275
12276
12277
12278
12279
12280
12281
12282
12283MLXSW_ITEM32(reg, sbpm, max_buff, 0x1C, 0, 24);
12284
12285static inline void mlxsw_reg_sbpm_pack(char *payload, u16 local_port, u8 pool,
12286 enum mlxsw_reg_sbxx_dir dir, bool clr,
12287 u32 min_buff, u32 max_buff)
12288{
12289 MLXSW_REG_ZERO(sbpm, payload);
12290 mlxsw_reg_sbpm_local_port_set(payload, local_port);
12291 mlxsw_reg_sbpm_pool_set(payload, pool);
12292 mlxsw_reg_sbpm_dir_set(payload, dir);
12293 mlxsw_reg_sbpm_clr_set(payload, clr);
12294 mlxsw_reg_sbpm_min_buff_set(payload, min_buff);
12295 mlxsw_reg_sbpm_max_buff_set(payload, max_buff);
12296}
12297
12298static inline void mlxsw_reg_sbpm_unpack(char *payload, u32 *p_buff_occupancy,
12299 u32 *p_max_buff_occupancy)
12300{
12301 *p_buff_occupancy = mlxsw_reg_sbpm_buff_occupancy_get(payload);
12302 *p_max_buff_occupancy = mlxsw_reg_sbpm_max_buff_occupancy_get(payload);
12303}
12304
12305
12306
12307
12308
12309
12310
12311#define MLXSW_REG_SBMM_ID 0xB004
12312#define MLXSW_REG_SBMM_LEN 0x28
12313
12314MLXSW_REG_DEFINE(sbmm, MLXSW_REG_SBMM_ID, MLXSW_REG_SBMM_LEN);
12315
12316
12317
12318
12319
12320MLXSW_ITEM32(reg, sbmm, prio, 0x00, 8, 4);
12321
12322
12323
12324
12325
12326MLXSW_ITEM32(reg, sbmm, min_buff, 0x18, 0, 24);
12327
12328
12329
12330
12331
12332
12333
12334
12335
12336
12337
12338
12339MLXSW_ITEM32(reg, sbmm, max_buff, 0x1C, 0, 24);
12340
12341
12342
12343
12344
12345MLXSW_ITEM32(reg, sbmm, pool, 0x24, 0, 4);
12346
12347static inline void mlxsw_reg_sbmm_pack(char *payload, u8 prio, u32 min_buff,
12348 u32 max_buff, u8 pool)
12349{
12350 MLXSW_REG_ZERO(sbmm, payload);
12351 mlxsw_reg_sbmm_prio_set(payload, prio);
12352 mlxsw_reg_sbmm_min_buff_set(payload, min_buff);
12353 mlxsw_reg_sbmm_max_buff_set(payload, max_buff);
12354 mlxsw_reg_sbmm_pool_set(payload, pool);
12355}
12356
12357
12358
12359
12360
12361
12362
12363
12364
12365#define MLXSW_REG_SBSR_ID 0xB005
12366#define MLXSW_REG_SBSR_BASE_LEN 0x5C
12367#define MLXSW_REG_SBSR_REC_LEN 0x8
12368#define MLXSW_REG_SBSR_REC_MAX_COUNT 120
12369#define MLXSW_REG_SBSR_LEN (MLXSW_REG_SBSR_BASE_LEN + \
12370 MLXSW_REG_SBSR_REC_LEN * \
12371 MLXSW_REG_SBSR_REC_MAX_COUNT)
12372
12373MLXSW_REG_DEFINE(sbsr, MLXSW_REG_SBSR_ID, MLXSW_REG_SBSR_LEN);
12374
12375
12376
12377
12378
12379
12380
12381MLXSW_ITEM32(reg, sbsr, clr, 0x00, 31, 1);
12382
12383#define MLXSW_REG_SBSR_NUM_PORTS_IN_PAGE 256
12384
12385
12386
12387
12388
12389
12390
12391MLXSW_ITEM32(reg, sbsr, port_page, 0x04, 0, 4);
12392
12393
12394
12395
12396
12397
12398
12399
12400MLXSW_ITEM_BIT_ARRAY(reg, sbsr, ingress_port_mask, 0x10, 0x20, 1);
12401
12402
12403
12404
12405
12406
12407
12408
12409
12410MLXSW_ITEM_BIT_ARRAY(reg, sbsr, pg_buff_mask, 0x30, 0x4, 1);
12411
12412
12413
12414
12415
12416
12417
12418
12419MLXSW_ITEM_BIT_ARRAY(reg, sbsr, egress_port_mask, 0x34, 0x20, 1);
12420
12421
12422
12423
12424
12425
12426
12427
12428
12429MLXSW_ITEM_BIT_ARRAY(reg, sbsr, tclass_mask, 0x54, 0x8, 1);
12430
12431static inline void mlxsw_reg_sbsr_pack(char *payload, bool clr)
12432{
12433 MLXSW_REG_ZERO(sbsr, payload);
12434 mlxsw_reg_sbsr_clr_set(payload, clr);
12435}
12436
12437
12438
12439
12440
12441MLXSW_ITEM32_INDEXED(reg, sbsr, rec_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN,
12442 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x00, false);
12443
12444
12445
12446
12447
12448
12449MLXSW_ITEM32_INDEXED(reg, sbsr, rec_max_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN,
12450 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x04, false);
12451
12452static inline void mlxsw_reg_sbsr_rec_unpack(char *payload, int rec_index,
12453 u32 *p_buff_occupancy,
12454 u32 *p_max_buff_occupancy)
12455{
12456 *p_buff_occupancy =
12457 mlxsw_reg_sbsr_rec_buff_occupancy_get(payload, rec_index);
12458 *p_max_buff_occupancy =
12459 mlxsw_reg_sbsr_rec_max_buff_occupancy_get(payload, rec_index);
12460}
12461
12462
12463
12464
12465
12466
12467
12468
12469
12470#define MLXSW_REG_SBIB_ID 0xB006
12471#define MLXSW_REG_SBIB_LEN 0x10
12472
12473MLXSW_REG_DEFINE(sbib, MLXSW_REG_SBIB_ID, MLXSW_REG_SBIB_LEN);
12474
12475
12476
12477
12478
12479
12480MLXSW_ITEM32_LP(reg, sbib, 0x00, 16, 0x00, 12);
12481
12482
12483
12484
12485
12486
12487
12488MLXSW_ITEM32(reg, sbib, buff_size, 0x08, 0, 24);
12489
12490static inline void mlxsw_reg_sbib_pack(char *payload, u16 local_port,
12491 u32 buff_size)
12492{
12493 MLXSW_REG_ZERO(sbib, payload);
12494 mlxsw_reg_sbib_local_port_set(payload, local_port);
12495 mlxsw_reg_sbib_buff_size_set(payload, buff_size);
12496}
12497
12498static const struct mlxsw_reg_info *mlxsw_reg_infos[] = {
12499 MLXSW_REG(sgcr),
12500 MLXSW_REG(spad),
12501 MLXSW_REG(sspr),
12502 MLXSW_REG(sfdat),
12503 MLXSW_REG(sfd),
12504 MLXSW_REG(sfn),
12505 MLXSW_REG(spms),
12506 MLXSW_REG(spvid),
12507 MLXSW_REG(spvm),
12508 MLXSW_REG(spaft),
12509 MLXSW_REG(sfgc),
12510 MLXSW_REG(sfdf),
12511 MLXSW_REG(sldr),
12512 MLXSW_REG(slcr),
12513 MLXSW_REG(slcor),
12514 MLXSW_REG(spmlr),
12515 MLXSW_REG(svfa),
12516 MLXSW_REG(spvtr),
12517 MLXSW_REG(svpe),
12518 MLXSW_REG(sfmr),
12519 MLXSW_REG(spvmlr),
12520 MLXSW_REG(spvc),
12521 MLXSW_REG(spevet),
12522 MLXSW_REG(sftr2),
12523 MLXSW_REG(smid2),
12524 MLXSW_REG(cwtp),
12525 MLXSW_REG(cwtpm),
12526 MLXSW_REG(pgcr),
12527 MLXSW_REG(ppbt),
12528 MLXSW_REG(pacl),
12529 MLXSW_REG(pagt),
12530 MLXSW_REG(ptar),
12531 MLXSW_REG(ppbs),
12532 MLXSW_REG(prcr),
12533 MLXSW_REG(pefa),
12534 MLXSW_REG(pemrbt),
12535 MLXSW_REG(ptce2),
12536 MLXSW_REG(perpt),
12537 MLXSW_REG(peabfe),
12538 MLXSW_REG(perar),
12539 MLXSW_REG(ptce3),
12540 MLXSW_REG(percr),
12541 MLXSW_REG(pererp),
12542 MLXSW_REG(iedr),
12543 MLXSW_REG(qpts),
12544 MLXSW_REG(qpcr),
12545 MLXSW_REG(qtct),
12546 MLXSW_REG(qeec),
12547 MLXSW_REG(qrwe),
12548 MLXSW_REG(qpdsm),
12549 MLXSW_REG(qpdp),
12550 MLXSW_REG(qpdpm),
12551 MLXSW_REG(qtctm),
12552 MLXSW_REG(qpsc),
12553 MLXSW_REG(pmlp),
12554 MLXSW_REG(pmtu),
12555 MLXSW_REG(ptys),
12556 MLXSW_REG(ppad),
12557 MLXSW_REG(paos),
12558 MLXSW_REG(pfcc),
12559 MLXSW_REG(ppcnt),
12560 MLXSW_REG(plib),
12561 MLXSW_REG(pptb),
12562 MLXSW_REG(pbmc),
12563 MLXSW_REG(pspa),
12564 MLXSW_REG(pmaos),
12565 MLXSW_REG(pplr),
12566 MLXSW_REG(pmtdb),
12567 MLXSW_REG(pmpe),
12568 MLXSW_REG(pddr),
12569 MLXSW_REG(pmmp),
12570 MLXSW_REG(pllp),
12571 MLXSW_REG(htgt),
12572 MLXSW_REG(hpkt),
12573 MLXSW_REG(rgcr),
12574 MLXSW_REG(ritr),
12575 MLXSW_REG(rtar),
12576 MLXSW_REG(ratr),
12577 MLXSW_REG(rtdp),
12578 MLXSW_REG(rips),
12579 MLXSW_REG(ratrad),
12580 MLXSW_REG(rdpm),
12581 MLXSW_REG(ricnt),
12582 MLXSW_REG(rrcr),
12583 MLXSW_REG(ralta),
12584 MLXSW_REG(ralst),
12585 MLXSW_REG(raltb),
12586 MLXSW_REG(ralue),
12587 MLXSW_REG(rauht),
12588 MLXSW_REG(raleu),
12589 MLXSW_REG(rauhtd),
12590 MLXSW_REG(rigr2),
12591 MLXSW_REG(recr2),
12592 MLXSW_REG(rmft2),
12593 MLXSW_REG(rxlte),
12594 MLXSW_REG(rxltm),
12595 MLXSW_REG(rlcmld),
12596 MLXSW_REG(rlpmce),
12597 MLXSW_REG(xltq),
12598 MLXSW_REG(xmdr),
12599 MLXSW_REG(xrmt),
12600 MLXSW_REG(xralta),
12601 MLXSW_REG(xralst),
12602 MLXSW_REG(xraltb),
12603 MLXSW_REG(mfcr),
12604 MLXSW_REG(mfsc),
12605 MLXSW_REG(mfsm),
12606 MLXSW_REG(mfsl),
12607 MLXSW_REG(fore),
12608 MLXSW_REG(mtcap),
12609 MLXSW_REG(mtmp),
12610 MLXSW_REG(mtwe),
12611 MLXSW_REG(mtbr),
12612 MLXSW_REG(mcia),
12613 MLXSW_REG(mpat),
12614 MLXSW_REG(mpar),
12615 MLXSW_REG(mgir),
12616 MLXSW_REG(mrsr),
12617 MLXSW_REG(mlcr),
12618 MLXSW_REG(mcion),
12619 MLXSW_REG(mtpps),
12620 MLXSW_REG(mtutc),
12621 MLXSW_REG(mpsc),
12622 MLXSW_REG(mcqi),
12623 MLXSW_REG(mcc),
12624 MLXSW_REG(mcda),
12625 MLXSW_REG(mgpc),
12626 MLXSW_REG(mprs),
12627 MLXSW_REG(mogcr),
12628 MLXSW_REG(mpagr),
12629 MLXSW_REG(momte),
12630 MLXSW_REG(mtpppc),
12631 MLXSW_REG(mtpptr),
12632 MLXSW_REG(mtptpt),
12633 MLXSW_REG(mfgd),
12634 MLXSW_REG(mgpir),
12635 MLXSW_REG(mfde),
12636 MLXSW_REG(tngcr),
12637 MLXSW_REG(tnumt),
12638 MLXSW_REG(tnqcr),
12639 MLXSW_REG(tnqdr),
12640 MLXSW_REG(tneem),
12641 MLXSW_REG(tndem),
12642 MLXSW_REG(tnpc),
12643 MLXSW_REG(tigcr),
12644 MLXSW_REG(tieem),
12645 MLXSW_REG(tidem),
12646 MLXSW_REG(sbpr),
12647 MLXSW_REG(sbcm),
12648 MLXSW_REG(sbpm),
12649 MLXSW_REG(sbmm),
12650 MLXSW_REG(sbsr),
12651 MLXSW_REG(sbib),
12652};
12653
12654static inline const char *mlxsw_reg_id_str(u16 reg_id)
12655{
12656 const struct mlxsw_reg_info *reg_info;
12657 int i;
12658
12659 for (i = 0; i < ARRAY_SIZE(mlxsw_reg_infos); i++) {
12660 reg_info = mlxsw_reg_infos[i];
12661 if (reg_info->id == reg_id)
12662 return reg_info->name;
12663 }
12664 return "*UNKNOWN*";
12665}
12666
12667
12668
12669
12670
12671#define MLXSW_REG_PUDE_LEN 0x10
12672
12673
12674
12675
12676
12677MLXSW_ITEM32(reg, pude, swid, 0x00, 24, 8);
12678
12679
12680
12681
12682
12683MLXSW_ITEM32_LP(reg, pude, 0x00, 16, 0x00, 12);
12684
12685
12686
12687
12688
12689
12690
12691
12692
12693
12694MLXSW_ITEM32(reg, pude, admin_status, 0x00, 8, 4);
12695
12696
12697
12698
12699
12700
12701
12702
12703
12704MLXSW_ITEM32(reg, pude, oper_status, 0x00, 0, 4);
12705
12706#endif
12707