// SPDX-License-Identifier: GPL-2.0-only
/*******************************************************************************
  This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
  ST Ethernet IPs are built around a Synopsys IP Core.

        Copyright(C) 2007-2011 STMicroelectronics Ltd


  Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>

  Documentation available at:
        http://www.stlinux.com
  Support available at:
        https://bugzilla.stlinux.com/
*******************************************************************************/

#include <linux/clk.h>
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/ip.h>
#include <linux/tcp.h>
#include <linux/skbuff.h>
#include <linux/ethtool.h>
#include <linux/if_ether.h>
#include <linux/crc32.h>
#include <linux/mii.h>
#include <linux/if.h>
#include <linux/if_vlan.h>
#include <linux/dma-mapping.h>
#include <linux/slab.h>
#include <linux/pm_runtime.h>
#include <linux/prefetch.h>
#include <linux/pinctrl/consumer.h>
#ifdef CONFIG_DEBUG_FS
#include <linux/debugfs.h>
#include <linux/seq_file.h>
#endif /* CONFIG_DEBUG_FS */
#include <linux/net_tstamp.h>
#include <linux/phylink.h>
#include <linux/udp.h>
#include <linux/bpf_trace.h>
#include <net/pkt_cls.h>
#include <net/xdp_sock_drv.h>
#include "stmmac_ptp.h"
#include "stmmac.h"
#include "stmmac_xdp.h"
#include <linux/reset.h>
#include <linux/of_mdio.h>
#include "dwmac1000.h"
#include "dwxgmac2.h"
#include "hwif.h"

/* As long as the interface is active, we keep the timestamping counter enabled
 * with fine resolution and binary rollover. This avoid non-monotonic behavior
 * (clock jumps) when changing timestamping settings at runtime.
 */
#define STMMAC_HWTS_ACTIVE      (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | \
                                 PTP_TCR_TSCTRLSSR)

#define STMMAC_ALIGN(x)         ALIGN(ALIGN(x, SMP_CACHE_BYTES), 16)
#define TSO_MAX_BUFF_SIZE       (SZ_16K - 1)

/* Module parameters */
#define TX_TIMEO        5000
static int watchdog = TX_TIMEO;
module_param(watchdog, int, 0644);
MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)");

static int debug = -1;
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");

static int phyaddr = -1;
module_param(phyaddr, int, 0444);
MODULE_PARM_DESC(phyaddr, "Physical device address");

#define STMMAC_TX_THRESH(x)     ((x)->dma_tx_size / 4)
#define STMMAC_RX_THRESH(x)     ((x)->dma_rx_size / 4)

/* Limit to make sure XDP TX and slow path can coexist */
#define STMMAC_XSK_TX_BUDGET_MAX        256
#define STMMAC_TX_XSK_AVAIL             16
#define STMMAC_RX_FILL_BATCH            16

#define STMMAC_XDP_PASS         0
#define STMMAC_XDP_CONSUMED     BIT(0)
#define STMMAC_XDP_TX           BIT(1)
#define STMMAC_XDP_REDIRECT     BIT(2)

static int flow_ctrl = FLOW_AUTO;
module_param(flow_ctrl, int, 0644);
MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");

static int pause = PAUSE_TIME;
module_param(pause, int, 0644);
MODULE_PARM_DESC(pause, "Flow Control Pause Time");

#define TC_DEFAULT 64
static int tc = TC_DEFAULT;
module_param(tc, int, 0644);
MODULE_PARM_DESC(tc, "DMA threshold control value");

#define DEFAULT_BUFSIZE 1536
static int buf_sz = DEFAULT_BUFSIZE;
module_param(buf_sz, int, 0644);
MODULE_PARM_DESC(buf_sz, "DMA buffer size");

#define STMMAC_RX_COPYBREAK     256

static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
                                      NETIF_MSG_LINK | NETIF_MSG_IFUP |
                                      NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);

#define STMMAC_DEFAULT_LPI_TIMER        1000
static int eee_timer = STMMAC_DEFAULT_LPI_TIMER;
module_param(eee_timer, int, 0644);
MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec");
#define STMMAC_LPI_T(x) (jiffies + usecs_to_jiffies(x))

/* By default the driver will use the ring mode to manage tx and rx descriptors,
 * but allow user to force to use the chain instead of the ring
 */
static unsigned int chain_mode;
module_param(chain_mode, int, 0444);
MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode");

static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
/* For MSI interrupts handling */
static irqreturn_t stmmac_mac_interrupt(int irq, void *dev_id);
static irqreturn_t stmmac_safety_interrupt(int irq, void *dev_id);
static irqreturn_t stmmac_msi_intr_tx(int irq, void *data);
static irqreturn_t stmmac_msi_intr_rx(int irq, void *data);
static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue);
static void stmmac_flush_tx_descriptors(struct stmmac_priv *priv, int queue);
static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode,
                                          u32 rxmode, u32 chan);

#ifdef CONFIG_DEBUG_FS
static const struct net_device_ops stmmac_netdev_ops;
static void stmmac_init_fs(struct net_device *dev);
static void stmmac_exit_fs(struct net_device *dev);
#endif

#define STMMAC_COAL_TIMER(x) (ns_to_ktime((x) * NSEC_PER_USEC))

int stmmac_bus_clks_config(struct stmmac_priv *priv, bool enabled)
{
        int ret = 0;

        if (enabled) {
                ret = clk_prepare_enable(priv->plat->stmmac_clk);
                if (ret)
                        return ret;
                ret = clk_prepare_enable(priv->plat->pclk);
                if (ret) {
                        clk_disable_unprepare(priv->plat->stmmac_clk);
                        return ret;
                }
                if (priv->plat->clks_config) {
                        ret = priv->plat->clks_config(priv->plat->bsp_priv, enabled);
                        if (ret) {
                                clk_disable_unprepare(priv->plat->stmmac_clk);
                                clk_disable_unprepare(priv->plat->pclk);
                                return ret;
                        }
                }
        } else {
                clk_disable_unprepare(priv->plat->stmmac_clk);
                clk_disable_unprepare(priv->plat->pclk);
                if (priv->plat->clks_config)
                        priv->plat->clks_config(priv->plat->bsp_priv, enabled);
        }

        return ret;
}
EXPORT_SYMBOL_GPL(stmmac_bus_clks_config);

/**
 * stmmac_verify_args - verify the driver parameters.
 * Description: it checks the driver parameters and set a default in case of
 * errors.
 */
static void stmmac_verify_args(void)
{
        if (unlikely(watchdog < 0))
                watchdog = TX_TIMEO;
        if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB)))
                buf_sz = DEFAULT_BUFSIZE;
        if (unlikely(flow_ctrl > 1))
                flow_ctrl = FLOW_AUTO;
        else if (likely(flow_ctrl < 0))
                flow_ctrl = FLOW_OFF;
        if (unlikely((pause < 0) || (pause > 0xffff)))
                pause = PAUSE_TIME;
        if (eee_timer < 0)
                eee_timer = STMMAC_DEFAULT_LPI_TIMER;
}

static void __stmmac_disable_all_queues(struct stmmac_priv *priv)
{
        u32 rx_queues_cnt = priv->plat->rx_queues_to_use;
        u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
        u32 maxq = max(rx_queues_cnt, tx_queues_cnt);
        u32 queue;

        for (queue = 0; queue < maxq; queue++) {
                struct stmmac_channel *ch = &priv->channel[queue];

                if (stmmac_xdp_is_enabled(priv) &&
                    test_bit(queue, priv->af_xdp_zc_qps)) {
                        napi_disable(&ch->rxtx_napi);
                        continue;
                }

                if (queue < rx_queues_cnt)
                        napi_disable(&ch->rx_napi);
                if (queue < tx_queues_cnt)
                        napi_disable(&ch->tx_napi);
        }
}

/**
 * stmmac_disable_all_queues - Disable all queues
 * @priv: driver private structure
 */
static void stmmac_disable_all_queues(struct stmmac_priv *priv)
{
        u32 rx_queues_cnt = priv->plat->rx_queues_to_use;
        struct stmmac_rx_queue *rx_q;
        u32 queue;

        /* synchronize_rcu() needed for pending XDP buffers to drain */
        for (queue = 0; queue < rx_queues_cnt; queue++) {
                rx_q = &priv->rx_queue[queue];
                if (rx_q->xsk_pool) {
                        synchronize_rcu();
                        break;
                }
        }

        __stmmac_disable_all_queues(priv);
}

/**
 * stmmac_enable_all_queues - Enable all queues
 * @priv: driver private structure
 */
static void stmmac_enable_all_queues(struct stmmac_priv *priv)
{
        u32 rx_queues_cnt = priv->plat->rx_queues_to_use;
        u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
        u32 maxq = max(rx_queues_cnt, tx_queues_cnt);
        u32 queue;

        for (queue = 0; queue < maxq; queue++) {
                struct stmmac_channel *ch = &priv->channel[queue];

                if (stmmac_xdp_is_enabled(priv) &&
                    test_bit(queue, priv->af_xdp_zc_qps)) {
                        napi_enable(&ch->rxtx_napi);
                        continue;
                }

                if (queue < rx_queues_cnt)
                        napi_enable(&ch->rx_napi);
                if (queue < tx_queues_cnt)
                        napi_enable(&ch->tx_napi);
        }
}

static void stmmac_service_event_schedule(struct stmmac_priv *priv)
{
        if (!test_bit(STMMAC_DOWN, &priv->state) &&
            !test_and_set_bit(STMMAC_SERVICE_SCHED, &priv->state))
                queue_work(priv->wq, &priv->service_task);
}

static void stmmac_global_err(struct stmmac_priv *priv)
{
        netif_carrier_off(priv->dev);
        set_bit(STMMAC_RESET_REQUESTED, &priv->state);
        stmmac_service_event_schedule(priv);
}

/**
 * stmmac_clk_csr_set - dynamically set the MDC clock
 * @priv: driver private structure
 * Description: this is to dynamically set the MDC clock according to the csr
 * clock input.
 * Note:
 *      If a specific clk_csr value is passed from the platform
 *      this means that the CSR Clock Range selection cannot be
 *      changed at run-time and it is fixed (as reported in the driver
 *      documentation). Viceversa the driver will try to set the MDC
 *      clock dynamically according to the actual clock input.
 */
static void stmmac_clk_csr_set(struct stmmac_priv *priv)
{
        u32 clk_rate;

        clk_rate = clk_get_rate(priv->plat->stmmac_clk);

        /* Platform provided default clk_csr would be assumed valid
         * for all other cases except for the below mentioned ones.
         * For values higher than the IEEE 802.3 specified frequency
         * we can not estimate the proper divider as it is not known
         * the frequency of clk_csr_i. So we do not change the default
         * divider.
         */
        if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) {
                if (clk_rate < CSR_F_35M)
                        priv->clk_csr = STMMAC_CSR_20_35M;
                else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M))
                        priv->clk_csr = STMMAC_CSR_35_60M;
                else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M))
                        priv->clk_csr = STMMAC_CSR_60_100M;
                else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M))
                        priv->clk_csr = STMMAC_CSR_100_150M;
                else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))
                        priv->clk_csr = STMMAC_CSR_150_250M;
                else if ((clk_rate >= CSR_F_250M) && (clk_rate <= CSR_F_300M))
                        priv->clk_csr = STMMAC_CSR_250_300M;
        }

        if (priv->plat->has_sun8i) {
                if (clk_rate > 160000000)
                        priv->clk_csr = 0x03;
                else if (clk_rate > 80000000)
                        priv->clk_csr = 0x02;
                else if (clk_rate > 40000000)
                        priv->clk_csr = 0x01;
                else
                        priv->clk_csr = 0;
        }

        if (priv->plat->has_xgmac) {
                if (clk_rate > 400000000)
                        priv->clk_csr = 0x5;
                else if (clk_rate > 350000000)
                        priv->clk_csr = 0x4;
                else if (clk_rate > 300000000)
                        priv->clk_csr = 0x3;
                else if (clk_rate > 250000000)
                        priv->clk_csr = 0x2;
                else if (clk_rate > 150000000)
                        priv->clk_csr = 0x1;
                else
                        priv->clk_csr = 0x0;
        }
}

static void print_pkt(unsigned char *buf, int len)
{
        pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf);
        print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len);
}

static inline u32 stmmac_tx_avail(struct stmmac_priv *priv, u32 queue)
{
        struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
        u32 avail;

        if (tx_q->dirty_tx > tx_q->cur_tx)
                avail = tx_q->dirty_tx - tx_q->cur_tx - 1;
        else
                avail = priv->dma_tx_size - tx_q->cur_tx + tx_q->dirty_tx - 1;

        return avail;
}

/**
 * stmmac_rx_dirty - Get RX queue dirty
 * @priv: driver private structure
 * @queue: RX queue index
 */
static inline u32 stmmac_rx_dirty(struct stmmac_priv *priv, u32 queue)
{
        struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
        u32 dirty;

        if (rx_q->dirty_rx <= rx_q->cur_rx)
                dirty = rx_q->cur_rx - rx_q->dirty_rx;
        else
                dirty = priv->dma_rx_size - rx_q->dirty_rx + rx_q->cur_rx;

        return dirty;
}

static void stmmac_lpi_entry_timer_config(struct stmmac_priv *priv, bool en)
{
        int tx_lpi_timer;

        /* Clear/set the SW EEE timer flag based on LPI ET enablement */
        priv->eee_sw_timer_en = en ? 0 : 1;
        tx_lpi_timer  = en ? priv->tx_lpi_timer : 0;
        stmmac_set_eee_lpi_timer(priv, priv->hw, tx_lpi_timer);
}

/**
 * stmmac_enable_eee_mode - check and enter in LPI mode
 * @priv: driver private structure
 * Description: this function is to verify and enter in LPI mode in case of
 * EEE.
 */
static int stmmac_enable_eee_mode(struct stmmac_priv *priv)
{
        u32 tx_cnt = priv->plat->tx_queues_to_use;
        u32 queue;

        /* check if all TX queues have the work finished */
        for (queue = 0; queue < tx_cnt; queue++) {
                struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];

                if (tx_q->dirty_tx != tx_q->cur_tx)
                        return -EBUSY; /* still unfinished work */
        }

        /* Check and enter in LPI mode */
        if (!priv->tx_path_in_lpi_mode)
                stmmac_set_eee_mode(priv, priv->hw,
                                priv->plat->en_tx_lpi_clockgating);
        return 0;
}

/**
 * stmmac_disable_eee_mode - disable and exit from LPI mode
 * @priv: driver private structure
 * Description: this function is to exit and disable EEE in case of
 * LPI state is true. This is called by the xmit.
 */
void stmmac_disable_eee_mode(struct stmmac_priv *priv)
{
        if (!priv->eee_sw_timer_en) {
                stmmac_lpi_entry_timer_config(priv, 0);
                return;
        }

        stmmac_reset_eee_mode(priv, priv->hw);
        del_timer_sync(&priv->eee_ctrl_timer);
        priv->tx_path_in_lpi_mode = false;
}

/**
 * stmmac_eee_ctrl_timer - EEE TX SW timer.
 * @t:  timer_list struct containing private info
 * Description:
 *  if there is no data transfer and if we are not in LPI state,
 *  then MAC Transmitter can be moved to LPI state.
 */
static void stmmac_eee_ctrl_timer(struct timer_list *t)
{
        struct stmmac_priv *priv = from_timer(priv, t, eee_ctrl_timer);

        if (stmmac_enable_eee_mode(priv))
                mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(priv->tx_lpi_timer));
}

/**
 * stmmac_eee_init - init EEE
 * @priv: driver private structure
 * Description:
 *  if the GMAC supports the EEE (from the HW cap reg) and the phy device
 *  can also manage EEE, this function enable the LPI state and start related
 *  timer.
 */
bool stmmac_eee_init(struct stmmac_priv *priv)
{
        int eee_tw_timer = priv->eee_tw_timer;

        /* Using PCS we cannot dial with the phy registers at this stage
         * so we do not support extra feature like EEE.
         */
        if (priv->hw->pcs == STMMAC_PCS_TBI ||
            priv->hw->pcs == STMMAC_PCS_RTBI)
                return false;

        /* Check if MAC core supports the EEE feature. */
        if (!priv->dma_cap.eee)
                return false;

        mutex_lock(&priv->lock);

        /* Check if it needs to be deactivated */
        if (!priv->eee_active) {
                if (priv->eee_enabled) {
                        netdev_dbg(priv->dev, "disable EEE\n");
                        stmmac_lpi_entry_timer_config(priv, 0);
                        del_timer_sync(&priv->eee_ctrl_timer);
                        stmmac_set_eee_timer(priv, priv->hw, 0, eee_tw_timer);
                        if (priv->hw->xpcs)
                                xpcs_config_eee(priv->hw->xpcs,
                                                priv->plat->mult_fact_100ns,
                                                false);
                }
                mutex_unlock(&priv->lock);
                return false;
        }

        if (priv->eee_active && !priv->eee_enabled) {
                timer_setup(&priv->eee_ctrl_timer, stmmac_eee_ctrl_timer, 0);
                stmmac_set_eee_timer(priv, priv->hw, STMMAC_DEFAULT_LIT_LS,
                                     eee_tw_timer);
                if (priv->hw->xpcs)
                        xpcs_config_eee(priv->hw->xpcs,
                                        priv->plat->mult_fact_100ns,
                                        true);
        }

        if (priv->plat->has_gmac4 && priv->tx_lpi_timer <= STMMAC_ET_MAX) {
                del_timer_sync(&priv->eee_ctrl_timer);
                priv->tx_path_in_lpi_mode = false;
                stmmac_lpi_entry_timer_config(priv, 1);
        } else {
                stmmac_lpi_entry_timer_config(priv, 0);
                mod_timer(&priv->eee_ctrl_timer,
                          STMMAC_LPI_T(priv->tx_lpi_timer));
        }

        mutex_unlock(&priv->lock);
        netdev_dbg(priv->dev, "Energy-Efficient Ethernet initialized\n");
        return true;
}

/* stmmac_get_tx_hwtstamp - get HW TX timestamps
 * @priv: driver private structure
 * @p : descriptor pointer
 * @skb : the socket buffer
 * Description :
 * This function will read timestamp from the descriptor & pass it to stack.
 * and also perform some sanity checks.
 */
static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv,
                                   struct dma_desc *p, struct sk_buff *skb)
{
        struct skb_shared_hwtstamps shhwtstamp;
        bool found = false;
        u64 ns = 0;

        if (!priv->hwts_tx_en)
                return;

        /* exit if skb doesn't support hw tstamp */
        if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)))
                return;

        /* check tx tstamp status */
        if (stmmac_get_tx_timestamp_status(priv, p)) {
                stmmac_get_timestamp(priv, p, priv->adv_ts, &ns);
                found = true;
        } else if (!stmmac_get_mac_tx_timestamp(priv, priv->hw, &ns)) {
                found = true;
        }

        if (found) {
                ns -= priv->plat->cdc_error_adj;

                memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
                shhwtstamp.hwtstamp = ns_to_ktime(ns);

                netdev_dbg(priv->dev, "get valid TX hw timestamp %llu\n", ns);
                /* pass tstamp to stack */
                skb_tstamp_tx(skb, &shhwtstamp);
        }
}

/* stmmac_get_rx_hwtstamp - get HW RX timestamps
 * @priv: driver private structure
 * @p : descriptor pointer
 * @np : next descriptor pointer
 * @skb : the socket buffer
 * Description :
 * This function will read received packet's timestamp from the descriptor
 * and pass it to stack. It also perform some sanity checks.
 */
static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, struct dma_desc *p,
                                   struct dma_desc *np, struct sk_buff *skb)
{
        struct skb_shared_hwtstamps *shhwtstamp = NULL;
        struct dma_desc *desc = p;
        u64 ns = 0;

        if (!priv->hwts_rx_en)
                return;
        /* For GMAC4, the valid timestamp is from CTX next desc. */
        if (priv->plat->has_gmac4 || priv->plat->has_xgmac)
                desc = np;

        /* Check if timestamp is available */
        if (stmmac_get_rx_timestamp_status(priv, p, np, priv->adv_ts)) {
                stmmac_get_timestamp(priv, desc, priv->adv_ts, &ns);

                ns -= priv->plat->cdc_error_adj;

                netdev_dbg(priv->dev, "get valid RX hw timestamp %llu\n", ns);
                shhwtstamp = skb_hwtstamps(skb);
                memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
                shhwtstamp->hwtstamp = ns_to_ktime(ns);
        } else  {
                netdev_dbg(priv->dev, "cannot get RX hw timestamp\n");
        }
}

/**
 *  stmmac_hwtstamp_set - control hardware timestamping.
 *  @dev: device pointer.
 *  @ifr: An IOCTL specific structure, that can contain a pointer to
 *  a proprietary structure used to pass information to the driver.
 *  Description:
 *  This function configures the MAC to enable/disable both outgoing(TX)
 *  and incoming(RX) packets time stamping based on user input.
 *  Return Value:
 *  0 on success and an appropriate -ve integer on failure.
 */
static int stmmac_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
{
        struct stmmac_priv *priv = netdev_priv(dev);
        struct hwtstamp_config config;
        u32 ptp_v2 = 0;
        u32 tstamp_all = 0;
        u32 ptp_over_ipv4_udp = 0;
        u32 ptp_over_ipv6_udp = 0;
        u32 ptp_over_ethernet = 0;
        u32 snap_type_sel = 0;
        u32 ts_master_en = 0;
        u32 ts_event_en = 0;

        if (!(priv->dma_cap.time_stamp || priv->adv_ts)) {
                netdev_alert(priv->dev, "No support for HW time stamping\n");
                priv->hwts_tx_en = 0;
                priv->hwts_rx_en = 0;

                return -EOPNOTSUPP;
        }

        if (copy_from_user(&config, ifr->ifr_data,
                           sizeof(config)))
                return -EFAULT;

        netdev_dbg(priv->dev, "%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
                   __func__, config.flags, config.tx_type, config.rx_filter);

        if (config.tx_type != HWTSTAMP_TX_OFF &&
            config.tx_type != HWTSTAMP_TX_ON)
                return -ERANGE;

        if (priv->adv_ts) {
                switch (config.rx_filter) {
                case HWTSTAMP_FILTER_NONE:
                        /* time stamp no incoming packet at all */
                        config.rx_filter = HWTSTAMP_FILTER_NONE;
                        break;

                case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
                        /* PTP v1, UDP, any kind of event packet */
                        config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
                        /* 'xmac' hardware can support Sync, Pdelay_Req and
                         * Pdelay_resp by setting bit14 and bits17/16 to 01
                         * This leaves Delay_Req timestamps out.
                         * Enable all events *and* general purpose message
                         * timestamping
                         */
                        snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
                        ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
                        ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
                        break;

                case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
                        /* PTP v1, UDP, Sync packet */
                        config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
                        /* take time stamp for SYNC messages only */
                        ts_event_en = PTP_TCR_TSEVNTENA;

                        ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
                        ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
                        break;

                case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
                        /* PTP v1, UDP, Delay_req packet */
                        config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
                        /* take time stamp for Delay_Req messages only */
                        ts_master_en = PTP_TCR_TSMSTRENA;
                        ts_event_en = PTP_TCR_TSEVNTENA;

                        ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
                        ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
                        break;

                case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
                        /* PTP v2, UDP, any kind of event packet */
                        config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
                        ptp_v2 = PTP_TCR_TSVER2ENA;
                        /* take time stamp for all event messages */
                        snap_type_sel = PTP_TCR_SNAPTYPSEL_1;

                        ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
                        ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
                        break;

                case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
                        /* PTP v2, UDP, Sync packet */
                        config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
                        ptp_v2 = PTP_TCR_TSVER2ENA;
                        /* take time stamp for SYNC messages only */
                        ts_event_en = PTP_TCR_TSEVNTENA;

                        ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
                        ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
                        break;

                case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
                        /* PTP v2, UDP, Delay_req packet */
                        config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
                        ptp_v2 = PTP_TCR_TSVER2ENA;
                        /* take time stamp for Delay_Req messages only */
                        ts_master_en = PTP_TCR_TSMSTRENA;
                        ts_event_en = PTP_TCR_TSEVNTENA;

                        ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
                        ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
                        break;

                case HWTSTAMP_FILTER_PTP_V2_EVENT:
                        /* PTP v2/802.AS1 any layer, any kind of event packet */
                        config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
                        ptp_v2 = PTP_TCR_TSVER2ENA;
                        snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
                        if (priv->synopsys_id < DWMAC_CORE_4_10)
                                ts_event_en = PTP_TCR_TSEVNTENA;
                        ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
                        ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
                        ptp_over_ethernet = PTP_TCR_TSIPENA;
                        break;

                case HWTSTAMP_FILTER_PTP_V2_SYNC:
                        /* PTP v2/802.AS1, any layer, Sync packet */
                        config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
                        ptp_v2 = PTP_TCR_TSVER2ENA;
                        /* take time stamp for SYNC messages only */
                        ts_event_en = PTP_TCR_TSEVNTENA;

                        ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
                        ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
                        ptp_over_ethernet = PTP_TCR_TSIPENA;
                        break;

                case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
                        /* PTP v2/802.AS1, any layer, Delay_req packet */
                        config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
                        ptp_v2 = PTP_TCR_TSVER2ENA;
                        /* take time stamp for Delay_Req messages only */
                        ts_master_en = PTP_TCR_TSMSTRENA;
                        ts_event_en = PTP_TCR_TSEVNTENA;

                        ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
                        ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
                        ptp_over_ethernet = PTP_TCR_TSIPENA;
                        break;

                case HWTSTAMP_FILTER_NTP_ALL:
                case HWTSTAMP_FILTER_ALL:
                        /* time stamp any incoming packet */
                        config.rx_filter = HWTSTAMP_FILTER_ALL;
                        tstamp_all = PTP_TCR_TSENALL;
                        break;

                default:
                        return -ERANGE;
                }
        } else {
                switch (config.rx_filter) {
                case HWTSTAMP_FILTER_NONE:
                        config.rx_filter = HWTSTAMP_FILTER_NONE;
                        break;
                default:
                        /* PTP v1, UDP, any kind of event packet */
                        config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
                        break;
                }
        }
        priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1);
        priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON;

        priv->systime_flags = STMMAC_HWTS_ACTIVE;

        if (priv->hwts_tx_en || priv->hwts_rx_en) {
                priv->systime_flags |= tstamp_all | ptp_v2 |
                                       ptp_over_ethernet | ptp_over_ipv6_udp |
                                       ptp_over_ipv4_udp | ts_event_en |
                                       ts_master_en | snap_type_sel;
        }

        stmmac_config_hw_tstamping(priv, priv->ptpaddr, priv->systime_flags);

        memcpy(&priv->tstamp_config, &config, sizeof(config));

        return copy_to_user(ifr->ifr_data, &config,
                            sizeof(config)) ? -EFAULT : 0;
}

/**
 *  stmmac_hwtstamp_get - read hardware timestamping.
 *  @dev: device pointer.
 *  @ifr: An IOCTL specific structure, that can contain a pointer to
 *  a proprietary structure used to pass information to the driver.
 *  Description:
 *  This function obtain the current hardware timestamping settings
 *  as requested.
 */
static int stmmac_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
{
        struct stmmac_priv *priv = netdev_priv(dev);
        struct hwtstamp_config *config = &priv->tstamp_config;

        if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
                return -EOPNOTSUPP;

        return copy_to_user(ifr->ifr_data, config,
                            sizeof(*config)) ? -EFAULT : 0;
}

/**
 * stmmac_init_tstamp_counter - init hardware timestamping counter
 * @priv: driver private structure
 * @systime_flags: timestamping flags
 * Description:
 * Initialize hardware counter for packet timestamping.
 * This is valid as long as the interface is open and not suspended.
 * Will be rerun after resuming from suspend, case in which the timestamping
 * flags updated by stmmac_hwtstamp_set() also need to be restored.
 */
int stmmac_init_tstamp_counter(struct stmmac_priv *priv, u32 systime_flags)
{
        bool xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
        struct timespec64 now;
        u32 sec_inc = 0;
        u64 temp = 0;
        int ret;

        if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
                return -EOPNOTSUPP;

        ret = clk_prepare_enable(priv->plat->clk_ptp_ref);
        if (ret < 0) {
                netdev_warn(priv->dev,
                            "failed to enable PTP reference clock: %pe\n",
                            ERR_PTR(ret));
                return ret;
        }

        stmmac_config_hw_tstamping(priv, priv->ptpaddr, systime_flags);
        priv->systime_flags = systime_flags;

        /* program Sub Second Increment reg */
        stmmac_config_sub_second_increment(priv, priv->ptpaddr,
                                           priv->plat->clk_ptp_rate,
                                           xmac, &sec_inc);
        temp = div_u64(1000000000ULL, sec_inc);

        /* Store sub second increment for later use */
        priv->sub_second_inc = sec_inc;

        /* calculate default added value:
         * formula is :
         * addend = (2^32)/freq_div_ratio;
         * where, freq_div_ratio = 1e9ns/sec_inc
         */
        temp = (u64)(temp << 32);
        priv->default_addend = div_u64(temp, priv->plat->clk_ptp_rate);
        stmmac_config_addend(priv, priv->ptpaddr, priv->default_addend);

        /* initialize system time */
        ktime_get_real_ts64(&now);

        /* lower 32 bits of tv_sec are safe until y2106 */
        stmmac_init_systime(priv, priv->ptpaddr, (u32)now.tv_sec, now.tv_nsec);

        return 0;
}
EXPORT_SYMBOL_GPL(stmmac_init_tstamp_counter);

/**
 * stmmac_init_ptp - init PTP
 * @priv: driver private structure
 * Description: this is to verify if the HW supports the PTPv1 or PTPv2.
 * This is done by looking at the HW cap. register.
 * This function also registers the ptp driver.
 */
static int stmmac_init_ptp(struct stmmac_priv *priv)
{
        bool xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
        int ret;

        if (priv->plat->ptp_clk_freq_config)
                priv->plat->ptp_clk_freq_config(priv);

        ret = stmmac_init_tstamp_counter(priv, STMMAC_HWTS_ACTIVE);
        if (ret)
                return ret;

        priv->adv_ts = 0;
        /* Check if adv_ts can be enabled for dwmac 4.x / xgmac core */
        if (xmac && priv->dma_cap.atime_stamp)
                priv->adv_ts = 1;
        /* Dwmac 3.x core with extend_desc can support adv_ts */
        else if (priv->extend_desc && priv->dma_cap.atime_stamp)
                priv->adv_ts = 1;

        if (priv->dma_cap.time_stamp)
                netdev_info(priv->dev, "IEEE 1588-2002 Timestamp supported\n");

        if (priv->adv_ts)
                netdev_info(priv->dev,
                            "IEEE 1588-2008 Advanced Timestamp supported\n");

        priv->hwts_tx_en = 0;
        priv->hwts_rx_en = 0;

        return 0;
}

static void stmmac_release_ptp(struct stmmac_priv *priv)
{
        clk_disable_unprepare(priv->plat->clk_ptp_ref);
        stmmac_ptp_unregister(priv);
}

/**
 *  stmmac_mac_flow_ctrl - Configure flow control in all queues
 *  @priv: driver private structure
 *  @duplex: duplex passed to the next function
 *  Description: It is used for configuring the flow control in all queues
 */
static void stmmac_mac_flow_ctrl(struct stmmac_priv *priv, u32 duplex)
{
        u32 tx_cnt = priv->plat->tx_queues_to_use;

        stmmac_flow_ctrl(priv, priv->hw, duplex, priv->flow_ctrl,
                        priv->pause, tx_cnt);
}

static void stmmac_validate(struct phylink_config *config,
                            unsigned long *supported,
                            struct phylink_link_state *state)
{
        struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
        __ETHTOOL_DECLARE_LINK_MODE_MASK(mac_supported) = { 0, };
        __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
        int tx_cnt = priv->plat->tx_queues_to_use;
        int max_speed = priv->plat->max_speed;

        phylink_set(mac_supported, 10baseT_Half);
        phylink_set(mac_supported, 10baseT_Full);
        phylink_set(mac_supported, 100baseT_Half);
        phylink_set(mac_supported, 100baseT_Full);
        phylink_set(mac_supported, 1000baseT_Half);
        phylink_set(mac_supported, 1000baseT_Full);
        phylink_set(mac_supported, 1000baseKX_Full);

        phylink_set(mac_supported, Autoneg);
        phylink_set(mac_supported, Pause);
        phylink_set(mac_supported, Asym_Pause);
        phylink_set_port_modes(mac_supported);

        /* Cut down 1G if asked to */
        if ((max_speed > 0) && (max_speed < 1000)) {
                phylink_set(mask, 1000baseT_Full);
                phylink_set(mask, 1000baseX_Full);
        } else if (priv->plat->has_gmac4) {
                if (!max_speed || max_speed >= 2500) {
                        phylink_set(mac_supported, 2500baseT_Full);
                        phylink_set(mac_supported, 2500baseX_Full);
                }
        } else if (priv->plat->has_xgmac) {
                if (!max_speed || (max_speed >= 2500)) {
                        phylink_set(mac_supported, 2500baseT_Full);
                        phylink_set(mac_supported, 2500baseX_Full);
                }
                if (!max_speed || (max_speed >= 5000)) {
                        phylink_set(mac_supported, 5000baseT_Full);
                }
                if (!max_speed || (max_speed >= 10000)) {
                        phylink_set(mac_supported, 10000baseSR_Full);
                        phylink_set(mac_supported, 10000baseLR_Full);
                        phylink_set(mac_supported, 10000baseER_Full);
                        phylink_set(mac_supported, 10000baseLRM_Full);
                        phylink_set(mac_supported, 10000baseT_Full);
                        phylink_set(mac_supported, 10000baseKX4_Full);
                        phylink_set(mac_supported, 10000baseKR_Full);
                }
                if (!max_speed || (max_speed >= 25000)) {
                        phylink_set(mac_supported, 25000baseCR_Full);
                        phylink_set(mac_supported, 25000baseKR_Full);
                        phylink_set(mac_supported, 25000baseSR_Full);
                }
                if (!max_speed || (max_speed >= 40000)) {
                        phylink_set(mac_supported, 40000baseKR4_Full);
                        phylink_set(mac_supported, 40000baseCR4_Full);
                        phylink_set(mac_supported, 40000baseSR4_Full);
                        phylink_set(mac_supported, 40000baseLR4_Full);
                }

                if (!max_speed || (max_speed >= 50000)) {
                        phylink_set(mac_supported, 50000baseCR2_Full);
                        phylink_set(mac_supported, 50000baseKR2_Full);
                        phylink_set(mac_supported, 50000baseSR2_Full);
                        phylink_set(mac_supported, 50000baseKR_Full);
                        phylink_set(mac_supported, 50000baseSR_Full);
                        phylink_set(mac_supported, 50000baseCR_Full);
                        phylink_set(mac_supported, 50000baseLR_ER_FR_Full);
                        phylink_set(mac_supported, 50000baseDR_Full);
                }
                if (!max_speed || (max_speed >= 100000)) {
                        phylink_set(mac_supported, 100000baseKR4_Full);
                        phylink_set(mac_supported, 100000baseSR4_Full);
                        phylink_set(mac_supported, 100000baseCR4_Full);
                        phylink_set(mac_supported, 100000baseLR4_ER4_Full);
                        phylink_set(mac_supported, 100000baseKR2_Full);
                        phylink_set(mac_supported, 100000baseSR2_Full);
                        phylink_set(mac_supported, 100000baseCR2_Full);
                        phylink_set(mac_supported, 100000baseLR2_ER2_FR2_Full);
                        phylink_set(mac_supported, 100000baseDR2_Full);
                }
        }

        /* Half-Duplex can only work with single queue */
        if (tx_cnt > 1) {
                phylink_set(mask, 10baseT_Half);
                phylink_set(mask, 100baseT_Half);
                phylink_set(mask, 1000baseT_Half);
        }

        linkmode_and(supported, supported, mac_supported);
        linkmode_andnot(supported, supported, mask);

        linkmode_and(state->advertising, state->advertising, mac_supported);
        linkmode_andnot(state->advertising, state->advertising, mask);

        /* If PCS is supported, check which modes it supports. */
        if (priv->hw->xpcs)
                xpcs_validate(priv->hw->xpcs, supported, state);
}

static void stmmac_mac_config(struct phylink_config *config, unsigned int mode,
                              const struct phylink_link_state *state)
{
        /* Nothing to do, xpcs_config() handles everything */
}

static void stmmac_fpe_link_state_handle(struct stmmac_priv *priv, bool is_up)
{
        struct stmmac_fpe_cfg *fpe_cfg = priv->plat->fpe_cfg;
        enum stmmac_fpe_state *lo_state = &fpe_cfg->lo_fpe_state;
        enum stmmac_fpe_state *lp_state = &fpe_cfg->lp_fpe_state;
        bool *hs_enable = &fpe_cfg->hs_enable;

        if (is_up && *hs_enable) {
                stmmac_fpe_send_mpacket(priv, priv->ioaddr, MPACKET_VERIFY);
        } else {
                *lo_state = FPE_STATE_OFF;
                *lp_state = FPE_STATE_OFF;
        }
}

static void stmmac_mac_link_down(struct phylink_config *config,
                                 unsigned int mode, phy_interface_t interface)
{
        struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));

        stmmac_mac_set(priv, priv->ioaddr, false);
        priv->eee_active = false;
        priv->tx_lpi_enabled = false;
        priv->eee_enabled = stmmac_eee_init(priv);
        stmmac_set_eee_pls(priv, priv->hw, false);

        if (priv->dma_cap.fpesel)
                stmmac_fpe_link_state_handle(priv, false);
}

static void stmmac_mac_link_up(struct phylink_config *config,
                               struct phy_device *phy,
                               unsigned int mode, phy_interface_t interface,
                               int speed, int duplex,
                               bool tx_pause, bool rx_pause)
{
        struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
        u32 ctrl;

        ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
        ctrl &= ~priv->hw->link.speed_mask;

        if (interface == PHY_INTERFACE_MODE_USXGMII) {
                switch (speed) {
                case SPEED_10000:
                        ctrl |= priv->hw->link.xgmii.speed10000;
                        break;
                case SPEED_5000:
                        ctrl |= priv->hw->link.xgmii.speed5000;
                        break;
                case SPEED_2500:
                        ctrl |= priv->hw->link.xgmii.speed2500;
                        break;
                default:
                        return;
                }
        } else if (interface == PHY_INTERFACE_MODE_XLGMII) {
                switch (speed) {
                case SPEED_100000:
                        ctrl |= priv->hw->link.xlgmii.speed100000;
                        break;
                case SPEED_50000:
                        ctrl |= priv->hw->link.xlgmii.speed50000;
                        break;
                case SPEED_40000:
                        ctrl |= priv->hw->link.xlgmii.speed40000;
                        break;
                case SPEED_25000:
                        ctrl |= priv->hw->link.xlgmii.speed25000;
                        break;
                case SPEED_10000:
                        ctrl |= priv->hw->link.xgmii.speed10000;
                        break;
                case SPEED_2500:
                        ctrl |= priv->hw->link.speed2500;
                        break;
                case SPEED_1000:
                        ctrl |= priv->hw->link.speed1000;
                        break;
                default:
                        return;
                }
        } else {
                switch (speed) {
                case SPEED_2500:
                        ctrl |= priv->hw->link.speed2500;
                        break;
                case SPEED_1000:
                        ctrl |= priv->hw->link.speed1000;
                        break;
                case SPEED_100:
                        ctrl |= priv->hw->link.speed100;
                        break;
                case SPEED_10:
                        ctrl |= priv->hw->link.speed10;
                        break;
                default:
                        return;
                }
        }

        priv->speed = speed;

        if (priv->plat->fix_mac_speed)
                priv->plat->fix_mac_speed(priv->plat->bsp_priv, speed);

        if (!duplex)
                ctrl &= ~priv->hw->link.duplex;
        else
                ctrl |= priv->hw->link.duplex;

        /* Flow Control operation */
        if (tx_pause && rx_pause)
                stmmac_mac_flow_ctrl(priv, duplex);

        writel(ctrl, priv->ioaddr + MAC_CTRL_REG);

        stmmac_mac_set(priv, priv->ioaddr, true);
        if (phy && priv->dma_cap.eee) {
                priv->eee_active = phy_init_eee(phy, 1) >= 0;
                priv->eee_enabled = stmmac_eee_init(priv);
                priv->tx_lpi_enabled = priv->eee_enabled;
                stmmac_set_eee_pls(priv, priv->hw, true);
        }

        if (priv->dma_cap.fpesel)
                stmmac_fpe_link_state_handle(priv, true);
}

static const struct phylink_mac_ops stmmac_phylink_mac_ops = {
        .validate = stmmac_validate,
        .mac_config = stmmac_mac_config,
        .mac_link_down = stmmac_mac_link_down,
        .mac_link_up = stmmac_mac_link_up,
};

/**
 * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported
 * @priv: driver private structure
 * Description: this is to verify if the HW supports the PCS.
 * Physical Coding Sublayer (PCS) interface that can be used when the MAC is
 * configured for the TBI, RTBI, or SGMII PHY interface.
 */
static void stmmac_check_pcs_mode(struct stmmac_priv *priv)
{
        int interface = priv->plat->interface;

        if (priv->dma_cap.pcs) {
                if ((interface == PHY_INTERFACE_MODE_RGMII) ||
                    (interface == PHY_INTERFACE_MODE_RGMII_ID) ||
                    (interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
                    (interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
                        netdev_dbg(priv->dev, "PCS RGMII support enabled\n");
                        priv->hw->pcs = STMMAC_PCS_RGMII;
                } else if (interface == PHY_INTERFACE_MODE_SGMII) {
                        netdev_dbg(priv->dev, "PCS SGMII support enabled\n");
                        priv->hw->pcs = STMMAC_PCS_SGMII;
                }
        }
}

/**
 * stmmac_init_phy - PHY initialization
 * @dev: net device structure
 * Description: it initializes the driver's PHY state, and attaches the PHY
 * to the mac driver.
 *  Return value:
 *  0 on success
 */
static int stmmac_init_phy(struct net_device *dev)
{
        struct stmmac_priv *priv = netdev_priv(dev);
        struct device_node *node;
        int ret;

        node = priv->plat->phylink_node;

        if (node)
                ret = phylink_of_phy_connect(priv->phylink, node, 0);

        /* Some DT bindings do not set-up the PHY handle. Let's try to
         * manually parse it
         */
        if (!node || ret) {
                int addr = priv->plat->phy_addr;
                struct phy_device *phydev;

                phydev = mdiobus_get_phy(priv->mii, addr);
                if (!phydev) {
                        netdev_err(priv->dev, "no phy at addr %d\n", addr);
                        return -ENODEV;
                }

                ret = phylink_connect_phy(priv->phylink, phydev);
        }

        if (!priv->plat->pmt) {
                struct ethtool_wolinfo wol = { .cmd = ETHTOOL_GWOL };

                phylink_ethtool_get_wol(priv->phylink, &wol);
                device_set_wakeup_capable(priv->device, !!wol.supported);
        }

        return ret;
}

static int stmmac_phy_setup(struct stmmac_priv *priv)
{
        struct stmmac_mdio_bus_data *mdio_bus_data = priv->plat->mdio_bus_data;
        struct fwnode_handle *fwnode = of_fwnode_handle(priv->plat->phylink_node);
        int mode = priv->plat->phy_interface;
        struct phylink *phylink;

        priv->phylink_config.dev = &priv->dev->dev;
        priv->phylink_config.type = PHYLINK_NETDEV;
        priv->phylink_config.pcs_poll = true;
        if (priv->plat->mdio_bus_data)
                priv->phylink_config.ovr_an_inband =
                        mdio_bus_data->xpcs_an_inband;

        if (!fwnode)
                fwnode = dev_fwnode(priv->device);

        phylink = phylink_create(&priv->phylink_config, fwnode,
                                 mode, &stmmac_phylink_mac_ops);
        if (IS_ERR(phylink))
                return PTR_ERR(phylink);

        if (priv->hw->xpcs)
                phylink_set_pcs(phylink, &priv->hw->xpcs->pcs);

        priv->phylink = phylink;
        return 0;
}

static void stmmac_display_rx_rings(struct stmmac_priv *priv)
{
        u32 rx_cnt = priv->plat->rx_queues_to_use;
        unsigned int desc_size;
        void *head_rx;
        u32 queue;

        /* Display RX rings */
        for (queue = 0; queue < rx_cnt; queue++) {
                struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];

                pr_info("\tRX Queue %u rings\n", queue);

                if (priv->extend_desc) {
                        head_rx = (void *)rx_q->dma_erx;
                        desc_size = sizeof(struct dma_extended_desc);
                } else {
                        head_rx = (void *)rx_q->dma_rx;
                        desc_size = sizeof(struct dma_desc);
                }

                /* Display RX ring */
                stmmac_display_ring(priv, head_rx, priv->dma_rx_size, true,
                                    rx_q->dma_rx_phy, desc_size);
        }
}

static void stmmac_display_tx_rings(struct stmmac_priv *priv)
{
        u32 tx_cnt = priv->plat->tx_queues_to_use;
        unsigned int desc_size;
        void *head_tx;
        u32 queue;

        /* Display TX rings */
        for (queue = 0; queue < tx_cnt; queue++) {
                struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];

                pr_info("\tTX Queue %d rings\n", queue);

                if (priv->extend_desc) {
                        head_tx = (void *)tx_q->dma_etx;
                        desc_size = sizeof(struct dma_extended_desc);
                } else if (tx_q->tbs & STMMAC_TBS_AVAIL) {
                        head_tx = (void *)tx_q->dma_entx;
                        desc_size = sizeof(struct dma_edesc);
                } else {
                        head_tx = (void *)tx_q->dma_tx;
                        desc_size = sizeof(struct dma_desc);
                }

                stmmac_display_ring(priv, head_tx, priv->dma_tx_size, false,
                                    tx_q->dma_tx_phy, desc_size);
        }
}

static void stmmac_display_rings(struct stmmac_priv *priv)
{
        /* Display RX ring */
        stmmac_display_rx_rings(priv);

        /* Display TX ring */
        stmmac_display_tx_rings(priv);
}

static int stmmac_set_bfsize(int mtu, int bufsize)
{
        int ret = bufsize;

        if (mtu >= BUF_SIZE_8KiB)
                ret = BUF_SIZE_16KiB;
        else if (mtu >= BUF_SIZE_4KiB)
                ret = BUF_SIZE_8KiB;
        else if (mtu >= BUF_SIZE_2KiB)
                ret = BUF_SIZE_4KiB;
        else if (mtu > DEFAULT_BUFSIZE)
                ret = BUF_SIZE_2KiB;
        else
                ret = DEFAULT_BUFSIZE;

        return ret;
}

/**
 * stmmac_clear_rx_descriptors - clear RX descriptors
 * @priv: driver private structure
 * @queue: RX queue index
 * Description: this function is called to clear the RX descriptors
 * in case of both basic and extended descriptors are used.
 */
static void stmmac_clear_rx_descriptors(struct stmmac_priv *priv, u32 queue)
{
        struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
        int i;

        /* Clear the RX descriptors */
        for (i = 0; i < priv->dma_rx_size; i++)
                if (priv->extend_desc)
                        stmmac_init_rx_desc(priv, &rx_q->dma_erx[i].basic,
                                        priv->use_riwt, priv->mode,
                                        (i == priv->dma_rx_size - 1),
                                        priv->dma_buf_sz);
                else
                        stmmac_init_rx_desc(priv, &rx_q->dma_rx[i],
                                        priv->use_riwt, priv->mode,
                                        (i == priv->dma_rx_size - 1),
                                        priv->dma_buf_sz);
}

/**
 * stmmac_clear_tx_descriptors - clear tx descriptors
 * @priv: driver private structure
 * @queue: TX queue index.
 * Description: this function is called to clear the TX descriptors
 * in case of both basic and extended descriptors are used.
 */
static void stmmac_clear_tx_descriptors(struct stmmac_priv *priv, u32 queue)
{
        struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
        int i;

        /* Clear the TX descriptors */
        for (i = 0; i < priv->dma_tx_size; i++) {
                int last = (i == (priv->dma_tx_size - 1));
                struct dma_desc *p;

                if (priv->extend_desc)
                        p = &tx_q->dma_etx[i].basic;
                else if (tx_q->tbs & STMMAC_TBS_AVAIL)
                        p = &tx_q->dma_entx[i].basic;
                else
                        p = &tx_q->dma_tx[i];

                stmmac_init_tx_desc(priv, p, priv->mode, last);
        }
}

/**
 * stmmac_clear_descriptors - clear descriptors
 * @priv: driver private structure
 * Description: this function is called to clear the TX and RX descriptors
 * in case of both basic and extended descriptors are used.
 */
static void stmmac_clear_descriptors(struct stmmac_priv *priv)
{
        u32 rx_queue_cnt = priv->plat->rx_queues_to_use;
        u32 tx_queue_cnt = priv->plat->tx_queues_to_use;
        u32 queue;

        /* Clear the RX descriptors */
        for (queue = 0; queue < rx_queue_cnt; queue++)
                stmmac_clear_rx_descriptors(priv, queue);

        /* Clear the TX descriptors */
        for (queue = 0; queue < tx_queue_cnt; queue++)
                stmmac_clear_tx_descriptors(priv, queue);
}

/**
 * stmmac_init_rx_buffers - init the RX descriptor buffer.
 * @priv: driver private structure
 * @p: descriptor pointer
 * @i: descriptor index
 * @flags: gfp flag
 * @queue: RX queue index
 * Description: this function is called to allocate a receive buffer, perform
 * the DMA mapping and init the descriptor.
 */
static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p,
                                  int i, gfp_t flags, u32 queue)
{
        struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
        struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i];
        gfp_t gfp = (GFP_ATOMIC | __GFP_NOWARN);

        if (priv->dma_cap.addr64 <= 32)
                gfp |= GFP_DMA32;

        if (!buf->page) {
                buf->page = page_pool_alloc_pages(rx_q->page_pool, gfp);
                if (!buf->page)
                        return -ENOMEM;
                buf->page_offset = stmmac_rx_offset(priv);
        }

        if (priv->sph && !buf->sec_page) {
                buf->sec_page = page_pool_alloc_pages(rx_q->page_pool, gfp);
                if (!buf->sec_page)
                        return -ENOMEM;

                buf->sec_addr = page_pool_get_dma_addr(buf->sec_page);
                stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, true);
        } else {
                buf->sec_page = NULL;
                stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, false);
        }

        buf->addr = page_pool_get_dma_addr(buf->page) + buf->page_offset;

        stmmac_set_desc_addr(priv, p, buf->addr);
        if (priv->dma_buf_sz == BUF_SIZE_16KiB)
                stmmac_init_desc3(priv, p);

        return 0;
}

/**
 * stmmac_free_rx_buffer - free RX dma buffers
 * @priv: private structure
 * @queue: RX queue index
 * @i: buffer index.
 */
static void stmmac_free_rx_buffer(struct stmmac_priv *priv, u32 queue, int i)
{
        struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
        struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i];

        if (buf->page)
                page_pool_put_full_page(rx_q->page_pool, buf->page, false);
        buf->page = NULL;

        if (buf->sec_page)
                page_pool_put_full_page(rx_q->page_pool, buf->sec_page, false);
        buf->sec_page = NULL;
}

/**
 * stmmac_free_tx_buffer - free RX dma buffers
 * @priv: private structure
 * @queue: RX queue index
 * @i: buffer index.
 */
static void stmmac_free_tx_buffer(struct stmmac_priv *priv, u32 queue, int i)
{
        struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];

        if (tx_q->tx_skbuff_dma[i].buf &&
            tx_q->tx_skbuff_dma[i].buf_type != STMMAC_TXBUF_T_XDP_TX) {
                if (tx_q->tx_skbuff_dma[i].map_as_page)
                        dma_unmap_page(priv->device,
                                       tx_q->tx_skbuff_dma[i].buf,
                                       tx_q->tx_skbuff_dma[i].len,
                                       DMA_TO_DEVICE);
                else
                        dma_unmap_single(priv->device,
                                         tx_q->tx_skbuff_dma[i].buf,
                                         tx_q->tx_skbuff_dma[i].len,
                                         DMA_TO_DEVICE);
        }

        if (tx_q->xdpf[i] &&
            (tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_XDP_TX ||
             tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_XDP_NDO)) {
                xdp_return_frame(tx_q->xdpf[i]);
                tx_q->xdpf[i] = NULL;
        }

        if (tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_XSK_TX)
                tx_q->xsk_frames_done++;

        if (tx_q->tx_skbuff[i] &&
            tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_SKB) {
                dev_kfree_skb_any(tx_q->tx_skbuff[i]);
                tx_q->tx_skbuff[i] = NULL;
        }

        tx_q->tx_skbuff_dma[i].buf = 0;
        tx_q->tx_skbuff_dma[i].map_as_page = false;
}

/**
 * dma_free_rx_skbufs - free RX dma buffers
 * @priv: private structure
 * @queue: RX queue index
 */
static void dma_free_rx_skbufs(struct stmmac_priv *priv, u32 queue)
{
        int i;

        for (i = 0; i < priv->dma_rx_size; i++)
                stmmac_free_rx_buffer(priv, queue, i);
}

static int stmmac_alloc_rx_buffers(struct stmmac_priv *priv, u32 queue,
                                   gfp_t flags)
{
        struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
        int i;

        for (i = 0; i < priv->dma_rx_size; i++) {
                struct dma_desc *p;
                int ret;

                if (priv->extend_desc)
                        p = &((rx_q->dma_erx + i)->basic);
                else
                        p = rx_q->dma_rx + i;

                ret = stmmac_init_rx_buffers(priv, p, i, flags,
                                             queue);
                if (ret)
                        return ret;

                rx_q->buf_alloc_num++;
        }

        return 0;
}

/**
 * dma_free_rx_xskbufs - free RX dma buffers from XSK pool
 * @priv: private structure
 * @queue: RX queue index
 */
static void dma_free_rx_xskbufs(struct stmmac_priv *priv, u32 queue)
{
        struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
        int i;

        for (i = 0; i < priv->dma_rx_size; i++) {
                struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i];

                if (!buf->xdp)
                        continue;

                xsk_buff_free(buf->xdp);
                buf->xdp = NULL;
        }
}

static int stmmac_alloc_rx_buffers_zc(struct stmmac_priv *priv, u32 queue)
{
        struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
        int i;

        for (i = 0; i < priv->dma_rx_size; i++) {
                struct stmmac_rx_buffer *buf;
                dma_addr_t dma_addr;
                struct dma_desc *p;

                if (priv->extend_desc)
                        p = (struct dma_desc *)(rx_q->dma_erx + i);
                else
                        p = rx_q->dma_rx + i;

                buf = &rx_q->buf_pool[i];

                buf->xdp = xsk_buff_alloc(rx_q->xsk_pool);
                if (!buf->xdp)
                        return -ENOMEM;

                dma_addr = xsk_buff_xdp_get_dma(buf->xdp);
                stmmac_set_desc_addr(priv, p, dma_addr);
                rx_q->buf_alloc_num++;
        }

        return 0;
}

static struct xsk_buff_pool *stmmac_get_xsk_pool(struct stmmac_priv *priv, u32 queue)
{
        if (!stmmac_xdp_is_enabled(priv) || !test_bit(queue, priv->af_xdp_zc_qps))
                return NULL;

        return xsk_get_pool_from_qid(priv->dev, queue);
}

/**
 * __init_dma_rx_desc_rings - init the RX descriptor ring (per queue)
 * @priv: driver private structure
 * @queue: RX queue index
 * @flags: gfp flag.
 * Description: this function initializes the DMA RX descriptors
 * and allocates the socket buffers. It supports the chained and ring
 * modes.
 */
static int __init_dma_rx_desc_rings(struct stmmac_priv *priv, u32 queue, gfp_t flags)
{
        struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
        int ret;

        netif_dbg(priv, probe, priv->dev,
                  "(%s) dma_rx_phy=0x%08x\n", __func__,
                  (u32)rx_q->dma_rx_phy);

        stmmac_clear_rx_descriptors(priv, queue);

        xdp_rxq_info_unreg_mem_model(&rx_q->xdp_rxq);

        rx_q->xsk_pool = stmmac_get_xsk_pool(priv, queue);

        if (rx_q->xsk_pool) {
                WARN_ON(xdp_rxq_info_reg_mem_model(&rx_q->xdp_rxq,
                                                   MEM_TYPE_XSK_BUFF_POOL,
                                                   NULL));
                netdev_info(priv->dev,
                            "Register MEM_TYPE_XSK_BUFF_POOL RxQ-%d\n",
                            rx_q->queue_index);
                xsk_pool_set_rxq_info(rx_q->xsk_pool, &rx_q->xdp_rxq);
        } else {
                WARN_ON(xdp_rxq_info_reg_mem_model(&rx_q->xdp_rxq,
                                                   MEM_TYPE_PAGE_POOL,
                                                   rx_q->page_pool));
                netdev_info(priv->dev,
                            "Register MEM_TYPE_PAGE_POOL RxQ-%d\n",
                            rx_q->queue_index);
        }

        if (rx_q->xsk_pool) {
                /* RX XDP ZC buffer pool may not be populated, e.g.
                 * xdpsock TX-only.
                 */
                stmmac_alloc_rx_buffers_zc(priv, queue);
        } else {
                ret = stmmac_alloc_rx_buffers(priv, queue, flags);
                if (ret < 0)
                        return -ENOMEM;
        }

        rx_q->cur_rx = 0;
        rx_q->dirty_rx = 0;

        /* Setup the chained descriptor addresses */
        if (priv->mode == STMMAC_CHAIN_MODE) {
                if (priv->extend_desc)
                        stmmac_mode_init(priv, rx_q->dma_erx,
                                         rx_q->dma_rx_phy,
                                         priv->dma_rx_size, 1);
                else
                        stmmac_mode_init(priv, rx_q->dma_rx,
                                         rx_q->dma_rx_phy,
                                         priv->dma_rx_size, 0);
        }

        return 0;
}

static int init_dma_rx_desc_rings(struct net_device *dev, gfp_t flags)
{
        struct stmmac_priv *priv = netdev_priv(dev);
        u32 rx_count = priv->plat->rx_queues_to_use;
        u32 queue;
        int ret;

        /* RX INITIALIZATION */
        netif_dbg(priv, probe, priv->dev,
                  "SKB addresses:\nskb\t\tskb data\tdma data\n");

        for (queue = 0; queue < rx_count; queue++) {
                ret = __init_dma_rx_desc_rings(priv, queue, flags);
                if (ret)
                        goto err_init_rx_buffers;
        }

        return 0;

err_init_rx_buffers:
        while (queue >= 0) {
                struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];

                if (rx_q->xsk_pool)
                        dma_free_rx_xskbufs(priv, queue);
                else
                        dma_free_rx_skbufs(priv, queue);

                rx_q->buf_alloc_num = 0;
                rx_q->xsk_pool = NULL;

                if (queue == 0)
                        break;

                queue--;
        }

        return ret;
}

/**
 * __init_dma_tx_desc_rings - init the TX descriptor ring (per queue)
 * @priv: driver private structure
 * @queue : TX queue index
 * Description: this function initializes the DMA TX descriptors
 * and allocates the socket buffers. It supports the chained and ring
 * modes.
 */
static int __init_dma_tx_desc_rings(struct stmmac_priv *priv, u32 queue)
{
        struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
        int i;

        netif_dbg(priv, probe, priv->dev,
                  "(%s) dma_tx_phy=0x%08x\n", __func__,
                  (u32)tx_q->dma_tx_phy);

        /* Setup the chained descriptor addresses */
        if (priv->mode == STMMAC_CHAIN_MODE) {
                if (priv->extend_desc)
                        stmmac_mode_init(priv, tx_q->dma_etx,
                                         tx_q->dma_tx_phy,
                                         priv->dma_tx_size, 1);
                else if (!(tx_q->tbs & STMMAC_TBS_AVAIL))
                        stmmac_mode_init(priv, tx_q->dma_tx,
                                         tx_q->dma_tx_phy,
                                         priv->dma_tx_size, 0);
        }

        tx_q->xsk_pool = stmmac_get_xsk_pool(priv, queue);

        for (i = 0; i < priv->dma_tx_size; i++) {
                struct dma_desc *p;

                if (priv->extend_desc)
                        p = &((tx_q->dma_etx + i)->basic);
                else if (tx_q->tbs & STMMAC_TBS_AVAIL)
                        p = &((tx_q->dma_entx + i)->basic);
                else
                        p = tx_q->dma_tx + i;

                stmmac_clear_desc(priv, p);

                tx_q->tx_skbuff_dma[i].buf = 0;
                tx_q->tx_skbuff_dma[i].map_as_page = false;
                tx_q->tx_skbuff_dma[i].len = 0;
                tx_q->tx_skbuff_dma[i].last_segment = false;
                tx_q->tx_skbuff[i] = NULL;
        }

        tx_q->dirty_tx = 0;
        tx_q->cur_tx = 0;
        tx_q->mss = 0;

        netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, queue));

        return 0;
}

static int init_dma_tx_desc_rings(struct net_device *dev)
{
        struct stmmac_priv *priv = netdev_priv(dev);
        u32 tx_queue_cnt;
        u32 queue;

        tx_queue_cnt = priv->plat->tx_queues_to_use;

        for (queue = 0; queue < tx_queue_cnt; queue++)
                __init_dma_tx_desc_rings(priv, queue);

        return 0;
}

/**
 * init_dma_desc_rings - init the RX/TX descriptor rings
 * @dev: net device structure
 * @flags: gfp flag.
 * Description: this function initializes the DMA RX/TX descriptors
 * and allocates the socket buffers. It supports the chained and ring
 * modes.
 */
static int init_dma_desc_rings(struct net_device *dev, gfp_t flags)
{
        struct stmmac_priv *priv = netdev_priv(dev);
        int ret;

        ret = init_dma_rx_desc_rings(dev, flags);
        if (ret)
                return ret;

        ret = init_dma_tx_desc_rings(dev);

        stmmac_clear_descriptors(priv);

        if (netif_msg_hw(priv))
                stmmac_display_rings(priv);

        return ret;
}

/**
 * dma_free_tx_skbufs - free TX dma buffers
 * @priv: private structure
 * @queue: TX queue index
 */
static void dma_free_tx_skbufs(struct stmmac_priv *priv, u32 queue)
{
        struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
        int i;

        tx_q->xsk_frames_done = 0;

        for (i = 0; i < priv->dma_tx_size; i++)
                stmmac_free_tx_buffer(priv, queue, i);

        if (tx_q->xsk_pool && tx_q->xsk_frames_done) {
                xsk_tx_completed(tx_q->xsk_pool, tx_q->xsk_frames_done);
                tx_q->xsk_frames_done = 0;
                tx_q->xsk_pool = NULL;
        }
}

/**
 * stmmac_free_tx_skbufs - free TX skb buffers
 * @priv: private structure
 */
static void stmmac_free_tx_skbufs(struct stmmac_priv *priv)
{
        u32 tx_queue_cnt = priv->plat->tx_queues_to_use;
        u32 queue;

        for (queue = 0; queue < tx_queue_cnt; queue++)
                dma_free_tx_skbufs(priv, queue);
}

/**
 * __free_dma_rx_desc_resources - free RX dma desc resources (per queue)
 * @priv: private structure
 * @queue: RX queue index
 */
static void __free_dma_rx_desc_resources(struct stmmac_priv *priv, u32 queue)
{
        struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];

        /* Release the DMA RX socket buffers */
        if (rx_q->xsk_pool)
                dma_free_rx_xskbufs(priv, queue);
        else
                dma_free_rx_skbufs(priv, queue);

        rx_q->buf_alloc_num = 0;
        rx_q->xsk_pool = NULL;

        /* Free DMA regions of consistent memory previously allocated */
        if (!priv->extend_desc)
                dma_free_coherent(priv->device, priv->dma_rx_size *
                                  sizeof(struct dma_desc),
                                  rx_q->dma_rx, rx_q->dma_rx_phy);
        else
                dma_free_coherent(priv->device, priv->dma_rx_size *
                                  sizeof(struct dma_extended_desc),
                                  rx_q->dma_erx, rx_q->dma_rx_phy);

        if (xdp_rxq_info_is_reg(&rx_q->xdp_rxq))
                xdp_rxq_info_unreg(&rx_q->xdp_rxq);

        kfree(rx_q->buf_pool);
        if (rx_q->page_pool)
                page_pool_destroy(rx_q->page_pool);
}

static void free_dma_rx_desc_resources(struct stmmac_priv *priv)
{
        u32 rx_count = priv->plat->rx_queues_to_use;
        u32 queue;

        /* Free RX queue resources */
        for (queue = 0; queue < rx_count; queue++)
                __free_dma_rx_desc_resources(priv, queue);
}

/**
 * __free_dma_tx_desc_resources - free TX dma desc resources (per queue)
 * @priv: private structure
 * @queue: TX queue index
 */
static void __free_dma_tx_desc_resources(struct stmmac_priv *priv, u32 queue)
{
        struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
        size_t size;
        void *addr;

        /* Release the DMA TX socket buffers */
        dma_free_tx_skbufs(priv, queue);

        if (priv->extend_desc) {
                size = sizeof(struct dma_extended_desc);
                addr = tx_q->dma_etx;
        } else if (tx_q->tbs & STMMAC_TBS_AVAIL) {
                size = sizeof(struct dma_edesc);
                addr = tx_q->dma_entx;
        } else {
                size = sizeof(struct dma_desc);
                addr = tx_q->dma_tx;
        }

        size *= priv->dma_tx_size;

        dma_free_coherent(priv->device, size, addr, tx_q->dma_tx_phy);

        kfree(tx_q->tx_skbuff_dma);
        kfree(tx_q->tx_skbuff);
}

static void free_dma_tx_desc_resources(struct stmmac_priv *priv)
{
        u32 tx_count = priv->plat->tx_queues_to_use;
        u32 queue;

        /* Free TX queue resources */
        for (queue = 0; queue < tx_count; queue++)
                __free_dma_tx_desc_resources(priv, queue);
}

/**
 * __alloc_dma_rx_desc_resources - alloc RX resources (per queue).
 * @priv: private structure
 * @queue: RX queue index
 * Description: according to which descriptor can be used (extend or basic)
 * this function allocates the resources for TX and RX paths. In case of
 * reception, for example, it pre-allocated the RX socket buffer in order to
 * allow zero-copy mechanism.
 */
static int __alloc_dma_rx_desc_resources(struct stmmac_priv *priv, u32 queue)
{
        struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
        struct stmmac_channel *ch = &priv->channel[queue];
        bool xdp_prog = stmmac_xdp_is_enabled(priv);
        struct page_pool_params pp_params = { 0 };
        unsigned int num_pages;
        unsigned int napi_id;

        int ret;

        rx_q->queue_index = queue;
        rx_q->priv_data = priv;

        pp_params.flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV;
        pp_params.pool_size = priv->dma_rx_size;
        num_pages = DIV_ROUND_UP(priv->dma_buf_sz, PAGE_SIZE);
        pp_params.order = ilog2(num_pages);
        pp_params.nid = dev_to_node(priv->device);
        pp_params.dev = priv->device;
        pp_params.dma_dir = xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
        pp_params.offset = stmmac_rx_offset(priv);
        pp_params.max_len = STMMAC_MAX_RX_BUF_SIZE(num_pages);

        rx_q->page_pool = page_pool_create(&pp_params);
        if (IS_ERR(rx_q->page_pool)) {
                ret = PTR_ERR(rx_q->page_pool);
                rx_q->page_pool = NULL;
                return ret;
        }

        rx_q->buf_pool = kcalloc(priv->dma_rx_size,
                                 sizeof(*rx_q->buf_pool),
                                 GFP_KERNEL);
        if (!rx_q->buf_pool)
                return -ENOMEM;

        if (priv->extend_desc) {
                rx_q->dma_erx = dma_alloc_coherent(priv->device,
                                                   priv->dma_rx_size *
                                                   sizeof(struct dma_extended_desc),
                                                   &rx_q->dma_rx_phy,
                                                   GFP_KERNEL);
                if (!rx_q->dma_erx)
                        return -ENOMEM;

        } else {
                rx_q->dma_rx = dma_alloc_coherent(priv->device,
                                                  priv->dma_rx_size *
                                                  sizeof(struct dma_desc),
                                                  &rx_q->dma_rx_phy,
                                                  GFP_KERNEL);
                if (!rx_q->dma_rx)
                        return -ENOMEM;
        }

        if (stmmac_xdp_is_enabled(priv) &&
            test_bit(queue, priv->af_xdp_zc_qps))
                napi_id = ch->rxtx_napi.napi_id;
        else
                napi_id = ch->rx_napi.napi_id;

        ret = xdp_rxq_info_reg(&rx_q->xdp_rxq, priv->dev,
                               rx_q->queue_index,
                               napi_id);
        if (ret) {
                netdev_err(priv->dev, "Failed to register xdp rxq info\n");
                return -EINVAL;
        }

        return 0;
}

static int alloc_dma_rx_desc_resources(struct stmmac_priv *priv)
{
        u32 rx_count = priv->plat->rx_queues_to_use;
        u32 queue;
        int ret;

        /* RX queues buffers and DMA */
        for (queue = 0; queue < rx_count; queue++) {
                ret = __alloc_dma_rx_desc_resources(priv, queue);
                if (ret)
                        goto err_dma;
        }

        return 0;

err_dma:
        free_dma_rx_desc_resources(priv);

        return ret;
}

/**
 * __alloc_dma_tx_desc_resources - alloc TX resources (per queue).
 * @priv: private structure
 * @queue: TX queue index
 * Description: according to which descriptor can be used (extend or basic)
 * this function allocates the resources for TX and RX paths. In case of
 * reception, for example, it pre-allocated the RX socket buffer in order to
 * allow zero-copy mechanism.
 */
static int __alloc_dma_tx_desc_resources(struct stmmac_priv *priv, u32 queue)
{
        struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
        size_t size;
        void *addr;

        tx_q->queue_index = queue;
        tx_q->priv_data = priv;

        tx_q->tx_skbuff_dma = kcalloc(priv->dma_tx_size,
                                      sizeof(*tx_q->tx_skbuff_dma),
                                      GFP_KERNEL);
        if (!tx_q->tx_skbuff_dma)
                return -ENOMEM;

        tx_q->tx_skbuff = kcalloc(priv->dma_tx_size,
                                  sizeof(struct sk_buff *),
                                  GFP_KERNEL);
        if (!tx_q->tx_skbuff)
                return -ENOMEM;

        if (priv->extend_desc)
                size = sizeof(struct dma_extended_desc);
        else if (tx_q->tbs & STMMAC_TBS_AVAIL)
                size = sizeof(struct dma_edesc);
        else
                size = sizeof(struct dma_desc);

        size *= priv->dma_tx_size;

        addr = dma_alloc_coherent(priv->device, size,
                                  &tx_q->dma_tx_phy, GFP_KERNEL);
        if (!addr)
                return -ENOMEM;

        if (priv->extend_desc)
                tx_q->dma_etx = addr;
        else if (tx_q->tbs & STMMAC_TBS_AVAIL)
                tx_q->dma_entx = addr;
        else
                tx_q->dma_tx = addr;

        return 0;
}

static int alloc_dma_tx_desc_resources(struct stmmac_priv *priv)
{
        u32 tx_count = priv->plat->tx_queues_to_use;
        u32 queue;
        int ret;

        /* TX queues buffers and DMA */
        for (queue = 0; queue < tx_count; queue++) {
                ret = __alloc_dma_tx_desc_resources(priv, queue);
                if (ret)
                        goto err_dma;
        }

        return 0;

err_dma:
        free_dma_tx_desc_resources(priv);
        return ret;
}

/**
 * alloc_dma_desc_resources - alloc TX/RX resources.
 * @priv: private structure
 * Description: according to which descriptor can be used (extend or basic)
 * this function allocates the resources for TX and RX paths. In case of
 * reception, for example, it pre-allocated the RX socket buffer in order to
 * allow zero-copy mechanism.
 */
static int alloc_dma_desc_resources(struct stmmac_priv *priv)
{
        /* RX Allocation */
        int ret = alloc_dma_rx_desc_resources(priv);

        if (ret)
                return ret;

        ret = alloc_dma_tx_desc_resources(priv);

        return ret;
}

/**
 * free_dma_desc_resources - free dma desc resources
 * @priv: private structure
 */
static void free_dma_desc_resources(struct stmmac_priv *priv)
{
        /* Release the DMA TX socket buffers */
        free_dma_tx_desc_resources(priv);

        /* Release the DMA RX socket buffers later
         * to ensure all pending XDP_TX buffers are returned.
         */
        free_dma_rx_desc_resources(priv);
}

/**
 *  stmmac_mac_enable_rx_queues - Enable MAC rx queues
 *  @priv: driver private structure
 *  Description: It is used for enabling the rx queues in the MAC
 */
static void stmmac_mac_enable_rx_queues(struct stmmac_priv *priv)
{
        u32 rx_queues_count = priv->plat->rx_queues_to_use;
        int queue;
        u8 mode;

        for (queue = 0; queue < rx_queues_count; queue++) {
                mode = priv->plat->rx_queues_cfg[queue].mode_to_use;
                stmmac_rx_queue_enable(priv, priv->hw, mode, queue);
        }
}

/**
 * stmmac_start_rx_dma - start RX DMA channel
 * @priv: driver private structure
 * @chan: RX channel index
 * Description:
 * This starts a RX DMA channel
 */
static void stmmac_start_rx_dma(struct stmmac_priv *priv, u32 chan)
{
        netdev_dbg(priv->dev, "DMA RX processes started in channel %d\n", chan);
        stmmac_start_rx(priv, priv->ioaddr, chan);
}

/**
 * stmmac_start_tx_dma - start TX DMA channel
 * @priv: driver private structure
 * @chan: TX channel index
 * Description:
 * This starts a TX DMA channel
 */
static void stmmac_start_tx_dma(struct stmmac_priv *priv, u32 chan)
{
        netdev_dbg(priv->dev, "DMA TX processes started in channel %d\n", chan);
        stmmac_start_tx(priv, priv->ioaddr, chan);
}

/**
 * stmmac_stop_rx_dma - stop RX DMA channel
 * @priv: driver private structure
 * @chan: RX channel index
 * Description:
 * This stops a RX DMA channel
 */
static void stmmac_stop_rx_dma(struct stmmac_priv *priv, u32 chan)
{
        netdev_dbg(priv->dev, "DMA RX processes stopped in channel %d\n", chan);
        stmmac_stop_rx(priv, priv->ioaddr, chan);
}

/**
 * stmmac_stop_tx_dma - stop TX DMA channel
 * @priv: driver private structure
 * @chan: TX channel index
 * Description:
 * This stops a TX DMA channel
 */
static void stmmac_stop_tx_dma(struct stmmac_priv *priv, u32 chan)
{
        netdev_dbg(priv->dev, "DMA TX processes stopped in channel %d\n", chan);
        stmmac_stop_tx(priv, priv->ioaddr, chan);
}

static void stmmac_enable_all_dma_irq(struct stmmac_priv *priv)
{
        u32 rx_channels_count = priv->plat->rx_queues_to_use;
        u32 tx_channels_count = priv->plat->tx_queues_to_use;
        u32 dma_csr_ch = max(rx_channels_count, tx_channels_count);
        u32 chan;

        for (chan = 0; chan < dma_csr_ch; chan++) {
                struct stmmac_channel *ch = &priv->channel[chan];
                unsigned long flags;

                spin_lock_irqsave(&ch->lock, flags);
                stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 1, 1);
                spin_unlock_irqrestore(&ch->lock, flags);
        }
}

/**
 * stmmac_start_all_dma - start all RX and TX DMA channels
 * @priv: driver private structure
 * Description:
 * This starts all the RX and TX DMA channels
 */
static void stmmac_start_all_dma(struct stmmac_priv *priv)
{
        u32 rx_channels_count = priv->plat->rx_queues_to_use;
        u32 tx_channels_count = priv->plat->tx_queues_to_use;
        u32 chan = 0;

        for (chan = 0; chan < rx_channels_count; chan++)
                stmmac_start_rx_dma(priv, chan);

        for (chan = 0; chan < tx_channels_count; chan++)
                stmmac_start_tx_dma(priv, chan);
}

/**
 * stmmac_stop_all_dma - stop all RX and TX DMA channels
 * @priv: driver private structure
 * Description:
 * This stops the RX and TX DMA channels
 */
static void stmmac_stop_all_dma(struct stmmac_priv *priv)
{
        u32 rx_channels_count = priv->plat->rx_queues_to_use;
        u32 tx_channels_count = priv->plat->tx_queues_to_use;
        u32 chan = 0;

        for (chan = 0; chan < rx_channels_count; chan++)
                stmmac_stop_rx_dma(priv, chan);

        for (chan = 0; chan < tx_channels_count; chan++)
                stmmac_stop_tx_dma(priv, chan);
}

/**
 *  stmmac_dma_operation_mode - HW DMA operation mode
 *  @priv: driver private structure
 *  Description: it is used for configuring the DMA operation mode register in
 *  order to program the tx/rx DMA thresholds or Store-And-Forward mode.
 */
static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
{
        u32 rx_channels_count = priv->plat->rx_queues_to_use;
        u32 tx_channels_count = priv->plat->tx_queues_to_use;
        int rxfifosz = priv->plat->rx_fifo_size;
        int txfifosz = priv->plat->tx_fifo_size;
        u32 txmode = 0;
        u32 rxmode = 0;
        u32 chan = 0;
        u8 qmode = 0;

        if (rxfifosz == 0)
                rxfifosz = priv->dma_cap.rx_fifo_size;
        if (txfifosz == 0)
                txfifosz = priv->dma_cap.tx_fifo_size;

        /* Adjust for real per queue fifo size */
        rxfifosz /= rx_channels_count;
        txfifosz /= tx_channels_count;

        if (priv->plat->force_thresh_dma_mode) {
                txmode = tc;
                rxmode = tc;
        } else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) {
                /*
                 * In case of GMAC, SF mode can be enabled
                 * to perform the TX COE in HW. This depends on:
                 * 1) TX COE if actually supported
                 * 2) There is no bugged Jumbo frame support
                 *    that needs to not insert csum in the TDES.
                 */
                txmode = SF_DMA_MODE;
                rxmode = SF_DMA_MODE;
                priv->xstats.threshold = SF_DMA_MODE;
        } else {
                txmode = tc;
                rxmode = SF_DMA_MODE;
        }

        /* configure all channels */
        for (chan = 0; chan < rx_channels_count; chan++) {
                struct stmmac_rx_queue *rx_q = &priv->rx_queue[chan];
                u32 buf_size;

                qmode = priv->plat->rx_queues_cfg[chan].mode_to_use;

                stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan,
                                rxfifosz, qmode);

                if (rx_q->xsk_pool) {
                        buf_size = xsk_pool_get_rx_frame_size(rx_q->xsk_pool);
                        stmmac_set_dma_bfsize(priv, priv->ioaddr,
                                              buf_size,
                                              chan);
                } else {
                        stmmac_set_dma_bfsize(priv, priv->ioaddr,
                                              priv->dma_buf_sz,
                                              chan);
                }
        }

        for (chan = 0; chan < tx_channels_count; chan++) {
                qmode = priv->plat->tx_queues_cfg[chan].mode_to_use;

                stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan,
                                txfifosz, qmode);
        }
}

static bool stmmac_xdp_xmit_zc(struct stmmac_priv *priv, u32 queue, u32 budget)
{
        struct netdev_queue *nq = netdev_get_tx_queue(priv->dev, queue);
        struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
        struct xsk_buff_pool *pool = tx_q->xsk_pool;
        unsigned int entry = tx_q->cur_tx;
        struct dma_desc *tx_desc = NULL;
        struct xdp_desc xdp_desc;
        bool work_done = true;

        /* Avoids TX time-out as we are sharing with slow path */
        txq_trans_cond_update(nq);

        budget = min(budget, stmmac_tx_avail(priv, queue));

        while (budget-- > 0) {
                dma_addr_t dma_addr;
                bool set_ic;

                /* We are sharing with slow path and stop XSK TX desc submission when
                 * available TX ring is less than threshold.
                 */
                if (unlikely(stmmac_tx_avail(priv, queue) < STMMAC_TX_XSK_AVAIL) ||
                    !netif_carrier_ok(priv->dev)) {
                        work_done = false;
                        break;
                }

                if (!xsk_tx_peek_desc(pool, &xdp_desc))
                        break;

                if (likely(priv->extend_desc))
                        tx_desc = (struct dma_desc *)(tx_q->dma_etx + entry);
                else if (tx_q->tbs & STMMAC_TBS_AVAIL)
                        tx_desc = &tx_q->dma_entx[entry].basic;
                else
                        tx_desc = tx_q->dma_tx + entry;

                dma_addr = xsk_buff_raw_get_dma(pool, xdp_desc.addr);
                xsk_buff_raw_dma_sync_for_device(pool, dma_addr, xdp_desc.len);

                tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_XSK_TX;

                /* To return XDP buffer to XSK pool, we simple call
                 * xsk_tx_completed(), so we don't need to fill up
                 * 'buf' and 'xdpf'.
                 */
                tx_q->tx_skbuff_dma[entry].buf = 0;
                tx_q->xdpf[entry] = NULL;

                tx_q->tx_skbuff_dma[entry].map_as_page = false;
                tx_q->tx_skbuff_dma[entry].len = xdp_desc.len;
                tx_q->tx_skbuff_dma[entry].last_segment = true;
                tx_q->tx_skbuff_dma[entry].is_jumbo = false;

                stmmac_set_desc_addr(priv, tx_desc, dma_addr);

                tx_q->tx_count_frames++;

                if (!priv->tx_coal_frames[queue])
                        set_ic = false;
                else if (tx_q->tx_count_frames % priv->tx_coal_frames[queue] == 0)
                        set_ic = true;
                else
                        set_ic = false;

                if (set_ic) {
                        tx_q->tx_count_frames = 0;
                        stmmac_set_tx_ic(priv, tx_desc);
                        priv->xstats.tx_set_ic_bit++;
                }

                stmmac_prepare_tx_desc(priv, tx_desc, 1, xdp_desc.len,
                                       true, priv->mode, true, true,
                                       xdp_desc.len);

                stmmac_enable_dma_transmission(priv, priv->ioaddr);

                tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_tx_size);
                entry = tx_q->cur_tx;
        }

        if (tx_desc) {
                stmmac_flush_tx_descriptors(priv, queue);
                xsk_tx_release(pool);
        }

        /* Return true if all of the 3 conditions are met
         *  a) TX Budget is still available
         *  b) work_done = true when XSK TX desc peek is empty (no more
         *     pending XSK TX for transmission)
         */
        return !!budget && work_done;
}

static void stmmac_bump_dma_threshold(struct stmmac_priv *priv, u32 chan)
{
        if (unlikely(priv->xstats.threshold != SF_DMA_MODE) && tc <= 256) {
                tc += 64;

                if (priv->plat->force_thresh_dma_mode)
                        stmmac_set_dma_operation_mode(priv, tc, tc, chan);
                else
                        stmmac_set_dma_operation_mode(priv, tc, SF_DMA_MODE,
                                                      chan);

                priv->xstats.threshold = tc;
        }
}

/**
 * stmmac_tx_clean - to manage the transmission completion
 * @priv: driver private structure
 * @budget: napi budget limiting this functions packet handling
 * @queue: TX queue index
 * Description: it reclaims the transmit resources after transmission completes.
 */
static int stmmac_tx_clean(struct stmmac_priv *priv, int budget, u32 queue)
{
        struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
        unsigned int bytes_compl = 0, pkts_compl = 0;
        unsigned int entry, xmits = 0, count = 0;

        __netif_tx_lock_bh(netdev_get_tx_queue(priv->dev, queue));

        priv->xstats.tx_clean++;

        tx_q->xsk_frames_done = 0;

        entry = tx_q->dirty_tx;

        /* Try to clean all TX complete frame in 1 shot */
        while ((entry != tx_q->cur_tx) && count < priv->dma_tx_size) {
                struct xdp_frame *xdpf;
                struct sk_buff *skb;
                struct dma_desc *p;
                int status;

                if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_TX ||
                    tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_NDO) {
                        xdpf = tx_q->xdpf[entry];
                        skb = NULL;
                } else if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_SKB) {
                        xdpf = NULL;
                        skb = tx_q->tx_skbuff[entry];
                } else {
                        xdpf = NULL;
                        skb = NULL;
                }

                if (priv->extend_desc)
                        p = (struct dma_desc *)(tx_q->dma_etx + entry);
                else if (tx_q->tbs & STMMAC_TBS_AVAIL)
                        p = &tx_q->dma_entx[entry].basic;
                else
                        p = tx_q->dma_tx + entry;

                status = stmmac_tx_status(priv, &priv->dev->stats,
                                &priv->xstats, p, priv->ioaddr);
                /* Check if the descriptor is owned by the DMA */
                if (unlikely(status & tx_dma_own))
                        break;

                count++;

                /* Make sure descriptor fields are read after reading
                 * the own bit.
                 */
                dma_rmb();

                /* Just consider the last segment and ...*/
                if (likely(!(status & tx_not_ls))) {
                        /* ... verify the status error condition */
                        if (unlikely(status & tx_err)) {
                                priv->dev->stats.tx_errors++;
                                if (unlikely(status & tx_err_bump_tc))
                                        stmmac_bump_dma_threshold(priv, queue);
                        } else {
                                priv->dev->stats.tx_packets++;
                                priv->xstats.tx_pkt_n++;
                                priv->xstats.txq_stats[queue].tx_pkt_n++;
                        }
                        if (skb)
                                stmmac_get_tx_hwtstamp(priv, p, skb);
                }

                if (likely(tx_q->tx_skbuff_dma[entry].buf &&
                           tx_q->tx_skbuff_dma[entry].buf_type != STMMAC_TXBUF_T_XDP_TX)) {
                        if (tx_q->tx_skbuff_dma[entry].map_as_page)
                                dma_unmap_page(priv->device,
                                               tx_q->tx_skbuff_dma[entry].buf,
                                               tx_q->tx_skbuff_dma[entry].len,
                                               DMA_TO_DEVICE);
                        else
                                dma_unmap_single(priv->device,
                                                 tx_q->tx_skbuff_dma[entry].buf,
                                                 tx_q->tx_skbuff_dma[entry].len,
                                                 DMA_TO_DEVICE);
                        tx_q->tx_skbuff_dma[entry].buf = 0;
                        tx_q->tx_skbuff_dma[entry].len = 0;
                        tx_q->tx_skbuff_dma[entry].map_as_page = false;
                }

                stmmac_clean_desc3(priv, tx_q, p);

                tx_q->tx_skbuff_dma[entry].last_segment = false;
                tx_q->tx_skbuff_dma[entry].is_jumbo = false;

                if (xdpf &&
                    tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_TX) {
                        xdp_return_frame_rx_napi(xdpf);
                        tx_q->xdpf[entry] = NULL;
                }

                if (xdpf &&
                    tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_NDO) {
                        xdp_return_frame(xdpf);
                        tx_q->xdpf[entry] = NULL;
                }

                if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XSK_TX)
                        tx_q->xsk_frames_done++;

                if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_SKB) {
                        if (likely(skb)) {
                                pkts_compl++;
                                bytes_compl += skb->len;
                                dev_consume_skb_any(skb);
                                tx_q->tx_skbuff[entry] = NULL;
                        }
                }

                stmmac_release_tx_desc(priv, p, priv->mode);

                entry = STMMAC_GET_ENTRY(entry, priv->dma_tx_size);
        }
        tx_q->dirty_tx = entry;

        netdev_tx_completed_queue(netdev_get_tx_queue(priv->dev, queue),
                                  pkts_compl, bytes_compl);

        if (unlikely(netif_tx_queue_stopped(netdev_get_tx_queue(priv->dev,
                                                                queue))) &&
            stmmac_tx_avail(priv, queue) > STMMAC_TX_THRESH(priv)) {

                netif_dbg(priv, tx_done, priv->dev,
                          "%s: restart transmit\n", __func__);
                netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, queue));
        }

        if (tx_q->xsk_pool) {
                bool work_done;

                if (tx_q->xsk_frames_done)
                        xsk_tx_completed(tx_q->xsk_pool, tx_q->xsk_frames_done);

                if (xsk_uses_need_wakeup(tx_q->xsk_pool))
                        xsk_set_tx_need_wakeup(tx_q->xsk_pool);

                /* For XSK TX, we try to send as many as possible.
                 * If XSK work done (XSK TX desc empty and budget still
                 * available), return "budget - 1" to reenable TX IRQ.
                 * Else, return "budget" to make NAPI continue polling.
                 */
                work_done = stmmac_xdp_xmit_zc(priv, queue,
                                               STMMAC_XSK_TX_BUDGET_MAX);
                if (work_done)
                        xmits = budget - 1;
                else
                        xmits = budget;
        }

        if (priv->eee_enabled && !priv->tx_path_in_lpi_mode &&
            priv->eee_sw_timer_en) {
                if (stmmac_enable_eee_mode(priv))
                        mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(priv->tx_lpi_timer));
        }

        /* We still have pending packets, let's call for a new scheduling */
        if (tx_q->dirty_tx != tx_q->cur_tx)
                hrtimer_start(&tx_q->txtimer,
                              STMMAC_COAL_TIMER(priv->tx_coal_timer[queue]),
                              HRTIMER_MODE_REL);

        __netif_tx_unlock_bh(netdev_get_tx_queue(priv->dev, queue));

        /* Combine decisions from TX clean and XSK TX */
        return max(count, xmits);
}

/**
 * stmmac_tx_err - to manage the tx error
 * @priv: driver private structure
 * @chan: channel index
 * Description: it cleans the descriptors and restarts the transmission
 * in case of transmission errors.
 */
static void stmmac_tx_err(struct stmmac_priv *priv, u32 chan)
{
        struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan];

        netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, chan));

        stmmac_stop_tx_dma(priv, chan);
        dma_free_tx_skbufs(priv, chan);
        stmmac_clear_tx_descriptors(priv, chan);
        tx_q->dirty_tx = 0;
        tx_q->cur_tx = 0;
        tx_q->mss = 0;
        netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, chan));
        stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
                            tx_q->dma_tx_phy, chan);
        stmmac_start_tx_dma(priv, chan);

        priv->dev->stats.tx_errors++;
        netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, chan));
}

/**
 *  stmmac_set_dma_operation_mode - Set DMA operation mode by channel
 *  @priv: driver private structure
 *  @txmode: TX operating mode
 *  @rxmode: RX operating mode
 *  @chan: channel index
 *  Description: it is used for configuring of the DMA operation mode in
 *  runtime in order to program the tx/rx DMA thresholds or Store-And-Forward
 *  mode.
 */
static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode,
                                          u32 rxmode, u32 chan)
{
        u8 rxqmode = priv->plat->rx_queues_cfg[chan].mode_to_use;
        u8 txqmode = priv->plat->tx_queues_cfg[chan].mode_to_use;
        u32 rx_channels_count = priv->plat->rx_queues_to_use;
        u32 tx_channels_count = priv->plat->tx_queues_to_use;
        int rxfifosz = priv->plat->rx_fifo_size;
        int txfifosz = priv->plat->tx_fifo_size;

        if (rxfifosz == 0)
                rxfifosz = priv->dma_cap.rx_fifo_size;
        if (txfifosz == 0)
                txfifosz = priv->dma_cap.tx_fifo_size;

        /* Adjust for real per queue fifo size */
        rxfifosz /= rx_channels_count;
        txfifosz /= tx_channels_count;

        stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, rxfifosz, rxqmode);
        stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, txfifosz, txqmode);
}

static bool stmmac_safety_feat_interrupt(struct stmmac_priv *priv)
{
        int ret;

        ret = stmmac_safety_feat_irq_status(priv, priv->dev,
                        priv->ioaddr, priv->dma_cap.asp, &priv->sstats);
        if (ret && (ret != -EINVAL)) {
                stmmac_global_err(priv);
                return true;
        }

        return false;
}

static int stmmac_napi_check(struct stmmac_priv *priv, u32 chan, u32 dir)
{
        int status = stmmac_dma_interrupt_status(priv, priv->ioaddr,
                                                 &priv->xstats, chan, dir);
        struct stmmac_rx_queue *rx_q = &priv->rx_queue[chan];
        struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan];
        struct stmmac_channel *ch = &priv->channel[chan];
        struct napi_struct *rx_napi;
        struct napi_struct *tx_napi;
        unsigned long flags;

        rx_napi = rx_q->xsk_pool ? &ch->rxtx_napi : &ch->rx_napi;
        tx_napi = tx_q->xsk_pool ? &ch->rxtx_napi : &ch->tx_napi;

        if ((status & handle_rx) && (chan < priv->plat->rx_queues_to_use)) {
                if (napi_schedule_prep(rx_napi)) {
                        spin_lock_irqsave(&ch->lock, flags);
                        stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 1, 0);
                        spin_unlock_irqrestore(&ch->lock, flags);
                        __napi_schedule(rx_napi);
                }
        }

        if ((status & handle_tx) && (chan < priv->plat->tx_queues_to_use)) {
                if (napi_schedule_prep(tx_napi)) {
                        spin_lock_irqsave(&ch->lock, flags);
                        stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 0, 1);
                        spin_unlock_irqrestore(&ch->lock, flags);
                        __napi_schedule(tx_napi);
                }
        }

        return status;
}

/**
 * stmmac_dma_interrupt - DMA ISR
 * @priv: driver private structure
 * Description: this is the DMA ISR. It is called by the main ISR.
 * It calls the dwmac dma routine and schedule poll method in case of some
 * work can be done.
 */
static void stmmac_dma_interrupt(struct stmmac_priv *priv)
{
        u32 tx_channel_count = priv->plat->tx_queues_to_use;
        u32 rx_channel_count = priv->plat->rx_queues_to_use;
        u32 channels_to_check = tx_channel_count > rx_channel_count ?
                                tx_channel_count : rx_channel_count;
        u32 chan;
        int status[max_t(u32, MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES)];

        /* Make sure we never check beyond our status buffer. */
        if (WARN_ON_ONCE(channels_to_check > ARRAY_SIZE(status)))
                channels_to_check = ARRAY_SIZE(status);

        for (chan = 0; chan < channels_to_check; chan++)
                status[chan] = stmmac_napi_check(priv, chan,
                                                 DMA_DIR_RXTX);

        for (chan = 0; chan < tx_channel_count; chan++) {
                if (unlikely(status[chan] & tx_hard_error_bump_tc)) {
                        /* Try to bump up the dma threshold on this failure */
                        stmmac_bump_dma_threshold(priv, chan);
                } else if (unlikely(status[chan] == tx_hard_error)) {
                        stmmac_tx_err(priv, chan);
                }
        }
}

/**
 * stmmac_mmc_setup: setup the Mac Management Counters (MMC)
 * @priv: driver private structure
 * Description: this masks the MMC irq, in fact, the counters are managed in SW.
 */
static void stmmac_mmc_setup(struct stmmac_priv *priv)
{
        unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
                            MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;

        stmmac_mmc_intr_all_mask(priv, priv->mmcaddr);

        if (priv->dma_cap.rmon) {
                stmmac_mmc_ctrl(priv, priv->mmcaddr, mode);
                memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
        } else
                netdev_info(priv->dev, "No MAC Management Counters available\n");
}

/**
 * stmmac_get_hw_features - get MAC capabilities from the HW cap. register.
 * @priv: driver private structure
 * Description:
 *  new GMAC chip generations have a new register to indicate the
 *  presence of the optional feature/functions.
 *  This can be also used to override the value passed through the
 *  platform and necessary for old MAC10/100 and GMAC chips.
 */
static int stmmac_get_hw_features(struct stmmac_priv *priv)
{
        return stmmac_get_hw_feature(priv, priv->ioaddr, &priv->dma_cap) == 0;
}

/**
 * stmmac_check_ether_addr - check if the MAC addr is valid
 * @priv: driver private structure
 * Description:
 * it is to verify if the MAC address is valid, in case of failures it
 * generates a random MAC address
 */
static void stmmac_check_ether_addr(struct stmmac_priv *priv)
{
        u8 addr[ETH_ALEN];

        if (!is_valid_ether_addr(priv->dev->dev_addr)) {
                stmmac_get_umac_addr(priv, priv->hw, addr, 0);
                if (is_valid_ether_addr(addr))
                        eth_hw_addr_set(priv->dev, addr);
                else
                        eth_hw_addr_random(priv->dev);
                dev_info(priv->device, "device MAC address %pM\n",
                         priv->dev->dev_addr);
        }
}

/**
 * stmmac_init_dma_engine - DMA init.
 * @priv: driver private structure
 * Description:
 * It inits the DMA invoking the specific MAC/GMAC callback.
 * Some DMA parameters can be passed from the platform;
 * in case of these are not passed a default is kept for the MAC or GMAC.
 */
static int stmmac_init_dma_engine(struct stmmac_priv *priv)
{
        u32 rx_channels_count = priv->plat->rx_queues_to_use;
        u32 tx_channels_count = priv->plat->tx_queues_to_use;
        u32 dma_csr_ch = max(rx_channels_count, tx_channels_count);
        struct stmmac_rx_queue *rx_q;
        struct stmmac_tx_queue *tx_q;
        u32 chan = 0;
        int atds = 0;
        int ret = 0;

        if (!priv->plat->dma_cfg || !priv->plat->dma_cfg->pbl) {
                dev_err(priv->device, "Invalid DMA configuration\n");
                return -EINVAL;
        }

        if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE))
                atds = 1;

        ret = stmmac_reset(priv, priv->ioaddr);
        if (ret) {
                dev_err(priv->device, "Failed to reset the dma\n");
                return ret;
        }

        /* DMA Configuration */
        stmmac_dma_init(priv, priv->ioaddr, priv->plat->dma_cfg, atds);

        if (priv->plat->axi)
                stmmac_axi(priv, priv->ioaddr, priv->plat->axi);

        /* DMA CSR Channel configuration */
        for (chan = 0; chan < dma_csr_ch; chan++) {
                stmmac_init_chan(priv, priv->ioaddr, priv->plat->dma_cfg, chan);
                stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 1, 1);
        }

        /* DMA RX Channel Configuration */
        for (chan = 0; chan < rx_channels_count; chan++) {
                rx_q = &priv->rx_queue[chan];

                stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
                                    rx_q->dma_rx_phy, chan);

                rx_q->rx_tail_addr = rx_q->dma_rx_phy +
                                     (rx_q->buf_alloc_num *
                                      sizeof(struct dma_desc));
                stmmac_set_rx_tail_ptr(priv, priv->ioaddr,
                                       rx_q->rx_tail_addr, chan);
        }

        /* DMA TX Channel Configuration */
        for (chan = 0; chan < tx_channels_count; chan++) {
                tx_q = &priv->tx_queue[chan];

                stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
                                    tx_q->dma_tx_phy, chan);

                tx_q->tx_tail_addr = tx_q->dma_tx_phy;
                stmmac_set_tx_tail_ptr(priv, priv->ioaddr,
                                       tx_q->tx_tail_addr, chan);
        }

        return ret;
}

static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue)
{
        struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];

        hrtimer_start(&tx_q->txtimer,
                      STMMAC_COAL_TIMER(priv->tx_coal_timer[queue]),
                      HRTIMER_MODE_REL);
}

/**
 * stmmac_tx_timer - mitigation sw timer for tx.
 * @t: data pointer
 * Description:
 * This is the timer handler to directly invoke the stmmac_tx_clean.
 */
static enum hrtimer_restart stmmac_tx_timer(struct hrtimer *t)
{
        struct stmmac_tx_queue *tx_q = container_of(t, struct stmmac_tx_queue, txtimer);
        struct stmmac_priv *priv = tx_q->priv_data;
        struct stmmac_channel *ch;
        struct napi_struct *napi;

        ch = &priv->channel[tx_q->queue_index];
        napi = tx_q->xsk_pool ? &ch->rxtx_napi : &ch->tx_napi;

        if (likely(napi_schedule_prep(napi))) {
                unsigned long flags;

                spin_lock_irqsave(&ch->lock, flags);
                stmmac_disable_dma_irq(priv, priv->ioaddr, ch->index, 0, 1);
                spin_unlock_irqrestore(&ch->lock, flags);
                __napi_schedule(napi);
        }

        return HRTIMER_NORESTART;
}

/**
 * stmmac_init_coalesce - init mitigation options.
 * @priv: driver private structure
 * Description:
 * This inits the coalesce parameters: i.e. timer rate,
 * timer handler and default threshold used for enabling the