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8#include <linux/module.h>
9#include <linux/firmware.h>
10#include <linux/of.h>
11#include <linux/property.h>
12#include <linux/dmi.h>
13#include <linux/ctype.h>
14#include <linux/pm_qos.h>
15#include <linux/nvmem-consumer.h>
16#include <asm/byteorder.h>
17
18#include "core.h"
19#include "mac.h"
20#include "htc.h"
21#include "hif.h"
22#include "wmi.h"
23#include "bmi.h"
24#include "debug.h"
25#include "htt.h"
26#include "testmode.h"
27#include "wmi-ops.h"
28#include "coredump.h"
29
30unsigned int ath10k_debug_mask;
31EXPORT_SYMBOL(ath10k_debug_mask);
32
33static unsigned int ath10k_cryptmode_param;
34static bool uart_print;
35static bool skip_otp;
36static bool rawmode;
37static bool fw_diag_log;
38
39unsigned long ath10k_coredump_mask = BIT(ATH10K_FW_CRASH_DUMP_REGISTERS) |
40 BIT(ATH10K_FW_CRASH_DUMP_CE_DATA);
41
42
43module_param_named(debug_mask, ath10k_debug_mask, uint, 0644);
44module_param_named(cryptmode, ath10k_cryptmode_param, uint, 0644);
45module_param(uart_print, bool, 0644);
46module_param(skip_otp, bool, 0644);
47module_param(rawmode, bool, 0644);
48module_param(fw_diag_log, bool, 0644);
49module_param_named(coredump_mask, ath10k_coredump_mask, ulong, 0444);
50
51MODULE_PARM_DESC(debug_mask, "Debugging mask");
52MODULE_PARM_DESC(uart_print, "Uart target debugging");
53MODULE_PARM_DESC(skip_otp, "Skip otp failure for calibration in testmode");
54MODULE_PARM_DESC(cryptmode, "Crypto mode: 0-hardware, 1-software");
55MODULE_PARM_DESC(rawmode, "Use raw 802.11 frame datapath");
56MODULE_PARM_DESC(coredump_mask, "Bitfield of what to include in firmware crash file");
57MODULE_PARM_DESC(fw_diag_log, "Diag based fw log debugging");
58
59static const struct ath10k_hw_params ath10k_hw_params_list[] = {
60 {
61 .id = QCA988X_HW_2_0_VERSION,
62 .dev_id = QCA988X_2_0_DEVICE_ID,
63 .bus = ATH10K_BUS_PCI,
64 .name = "qca988x hw2.0",
65 .patch_load_addr = QCA988X_HW_2_0_PATCH_LOAD_ADDR,
66 .uart_pin = 7,
67 .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_ALL,
68 .otp_exe_param = 0,
69 .channel_counters_freq_hz = 88000,
70 .max_probe_resp_desc_thres = 0,
71 .cal_data_len = 2116,
72 .fw = {
73 .dir = QCA988X_HW_2_0_FW_DIR,
74 .board = QCA988X_HW_2_0_BOARD_DATA_FILE,
75 .board_size = QCA988X_BOARD_DATA_SZ,
76 .board_ext_size = QCA988X_BOARD_EXT_DATA_SZ,
77 },
78 .hw_ops = &qca988x_ops,
79 .decap_align_bytes = 4,
80 .spectral_bin_discard = 0,
81 .spectral_bin_offset = 0,
82 .vht160_mcs_rx_highest = 0,
83 .vht160_mcs_tx_highest = 0,
84 .n_cipher_suites = 8,
85 .ast_skid_limit = 0x10,
86 .num_wds_entries = 0x20,
87 .target_64bit = false,
88 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
89 .shadow_reg_support = false,
90 .rri_on_ddr = false,
91 .hw_filter_reset_required = true,
92 .fw_diag_ce_download = false,
93 .credit_size_workaround = false,
94 .tx_stats_over_pktlog = true,
95 .dynamic_sar_support = false,
96 },
97 {
98 .id = QCA988X_HW_2_0_VERSION,
99 .dev_id = QCA988X_2_0_DEVICE_ID_UBNT,
100 .name = "qca988x hw2.0 ubiquiti",
101 .patch_load_addr = QCA988X_HW_2_0_PATCH_LOAD_ADDR,
102 .uart_pin = 7,
103 .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_ALL,
104 .otp_exe_param = 0,
105 .channel_counters_freq_hz = 88000,
106 .max_probe_resp_desc_thres = 0,
107 .cal_data_len = 2116,
108 .fw = {
109 .dir = QCA988X_HW_2_0_FW_DIR,
110 .board = QCA988X_HW_2_0_BOARD_DATA_FILE,
111 .board_size = QCA988X_BOARD_DATA_SZ,
112 .board_ext_size = QCA988X_BOARD_EXT_DATA_SZ,
113 },
114 .hw_ops = &qca988x_ops,
115 .decap_align_bytes = 4,
116 .spectral_bin_discard = 0,
117 .spectral_bin_offset = 0,
118 .vht160_mcs_rx_highest = 0,
119 .vht160_mcs_tx_highest = 0,
120 .n_cipher_suites = 8,
121 .ast_skid_limit = 0x10,
122 .num_wds_entries = 0x20,
123 .target_64bit = false,
124 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
125 .shadow_reg_support = false,
126 .rri_on_ddr = false,
127 .hw_filter_reset_required = true,
128 .fw_diag_ce_download = false,
129 .credit_size_workaround = false,
130 .tx_stats_over_pktlog = true,
131 .dynamic_sar_support = false,
132 },
133 {
134 .id = QCA9887_HW_1_0_VERSION,
135 .dev_id = QCA9887_1_0_DEVICE_ID,
136 .bus = ATH10K_BUS_PCI,
137 .name = "qca9887 hw1.0",
138 .patch_load_addr = QCA9887_HW_1_0_PATCH_LOAD_ADDR,
139 .uart_pin = 7,
140 .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_ALL,
141 .otp_exe_param = 0,
142 .channel_counters_freq_hz = 88000,
143 .max_probe_resp_desc_thres = 0,
144 .cal_data_len = 2116,
145 .fw = {
146 .dir = QCA9887_HW_1_0_FW_DIR,
147 .board = QCA9887_HW_1_0_BOARD_DATA_FILE,
148 .board_size = QCA9887_BOARD_DATA_SZ,
149 .board_ext_size = QCA9887_BOARD_EXT_DATA_SZ,
150 },
151 .hw_ops = &qca988x_ops,
152 .decap_align_bytes = 4,
153 .spectral_bin_discard = 0,
154 .spectral_bin_offset = 0,
155 .vht160_mcs_rx_highest = 0,
156 .vht160_mcs_tx_highest = 0,
157 .n_cipher_suites = 8,
158 .ast_skid_limit = 0x10,
159 .num_wds_entries = 0x20,
160 .target_64bit = false,
161 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
162 .shadow_reg_support = false,
163 .rri_on_ddr = false,
164 .hw_filter_reset_required = true,
165 .fw_diag_ce_download = false,
166 .credit_size_workaround = false,
167 .tx_stats_over_pktlog = false,
168 .dynamic_sar_support = false,
169 },
170 {
171 .id = QCA6174_HW_3_2_VERSION,
172 .dev_id = QCA6174_3_2_DEVICE_ID,
173 .bus = ATH10K_BUS_SDIO,
174 .name = "qca6174 hw3.2 sdio",
175 .patch_load_addr = QCA6174_HW_3_0_PATCH_LOAD_ADDR,
176 .uart_pin = 19,
177 .otp_exe_param = 0,
178 .channel_counters_freq_hz = 88000,
179 .max_probe_resp_desc_thres = 0,
180 .cal_data_len = 0,
181 .fw = {
182 .dir = QCA6174_HW_3_0_FW_DIR,
183 .board = QCA6174_HW_3_0_BOARD_DATA_FILE,
184 .board_size = QCA6174_BOARD_DATA_SZ,
185 .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ,
186 },
187 .hw_ops = &qca6174_sdio_ops,
188 .hw_clk = qca6174_clk,
189 .target_cpu_freq = 176000000,
190 .decap_align_bytes = 4,
191 .n_cipher_suites = 8,
192 .num_peers = 10,
193 .ast_skid_limit = 0x10,
194 .num_wds_entries = 0x20,
195 .uart_pin_workaround = true,
196 .tx_stats_over_pktlog = false,
197 .credit_size_workaround = false,
198 .bmi_large_size_download = true,
199 .supports_peer_stats_info = true,
200 .dynamic_sar_support = true,
201 },
202 {
203 .id = QCA6174_HW_2_1_VERSION,
204 .dev_id = QCA6164_2_1_DEVICE_ID,
205 .bus = ATH10K_BUS_PCI,
206 .name = "qca6164 hw2.1",
207 .patch_load_addr = QCA6174_HW_2_1_PATCH_LOAD_ADDR,
208 .uart_pin = 6,
209 .otp_exe_param = 0,
210 .channel_counters_freq_hz = 88000,
211 .max_probe_resp_desc_thres = 0,
212 .cal_data_len = 8124,
213 .fw = {
214 .dir = QCA6174_HW_2_1_FW_DIR,
215 .board = QCA6174_HW_2_1_BOARD_DATA_FILE,
216 .board_size = QCA6174_BOARD_DATA_SZ,
217 .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ,
218 },
219 .hw_ops = &qca988x_ops,
220 .decap_align_bytes = 4,
221 .spectral_bin_discard = 0,
222 .spectral_bin_offset = 0,
223 .vht160_mcs_rx_highest = 0,
224 .vht160_mcs_tx_highest = 0,
225 .n_cipher_suites = 8,
226 .ast_skid_limit = 0x10,
227 .num_wds_entries = 0x20,
228 .target_64bit = false,
229 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
230 .shadow_reg_support = false,
231 .rri_on_ddr = false,
232 .hw_filter_reset_required = true,
233 .fw_diag_ce_download = false,
234 .credit_size_workaround = false,
235 .tx_stats_over_pktlog = false,
236 .dynamic_sar_support = false,
237 },
238 {
239 .id = QCA6174_HW_2_1_VERSION,
240 .dev_id = QCA6174_2_1_DEVICE_ID,
241 .bus = ATH10K_BUS_PCI,
242 .name = "qca6174 hw2.1",
243 .patch_load_addr = QCA6174_HW_2_1_PATCH_LOAD_ADDR,
244 .uart_pin = 6,
245 .otp_exe_param = 0,
246 .channel_counters_freq_hz = 88000,
247 .max_probe_resp_desc_thres = 0,
248 .cal_data_len = 8124,
249 .fw = {
250 .dir = QCA6174_HW_2_1_FW_DIR,
251 .board = QCA6174_HW_2_1_BOARD_DATA_FILE,
252 .board_size = QCA6174_BOARD_DATA_SZ,
253 .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ,
254 },
255 .hw_ops = &qca988x_ops,
256 .decap_align_bytes = 4,
257 .spectral_bin_discard = 0,
258 .spectral_bin_offset = 0,
259 .vht160_mcs_rx_highest = 0,
260 .vht160_mcs_tx_highest = 0,
261 .n_cipher_suites = 8,
262 .ast_skid_limit = 0x10,
263 .num_wds_entries = 0x20,
264 .target_64bit = false,
265 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
266 .shadow_reg_support = false,
267 .rri_on_ddr = false,
268 .hw_filter_reset_required = true,
269 .fw_diag_ce_download = false,
270 .credit_size_workaround = false,
271 .tx_stats_over_pktlog = false,
272 .dynamic_sar_support = false,
273 },
274 {
275 .id = QCA6174_HW_3_0_VERSION,
276 .dev_id = QCA6174_2_1_DEVICE_ID,
277 .bus = ATH10K_BUS_PCI,
278 .name = "qca6174 hw3.0",
279 .patch_load_addr = QCA6174_HW_3_0_PATCH_LOAD_ADDR,
280 .uart_pin = 6,
281 .otp_exe_param = 0,
282 .channel_counters_freq_hz = 88000,
283 .max_probe_resp_desc_thres = 0,
284 .cal_data_len = 8124,
285 .fw = {
286 .dir = QCA6174_HW_3_0_FW_DIR,
287 .board = QCA6174_HW_3_0_BOARD_DATA_FILE,
288 .board_size = QCA6174_BOARD_DATA_SZ,
289 .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ,
290 },
291 .hw_ops = &qca988x_ops,
292 .decap_align_bytes = 4,
293 .spectral_bin_discard = 0,
294 .spectral_bin_offset = 0,
295 .vht160_mcs_rx_highest = 0,
296 .vht160_mcs_tx_highest = 0,
297 .n_cipher_suites = 8,
298 .ast_skid_limit = 0x10,
299 .num_wds_entries = 0x20,
300 .target_64bit = false,
301 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
302 .shadow_reg_support = false,
303 .rri_on_ddr = false,
304 .hw_filter_reset_required = true,
305 .fw_diag_ce_download = false,
306 .credit_size_workaround = false,
307 .tx_stats_over_pktlog = false,
308 .dynamic_sar_support = false,
309 },
310 {
311 .id = QCA6174_HW_3_2_VERSION,
312 .dev_id = QCA6174_2_1_DEVICE_ID,
313 .bus = ATH10K_BUS_PCI,
314 .name = "qca6174 hw3.2",
315 .patch_load_addr = QCA6174_HW_3_0_PATCH_LOAD_ADDR,
316 .uart_pin = 6,
317 .otp_exe_param = 0,
318 .channel_counters_freq_hz = 88000,
319 .max_probe_resp_desc_thres = 0,
320 .cal_data_len = 8124,
321 .fw = {
322
323 .dir = QCA6174_HW_3_0_FW_DIR,
324 .board = QCA6174_HW_3_0_BOARD_DATA_FILE,
325 .board_size = QCA6174_BOARD_DATA_SZ,
326 .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ,
327 },
328 .hw_ops = &qca6174_ops,
329 .hw_clk = qca6174_clk,
330 .target_cpu_freq = 176000000,
331 .decap_align_bytes = 4,
332 .spectral_bin_discard = 0,
333 .spectral_bin_offset = 0,
334 .vht160_mcs_rx_highest = 0,
335 .vht160_mcs_tx_highest = 0,
336 .n_cipher_suites = 8,
337 .ast_skid_limit = 0x10,
338 .num_wds_entries = 0x20,
339 .target_64bit = false,
340 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
341 .shadow_reg_support = false,
342 .rri_on_ddr = false,
343 .hw_filter_reset_required = true,
344 .fw_diag_ce_download = true,
345 .credit_size_workaround = false,
346 .tx_stats_over_pktlog = false,
347 .supports_peer_stats_info = true,
348 .dynamic_sar_support = true,
349 },
350 {
351 .id = QCA99X0_HW_2_0_DEV_VERSION,
352 .dev_id = QCA99X0_2_0_DEVICE_ID,
353 .bus = ATH10K_BUS_PCI,
354 .name = "qca99x0 hw2.0",
355 .patch_load_addr = QCA99X0_HW_2_0_PATCH_LOAD_ADDR,
356 .uart_pin = 7,
357 .otp_exe_param = 0x00000700,
358 .continuous_frag_desc = true,
359 .cck_rate_map_rev2 = true,
360 .channel_counters_freq_hz = 150000,
361 .max_probe_resp_desc_thres = 24,
362 .tx_chain_mask = 0xf,
363 .rx_chain_mask = 0xf,
364 .max_spatial_stream = 4,
365 .cal_data_len = 12064,
366 .fw = {
367 .dir = QCA99X0_HW_2_0_FW_DIR,
368 .board = QCA99X0_HW_2_0_BOARD_DATA_FILE,
369 .board_size = QCA99X0_BOARD_DATA_SZ,
370 .board_ext_size = QCA99X0_BOARD_EXT_DATA_SZ,
371 },
372 .sw_decrypt_mcast_mgmt = true,
373 .hw_ops = &qca99x0_ops,
374 .decap_align_bytes = 1,
375 .spectral_bin_discard = 4,
376 .spectral_bin_offset = 0,
377 .vht160_mcs_rx_highest = 0,
378 .vht160_mcs_tx_highest = 0,
379 .n_cipher_suites = 11,
380 .ast_skid_limit = 0x10,
381 .num_wds_entries = 0x20,
382 .target_64bit = false,
383 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
384 .shadow_reg_support = false,
385 .rri_on_ddr = false,
386 .hw_filter_reset_required = true,
387 .fw_diag_ce_download = false,
388 .credit_size_workaround = false,
389 .tx_stats_over_pktlog = false,
390 .dynamic_sar_support = false,
391 },
392 {
393 .id = QCA9984_HW_1_0_DEV_VERSION,
394 .dev_id = QCA9984_1_0_DEVICE_ID,
395 .bus = ATH10K_BUS_PCI,
396 .name = "qca9984/qca9994 hw1.0",
397 .patch_load_addr = QCA9984_HW_1_0_PATCH_LOAD_ADDR,
398 .uart_pin = 7,
399 .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_EACH,
400 .otp_exe_param = 0x00000700,
401 .continuous_frag_desc = true,
402 .cck_rate_map_rev2 = true,
403 .channel_counters_freq_hz = 150000,
404 .max_probe_resp_desc_thres = 24,
405 .tx_chain_mask = 0xf,
406 .rx_chain_mask = 0xf,
407 .max_spatial_stream = 4,
408 .cal_data_len = 12064,
409 .fw = {
410 .dir = QCA9984_HW_1_0_FW_DIR,
411 .board = QCA9984_HW_1_0_BOARD_DATA_FILE,
412 .eboard = QCA9984_HW_1_0_EBOARD_DATA_FILE,
413 .board_size = QCA99X0_BOARD_DATA_SZ,
414 .board_ext_size = QCA99X0_BOARD_EXT_DATA_SZ,
415 .ext_board_size = QCA99X0_EXT_BOARD_DATA_SZ,
416 },
417 .sw_decrypt_mcast_mgmt = true,
418 .hw_ops = &qca99x0_ops,
419 .decap_align_bytes = 1,
420 .spectral_bin_discard = 12,
421 .spectral_bin_offset = 8,
422
423
424
425
426 .vht160_mcs_rx_highest = 1560,
427 .vht160_mcs_tx_highest = 1560,
428 .n_cipher_suites = 11,
429 .ast_skid_limit = 0x10,
430 .num_wds_entries = 0x20,
431 .target_64bit = false,
432 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
433 .shadow_reg_support = false,
434 .rri_on_ddr = false,
435 .hw_filter_reset_required = true,
436 .fw_diag_ce_download = false,
437 .credit_size_workaround = false,
438 .tx_stats_over_pktlog = false,
439 .dynamic_sar_support = false,
440 },
441 {
442 .id = QCA9888_HW_2_0_DEV_VERSION,
443 .dev_id = QCA9888_2_0_DEVICE_ID,
444 .bus = ATH10K_BUS_PCI,
445 .name = "qca9888 hw2.0",
446 .patch_load_addr = QCA9888_HW_2_0_PATCH_LOAD_ADDR,
447 .uart_pin = 7,
448 .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_EACH,
449 .otp_exe_param = 0x00000700,
450 .continuous_frag_desc = true,
451 .channel_counters_freq_hz = 150000,
452 .max_probe_resp_desc_thres = 24,
453 .tx_chain_mask = 3,
454 .rx_chain_mask = 3,
455 .max_spatial_stream = 2,
456 .cal_data_len = 12064,
457 .fw = {
458 .dir = QCA9888_HW_2_0_FW_DIR,
459 .board = QCA9888_HW_2_0_BOARD_DATA_FILE,
460 .board_size = QCA99X0_BOARD_DATA_SZ,
461 .board_ext_size = QCA99X0_BOARD_EXT_DATA_SZ,
462 },
463 .sw_decrypt_mcast_mgmt = true,
464 .hw_ops = &qca99x0_ops,
465 .decap_align_bytes = 1,
466 .spectral_bin_discard = 12,
467 .spectral_bin_offset = 8,
468
469
470
471
472 .vht160_mcs_rx_highest = 780,
473 .vht160_mcs_tx_highest = 780,
474 .n_cipher_suites = 11,
475 .ast_skid_limit = 0x10,
476 .num_wds_entries = 0x20,
477 .target_64bit = false,
478 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
479 .shadow_reg_support = false,
480 .rri_on_ddr = false,
481 .hw_filter_reset_required = true,
482 .fw_diag_ce_download = false,
483 .credit_size_workaround = false,
484 .tx_stats_over_pktlog = false,
485 .dynamic_sar_support = false,
486 },
487 {
488 .id = QCA9377_HW_1_0_DEV_VERSION,
489 .dev_id = QCA9377_1_0_DEVICE_ID,
490 .bus = ATH10K_BUS_PCI,
491 .name = "qca9377 hw1.0",
492 .patch_load_addr = QCA9377_HW_1_0_PATCH_LOAD_ADDR,
493 .uart_pin = 6,
494 .otp_exe_param = 0,
495 .channel_counters_freq_hz = 88000,
496 .max_probe_resp_desc_thres = 0,
497 .cal_data_len = 8124,
498 .fw = {
499 .dir = QCA9377_HW_1_0_FW_DIR,
500 .board = QCA9377_HW_1_0_BOARD_DATA_FILE,
501 .board_size = QCA9377_BOARD_DATA_SZ,
502 .board_ext_size = QCA9377_BOARD_EXT_DATA_SZ,
503 },
504 .hw_ops = &qca988x_ops,
505 .decap_align_bytes = 4,
506 .spectral_bin_discard = 0,
507 .spectral_bin_offset = 0,
508 .vht160_mcs_rx_highest = 0,
509 .vht160_mcs_tx_highest = 0,
510 .n_cipher_suites = 8,
511 .ast_skid_limit = 0x10,
512 .num_wds_entries = 0x20,
513 .target_64bit = false,
514 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
515 .shadow_reg_support = false,
516 .rri_on_ddr = false,
517 .hw_filter_reset_required = true,
518 .fw_diag_ce_download = false,
519 .credit_size_workaround = false,
520 .tx_stats_over_pktlog = false,
521 .dynamic_sar_support = false,
522 },
523 {
524 .id = QCA9377_HW_1_1_DEV_VERSION,
525 .dev_id = QCA9377_1_0_DEVICE_ID,
526 .bus = ATH10K_BUS_PCI,
527 .name = "qca9377 hw1.1",
528 .patch_load_addr = QCA9377_HW_1_0_PATCH_LOAD_ADDR,
529 .uart_pin = 6,
530 .otp_exe_param = 0,
531 .channel_counters_freq_hz = 88000,
532 .max_probe_resp_desc_thres = 0,
533 .cal_data_len = 8124,
534 .fw = {
535 .dir = QCA9377_HW_1_0_FW_DIR,
536 .board = QCA9377_HW_1_0_BOARD_DATA_FILE,
537 .board_size = QCA9377_BOARD_DATA_SZ,
538 .board_ext_size = QCA9377_BOARD_EXT_DATA_SZ,
539 },
540 .hw_ops = &qca6174_ops,
541 .hw_clk = qca6174_clk,
542 .target_cpu_freq = 176000000,
543 .decap_align_bytes = 4,
544 .spectral_bin_discard = 0,
545 .spectral_bin_offset = 0,
546 .vht160_mcs_rx_highest = 0,
547 .vht160_mcs_tx_highest = 0,
548 .n_cipher_suites = 8,
549 .ast_skid_limit = 0x10,
550 .num_wds_entries = 0x20,
551 .target_64bit = false,
552 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
553 .shadow_reg_support = false,
554 .rri_on_ddr = false,
555 .hw_filter_reset_required = true,
556 .fw_diag_ce_download = true,
557 .credit_size_workaround = false,
558 .tx_stats_over_pktlog = false,
559 .dynamic_sar_support = false,
560 },
561 {
562 .id = QCA9377_HW_1_1_DEV_VERSION,
563 .dev_id = QCA9377_1_0_DEVICE_ID,
564 .bus = ATH10K_BUS_SDIO,
565 .name = "qca9377 hw1.1 sdio",
566 .patch_load_addr = QCA9377_HW_1_0_PATCH_LOAD_ADDR,
567 .uart_pin = 19,
568 .otp_exe_param = 0,
569 .channel_counters_freq_hz = 88000,
570 .max_probe_resp_desc_thres = 0,
571 .cal_data_len = 8124,
572 .fw = {
573 .dir = QCA9377_HW_1_0_FW_DIR,
574 .board = QCA9377_HW_1_0_BOARD_DATA_FILE,
575 .board_size = QCA9377_BOARD_DATA_SZ,
576 .board_ext_size = QCA9377_BOARD_EXT_DATA_SZ,
577 },
578 .hw_ops = &qca6174_ops,
579 .hw_clk = qca6174_clk,
580 .target_cpu_freq = 176000000,
581 .decap_align_bytes = 4,
582 .n_cipher_suites = 8,
583 .num_peers = TARGET_QCA9377_HL_NUM_PEERS,
584 .ast_skid_limit = 0x10,
585 .num_wds_entries = 0x20,
586 .uart_pin_workaround = true,
587 .credit_size_workaround = true,
588 .dynamic_sar_support = false,
589 },
590 {
591 .id = QCA4019_HW_1_0_DEV_VERSION,
592 .dev_id = 0,
593 .bus = ATH10K_BUS_AHB,
594 .name = "qca4019 hw1.0",
595 .patch_load_addr = QCA4019_HW_1_0_PATCH_LOAD_ADDR,
596 .uart_pin = 7,
597 .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_EACH,
598 .otp_exe_param = 0x0010000,
599 .continuous_frag_desc = true,
600 .cck_rate_map_rev2 = true,
601 .channel_counters_freq_hz = 125000,
602 .max_probe_resp_desc_thres = 24,
603 .tx_chain_mask = 0x3,
604 .rx_chain_mask = 0x3,
605 .max_spatial_stream = 2,
606 .cal_data_len = 12064,
607 .fw = {
608 .dir = QCA4019_HW_1_0_FW_DIR,
609 .board = QCA4019_HW_1_0_BOARD_DATA_FILE,
610 .board_size = QCA4019_BOARD_DATA_SZ,
611 .board_ext_size = QCA4019_BOARD_EXT_DATA_SZ,
612 },
613 .sw_decrypt_mcast_mgmt = true,
614 .hw_ops = &qca99x0_ops,
615 .decap_align_bytes = 1,
616 .spectral_bin_discard = 4,
617 .spectral_bin_offset = 0,
618 .vht160_mcs_rx_highest = 0,
619 .vht160_mcs_tx_highest = 0,
620 .n_cipher_suites = 11,
621 .ast_skid_limit = 0x10,
622 .num_wds_entries = 0x20,
623 .target_64bit = false,
624 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
625 .shadow_reg_support = false,
626 .rri_on_ddr = false,
627 .hw_filter_reset_required = true,
628 .fw_diag_ce_download = false,
629 .credit_size_workaround = false,
630 .tx_stats_over_pktlog = false,
631 .dynamic_sar_support = false,
632 },
633 {
634 .id = WCN3990_HW_1_0_DEV_VERSION,
635 .dev_id = 0,
636 .bus = ATH10K_BUS_SNOC,
637 .name = "wcn3990 hw1.0",
638 .continuous_frag_desc = true,
639 .tx_chain_mask = 0x7,
640 .rx_chain_mask = 0x7,
641 .max_spatial_stream = 4,
642 .fw = {
643 .dir = WCN3990_HW_1_0_FW_DIR,
644 },
645 .sw_decrypt_mcast_mgmt = true,
646 .hw_ops = &wcn3990_ops,
647 .decap_align_bytes = 1,
648 .num_peers = TARGET_HL_TLV_NUM_PEERS,
649 .n_cipher_suites = 11,
650 .ast_skid_limit = TARGET_HL_TLV_AST_SKID_LIMIT,
651 .num_wds_entries = TARGET_HL_TLV_NUM_WDS_ENTRIES,
652 .target_64bit = true,
653 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL_DUAL_MAC,
654 .shadow_reg_support = true,
655 .rri_on_ddr = true,
656 .hw_filter_reset_required = false,
657 .fw_diag_ce_download = false,
658 .credit_size_workaround = false,
659 .tx_stats_over_pktlog = false,
660 .dynamic_sar_support = true,
661 },
662};
663
664static const char *const ath10k_core_fw_feature_str[] = {
665 [ATH10K_FW_FEATURE_EXT_WMI_MGMT_RX] = "wmi-mgmt-rx",
666 [ATH10K_FW_FEATURE_WMI_10X] = "wmi-10.x",
667 [ATH10K_FW_FEATURE_HAS_WMI_MGMT_TX] = "has-wmi-mgmt-tx",
668 [ATH10K_FW_FEATURE_NO_P2P] = "no-p2p",
669 [ATH10K_FW_FEATURE_WMI_10_2] = "wmi-10.2",
670 [ATH10K_FW_FEATURE_MULTI_VIF_PS_SUPPORT] = "multi-vif-ps",
671 [ATH10K_FW_FEATURE_WOWLAN_SUPPORT] = "wowlan",
672 [ATH10K_FW_FEATURE_IGNORE_OTP_RESULT] = "ignore-otp",
673 [ATH10K_FW_FEATURE_NO_NWIFI_DECAP_4ADDR_PADDING] = "no-4addr-pad",
674 [ATH10K_FW_FEATURE_SUPPORTS_SKIP_CLOCK_INIT] = "skip-clock-init",
675 [ATH10K_FW_FEATURE_RAW_MODE_SUPPORT] = "raw-mode",
676 [ATH10K_FW_FEATURE_SUPPORTS_ADAPTIVE_CCA] = "adaptive-cca",
677 [ATH10K_FW_FEATURE_MFP_SUPPORT] = "mfp",
678 [ATH10K_FW_FEATURE_PEER_FLOW_CONTROL] = "peer-flow-ctrl",
679 [ATH10K_FW_FEATURE_BTCOEX_PARAM] = "btcoex-param",
680 [ATH10K_FW_FEATURE_SKIP_NULL_FUNC_WAR] = "skip-null-func-war",
681 [ATH10K_FW_FEATURE_ALLOWS_MESH_BCAST] = "allows-mesh-bcast",
682 [ATH10K_FW_FEATURE_NO_PS] = "no-ps",
683 [ATH10K_FW_FEATURE_MGMT_TX_BY_REF] = "mgmt-tx-by-reference",
684 [ATH10K_FW_FEATURE_NON_BMI] = "non-bmi",
685 [ATH10K_FW_FEATURE_SINGLE_CHAN_INFO_PER_CHANNEL] = "single-chan-info-per-channel",
686 [ATH10K_FW_FEATURE_PEER_FIXED_RATE] = "peer-fixed-rate",
687 [ATH10K_FW_FEATURE_IRAM_RECOVERY] = "iram-recovery",
688};
689
690static unsigned int ath10k_core_get_fw_feature_str(char *buf,
691 size_t buf_len,
692 enum ath10k_fw_features feat)
693{
694
695 BUILD_BUG_ON(ARRAY_SIZE(ath10k_core_fw_feature_str) !=
696 ATH10K_FW_FEATURE_COUNT);
697
698 if (feat >= ARRAY_SIZE(ath10k_core_fw_feature_str) ||
699 WARN_ON(!ath10k_core_fw_feature_str[feat])) {
700 return scnprintf(buf, buf_len, "bit%d", feat);
701 }
702
703 return scnprintf(buf, buf_len, "%s", ath10k_core_fw_feature_str[feat]);
704}
705
706void ath10k_core_get_fw_features_str(struct ath10k *ar,
707 char *buf,
708 size_t buf_len)
709{
710 size_t len = 0;
711 int i;
712
713 for (i = 0; i < ATH10K_FW_FEATURE_COUNT; i++) {
714 if (test_bit(i, ar->normal_mode_fw.fw_file.fw_features)) {
715 if (len > 0)
716 len += scnprintf(buf + len, buf_len - len, ",");
717
718 len += ath10k_core_get_fw_feature_str(buf + len,
719 buf_len - len,
720 i);
721 }
722 }
723}
724
725static void ath10k_send_suspend_complete(struct ath10k *ar)
726{
727 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot suspend complete\n");
728
729 complete(&ar->target_suspend);
730}
731
732static int ath10k_init_sdio(struct ath10k *ar, enum ath10k_firmware_mode mode)
733{
734 bool mtu_workaround = ar->hw_params.credit_size_workaround;
735 int ret;
736 u32 param = 0;
737
738 ret = ath10k_bmi_write32(ar, hi_mbox_io_block_sz, 256);
739 if (ret)
740 return ret;
741
742 ret = ath10k_bmi_write32(ar, hi_mbox_isr_yield_limit, 99);
743 if (ret)
744 return ret;
745
746 ret = ath10k_bmi_read32(ar, hi_acs_flags, ¶m);
747 if (ret)
748 return ret;
749
750 param |= HI_ACS_FLAGS_SDIO_REDUCE_TX_COMPL_SET;
751
752 if (mode == ATH10K_FIRMWARE_MODE_NORMAL && !mtu_workaround)
753 param |= HI_ACS_FLAGS_ALT_DATA_CREDIT_SIZE;
754 else
755 param &= ~HI_ACS_FLAGS_ALT_DATA_CREDIT_SIZE;
756
757 if (mode == ATH10K_FIRMWARE_MODE_UTF)
758 param &= ~HI_ACS_FLAGS_SDIO_SWAP_MAILBOX_SET;
759 else
760 param |= HI_ACS_FLAGS_SDIO_SWAP_MAILBOX_SET;
761
762 ret = ath10k_bmi_write32(ar, hi_acs_flags, param);
763 if (ret)
764 return ret;
765
766 ret = ath10k_bmi_read32(ar, hi_option_flag2, ¶m);
767 if (ret)
768 return ret;
769
770 param |= HI_OPTION_SDIO_CRASH_DUMP_ENHANCEMENT_HOST;
771
772 ret = ath10k_bmi_write32(ar, hi_option_flag2, param);
773 if (ret)
774 return ret;
775
776 return 0;
777}
778
779static int ath10k_init_configure_target(struct ath10k *ar)
780{
781 u32 param_host;
782 int ret;
783
784
785 ret = ath10k_bmi_write32(ar, hi_app_host_interest,
786 HTC_PROTOCOL_VERSION);
787 if (ret) {
788 ath10k_err(ar, "settings HTC version failed\n");
789 return ret;
790 }
791
792
793 ret = ath10k_bmi_read32(ar, hi_option_flag, ¶m_host);
794 if (ret) {
795 ath10k_err(ar, "setting firmware mode (1/2) failed\n");
796 return ret;
797 }
798
799
800
801 param_host |= (1 << HI_OPTION_NUM_DEV_SHIFT);
802
803
804 param_host |= (HI_OPTION_FW_MODE_AP << HI_OPTION_FW_MODE_SHIFT);
805
806 param_host |= (1 << HI_OPTION_MAC_ADDR_METHOD_SHIFT);
807
808 param_host |= (0 << HI_OPTION_FW_BRIDGE_SHIFT);
809
810 param_host |= (0 << HI_OPTION_FW_SUBMODE_SHIFT);
811
812 ret = ath10k_bmi_write32(ar, hi_option_flag, param_host);
813 if (ret) {
814 ath10k_err(ar, "setting firmware mode (2/2) failed\n");
815 return ret;
816 }
817
818
819 ret = ath10k_bmi_write32(ar, hi_be, 0);
820 if (ret) {
821 ath10k_err(ar, "setting host CPU BE mode failed\n");
822 return ret;
823 }
824
825
826 ret = ath10k_bmi_write32(ar, hi_fw_swap, 0);
827
828 if (ret) {
829 ath10k_err(ar, "setting FW data/desc swap flags failed\n");
830 return ret;
831 }
832
833
834
835
836
837 ret = ath10k_bmi_write32(ar, hi_hci_uart_pwr_mgmt_params_ext,
838 ar->dev_id);
839 if (ret) {
840 ath10k_err(ar, "failed to set pwr_mgmt_params: %d\n", ret);
841 return ret;
842 }
843
844 return 0;
845}
846
847static const struct firmware *ath10k_fetch_fw_file(struct ath10k *ar,
848 const char *dir,
849 const char *file)
850{
851 char filename[100];
852 const struct firmware *fw;
853 int ret;
854
855 if (file == NULL)
856 return ERR_PTR(-ENOENT);
857
858 if (dir == NULL)
859 dir = ".";
860
861 snprintf(filename, sizeof(filename), "%s/%s", dir, file);
862 ret = firmware_request_nowarn(&fw, filename, ar->dev);
863 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot fw request '%s': %d\n",
864 filename, ret);
865
866 if (ret)
867 return ERR_PTR(ret);
868
869 return fw;
870}
871
872static int ath10k_push_board_ext_data(struct ath10k *ar, const void *data,
873 size_t data_len)
874{
875 u32 board_data_size = ar->hw_params.fw.board_size;
876 u32 board_ext_data_size = ar->hw_params.fw.board_ext_size;
877 u32 board_ext_data_addr;
878 int ret;
879
880 ret = ath10k_bmi_read32(ar, hi_board_ext_data, &board_ext_data_addr);
881 if (ret) {
882 ath10k_err(ar, "could not read board ext data addr (%d)\n",
883 ret);
884 return ret;
885 }
886
887 ath10k_dbg(ar, ATH10K_DBG_BOOT,
888 "boot push board extended data addr 0x%x\n",
889 board_ext_data_addr);
890
891 if (board_ext_data_addr == 0)
892 return 0;
893
894 if (data_len != (board_data_size + board_ext_data_size)) {
895 ath10k_err(ar, "invalid board (ext) data sizes %zu != %d+%d\n",
896 data_len, board_data_size, board_ext_data_size);
897 return -EINVAL;
898 }
899
900 ret = ath10k_bmi_write_memory(ar, board_ext_data_addr,
901 data + board_data_size,
902 board_ext_data_size);
903 if (ret) {
904 ath10k_err(ar, "could not write board ext data (%d)\n", ret);
905 return ret;
906 }
907
908 ret = ath10k_bmi_write32(ar, hi_board_ext_data_config,
909 (board_ext_data_size << 16) | 1);
910 if (ret) {
911 ath10k_err(ar, "could not write board ext data bit (%d)\n",
912 ret);
913 return ret;
914 }
915
916 return 0;
917}
918
919static int ath10k_core_get_board_id_from_otp(struct ath10k *ar)
920{
921 u32 result, address;
922 u8 board_id, chip_id;
923 bool ext_bid_support;
924 int ret, bmi_board_id_param;
925
926 address = ar->hw_params.patch_load_addr;
927
928 if (!ar->normal_mode_fw.fw_file.otp_data ||
929 !ar->normal_mode_fw.fw_file.otp_len) {
930 ath10k_warn(ar,
931 "failed to retrieve board id because of invalid otp\n");
932 return -ENODATA;
933 }
934
935 if (ar->id.bmi_ids_valid) {
936 ath10k_dbg(ar, ATH10K_DBG_BOOT,
937 "boot already acquired valid otp board id,skip download, board_id %d chip_id %d\n",
938 ar->id.bmi_board_id, ar->id.bmi_chip_id);
939 goto skip_otp_download;
940 }
941
942 ath10k_dbg(ar, ATH10K_DBG_BOOT,
943 "boot upload otp to 0x%x len %zd for board id\n",
944 address, ar->normal_mode_fw.fw_file.otp_len);
945
946 ret = ath10k_bmi_fast_download(ar, address,
947 ar->normal_mode_fw.fw_file.otp_data,
948 ar->normal_mode_fw.fw_file.otp_len);
949 if (ret) {
950 ath10k_err(ar, "could not write otp for board id check: %d\n",
951 ret);
952 return ret;
953 }
954
955 if (ar->cal_mode == ATH10K_PRE_CAL_MODE_DT ||
956 ar->cal_mode == ATH10K_PRE_CAL_MODE_FILE ||
957 ar->cal_mode == ATH10K_PRE_CAL_MODE_NVMEM)
958 bmi_board_id_param = BMI_PARAM_GET_FLASH_BOARD_ID;
959 else
960 bmi_board_id_param = BMI_PARAM_GET_EEPROM_BOARD_ID;
961
962 ret = ath10k_bmi_execute(ar, address, bmi_board_id_param, &result);
963 if (ret) {
964 ath10k_err(ar, "could not execute otp for board id check: %d\n",
965 ret);
966 return ret;
967 }
968
969 board_id = MS(result, ATH10K_BMI_BOARD_ID_FROM_OTP);
970 chip_id = MS(result, ATH10K_BMI_CHIP_ID_FROM_OTP);
971 ext_bid_support = (result & ATH10K_BMI_EXT_BOARD_ID_SUPPORT);
972
973 ath10k_dbg(ar, ATH10K_DBG_BOOT,
974 "boot get otp board id result 0x%08x board_id %d chip_id %d ext_bid_support %d\n",
975 result, board_id, chip_id, ext_bid_support);
976
977 ar->id.ext_bid_supported = ext_bid_support;
978
979 if ((result & ATH10K_BMI_BOARD_ID_STATUS_MASK) != 0 ||
980 (board_id == 0)) {
981 ath10k_dbg(ar, ATH10K_DBG_BOOT,
982 "board id does not exist in otp, ignore it\n");
983 return -EOPNOTSUPP;
984 }
985
986 ar->id.bmi_ids_valid = true;
987 ar->id.bmi_board_id = board_id;
988 ar->id.bmi_chip_id = chip_id;
989
990skip_otp_download:
991
992 return 0;
993}
994
995static void ath10k_core_check_bdfext(const struct dmi_header *hdr, void *data)
996{
997 struct ath10k *ar = data;
998 const char *bdf_ext;
999 const char *magic = ATH10K_SMBIOS_BDF_EXT_MAGIC;
1000 u8 bdf_enabled;
1001 int i;
1002
1003 if (hdr->type != ATH10K_SMBIOS_BDF_EXT_TYPE)
1004 return;
1005
1006 if (hdr->length != ATH10K_SMBIOS_BDF_EXT_LENGTH) {
1007 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1008 "wrong smbios bdf ext type length (%d).\n",
1009 hdr->length);
1010 return;
1011 }
1012
1013 bdf_enabled = *((u8 *)hdr + ATH10K_SMBIOS_BDF_EXT_OFFSET);
1014 if (!bdf_enabled) {
1015 ath10k_dbg(ar, ATH10K_DBG_BOOT, "bdf variant name not found.\n");
1016 return;
1017 }
1018
1019
1020 bdf_ext = (char *)hdr + hdr->length;
1021
1022 if (memcmp(bdf_ext, magic, strlen(magic)) != 0) {
1023 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1024 "bdf variant magic does not match.\n");
1025 return;
1026 }
1027
1028 for (i = 0; i < strlen(bdf_ext); i++) {
1029 if (!isascii(bdf_ext[i]) || !isprint(bdf_ext[i])) {
1030 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1031 "bdf variant name contains non ascii chars.\n");
1032 return;
1033 }
1034 }
1035
1036
1037 if (strscpy(ar->id.bdf_ext, bdf_ext + strlen(magic),
1038 sizeof(ar->id.bdf_ext)) < 0) {
1039 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1040 "bdf variant string is longer than the buffer can accommodate (variant: %s)\n",
1041 bdf_ext);
1042 return;
1043 }
1044
1045 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1046 "found and validated bdf variant smbios_type 0x%x bdf %s\n",
1047 ATH10K_SMBIOS_BDF_EXT_TYPE, bdf_ext);
1048}
1049
1050static int ath10k_core_check_smbios(struct ath10k *ar)
1051{
1052 ar->id.bdf_ext[0] = '\0';
1053 dmi_walk(ath10k_core_check_bdfext, ar);
1054
1055 if (ar->id.bdf_ext[0] == '\0')
1056 return -ENODATA;
1057
1058 return 0;
1059}
1060
1061int ath10k_core_check_dt(struct ath10k *ar)
1062{
1063 struct device_node *node;
1064 const char *variant = NULL;
1065
1066 node = ar->dev->of_node;
1067 if (!node)
1068 return -ENOENT;
1069
1070 of_property_read_string(node, "qcom,ath10k-calibration-variant",
1071 &variant);
1072 if (!variant)
1073 return -ENODATA;
1074
1075 if (strscpy(ar->id.bdf_ext, variant, sizeof(ar->id.bdf_ext)) < 0)
1076 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1077 "bdf variant string is longer than the buffer can accommodate (variant: %s)\n",
1078 variant);
1079
1080 return 0;
1081}
1082EXPORT_SYMBOL(ath10k_core_check_dt);
1083
1084static int ath10k_download_fw(struct ath10k *ar)
1085{
1086 u32 address, data_len;
1087 const void *data;
1088 int ret;
1089 struct pm_qos_request latency_qos;
1090
1091 address = ar->hw_params.patch_load_addr;
1092
1093 data = ar->running_fw->fw_file.firmware_data;
1094 data_len = ar->running_fw->fw_file.firmware_len;
1095
1096 ret = ath10k_swap_code_seg_configure(ar, &ar->running_fw->fw_file);
1097 if (ret) {
1098 ath10k_err(ar, "failed to configure fw code swap: %d\n",
1099 ret);
1100 return ret;
1101 }
1102
1103 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1104 "boot uploading firmware image %pK len %d\n",
1105 data, data_len);
1106
1107
1108
1109
1110
1111 if (ar->hw_params.fw_diag_ce_download) {
1112 ret = ath10k_hw_diag_fast_download(ar, address,
1113 data, data_len);
1114 if (ret == 0)
1115
1116 return 0;
1117
1118 ath10k_warn(ar,
1119 "failed to upload firmware via diag ce, trying BMI: %d",
1120 ret);
1121 }
1122
1123 memset(&latency_qos, 0, sizeof(latency_qos));
1124 cpu_latency_qos_add_request(&latency_qos, 0);
1125
1126 ret = ath10k_bmi_fast_download(ar, address, data, data_len);
1127
1128 cpu_latency_qos_remove_request(&latency_qos);
1129
1130 return ret;
1131}
1132
1133void ath10k_core_free_board_files(struct ath10k *ar)
1134{
1135 if (!IS_ERR(ar->normal_mode_fw.board))
1136 release_firmware(ar->normal_mode_fw.board);
1137
1138 if (!IS_ERR(ar->normal_mode_fw.ext_board))
1139 release_firmware(ar->normal_mode_fw.ext_board);
1140
1141 ar->normal_mode_fw.board = NULL;
1142 ar->normal_mode_fw.board_data = NULL;
1143 ar->normal_mode_fw.board_len = 0;
1144 ar->normal_mode_fw.ext_board = NULL;
1145 ar->normal_mode_fw.ext_board_data = NULL;
1146 ar->normal_mode_fw.ext_board_len = 0;
1147}
1148EXPORT_SYMBOL(ath10k_core_free_board_files);
1149
1150static void ath10k_core_free_firmware_files(struct ath10k *ar)
1151{
1152 if (!IS_ERR(ar->normal_mode_fw.fw_file.firmware))
1153 release_firmware(ar->normal_mode_fw.fw_file.firmware);
1154
1155 if (!IS_ERR(ar->cal_file))
1156 release_firmware(ar->cal_file);
1157
1158 if (!IS_ERR(ar->pre_cal_file))
1159 release_firmware(ar->pre_cal_file);
1160
1161 ath10k_swap_code_seg_release(ar, &ar->normal_mode_fw.fw_file);
1162
1163 ar->normal_mode_fw.fw_file.otp_data = NULL;
1164 ar->normal_mode_fw.fw_file.otp_len = 0;
1165
1166 ar->normal_mode_fw.fw_file.firmware = NULL;
1167 ar->normal_mode_fw.fw_file.firmware_data = NULL;
1168 ar->normal_mode_fw.fw_file.firmware_len = 0;
1169
1170 ar->cal_file = NULL;
1171 ar->pre_cal_file = NULL;
1172}
1173
1174static int ath10k_fetch_cal_file(struct ath10k *ar)
1175{
1176 char filename[100];
1177
1178
1179 scnprintf(filename, sizeof(filename), "pre-cal-%s-%s.bin",
1180 ath10k_bus_str(ar->hif.bus), dev_name(ar->dev));
1181
1182 ar->pre_cal_file = ath10k_fetch_fw_file(ar, ATH10K_FW_DIR, filename);
1183 if (!IS_ERR(ar->pre_cal_file))
1184 goto success;
1185
1186
1187 scnprintf(filename, sizeof(filename), "cal-%s-%s.bin",
1188 ath10k_bus_str(ar->hif.bus), dev_name(ar->dev));
1189
1190 ar->cal_file = ath10k_fetch_fw_file(ar, ATH10K_FW_DIR, filename);
1191 if (IS_ERR(ar->cal_file))
1192
1193 return PTR_ERR(ar->cal_file);
1194success:
1195 ath10k_dbg(ar, ATH10K_DBG_BOOT, "found calibration file %s/%s\n",
1196 ATH10K_FW_DIR, filename);
1197
1198 return 0;
1199}
1200
1201static int ath10k_core_fetch_board_data_api_1(struct ath10k *ar, int bd_ie_type)
1202{
1203 const struct firmware *fw;
1204
1205 if (bd_ie_type == ATH10K_BD_IE_BOARD) {
1206 if (!ar->hw_params.fw.board) {
1207 ath10k_err(ar, "failed to find board file fw entry\n");
1208 return -EINVAL;
1209 }
1210
1211 ar->normal_mode_fw.board = ath10k_fetch_fw_file(ar,
1212 ar->hw_params.fw.dir,
1213 ar->hw_params.fw.board);
1214 if (IS_ERR(ar->normal_mode_fw.board))
1215 return PTR_ERR(ar->normal_mode_fw.board);
1216
1217 ar->normal_mode_fw.board_data = ar->normal_mode_fw.board->data;
1218 ar->normal_mode_fw.board_len = ar->normal_mode_fw.board->size;
1219 } else if (bd_ie_type == ATH10K_BD_IE_BOARD_EXT) {
1220 if (!ar->hw_params.fw.eboard) {
1221 ath10k_err(ar, "failed to find eboard file fw entry\n");
1222 return -EINVAL;
1223 }
1224
1225 fw = ath10k_fetch_fw_file(ar, ar->hw_params.fw.dir,
1226 ar->hw_params.fw.eboard);
1227 ar->normal_mode_fw.ext_board = fw;
1228 if (IS_ERR(ar->normal_mode_fw.ext_board))
1229 return PTR_ERR(ar->normal_mode_fw.ext_board);
1230
1231 ar->normal_mode_fw.ext_board_data = ar->normal_mode_fw.ext_board->data;
1232 ar->normal_mode_fw.ext_board_len = ar->normal_mode_fw.ext_board->size;
1233 }
1234
1235 return 0;
1236}
1237
1238static int ath10k_core_parse_bd_ie_board(struct ath10k *ar,
1239 const void *buf, size_t buf_len,
1240 const char *boardname,
1241 int bd_ie_type)
1242{
1243 const struct ath10k_fw_ie *hdr;
1244 bool name_match_found;
1245 int ret, board_ie_id;
1246 size_t board_ie_len;
1247 const void *board_ie_data;
1248
1249 name_match_found = false;
1250
1251
1252 while (buf_len > sizeof(struct ath10k_fw_ie)) {
1253 hdr = buf;
1254 board_ie_id = le32_to_cpu(hdr->id);
1255 board_ie_len = le32_to_cpu(hdr->len);
1256 board_ie_data = hdr->data;
1257
1258 buf_len -= sizeof(*hdr);
1259 buf += sizeof(*hdr);
1260
1261 if (buf_len < ALIGN(board_ie_len, 4)) {
1262 ath10k_err(ar, "invalid ATH10K_BD_IE_BOARD length: %zu < %zu\n",
1263 buf_len, ALIGN(board_ie_len, 4));
1264 ret = -EINVAL;
1265 goto out;
1266 }
1267
1268 switch (board_ie_id) {
1269 case ATH10K_BD_IE_BOARD_NAME:
1270 ath10k_dbg_dump(ar, ATH10K_DBG_BOOT, "board name", "",
1271 board_ie_data, board_ie_len);
1272
1273 if (board_ie_len != strlen(boardname))
1274 break;
1275
1276 ret = memcmp(board_ie_data, boardname, strlen(boardname));
1277 if (ret)
1278 break;
1279
1280 name_match_found = true;
1281 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1282 "boot found match for name '%s'",
1283 boardname);
1284 break;
1285 case ATH10K_BD_IE_BOARD_DATA:
1286 if (!name_match_found)
1287
1288 break;
1289
1290 if (bd_ie_type == ATH10K_BD_IE_BOARD) {
1291 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1292 "boot found board data for '%s'",
1293 boardname);
1294
1295 ar->normal_mode_fw.board_data = board_ie_data;
1296 ar->normal_mode_fw.board_len = board_ie_len;
1297 } else if (bd_ie_type == ATH10K_BD_IE_BOARD_EXT) {
1298 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1299 "boot found eboard data for '%s'",
1300 boardname);
1301
1302 ar->normal_mode_fw.ext_board_data = board_ie_data;
1303 ar->normal_mode_fw.ext_board_len = board_ie_len;
1304 }
1305
1306 ret = 0;
1307 goto out;
1308 default:
1309 ath10k_warn(ar, "unknown ATH10K_BD_IE_BOARD found: %d\n",
1310 board_ie_id);
1311 break;
1312 }
1313
1314
1315 board_ie_len = ALIGN(board_ie_len, 4);
1316
1317 buf_len -= board_ie_len;
1318 buf += board_ie_len;
1319 }
1320
1321
1322 ret = -ENOENT;
1323
1324out:
1325 return ret;
1326}
1327
1328static int ath10k_core_search_bd(struct ath10k *ar,
1329 const char *boardname,
1330 const u8 *data,
1331 size_t len)
1332{
1333 size_t ie_len;
1334 struct ath10k_fw_ie *hdr;
1335 int ret = -ENOENT, ie_id;
1336
1337 while (len > sizeof(struct ath10k_fw_ie)) {
1338 hdr = (struct ath10k_fw_ie *)data;
1339 ie_id = le32_to_cpu(hdr->id);
1340 ie_len = le32_to_cpu(hdr->len);
1341
1342 len -= sizeof(*hdr);
1343 data = hdr->data;
1344
1345 if (len < ALIGN(ie_len, 4)) {
1346 ath10k_err(ar, "invalid length for board ie_id %d ie_len %zu len %zu\n",
1347 ie_id, ie_len, len);
1348 return -EINVAL;
1349 }
1350
1351 switch (ie_id) {
1352 case ATH10K_BD_IE_BOARD:
1353 ret = ath10k_core_parse_bd_ie_board(ar, data, ie_len,
1354 boardname,
1355 ATH10K_BD_IE_BOARD);
1356 if (ret == -ENOENT)
1357
1358 break;
1359
1360
1361 goto out;
1362 case ATH10K_BD_IE_BOARD_EXT:
1363 ret = ath10k_core_parse_bd_ie_board(ar, data, ie_len,
1364 boardname,
1365 ATH10K_BD_IE_BOARD_EXT);
1366 if (ret == -ENOENT)
1367
1368 break;
1369
1370
1371 goto out;
1372 }
1373
1374
1375 ie_len = ALIGN(ie_len, 4);
1376
1377 len -= ie_len;
1378 data += ie_len;
1379 }
1380
1381out:
1382
1383 return ret;
1384}
1385
1386static int ath10k_core_fetch_board_data_api_n(struct ath10k *ar,
1387 const char *boardname,
1388 const char *fallback_boardname1,
1389 const char *fallback_boardname2,
1390 const char *filename)
1391{
1392 size_t len, magic_len;
1393 const u8 *data;
1394 int ret;
1395
1396
1397 if (!ar->normal_mode_fw.board)
1398 ar->normal_mode_fw.board = ath10k_fetch_fw_file(ar,
1399 ar->hw_params.fw.dir,
1400 filename);
1401 if (IS_ERR(ar->normal_mode_fw.board))
1402 return PTR_ERR(ar->normal_mode_fw.board);
1403
1404 data = ar->normal_mode_fw.board->data;
1405 len = ar->normal_mode_fw.board->size;
1406
1407
1408 magic_len = strlen(ATH10K_BOARD_MAGIC) + 1;
1409 if (len < magic_len) {
1410 ath10k_err(ar, "failed to find magic value in %s/%s, file too short: %zu\n",
1411 ar->hw_params.fw.dir, filename, len);
1412 ret = -EINVAL;
1413 goto err;
1414 }
1415
1416 if (memcmp(data, ATH10K_BOARD_MAGIC, magic_len)) {
1417 ath10k_err(ar, "found invalid board magic\n");
1418 ret = -EINVAL;
1419 goto err;
1420 }
1421
1422
1423 magic_len = ALIGN(magic_len, 4);
1424 if (len < magic_len) {
1425 ath10k_err(ar, "failed: %s/%s too small to contain board data, len: %zu\n",
1426 ar->hw_params.fw.dir, filename, len);
1427 ret = -EINVAL;
1428 goto err;
1429 }
1430
1431 data += magic_len;
1432 len -= magic_len;
1433
1434
1435 ret = ath10k_core_search_bd(ar, boardname, data, len);
1436
1437
1438 if (ret == -ENOENT && fallback_boardname1)
1439 ret = ath10k_core_search_bd(ar, fallback_boardname1, data, len);
1440
1441 if (ret == -ENOENT && fallback_boardname2)
1442 ret = ath10k_core_search_bd(ar, fallback_boardname2, data, len);
1443
1444 if (ret == -ENOENT) {
1445 ath10k_err(ar,
1446 "failed to fetch board data for %s from %s/%s\n",
1447 boardname, ar->hw_params.fw.dir, filename);
1448 ret = -ENODATA;
1449 }
1450
1451 if (ret)
1452 goto err;
1453
1454 return 0;
1455
1456err:
1457 ath10k_core_free_board_files(ar);
1458 return ret;
1459}
1460
1461static int ath10k_core_create_board_name(struct ath10k *ar, char *name,
1462 size_t name_len, bool with_variant,
1463 bool with_chip_id)
1464{
1465
1466 char variant[9 + ATH10K_SMBIOS_BDF_EXT_STR_LENGTH] = { 0 };
1467
1468 if (with_variant && ar->id.bdf_ext[0] != '\0')
1469 scnprintf(variant, sizeof(variant), ",variant=%s",
1470 ar->id.bdf_ext);
1471
1472 if (ar->id.bmi_ids_valid) {
1473 scnprintf(name, name_len,
1474 "bus=%s,bmi-chip-id=%d,bmi-board-id=%d%s",
1475 ath10k_bus_str(ar->hif.bus),
1476 ar->id.bmi_chip_id,
1477 ar->id.bmi_board_id, variant);
1478 goto out;
1479 }
1480
1481 if (ar->id.qmi_ids_valid) {
1482 if (with_chip_id)
1483 scnprintf(name, name_len,
1484 "bus=%s,qmi-board-id=%x,qmi-chip-id=%x%s",
1485 ath10k_bus_str(ar->hif.bus),
1486 ar->id.qmi_board_id, ar->id.qmi_chip_id,
1487 variant);
1488 else
1489 scnprintf(name, name_len,
1490 "bus=%s,qmi-board-id=%x",
1491 ath10k_bus_str(ar->hif.bus),
1492 ar->id.qmi_board_id);
1493 goto out;
1494 }
1495
1496 scnprintf(name, name_len,
1497 "bus=%s,vendor=%04x,device=%04x,subsystem-vendor=%04x,subsystem-device=%04x%s",
1498 ath10k_bus_str(ar->hif.bus),
1499 ar->id.vendor, ar->id.device,
1500 ar->id.subsystem_vendor, ar->id.subsystem_device, variant);
1501out:
1502 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot using board name '%s'\n", name);
1503
1504 return 0;
1505}
1506
1507static int ath10k_core_create_eboard_name(struct ath10k *ar, char *name,
1508 size_t name_len)
1509{
1510 if (ar->id.bmi_ids_valid) {
1511 scnprintf(name, name_len,
1512 "bus=%s,bmi-chip-id=%d,bmi-eboard-id=%d",
1513 ath10k_bus_str(ar->hif.bus),
1514 ar->id.bmi_chip_id,
1515 ar->id.bmi_eboard_id);
1516
1517 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot using eboard name '%s'\n", name);
1518 return 0;
1519 }
1520
1521 return -1;
1522}
1523
1524int ath10k_core_fetch_board_file(struct ath10k *ar, int bd_ie_type)
1525{
1526 char boardname[100], fallback_boardname1[100], fallback_boardname2[100];
1527 int ret;
1528
1529 if (bd_ie_type == ATH10K_BD_IE_BOARD) {
1530
1531 ret = ath10k_core_create_board_name(ar, boardname,
1532 sizeof(boardname), true,
1533 true);
1534 if (ret) {
1535 ath10k_err(ar, "failed to create board name: %d", ret);
1536 return ret;
1537 }
1538
1539
1540 ret = ath10k_core_create_board_name(ar, fallback_boardname1,
1541 sizeof(boardname), false,
1542 true);
1543 if (ret) {
1544 ath10k_err(ar, "failed to create 1st fallback board name: %d",
1545 ret);
1546 return ret;
1547 }
1548
1549
1550 ret = ath10k_core_create_board_name(ar, fallback_boardname2,
1551 sizeof(boardname), false,
1552 false);
1553 if (ret) {
1554 ath10k_err(ar, "failed to create 2nd fallback board name: %d",
1555 ret);
1556 return ret;
1557 }
1558 } else if (bd_ie_type == ATH10K_BD_IE_BOARD_EXT) {
1559 ret = ath10k_core_create_eboard_name(ar, boardname,
1560 sizeof(boardname));
1561 if (ret) {
1562 ath10k_err(ar, "fallback to eboard.bin since board id 0");
1563 goto fallback;
1564 }
1565 }
1566
1567 ar->bd_api = 2;
1568 ret = ath10k_core_fetch_board_data_api_n(ar, boardname,
1569 fallback_boardname1,
1570 fallback_boardname2,
1571 ATH10K_BOARD_API2_FILE);
1572 if (!ret)
1573 goto success;
1574
1575fallback:
1576 ar->bd_api = 1;
1577 ret = ath10k_core_fetch_board_data_api_1(ar, bd_ie_type);
1578 if (ret) {
1579 ath10k_err(ar, "failed to fetch board-2.bin or board.bin from %s\n",
1580 ar->hw_params.fw.dir);
1581 return ret;
1582 }
1583
1584success:
1585 ath10k_dbg(ar, ATH10K_DBG_BOOT, "using board api %d\n", ar->bd_api);
1586 return 0;
1587}
1588EXPORT_SYMBOL(ath10k_core_fetch_board_file);
1589
1590static int ath10k_core_get_ext_board_id_from_otp(struct ath10k *ar)
1591{
1592 u32 result, address;
1593 u8 ext_board_id;
1594 int ret;
1595
1596 address = ar->hw_params.patch_load_addr;
1597
1598 if (!ar->normal_mode_fw.fw_file.otp_data ||
1599 !ar->normal_mode_fw.fw_file.otp_len) {
1600 ath10k_warn(ar,
1601 "failed to retrieve extended board id due to otp binary missing\n");
1602 return -ENODATA;
1603 }
1604
1605 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1606 "boot upload otp to 0x%x len %zd for ext board id\n",
1607 address, ar->normal_mode_fw.fw_file.otp_len);
1608
1609 ret = ath10k_bmi_fast_download(ar, address,
1610 ar->normal_mode_fw.fw_file.otp_data,
1611 ar->normal_mode_fw.fw_file.otp_len);
1612 if (ret) {
1613 ath10k_err(ar, "could not write otp for ext board id check: %d\n",
1614 ret);
1615 return ret;
1616 }
1617
1618 ret = ath10k_bmi_execute(ar, address, BMI_PARAM_GET_EXT_BOARD_ID, &result);
1619 if (ret) {
1620 ath10k_err(ar, "could not execute otp for ext board id check: %d\n",
1621 ret);
1622 return ret;
1623 }
1624
1625 if (!result) {
1626 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1627 "ext board id does not exist in otp, ignore it\n");
1628 return -EOPNOTSUPP;
1629 }
1630
1631 ext_board_id = result & ATH10K_BMI_EBOARD_ID_STATUS_MASK;
1632
1633 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1634 "boot get otp ext board id result 0x%08x ext_board_id %d\n",
1635 result, ext_board_id);
1636
1637 ar->id.bmi_eboard_id = ext_board_id;
1638
1639 return 0;
1640}
1641
1642static int ath10k_download_board_data(struct ath10k *ar, const void *data,
1643 size_t data_len)
1644{
1645 u32 board_data_size = ar->hw_params.fw.board_size;
1646 u32 eboard_data_size = ar->hw_params.fw.ext_board_size;
1647 u32 board_address;
1648 u32 ext_board_address;
1649 int ret;
1650
1651 ret = ath10k_push_board_ext_data(ar, data, data_len);
1652 if (ret) {
1653 ath10k_err(ar, "could not push board ext data (%d)\n", ret);
1654 goto exit;
1655 }
1656
1657 ret = ath10k_bmi_read32(ar, hi_board_data, &board_address);
1658 if (ret) {
1659 ath10k_err(ar, "could not read board data addr (%d)\n", ret);
1660 goto exit;
1661 }
1662
1663 ret = ath10k_bmi_write_memory(ar, board_address, data,
1664 min_t(u32, board_data_size,
1665 data_len));
1666 if (ret) {
1667 ath10k_err(ar, "could not write board data (%d)\n", ret);
1668 goto exit;
1669 }
1670
1671 ret = ath10k_bmi_write32(ar, hi_board_data_initialized, 1);
1672 if (ret) {
1673 ath10k_err(ar, "could not write board data bit (%d)\n", ret);
1674 goto exit;
1675 }
1676
1677 if (!ar->id.ext_bid_supported)
1678 goto exit;
1679
1680
1681 ret = ath10k_core_get_ext_board_id_from_otp(ar);
1682 if (ret == -EOPNOTSUPP) {
1683
1684 ath10k_dbg(ar, ATH10K_DBG_BOOT, "otp returned ext board id 0\n");
1685 return 0;
1686 } else if (ret) {
1687 ath10k_err(ar, "failed to get extended board id: %d\n", ret);
1688 goto exit;
1689 }
1690
1691 ret = ath10k_core_fetch_board_file(ar, ATH10K_BD_IE_BOARD_EXT);
1692 if (ret)
1693 goto exit;
1694
1695 if (ar->normal_mode_fw.ext_board_data) {
1696 ext_board_address = board_address + EXT_BOARD_ADDRESS_OFFSET;
1697 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1698 "boot writing ext board data to addr 0x%x",
1699 ext_board_address);
1700 ret = ath10k_bmi_write_memory(ar, ext_board_address,
1701 ar->normal_mode_fw.ext_board_data,
1702 min_t(u32, eboard_data_size, data_len));
1703 if (ret)
1704 ath10k_err(ar, "failed to write ext board data: %d\n", ret);
1705 }
1706
1707exit:
1708 return ret;
1709}
1710
1711static int ath10k_download_and_run_otp(struct ath10k *ar)
1712{
1713 u32 result, address = ar->hw_params.patch_load_addr;
1714 u32 bmi_otp_exe_param = ar->hw_params.otp_exe_param;
1715 int ret;
1716
1717 ret = ath10k_download_board_data(ar,
1718 ar->running_fw->board_data,
1719 ar->running_fw->board_len);
1720 if (ret) {
1721 ath10k_err(ar, "failed to download board data: %d\n", ret);
1722 return ret;
1723 }
1724
1725
1726
1727 if (!ar->running_fw->fw_file.otp_data ||
1728 !ar->running_fw->fw_file.otp_len) {
1729 ath10k_warn(ar, "Not running otp, calibration will be incorrect (otp-data %pK otp_len %zd)!\n",
1730 ar->running_fw->fw_file.otp_data,
1731 ar->running_fw->fw_file.otp_len);
1732 return 0;
1733 }
1734
1735 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot upload otp to 0x%x len %zd\n",
1736 address, ar->running_fw->fw_file.otp_len);
1737
1738 ret = ath10k_bmi_fast_download(ar, address,
1739 ar->running_fw->fw_file.otp_data,
1740 ar->running_fw->fw_file.otp_len);
1741 if (ret) {
1742 ath10k_err(ar, "could not write otp (%d)\n", ret);
1743 return ret;
1744 }
1745
1746
1747 if (ar->cal_mode == ATH10K_PRE_CAL_MODE_DT ||
1748 ar->cal_mode == ATH10K_PRE_CAL_MODE_FILE ||
1749 ar->cal_mode == ATH10K_PRE_CAL_MODE_NVMEM)
1750 bmi_otp_exe_param = BMI_PARAM_FLASH_SECTION_ALL;
1751
1752 ret = ath10k_bmi_execute(ar, address, bmi_otp_exe_param, &result);
1753 if (ret) {
1754 ath10k_err(ar, "could not execute otp (%d)\n", ret);
1755 return ret;
1756 }
1757
1758 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot otp execute result %d\n", result);
1759
1760 if (!(skip_otp || test_bit(ATH10K_FW_FEATURE_IGNORE_OTP_RESULT,
1761 ar->running_fw->fw_file.fw_features)) &&
1762 result != 0) {
1763 ath10k_err(ar, "otp calibration failed: %d", result);
1764 return -EINVAL;
1765 }
1766
1767 return 0;
1768}
1769
1770static int ath10k_download_cal_file(struct ath10k *ar,
1771 const struct firmware *file)
1772{
1773 int ret;
1774
1775 if (!file)
1776 return -ENOENT;
1777
1778 if (IS_ERR(file))
1779 return PTR_ERR(file);
1780
1781 ret = ath10k_download_board_data(ar, file->data, file->size);
1782 if (ret) {
1783 ath10k_err(ar, "failed to download cal_file data: %d\n", ret);
1784 return ret;
1785 }
1786
1787 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cal file downloaded\n");
1788
1789 return 0;
1790}
1791
1792static int ath10k_download_cal_dt(struct ath10k *ar, const char *dt_name)
1793{
1794 struct device_node *node;
1795 int data_len;
1796 void *data;
1797 int ret;
1798
1799 node = ar->dev->of_node;
1800 if (!node)
1801
1802
1803
1804 return -ENOENT;
1805
1806 if (!of_get_property(node, dt_name, &data_len)) {
1807
1808 return -ENOENT;
1809 }
1810
1811 if (data_len != ar->hw_params.cal_data_len) {
1812 ath10k_warn(ar, "invalid calibration data length in DT: %d\n",
1813 data_len);
1814 ret = -EMSGSIZE;
1815 goto out;
1816 }
1817
1818 data = kmalloc(data_len, GFP_KERNEL);
1819 if (!data) {
1820 ret = -ENOMEM;
1821 goto out;
1822 }
1823
1824 ret = of_property_read_u8_array(node, dt_name, data, data_len);
1825 if (ret) {
1826 ath10k_warn(ar, "failed to read calibration data from DT: %d\n",
1827 ret);
1828 goto out_free;
1829 }
1830
1831 ret = ath10k_download_board_data(ar, data, data_len);
1832 if (ret) {
1833 ath10k_warn(ar, "failed to download calibration data from Device Tree: %d\n",
1834 ret);
1835 goto out_free;
1836 }
1837
1838 ret = 0;
1839
1840out_free:
1841 kfree(data);
1842
1843out:
1844 return ret;
1845}
1846
1847static int ath10k_download_cal_eeprom(struct ath10k *ar)
1848{
1849 size_t data_len;
1850 void *data = NULL;
1851 int ret;
1852
1853 ret = ath10k_hif_fetch_cal_eeprom(ar, &data, &data_len);
1854 if (ret) {
1855 if (ret != -EOPNOTSUPP)
1856 ath10k_warn(ar, "failed to read calibration data from EEPROM: %d\n",
1857 ret);
1858 goto out_free;
1859 }
1860
1861 ret = ath10k_download_board_data(ar, data, data_len);
1862 if (ret) {
1863 ath10k_warn(ar, "failed to download calibration data from EEPROM: %d\n",
1864 ret);
1865 goto out_free;
1866 }
1867
1868 ret = 0;
1869
1870out_free:
1871 kfree(data);
1872
1873 return ret;
1874}
1875
1876static int ath10k_download_cal_nvmem(struct ath10k *ar, const char *cell_name)
1877{
1878 struct nvmem_cell *cell;
1879 void *buf;
1880 size_t len;
1881 int ret;
1882
1883 cell = devm_nvmem_cell_get(ar->dev, cell_name);
1884 if (IS_ERR(cell)) {
1885 ret = PTR_ERR(cell);
1886 return ret;
1887 }
1888
1889 buf = nvmem_cell_read(cell, &len);
1890 if (IS_ERR(buf))
1891 return PTR_ERR(buf);
1892
1893 if (ar->hw_params.cal_data_len != len) {
1894 kfree(buf);
1895 ath10k_warn(ar, "invalid calibration data length in nvmem-cell '%s': %zu != %u\n",
1896 cell_name, len, ar->hw_params.cal_data_len);
1897 return -EMSGSIZE;
1898 }
1899
1900 ret = ath10k_download_board_data(ar, buf, len);
1901 kfree(buf);
1902 if (ret)
1903 ath10k_warn(ar, "failed to download calibration data from nvmem-cell '%s': %d\n",
1904 cell_name, ret);
1905
1906 return ret;
1907}
1908
1909int ath10k_core_fetch_firmware_api_n(struct ath10k *ar, const char *name,
1910 struct ath10k_fw_file *fw_file)
1911{
1912 size_t magic_len, len, ie_len;
1913 int ie_id, i, index, bit, ret;
1914 struct ath10k_fw_ie *hdr;
1915 const u8 *data;
1916 __le32 *timestamp, *version;
1917
1918
1919 fw_file->firmware = ath10k_fetch_fw_file(ar, ar->hw_params.fw.dir,
1920 name);
1921 if (IS_ERR(fw_file->firmware))
1922 return PTR_ERR(fw_file->firmware);
1923
1924 data = fw_file->firmware->data;
1925 len = fw_file->firmware->size;
1926
1927
1928 magic_len = strlen(ATH10K_FIRMWARE_MAGIC) + 1;
1929
1930 if (len < magic_len) {
1931 ath10k_err(ar, "firmware file '%s/%s' too small to contain magic: %zu\n",
1932 ar->hw_params.fw.dir, name, len);
1933 ret = -EINVAL;
1934 goto err;
1935 }
1936
1937 if (memcmp(data, ATH10K_FIRMWARE_MAGIC, magic_len) != 0) {
1938 ath10k_err(ar, "invalid firmware magic\n");
1939 ret = -EINVAL;
1940 goto err;
1941 }
1942
1943
1944 magic_len = ALIGN(magic_len, 4);
1945
1946 len -= magic_len;
1947 data += magic_len;
1948
1949
1950 while (len > sizeof(struct ath10k_fw_ie)) {
1951 hdr = (struct ath10k_fw_ie *)data;
1952
1953 ie_id = le32_to_cpu(hdr->id);
1954 ie_len = le32_to_cpu(hdr->len);
1955
1956 len -= sizeof(*hdr);
1957 data += sizeof(*hdr);
1958
1959 if (len < ie_len) {
1960 ath10k_err(ar, "invalid length for FW IE %d (%zu < %zu)\n",
1961 ie_id, len, ie_len);
1962 ret = -EINVAL;
1963 goto err;
1964 }
1965
1966 switch (ie_id) {
1967 case ATH10K_FW_IE_FW_VERSION:
1968 if (ie_len > sizeof(fw_file->fw_version) - 1)
1969 break;
1970
1971 memcpy(fw_file->fw_version, data, ie_len);
1972 fw_file->fw_version[ie_len] = '\0';
1973
1974 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1975 "found fw version %s\n",
1976 fw_file->fw_version);
1977 break;
1978 case ATH10K_FW_IE_TIMESTAMP:
1979 if (ie_len != sizeof(u32))
1980 break;
1981
1982 timestamp = (__le32 *)data;
1983
1984 ath10k_dbg(ar, ATH10K_DBG_BOOT, "found fw timestamp %d\n",
1985 le32_to_cpup(timestamp));
1986 break;
1987 case ATH10K_FW_IE_FEATURES:
1988 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1989 "found firmware features ie (%zd B)\n",
1990 ie_len);
1991
1992 for (i = 0; i < ATH10K_FW_FEATURE_COUNT; i++) {
1993 index = i / 8;
1994 bit = i % 8;
1995
1996 if (index == ie_len)
1997 break;
1998
1999 if (data[index] & (1 << bit)) {
2000 ath10k_dbg(ar, ATH10K_DBG_BOOT,
2001 "Enabling feature bit: %i\n",
2002 i);
2003 __set_bit(i, fw_file->fw_features);
2004 }
2005 }
2006
2007 ath10k_dbg_dump(ar, ATH10K_DBG_BOOT, "features", "",
2008 fw_file->fw_features,
2009 sizeof(fw_file->fw_features));
2010 break;
2011 case ATH10K_FW_IE_FW_IMAGE:
2012 ath10k_dbg(ar, ATH10K_DBG_BOOT,
2013 "found fw image ie (%zd B)\n",
2014 ie_len);
2015
2016 fw_file->firmware_data = data;
2017 fw_file->firmware_len = ie_len;
2018
2019 break;
2020 case ATH10K_FW_IE_OTP_IMAGE:
2021 ath10k_dbg(ar, ATH10K_DBG_BOOT,
2022 "found otp image ie (%zd B)\n",
2023 ie_len);
2024
2025 fw_file->otp_data = data;
2026 fw_file->otp_len = ie_len;
2027
2028 break;
2029 case ATH10K_FW_IE_WMI_OP_VERSION:
2030 if (ie_len != sizeof(u32))
2031 break;
2032
2033 version = (__le32 *)data;
2034
2035 fw_file->wmi_op_version = le32_to_cpup(version);
2036
2037 ath10k_dbg(ar, ATH10K_DBG_BOOT, "found fw ie wmi op version %d\n",
2038 fw_file->wmi_op_version);
2039 break;
2040 case ATH10K_FW_IE_HTT_OP_VERSION:
2041 if (ie_len != sizeof(u32))
2042 break;
2043
2044 version = (__le32 *)data;
2045
2046 fw_file->htt_op_version = le32_to_cpup(version);
2047
2048 ath10k_dbg(ar, ATH10K_DBG_BOOT, "found fw ie htt op version %d\n",
2049 fw_file->htt_op_version);
2050 break;
2051 case ATH10K_FW_IE_FW_CODE_SWAP_IMAGE:
2052 ath10k_dbg(ar, ATH10K_DBG_BOOT,
2053 "found fw code swap image ie (%zd B)\n",
2054 ie_len);
2055 fw_file->codeswap_data = data;
2056 fw_file->codeswap_len = ie_len;
2057 break;
2058 default:
2059 ath10k_warn(ar, "Unknown FW IE: %u\n",
2060 le32_to_cpu(hdr->id));
2061 break;
2062 }
2063
2064
2065 ie_len = ALIGN(ie_len, 4);
2066
2067 len -= ie_len;
2068 data += ie_len;
2069 }
2070
2071 if (!test_bit(ATH10K_FW_FEATURE_NON_BMI, fw_file->fw_features) &&
2072 (!fw_file->firmware_data || !fw_file->firmware_len)) {
2073 ath10k_warn(ar, "No ATH10K_FW_IE_FW_IMAGE found from '%s/%s', skipping\n",
2074 ar->hw_params.fw.dir, name);
2075 ret = -ENOMEDIUM;
2076 goto err;
2077 }
2078
2079 return 0;
2080
2081err:
2082 ath10k_core_free_firmware_files(ar);
2083 return ret;
2084}
2085
2086static void ath10k_core_get_fw_name(struct ath10k *ar, char *fw_name,
2087 size_t fw_name_len, int fw_api)
2088{
2089 switch (ar->hif.bus) {
2090 case ATH10K_BUS_SDIO:
2091 case ATH10K_BUS_USB:
2092 scnprintf(fw_name, fw_name_len, "%s-%s-%d.bin",
2093 ATH10K_FW_FILE_BASE, ath10k_bus_str(ar->hif.bus),
2094 fw_api);
2095 break;
2096 case ATH10K_BUS_PCI:
2097 case ATH10K_BUS_AHB:
2098 case ATH10K_BUS_SNOC:
2099 scnprintf(fw_name, fw_name_len, "%s-%d.bin",
2100 ATH10K_FW_FILE_BASE, fw_api);
2101 break;
2102 }
2103}
2104
2105static int ath10k_core_fetch_firmware_files(struct ath10k *ar)
2106{
2107 int ret, i;
2108 char fw_name[100];
2109
2110
2111 ath10k_fetch_cal_file(ar);
2112
2113 for (i = ATH10K_FW_API_MAX; i >= ATH10K_FW_API_MIN; i--) {
2114 ar->fw_api = i;
2115 ath10k_dbg(ar, ATH10K_DBG_BOOT, "trying fw api %d\n",
2116 ar->fw_api);
2117
2118 ath10k_core_get_fw_name(ar, fw_name, sizeof(fw_name), ar->fw_api);
2119 ret = ath10k_core_fetch_firmware_api_n(ar, fw_name,
2120 &ar->normal_mode_fw.fw_file);
2121 if (!ret)
2122 goto success;
2123 }
2124
2125
2126
2127 ath10k_err(ar, "Failed to find firmware-N.bin (N between %d and %d) from %s: %d",
2128 ATH10K_FW_API_MIN, ATH10K_FW_API_MAX, ar->hw_params.fw.dir,
2129 ret);
2130
2131 return ret;
2132
2133success:
2134 ath10k_dbg(ar, ATH10K_DBG_BOOT, "using fw api %d\n", ar->fw_api);
2135
2136 return 0;
2137}
2138
2139static int ath10k_core_pre_cal_download(struct ath10k *ar)
2140{
2141 int ret;
2142
2143 ret = ath10k_download_cal_nvmem(ar, "pre-calibration");
2144 if (ret == 0) {
2145 ar->cal_mode = ATH10K_PRE_CAL_MODE_NVMEM;
2146 goto success;
2147 } else if (ret == -EPROBE_DEFER) {
2148 return ret;
2149 }
2150
2151 ath10k_dbg(ar, ATH10K_DBG_BOOT,
2152 "boot did not find a pre-calibration nvmem-cell, try file next: %d\n",
2153 ret);
2154
2155 ret = ath10k_download_cal_file(ar, ar->pre_cal_file);
2156 if (ret == 0) {
2157 ar->cal_mode = ATH10K_PRE_CAL_MODE_FILE;
2158 goto success;
2159 }
2160
2161 ath10k_dbg(ar, ATH10K_DBG_BOOT,
2162 "boot did not find a pre calibration file, try DT next: %d\n",
2163 ret);
2164
2165 ret = ath10k_download_cal_dt(ar, "qcom,ath10k-pre-calibration-data");
2166 if (ret) {
2167 ath10k_dbg(ar, ATH10K_DBG_BOOT,
2168 "unable to load pre cal data from DT: %d\n", ret);
2169 return ret;
2170 }
2171 ar->cal_mode = ATH10K_PRE_CAL_MODE_DT;
2172
2173success:
2174 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot using calibration mode %s\n",
2175 ath10k_cal_mode_str(ar->cal_mode));
2176
2177 return 0;
2178}
2179
2180static int ath10k_core_pre_cal_config(struct ath10k *ar)
2181{
2182 int ret;
2183
2184 ret = ath10k_core_pre_cal_download(ar);
2185 if (ret) {
2186 ath10k_dbg(ar, ATH10K_DBG_BOOT,
2187 "failed to load pre cal data: %d\n", ret);
2188 return ret;
2189 }
2190
2191 ret = ath10k_core_get_board_id_from_otp(ar);
2192 if (ret) {
2193 ath10k_err(ar, "failed to get board id: %d\n", ret);
2194 return ret;
2195 }
2196
2197 ret = ath10k_download_and_run_otp(ar);
2198 if (ret) {
2199 ath10k_err(ar, "failed to run otp: %d\n", ret);
2200 return ret;
2201 }
2202
2203 ath10k_dbg(ar, ATH10K_DBG_BOOT,
2204 "pre cal configuration done successfully\n");
2205
2206 return 0;
2207}
2208
2209static int ath10k_download_cal_data(struct ath10k *ar)
2210{
2211 int ret;
2212
2213 ret = ath10k_core_pre_cal_config(ar);
2214 if (ret == 0)
2215 return 0;
2216
2217 ath10k_dbg(ar, ATH10K_DBG_BOOT,
2218 "pre cal download procedure failed, try cal file: %d\n",
2219 ret);
2220
2221 ret = ath10k_download_cal_nvmem(ar, "calibration");
2222 if (ret == 0) {
2223 ar->cal_mode = ATH10K_CAL_MODE_NVMEM;
2224 goto done;
2225 } else if (ret == -EPROBE_DEFER) {
2226 return ret;
2227 }
2228
2229 ath10k_dbg(ar, ATH10K_DBG_BOOT,
2230 "boot did not find a calibration nvmem-cell, try file next: %d\n",
2231 ret);
2232
2233 ret = ath10k_download_cal_file(ar, ar->cal_file);
2234 if (ret == 0) {
2235 ar->cal_mode = ATH10K_CAL_MODE_FILE;
2236 goto done;
2237 }
2238
2239 ath10k_dbg(ar, ATH10K_DBG_BOOT,
2240 "boot did not find a calibration file, try DT next: %d\n",
2241 ret);
2242
2243 ret = ath10k_download_cal_dt(ar, "qcom,ath10k-calibration-data");
2244 if (ret == 0) {
2245 ar->cal_mode = ATH10K_CAL_MODE_DT;
2246 goto done;
2247 }
2248
2249 ath10k_dbg(ar, ATH10K_DBG_BOOT,
2250 "boot did not find DT entry, try target EEPROM next: %d\n",
2251 ret);
2252
2253 ret = ath10k_download_cal_eeprom(ar);
2254 if (ret == 0) {
2255 ar->cal_mode = ATH10K_CAL_MODE_EEPROM;
2256 goto done;
2257 }
2258
2259 ath10k_dbg(ar, ATH10K_DBG_BOOT,
2260 "boot did not find target EEPROM entry, try OTP next: %d\n",
2261 ret);
2262
2263 ret = ath10k_download_and_run_otp(ar);
2264 if (ret) {
2265 ath10k_err(ar, "failed to run otp: %d\n", ret);
2266 return ret;
2267 }
2268
2269 ar->cal_mode = ATH10K_CAL_MODE_OTP;
2270
2271done:
2272 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot using calibration mode %s\n",
2273 ath10k_cal_mode_str(ar->cal_mode));
2274 return 0;
2275}
2276
2277static void ath10k_core_fetch_btcoex_dt(struct ath10k *ar)
2278{
2279 struct device_node *node;
2280 u8 coex_support = 0;
2281 int ret;
2282
2283 node = ar->dev->of_node;
2284 if (!node)
2285 goto out;
2286
2287 ret = of_property_read_u8(node, "qcom,coexist-support", &coex_support);
2288 if (ret) {
2289 ar->coex_support = true;
2290 goto out;
2291 }
2292
2293 if (coex_support) {
2294 ar->coex_support = true;
2295 } else {
2296 ar->coex_support = false;
2297 ar->coex_gpio_pin = -1;
2298 goto out;
2299 }
2300
2301 ret = of_property_read_u32(node, "qcom,coexist-gpio-pin",
2302 &ar->coex_gpio_pin);
2303 if (ret)
2304 ar->coex_gpio_pin = -1;
2305
2306out:
2307 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot coex_support %d coex_gpio_pin %d\n",
2308 ar->coex_support, ar->coex_gpio_pin);
2309}
2310
2311static int ath10k_init_uart(struct ath10k *ar)
2312{
2313 int ret;
2314
2315
2316
2317
2318
2319 ret = ath10k_bmi_write32(ar, hi_serial_enable, 0);
2320 if (ret) {
2321 ath10k_warn(ar, "could not disable UART prints (%d)\n", ret);
2322 return ret;
2323 }
2324
2325 if (!uart_print) {
2326 if (ar->hw_params.uart_pin_workaround) {
2327 ret = ath10k_bmi_write32(ar, hi_dbg_uart_txpin,
2328 ar->hw_params.uart_pin);
2329 if (ret) {
2330 ath10k_warn(ar, "failed to set UART TX pin: %d",
2331 ret);
2332 return ret;
2333 }
2334 }
2335
2336 return 0;
2337 }
2338
2339 ret = ath10k_bmi_write32(ar, hi_dbg_uart_txpin, ar->hw_params.uart_pin);
2340 if (ret) {
2341 ath10k_warn(ar, "could not enable UART prints (%d)\n", ret);
2342 return ret;
2343 }
2344
2345 ret = ath10k_bmi_write32(ar, hi_serial_enable, 1);
2346 if (ret) {
2347 ath10k_warn(ar, "could not enable UART prints (%d)\n", ret);
2348 return ret;
2349 }
2350
2351
2352 ret = ath10k_bmi_write32(ar, hi_desired_baud_rate, 19200);
2353 if (ret) {
2354 ath10k_warn(ar, "could not set the baud rate (%d)\n", ret);
2355 return ret;
2356 }
2357
2358 ath10k_info(ar, "UART prints enabled\n");
2359 return 0;
2360}
2361
2362static int ath10k_init_hw_params(struct ath10k *ar)
2363{
2364 const struct ath10k_hw_params *hw_params;
2365 int i;
2366
2367 for (i = 0; i < ARRAY_SIZE(ath10k_hw_params_list); i++) {
2368 hw_params = &ath10k_hw_params_list[i];
2369
2370 if (hw_params->bus == ar->hif.bus &&
2371 hw_params->id == ar->target_version &&
2372 hw_params->dev_id == ar->dev_id)
2373 break;
2374 }
2375
2376 if (i == ARRAY_SIZE(ath10k_hw_params_list)) {
2377 ath10k_err(ar, "Unsupported hardware version: 0x%x\n",
2378 ar->target_version);
2379 return -EINVAL;
2380 }
2381
2382 ar->hw_params = *hw_params;
2383
2384 ath10k_dbg(ar, ATH10K_DBG_BOOT, "Hardware name %s version 0x%x\n",
2385 ar->hw_params.name, ar->target_version);
2386
2387 return 0;
2388}
2389
2390void ath10k_core_start_recovery(struct ath10k *ar)
2391{
2392 if (test_and_set_bit(ATH10K_FLAG_RESTARTING, &ar->dev_flags)) {
2393 ath10k_warn(ar, "already restarting\n");
2394 return;
2395 }
2396
2397 queue_work(ar->workqueue, &ar->restart_work);
2398}
2399EXPORT_SYMBOL(ath10k_core_start_recovery);
2400
2401void ath10k_core_napi_enable(struct ath10k *ar)
2402{
2403 lockdep_assert_held(&ar->conf_mutex);
2404
2405 if (test_bit(ATH10K_FLAG_NAPI_ENABLED, &ar->dev_flags))
2406 return;
2407
2408 napi_enable(&ar->napi);
2409 set_bit(ATH10K_FLAG_NAPI_ENABLED, &ar->dev_flags);
2410}
2411EXPORT_SYMBOL(ath10k_core_napi_enable);
2412
2413void ath10k_core_napi_sync_disable(struct ath10k *ar)
2414{
2415 lockdep_assert_held(&ar->conf_mutex);
2416
2417 if (!test_bit(ATH10K_FLAG_NAPI_ENABLED, &ar->dev_flags))
2418 return;
2419
2420 napi_synchronize(&ar->napi);
2421 napi_disable(&ar->napi);
2422 clear_bit(ATH10K_FLAG_NAPI_ENABLED, &ar->dev_flags);
2423}
2424EXPORT_SYMBOL(ath10k_core_napi_sync_disable);
2425
2426static void ath10k_core_restart(struct work_struct *work)
2427{
2428 struct ath10k *ar = container_of(work, struct ath10k, restart_work);
2429 int ret;
2430
2431 set_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags);
2432
2433
2434
2435
2436 barrier();
2437
2438 ieee80211_stop_queues(ar->hw);
2439 ath10k_drain_tx(ar);
2440 complete(&ar->scan.started);
2441 complete(&ar->scan.completed);
2442 complete(&ar->scan.on_channel);
2443 complete(&ar->offchan_tx_completed);
2444 complete(&ar->install_key_done);
2445 complete(&ar->vdev_setup_done);
2446 complete(&ar->vdev_delete_done);
2447 complete(&ar->thermal.wmi_sync);
2448 complete(&ar->bss_survey_done);
2449 wake_up(&ar->htt.empty_tx_wq);
2450 wake_up(&ar->wmi.tx_credits_wq);
2451 wake_up(&ar->peer_mapping_wq);
2452
2453
2454
2455
2456
2457
2458 cancel_work_sync(&ar->set_coverage_class_work);
2459
2460 mutex_lock(&ar->conf_mutex);
2461
2462 switch (ar->state) {
2463 case ATH10K_STATE_ON:
2464 ar->state = ATH10K_STATE_RESTARTING;
2465 ath10k_halt(ar);
2466 ath10k_scan_finish(ar);
2467 ieee80211_restart_hw(ar->hw);
2468 break;
2469 case ATH10K_STATE_OFF:
2470
2471
2472
2473 ath10k_warn(ar, "cannot restart a device that hasn't been started\n");
2474 break;
2475 case ATH10K_STATE_RESTARTING:
2476
2477 break;
2478 case ATH10K_STATE_RESTARTED:
2479 ar->state = ATH10K_STATE_WEDGED;
2480 fallthrough;
2481 case ATH10K_STATE_WEDGED:
2482 ath10k_warn(ar, "device is wedged, will not restart\n");
2483 break;
2484 case ATH10K_STATE_UTF:
2485 ath10k_warn(ar, "firmware restart in UTF mode not supported\n");
2486 break;
2487 }
2488
2489 mutex_unlock(&ar->conf_mutex);
2490
2491 ret = ath10k_coredump_submit(ar);
2492 if (ret)
2493 ath10k_warn(ar, "failed to send firmware crash dump via devcoredump: %d",
2494 ret);
2495
2496 complete(&ar->driver_recovery);
2497}
2498
2499static void ath10k_core_set_coverage_class_work(struct work_struct *work)
2500{
2501 struct ath10k *ar = container_of(work, struct ath10k,
2502 set_coverage_class_work);
2503
2504 if (ar->hw_params.hw_ops->set_coverage_class)
2505 ar->hw_params.hw_ops->set_coverage_class(ar, -1);
2506}
2507
2508static int ath10k_core_init_firmware_features(struct ath10k *ar)
2509{
2510 struct ath10k_fw_file *fw_file = &ar->normal_mode_fw.fw_file;
2511 int max_num_peers;
2512
2513 if (test_bit(ATH10K_FW_FEATURE_WMI_10_2, fw_file->fw_features) &&
2514 !test_bit(ATH10K_FW_FEATURE_WMI_10X, fw_file->fw_features)) {
2515 ath10k_err(ar, "feature bits corrupted: 10.2 feature requires 10.x feature to be set as well");
2516 return -EINVAL;
2517 }
2518
2519 if (fw_file->wmi_op_version >= ATH10K_FW_WMI_OP_VERSION_MAX) {
2520 ath10k_err(ar, "unsupported WMI OP version (max %d): %d\n",
2521 ATH10K_FW_WMI_OP_VERSION_MAX, fw_file->wmi_op_version);
2522 return -EINVAL;
2523 }
2524
2525 ar->wmi.rx_decap_mode = ATH10K_HW_TXRX_NATIVE_WIFI;
2526 switch (ath10k_cryptmode_param) {
2527 case ATH10K_CRYPT_MODE_HW:
2528 clear_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags);
2529 clear_bit(ATH10K_FLAG_HW_CRYPTO_DISABLED, &ar->dev_flags);
2530 break;
2531 case ATH10K_CRYPT_MODE_SW:
2532 if (!test_bit(ATH10K_FW_FEATURE_RAW_MODE_SUPPORT,
2533 fw_file->fw_features)) {
2534 ath10k_err(ar, "cryptmode > 0 requires raw mode support from firmware");
2535 return -EINVAL;
2536 }
2537
2538 set_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags);
2539 set_bit(ATH10K_FLAG_HW_CRYPTO_DISABLED, &ar->dev_flags);
2540 break;
2541 default:
2542 ath10k_info(ar, "invalid cryptmode: %d\n",
2543 ath10k_cryptmode_param);
2544 return -EINVAL;
2545 }
2546
2547 ar->htt.max_num_amsdu = ATH10K_HTT_MAX_NUM_AMSDU_DEFAULT;
2548 ar->htt.max_num_ampdu = ATH10K_HTT_MAX_NUM_AMPDU_DEFAULT;
2549
2550 if (rawmode) {
2551 if (!test_bit(ATH10K_FW_FEATURE_RAW_MODE_SUPPORT,
2552 fw_file->fw_features)) {
2553 ath10k_err(ar, "rawmode = 1 requires support from firmware");
2554 return -EINVAL;
2555 }
2556 set_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags);
2557 }
2558
2559 if (test_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags)) {
2560 ar->wmi.rx_decap_mode = ATH10K_HW_TXRX_RAW;
2561
2562
2563
2564
2565
2566
2567
2568
2569
2570
2571 ar->htt.max_num_amsdu = 1;
2572 }
2573
2574
2575
2576
2577 if (fw_file->wmi_op_version == ATH10K_FW_WMI_OP_VERSION_UNSET) {
2578 if (test_bit(ATH10K_FW_FEATURE_WMI_10X, fw_file->fw_features)) {
2579 if (test_bit(ATH10K_FW_FEATURE_WMI_10_2,
2580 fw_file->fw_features))
2581 fw_file->wmi_op_version = ATH10K_FW_WMI_OP_VERSION_10_2;
2582 else
2583 fw_file->wmi_op_version = ATH10K_FW_WMI_OP_VERSION_10_1;
2584 } else {
2585 fw_file->wmi_op_version = ATH10K_FW_WMI_OP_VERSION_MAIN;
2586 }
2587 }
2588
2589 switch (fw_file->wmi_op_version) {
2590 case ATH10K_FW_WMI_OP_VERSION_MAIN:
2591 max_num_peers = TARGET_NUM_PEERS;
2592 ar->max_num_stations = TARGET_NUM_STATIONS;
2593 ar->max_num_vdevs = TARGET_NUM_VDEVS;
2594 ar->htt.max_num_pending_tx = TARGET_NUM_MSDU_DESC;
2595 ar->fw_stats_req_mask = WMI_STAT_PDEV | WMI_STAT_VDEV |
2596 WMI_STAT_PEER;
2597 ar->max_spatial_stream = WMI_MAX_SPATIAL_STREAM;
2598 break;
2599 case ATH10K_FW_WMI_OP_VERSION_10_1:
2600 case ATH10K_FW_WMI_OP_VERSION_10_2:
2601 case ATH10K_FW_WMI_OP_VERSION_10_2_4:
2602 if (ath10k_peer_stats_enabled(ar)) {
2603 max_num_peers = TARGET_10X_TX_STATS_NUM_PEERS;
2604 ar->max_num_stations = TARGET_10X_TX_STATS_NUM_STATIONS;
2605 } else {
2606 max_num_peers = TARGET_10X_NUM_PEERS;
2607 ar->max_num_stations = TARGET_10X_NUM_STATIONS;
2608 }
2609 ar->max_num_vdevs = TARGET_10X_NUM_VDEVS;
2610 ar->htt.max_num_pending_tx = TARGET_10X_NUM_MSDU_DESC;
2611 ar->fw_stats_req_mask = WMI_STAT_PEER;
2612 ar->max_spatial_stream = WMI_MAX_SPATIAL_STREAM;
2613 break;
2614 case ATH10K_FW_WMI_OP_VERSION_TLV:
2615 max_num_peers = TARGET_TLV_NUM_PEERS;
2616 ar->max_num_stations = TARGET_TLV_NUM_STATIONS;
2617 ar->max_num_vdevs = TARGET_TLV_NUM_VDEVS;
2618 ar->max_num_tdls_vdevs = TARGET_TLV_NUM_TDLS_VDEVS;
2619 if (ar->hif.bus == ATH10K_BUS_SDIO)
2620 ar->htt.max_num_pending_tx =
2621 TARGET_TLV_NUM_MSDU_DESC_HL;
2622 else
2623 ar->htt.max_num_pending_tx = TARGET_TLV_NUM_MSDU_DESC;
2624 ar->wow.max_num_patterns = TARGET_TLV_NUM_WOW_PATTERNS;
2625 ar->fw_stats_req_mask = WMI_TLV_STAT_PDEV | WMI_TLV_STAT_VDEV |
2626 WMI_TLV_STAT_PEER | WMI_TLV_STAT_PEER_EXTD;
2627 ar->max_spatial_stream = WMI_MAX_SPATIAL_STREAM;
2628 ar->wmi.mgmt_max_num_pending_tx = TARGET_TLV_MGMT_NUM_MSDU_DESC;
2629 break;
2630 case ATH10K_FW_WMI_OP_VERSION_10_4:
2631 max_num_peers = TARGET_10_4_NUM_PEERS;
2632 ar->max_num_stations = TARGET_10_4_NUM_STATIONS;
2633 ar->num_active_peers = TARGET_10_4_ACTIVE_PEERS;
2634 ar->max_num_vdevs = TARGET_10_4_NUM_VDEVS;
2635 ar->num_tids = TARGET_10_4_TGT_NUM_TIDS;
2636 ar->fw_stats_req_mask = WMI_10_4_STAT_PEER |
2637 WMI_10_4_STAT_PEER_EXTD |
2638 WMI_10_4_STAT_VDEV_EXTD;
2639 ar->max_spatial_stream = ar->hw_params.max_spatial_stream;
2640 ar->max_num_tdls_vdevs = TARGET_10_4_NUM_TDLS_VDEVS;
2641
2642 if (test_bit(ATH10K_FW_FEATURE_PEER_FLOW_CONTROL,
2643 fw_file->fw_features))
2644 ar->htt.max_num_pending_tx = TARGET_10_4_NUM_MSDU_DESC_PFC;
2645 else
2646 ar->htt.max_num_pending_tx = TARGET_10_4_NUM_MSDU_DESC;
2647 break;
2648 case ATH10K_FW_WMI_OP_VERSION_UNSET:
2649 case ATH10K_FW_WMI_OP_VERSION_MAX:
2650 default:
2651 WARN_ON(1);
2652 return -EINVAL;
2653 }
2654
2655 if (ar->hw_params.num_peers)
2656 ar->max_num_peers = ar->hw_params.num_peers;
2657 else
2658 ar->max_num_peers = max_num_peers;
2659
2660
2661
2662
2663 if (fw_file->htt_op_version == ATH10K_FW_HTT_OP_VERSION_UNSET) {
2664 switch (fw_file->wmi_op_version) {
2665 case ATH10K_FW_WMI_OP_VERSION_MAIN:
2666 fw_file->htt_op_version = ATH10K_FW_HTT_OP_VERSION_MAIN;
2667 break;
2668 case ATH10K_FW_WMI_OP_VERSION_10_1:
2669 case ATH10K_FW_WMI_OP_VERSION_10_2:
2670 case ATH10K_FW_WMI_OP_VERSION_10_2_4:
2671 fw_file->htt_op_version = ATH10K_FW_HTT_OP_VERSION_10_1;
2672 break;
2673 case ATH10K_FW_WMI_OP_VERSION_TLV:
2674 fw_file->htt_op_version = ATH10K_FW_HTT_OP_VERSION_TLV;
2675 break;
2676 case ATH10K_FW_WMI_OP_VERSION_10_4:
2677 case ATH10K_FW_WMI_OP_VERSION_UNSET:
2678 case ATH10K_FW_WMI_OP_VERSION_MAX:
2679 ath10k_err(ar, "htt op version not found from fw meta data");
2680 return -EINVAL;
2681 }
2682 }
2683
2684 return 0;
2685}
2686
2687static int ath10k_core_reset_rx_filter(struct ath10k *ar)
2688{
2689 int ret;
2690 int vdev_id;
2691 int vdev_type;
2692 int vdev_subtype;
2693 const u8 *vdev_addr;
2694
2695 vdev_id = 0;
2696 vdev_type = WMI_VDEV_TYPE_STA;
2697 vdev_subtype = ath10k_wmi_get_vdev_subtype(ar, WMI_VDEV_SUBTYPE_NONE);
2698 vdev_addr = ar->mac_addr;
2699
2700 ret = ath10k_wmi_vdev_create(ar, vdev_id, vdev_type, vdev_subtype,
2701 vdev_addr);
2702 if (ret) {
2703 ath10k_err(ar, "failed to create dummy vdev: %d\n", ret);
2704 return ret;
2705 }
2706
2707 ret = ath10k_wmi_vdev_delete(ar, vdev_id);
2708 if (ret) {
2709 ath10k_err(ar, "failed to delete dummy vdev: %d\n", ret);
2710 return ret;
2711 }
2712
2713
2714
2715
2716
2717
2718
2719
2720
2721
2722
2723
2724
2725
2726
2727 ret = ath10k_wmi_barrier(ar);
2728 if (ret) {
2729 ath10k_err(ar, "failed to ping firmware: %d\n", ret);
2730 return ret;
2731 }
2732
2733 return 0;
2734}
2735
2736static int ath10k_core_compat_services(struct ath10k *ar)
2737{
2738 struct ath10k_fw_file *fw_file = &ar->normal_mode_fw.fw_file;
2739
2740
2741
2742
2743
2744 switch (fw_file->wmi_op_version) {
2745 case ATH10K_FW_WMI_OP_VERSION_10_1:
2746 case ATH10K_FW_WMI_OP_VERSION_10_2:
2747 case ATH10K_FW_WMI_OP_VERSION_10_2_4:
2748 case ATH10K_FW_WMI_OP_VERSION_10_4:
2749 set_bit(WMI_SERVICE_THERM_THROT, ar->wmi.svc_map);
2750 break;
2751 default:
2752 break;
2753 }
2754
2755 return 0;
2756}
2757
2758#define TGT_IRAM_READ_PER_ITR (8 * 1024)
2759
2760static int ath10k_core_copy_target_iram(struct ath10k *ar)
2761{
2762 const struct ath10k_hw_mem_layout *hw_mem;
2763 const struct ath10k_mem_region *tmp, *mem_region = NULL;
2764 dma_addr_t paddr;
2765 void *vaddr = NULL;
2766 u8 num_read_itr;
2767 int i, ret;
2768 u32 len, remaining_len;
2769
2770
2771
2772
2773
2774 hw_mem = _ath10k_coredump_get_mem_layout(ar);
2775 if (!hw_mem)
2776
2777
2778
2779 return 0;
2780
2781 for (i = 0; i < hw_mem->region_table.size; i++) {
2782 tmp = &hw_mem->region_table.regions[i];
2783 if (tmp->type == ATH10K_MEM_REGION_TYPE_REG) {
2784 mem_region = tmp;
2785 break;
2786 }
2787 }
2788
2789 if (!mem_region)
2790 return -ENOMEM;
2791
2792 for (i = 0; i < ar->wmi.num_mem_chunks; i++) {
2793 if (ar->wmi.mem_chunks[i].req_id ==
2794 WMI_IRAM_RECOVERY_HOST_MEM_REQ_ID) {
2795 vaddr = ar->wmi.mem_chunks[i].vaddr;
2796 len = ar->wmi.mem_chunks[i].len;
2797 break;
2798 }
2799 }
2800
2801 if (!vaddr || !len) {
2802 ath10k_warn(ar, "No allocated memory for IRAM back up");
2803 return -ENOMEM;
2804 }
2805
2806 len = (len < mem_region->len) ? len : mem_region->len;
2807 paddr = mem_region->start;
2808 num_read_itr = len / TGT_IRAM_READ_PER_ITR;
2809 remaining_len = len % TGT_IRAM_READ_PER_ITR;
2810 for (i = 0; i < num_read_itr; i++) {
2811 ret = ath10k_hif_diag_read(ar, paddr, vaddr,
2812 TGT_IRAM_READ_PER_ITR);
2813 if (ret) {
2814 ath10k_warn(ar, "failed to copy firmware IRAM contents: %d",
2815 ret);
2816 return ret;
2817 }
2818
2819 paddr += TGT_IRAM_READ_PER_ITR;
2820 vaddr += TGT_IRAM_READ_PER_ITR;
2821 }
2822
2823 if (remaining_len) {
2824 ret = ath10k_hif_diag_read(ar, paddr, vaddr, remaining_len);
2825 if (ret) {
2826 ath10k_warn(ar, "failed to copy firmware IRAM contents: %d",
2827 ret);
2828 return ret;
2829 }
2830 }
2831
2832 ath10k_dbg(ar, ATH10K_DBG_BOOT, "target IRAM back up completed\n");
2833
2834 return 0;
2835}
2836
2837int ath10k_core_start(struct ath10k *ar, enum ath10k_firmware_mode mode,
2838 const struct ath10k_fw_components *fw)
2839{
2840 int status;
2841 u32 val;
2842
2843 lockdep_assert_held(&ar->conf_mutex);
2844
2845 clear_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags);
2846
2847 ar->running_fw = fw;
2848
2849 if (!test_bit(ATH10K_FW_FEATURE_NON_BMI,
2850 ar->running_fw->fw_file.fw_features)) {
2851 ath10k_bmi_start(ar);
2852
2853
2854 if (ar->hw_params.hw_ops->enable_pll_clk) {
2855 status = ar->hw_params.hw_ops->enable_pll_clk(ar);
2856 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot enable pll ret %d\n",
2857 status);
2858 }
2859
2860 if (ath10k_init_configure_target(ar)) {
2861 status = -EINVAL;
2862 goto err;
2863 }
2864
2865 status = ath10k_download_cal_data(ar);
2866 if (status)
2867 goto err;
2868
2869
2870
2871
2872
2873
2874
2875
2876 if (test_bit(ATH10K_FW_FEATURE_SUPPORTS_SKIP_CLOCK_INIT,
2877 ar->running_fw->fw_file.fw_features)) {
2878 status = ath10k_bmi_write32(ar, hi_skip_clock_init, 1);
2879 if (status) {
2880 ath10k_err(ar, "could not write to skip_clock_init: %d\n",
2881 status);
2882 goto err;
2883 }
2884 }
2885
2886 status = ath10k_download_fw(ar);
2887 if (status)
2888 goto err;
2889
2890 status = ath10k_init_uart(ar);
2891 if (status)
2892 goto err;
2893
2894 if (ar->hif.bus == ATH10K_BUS_SDIO) {
2895 status = ath10k_init_sdio(ar, mode);
2896 if (status) {
2897 ath10k_err(ar, "failed to init SDIO: %d\n", status);
2898 goto err;
2899 }
2900 }
2901 }
2902
2903 ar->htc.htc_ops.target_send_suspend_complete =
2904 ath10k_send_suspend_complete;
2905
2906 status = ath10k_htc_init(ar);
2907 if (status) {
2908 ath10k_err(ar, "could not init HTC (%d)\n", status);
2909 goto err;
2910 }
2911
2912 if (!test_bit(ATH10K_FW_FEATURE_NON_BMI,
2913 ar->running_fw->fw_file.fw_features)) {
2914 status = ath10k_bmi_done(ar);
2915 if (status)
2916 goto err;
2917 }
2918
2919 status = ath10k_wmi_attach(ar);
2920 if (status) {
2921 ath10k_err(ar, "WMI attach failed: %d\n", status);
2922 goto err;
2923 }
2924
2925 status = ath10k_htt_init(ar);
2926 if (status) {
2927 ath10k_err(ar, "failed to init htt: %d\n", status);
2928 goto err_wmi_detach;
2929 }
2930
2931 status = ath10k_htt_tx_start(&ar->htt);
2932 if (status) {
2933 ath10k_err(ar, "failed to alloc htt tx: %d\n", status);
2934 goto err_wmi_detach;
2935 }
2936
2937
2938
2939
2940 ar->htt.rx_ring.in_ord_rx = !!(test_bit(WMI_SERVICE_RX_FULL_REORDER,
2941 ar->wmi.svc_map));
2942
2943 status = ath10k_htt_rx_alloc(&ar->htt);
2944 if (status) {
2945 ath10k_err(ar, "failed to alloc htt rx: %d\n", status);
2946 goto err_htt_tx_detach;
2947 }
2948
2949 status = ath10k_hif_start(ar);
2950 if (status) {
2951 ath10k_err(ar, "could not start HIF: %d\n", status);
2952 goto err_htt_rx_detach;
2953 }
2954
2955 status = ath10k_htc_wait_target(&ar->htc);
2956 if (status) {
2957 ath10k_err(ar, "failed to connect to HTC: %d\n", status);
2958 goto err_hif_stop;
2959 }
2960
2961 status = ath10k_hif_start_post(ar);
2962 if (status) {
2963 ath10k_err(ar, "failed to swap mailbox: %d\n", status);
2964 goto err_hif_stop;
2965 }
2966
2967 if (mode == ATH10K_FIRMWARE_MODE_NORMAL) {
2968 status = ath10k_htt_connect(&ar->htt);
2969 if (status) {
2970 ath10k_err(ar, "failed to connect htt (%d)\n", status);
2971 goto err_hif_stop;
2972 }
2973 }
2974
2975 status = ath10k_wmi_connect(ar);
2976 if (status) {
2977 ath10k_err(ar, "could not connect wmi: %d\n", status);
2978 goto err_hif_stop;
2979 }
2980
2981 status = ath10k_htc_start(&ar->htc);
2982 if (status) {
2983 ath10k_err(ar, "failed to start htc: %d\n", status);
2984 goto err_hif_stop;
2985 }
2986
2987 if (mode == ATH10K_FIRMWARE_MODE_NORMAL) {
2988 status = ath10k_wmi_wait_for_service_ready(ar);
2989 if (status) {
2990 ath10k_warn(ar, "wmi service ready event not received");
2991 goto err_hif_stop;
2992 }
2993 }
2994
2995 ath10k_dbg(ar, ATH10K_DBG_BOOT, "firmware %s booted\n",
2996 ar->hw->wiphy->fw_version);
2997
2998 if (test_bit(ATH10K_FW_FEATURE_IRAM_RECOVERY,
2999 ar->running_fw->fw_file.fw_features)) {
3000 status = ath10k_core_copy_target_iram(ar);
3001 if (status) {
3002 ath10k_warn(ar, "failed to copy target iram contents: %d",
3003 status);
3004 goto err_hif_stop;
3005 }
3006 }
3007
3008 if (test_bit(WMI_SERVICE_EXT_RES_CFG_SUPPORT, ar->wmi.svc_map) &&
3009 mode == ATH10K_FIRMWARE_MODE_NORMAL) {
3010 val = 0;
3011 if (ath10k_peer_stats_enabled(ar))
3012 val = WMI_10_4_PEER_STATS;
3013
3014
3015 val |= WMI_10_4_VDEV_STATS;
3016
3017 if (test_bit(WMI_SERVICE_BSS_CHANNEL_INFO_64, ar->wmi.svc_map))
3018 val |= WMI_10_4_BSS_CHANNEL_INFO_64;
3019
3020 ath10k_core_fetch_btcoex_dt(ar);
3021
3022
3023
3024
3025
3026
3027
3028
3029
3030
3031
3032 if (test_bit(WMI_SERVICE_COEX_GPIO, ar->wmi.svc_map) &&
3033 test_bit(ATH10K_FW_FEATURE_BTCOEX_PARAM,
3034 ar->running_fw->fw_file.fw_features) &&
3035 ar->coex_support)
3036 val |= WMI_10_4_COEX_GPIO_SUPPORT;
3037
3038 if (test_bit(WMI_SERVICE_TDLS_EXPLICIT_MODE_ONLY,
3039 ar->wmi.svc_map))
3040 val |= WMI_10_4_TDLS_EXPLICIT_MODE_ONLY;
3041
3042 if (test_bit(WMI_SERVICE_TDLS_UAPSD_BUFFER_STA,
3043 ar->wmi.svc_map))
3044 val |= WMI_10_4_TDLS_UAPSD_BUFFER_STA;
3045
3046 if (test_bit(WMI_SERVICE_TX_DATA_ACK_RSSI,
3047 ar->wmi.svc_map))
3048 val |= WMI_10_4_TX_DATA_ACK_RSSI;
3049
3050 if (test_bit(WMI_SERVICE_REPORT_AIRTIME, ar->wmi.svc_map))
3051 val |= WMI_10_4_REPORT_AIRTIME;
3052
3053 if (test_bit(WMI_SERVICE_EXT_PEER_TID_CONFIGS_SUPPORT,
3054 ar->wmi.svc_map))
3055 val |= WMI_10_4_EXT_PEER_TID_CONFIGS_SUPPORT;
3056
3057 status = ath10k_mac_ext_resource_config(ar, val);
3058 if (status) {
3059 ath10k_err(ar,
3060 "failed to send ext resource cfg command : %d\n",
3061 status);
3062 goto err_hif_stop;
3063 }
3064 }
3065
3066 status = ath10k_wmi_cmd_init(ar);
3067 if (status) {
3068 ath10k_err(ar, "could not send WMI init command (%d)\n",
3069 status);
3070 goto err_hif_stop;
3071 }
3072
3073 status = ath10k_wmi_wait_for_unified_ready(ar);
3074 if (status) {
3075 ath10k_err(ar, "wmi unified ready event not received\n");
3076 goto err_hif_stop;
3077 }
3078
3079 status = ath10k_core_compat_services(ar);
3080 if (status) {
3081 ath10k_err(ar, "compat services failed: %d\n", status);
3082 goto err_hif_stop;
3083 }
3084
3085 status = ath10k_wmi_pdev_set_base_macaddr(ar, ar->mac_addr);
3086 if (status && status != -EOPNOTSUPP) {
3087 ath10k_err(ar,
3088 "failed to set base mac address: %d\n", status);
3089 goto err_hif_stop;
3090 }
3091
3092
3093
3094
3095
3096
3097
3098
3099
3100
3101
3102
3103
3104
3105 if (ar->hw_params.hw_filter_reset_required &&
3106 mode == ATH10K_FIRMWARE_MODE_NORMAL) {
3107 status = ath10k_core_reset_rx_filter(ar);
3108 if (status) {
3109 ath10k_err(ar,
3110 "failed to reset rx filter: %d\n", status);
3111 goto err_hif_stop;
3112 }
3113 }
3114
3115 status = ath10k_htt_rx_ring_refill(ar);
3116 if (status) {
3117 ath10k_err(ar, "failed to refill htt rx ring: %d\n", status);
3118 goto err_hif_stop;
3119 }
3120
3121 if (ar->max_num_vdevs >= 64)
3122 ar->free_vdev_map = 0xFFFFFFFFFFFFFFFFLL;
3123 else
3124 ar->free_vdev_map = (1LL << ar->max_num_vdevs) - 1;
3125
3126 INIT_LIST_HEAD(&ar->arvifs);
3127
3128
3129 if (mode == ATH10K_FIRMWARE_MODE_NORMAL) {
3130 status = ath10k_htt_setup(&ar->htt);
3131 if (status) {
3132 ath10k_err(ar, "failed to setup htt: %d\n", status);
3133 goto err_hif_stop;
3134 }
3135 }
3136
3137 status = ath10k_debug_start(ar);
3138 if (status)
3139 goto err_hif_stop;
3140
3141 status = ath10k_hif_set_target_log_mode(ar, fw_diag_log);
3142 if (status && status != -EOPNOTSUPP) {
3143 ath10k_warn(ar, "set target log mode failed: %d\n", status);
3144 goto err_hif_stop;
3145 }
3146
3147 return 0;
3148
3149err_hif_stop:
3150 ath10k_hif_stop(ar);
3151err_htt_rx_detach:
3152 ath10k_htt_rx_free(&ar->htt);
3153err_htt_tx_detach:
3154 ath10k_htt_tx_free(&ar->htt);
3155err_wmi_detach:
3156 ath10k_wmi_detach(ar);
3157err:
3158 return status;
3159}
3160EXPORT_SYMBOL(ath10k_core_start);
3161
3162int ath10k_wait_for_suspend(struct ath10k *ar, u32 suspend_opt)
3163{
3164 int ret;
3165 unsigned long time_left;
3166
3167 reinit_completion(&ar->target_suspend);
3168
3169 ret = ath10k_wmi_pdev_suspend_target(ar, suspend_opt);
3170 if (ret) {
3171 ath10k_warn(ar, "could not suspend target (%d)\n", ret);
3172 return ret;
3173 }
3174
3175 time_left = wait_for_completion_timeout(&ar->target_suspend, 1 * HZ);
3176
3177 if (!time_left) {
3178 ath10k_warn(ar, "suspend timed out - target pause event never came\n");
3179 return -ETIMEDOUT;
3180 }
3181
3182 return 0;
3183}
3184
3185void ath10k_core_stop(struct ath10k *ar)
3186{
3187 lockdep_assert_held(&ar->conf_mutex);
3188 ath10k_debug_stop(ar);
3189
3190
3191 if (ar->state != ATH10K_STATE_RESTARTING &&
3192 ar->state != ATH10K_STATE_UTF)
3193 ath10k_wait_for_suspend(ar, WMI_PDEV_SUSPEND_AND_DISABLE_INTR);
3194
3195 ath10k_hif_stop(ar);
3196 ath10k_htt_tx_stop(&ar->htt);
3197 ath10k_htt_rx_free(&ar->htt);
3198 ath10k_wmi_detach(ar);
3199
3200 ar->id.bmi_ids_valid = false;
3201}
3202EXPORT_SYMBOL(ath10k_core_stop);
3203
3204
3205
3206
3207
3208
3209static int ath10k_core_probe_fw(struct ath10k *ar)
3210{
3211 struct bmi_target_info target_info;
3212 int ret = 0;
3213
3214 ret = ath10k_hif_power_up(ar, ATH10K_FIRMWARE_MODE_NORMAL);
3215 if (ret) {
3216 ath10k_err(ar, "could not power on hif bus (%d)\n", ret);
3217 return ret;
3218 }
3219
3220 switch (ar->hif.bus) {
3221 case ATH10K_BUS_SDIO:
3222 memset(&target_info, 0, sizeof(target_info));
3223 ret = ath10k_bmi_get_target_info_sdio(ar, &target_info);
3224 if (ret) {
3225 ath10k_err(ar, "could not get target info (%d)\n", ret);
3226 goto err_power_down;
3227 }
3228 ar->target_version = target_info.version;
3229 ar->hw->wiphy->hw_version = target_info.version;
3230 break;
3231 case ATH10K_BUS_PCI:
3232 case ATH10K_BUS_AHB:
3233 case ATH10K_BUS_USB:
3234 memset(&target_info, 0, sizeof(target_info));
3235 ret = ath10k_bmi_get_target_info(ar, &target_info);
3236 if (ret) {
3237 ath10k_err(ar, "could not get target info (%d)\n", ret);
3238 goto err_power_down;
3239 }
3240 ar->target_version = target_info.version;
3241 ar->hw->wiphy->hw_version = target_info.version;
3242 break;
3243 case ATH10K_BUS_SNOC:
3244 memset(&target_info, 0, sizeof(target_info));
3245 ret = ath10k_hif_get_target_info(ar, &target_info);
3246 if (ret) {
3247 ath10k_err(ar, "could not get target info (%d)\n", ret);
3248 goto err_power_down;
3249 }
3250 ar->target_version = target_info.version;
3251 ar->hw->wiphy->hw_version = target_info.version;
3252 break;
3253 default:
3254 ath10k_err(ar, "incorrect hif bus type: %d\n", ar->hif.bus);
3255 }
3256
3257 ret = ath10k_init_hw_params(ar);
3258 if (ret) {
3259 ath10k_err(ar, "could not get hw params (%d)\n", ret);
3260 goto err_power_down;
3261 }
3262
3263 ret = ath10k_core_fetch_firmware_files(ar);
3264 if (ret) {
3265 ath10k_err(ar, "could not fetch firmware files (%d)\n", ret);
3266 goto err_power_down;
3267 }
3268
3269 BUILD_BUG_ON(sizeof(ar->hw->wiphy->fw_version) !=
3270 sizeof(ar->normal_mode_fw.fw_file.fw_version));
3271 memcpy(ar->hw->wiphy->fw_version, ar->normal_mode_fw.fw_file.fw_version,
3272 sizeof(ar->hw->wiphy->fw_version));
3273
3274 ath10k_debug_print_hwfw_info(ar);
3275
3276 if (!test_bit(ATH10K_FW_FEATURE_NON_BMI,
3277 ar->normal_mode_fw.fw_file.fw_features)) {
3278 ret = ath10k_core_pre_cal_download(ar);
3279 if (ret) {
3280
3281
3282
3283 ath10k_dbg(ar, ATH10K_DBG_BOOT,
3284 "could not load pre cal data: %d\n", ret);
3285 }
3286
3287 ret = ath10k_core_get_board_id_from_otp(ar);
3288 if (ret && ret != -EOPNOTSUPP) {
3289 ath10k_err(ar, "failed to get board id from otp: %d\n",
3290 ret);
3291 goto err_free_firmware_files;
3292 }
3293
3294 ret = ath10k_core_check_smbios(ar);
3295 if (ret)
3296 ath10k_dbg(ar, ATH10K_DBG_BOOT, "SMBIOS bdf variant name not set.\n");
3297
3298 ret = ath10k_core_check_dt(ar);
3299 if (ret)
3300 ath10k_dbg(ar, ATH10K_DBG_BOOT, "DT bdf variant name not set.\n");
3301
3302 ret = ath10k_core_fetch_board_file(ar, ATH10K_BD_IE_BOARD);
3303 if (ret) {
3304 ath10k_err(ar, "failed to fetch board file: %d\n", ret);
3305 goto err_free_firmware_files;
3306 }
3307
3308 ath10k_debug_print_board_info(ar);
3309 }
3310
3311 device_get_mac_address(ar->dev, ar->mac_addr);
3312
3313 ret = ath10k_core_init_firmware_features(ar);
3314 if (ret) {
3315 ath10k_err(ar, "fatal problem with firmware features: %d\n",
3316 ret);
3317 goto err_free_firmware_files;
3318 }
3319
3320 if (!test_bit(ATH10K_FW_FEATURE_NON_BMI,
3321 ar->normal_mode_fw.fw_file.fw_features)) {
3322 ret = ath10k_swap_code_seg_init(ar,
3323 &ar->normal_mode_fw.fw_file);
3324 if (ret) {
3325 ath10k_err(ar, "failed to initialize code swap segment: %d\n",
3326 ret);
3327 goto err_free_firmware_files;
3328 }
3329 }
3330
3331 mutex_lock(&ar->conf_mutex);
3332
3333 ret = ath10k_core_start(ar, ATH10K_FIRMWARE_MODE_NORMAL,
3334 &ar->normal_mode_fw);
3335 if (ret) {
3336 ath10k_err(ar, "could not init core (%d)\n", ret);
3337 goto err_unlock;
3338 }
3339
3340 ath10k_debug_print_boot_info(ar);
3341 ath10k_core_stop(ar);
3342
3343 mutex_unlock(&ar->conf_mutex);
3344
3345 ath10k_hif_power_down(ar);
3346 return 0;
3347
3348err_unlock:
3349 mutex_unlock(&ar->conf_mutex);
3350
3351err_free_firmware_files:
3352 ath10k_core_free_firmware_files(ar);
3353
3354err_power_down:
3355 ath10k_hif_power_down(ar);
3356
3357 return ret;
3358}
3359
3360static void ath10k_core_register_work(struct work_struct *work)
3361{
3362 struct ath10k *ar = container_of(work, struct ath10k, register_work);
3363 int status;
3364
3365
3366 set_bit(ATH10K_FLAG_PEER_STATS, &ar->dev_flags);
3367
3368 status = ath10k_core_probe_fw(ar);
3369 if (status) {
3370 ath10k_err(ar, "could not probe fw (%d)\n", status);
3371 goto err;
3372 }
3373
3374 status = ath10k_mac_register(ar);
3375 if (status) {
3376 ath10k_err(ar, "could not register to mac80211 (%d)\n", status);
3377 goto err_release_fw;
3378 }
3379
3380 status = ath10k_coredump_register(ar);
3381 if (status) {
3382 ath10k_err(ar, "unable to register coredump\n");
3383 goto err_unregister_mac;
3384 }
3385
3386 status = ath10k_debug_register(ar);
3387 if (status) {
3388 ath10k_err(ar, "unable to initialize debugfs\n");
3389 goto err_unregister_coredump;
3390 }
3391
3392 status = ath10k_spectral_create(ar);
3393 if (status) {
3394 ath10k_err(ar, "failed to initialize spectral\n");
3395 goto err_debug_destroy;
3396 }
3397
3398 status = ath10k_thermal_register(ar);
3399 if (status) {
3400 ath10k_err(ar, "could not register thermal device: %d\n",
3401 status);
3402 goto err_spectral_destroy;
3403 }
3404
3405 set_bit(ATH10K_FLAG_CORE_REGISTERED, &ar->dev_flags);
3406 return;
3407
3408err_spectral_destroy:
3409 ath10k_spectral_destroy(ar);
3410err_debug_destroy:
3411 ath10k_debug_destroy(ar);
3412err_unregister_coredump:
3413 ath10k_coredump_unregister(ar);
3414err_unregister_mac:
3415 ath10k_mac_unregister(ar);
3416err_release_fw:
3417 ath10k_core_free_firmware_files(ar);
3418err:
3419
3420
3421
3422 return;
3423}
3424
3425int ath10k_core_register(struct ath10k *ar,
3426 const struct ath10k_bus_params *bus_params)
3427{
3428 ar->bus_param = *bus_params;
3429
3430 queue_work(ar->workqueue, &ar->register_work);
3431
3432 return 0;
3433}
3434EXPORT_SYMBOL(ath10k_core_register);
3435
3436void ath10k_core_unregister(struct ath10k *ar)
3437{
3438 cancel_work_sync(&ar->register_work);
3439
3440 if (!test_bit(ATH10K_FLAG_CORE_REGISTERED, &ar->dev_flags))
3441 return;
3442
3443 ath10k_thermal_unregister(ar);
3444
3445
3446
3447
3448 ath10k_spectral_destroy(ar);
3449
3450
3451
3452
3453
3454 ath10k_mac_unregister(ar);
3455
3456 ath10k_testmode_destroy(ar);
3457
3458 ath10k_core_free_firmware_files(ar);
3459 ath10k_core_free_board_files(ar);
3460
3461 ath10k_debug_unregister(ar);
3462}
3463EXPORT_SYMBOL(ath10k_core_unregister);
3464
3465struct ath10k *ath10k_core_create(size_t priv_size, struct device *dev,
3466 enum ath10k_bus bus,
3467 enum ath10k_hw_rev hw_rev,
3468 const struct ath10k_hif_ops *hif_ops)
3469{
3470 struct ath10k *ar;
3471 int ret;
3472
3473 ar = ath10k_mac_create(priv_size);
3474 if (!ar)
3475 return NULL;
3476
3477 ar->ath_common.priv = ar;
3478 ar->ath_common.hw = ar->hw;
3479 ar->dev = dev;
3480 ar->hw_rev = hw_rev;
3481 ar->hif.ops = hif_ops;
3482 ar->hif.bus = bus;
3483
3484 switch (hw_rev) {
3485 case ATH10K_HW_QCA988X:
3486 case ATH10K_HW_QCA9887:
3487 ar->regs = &qca988x_regs;
3488 ar->hw_ce_regs = &qcax_ce_regs;
3489 ar->hw_values = &qca988x_values;
3490 break;
3491 case ATH10K_HW_QCA6174:
3492 case ATH10K_HW_QCA9377:
3493 ar->regs = &qca6174_regs;
3494 ar->hw_ce_regs = &qcax_ce_regs;
3495 ar->hw_values = &qca6174_values;
3496 break;
3497 case ATH10K_HW_QCA99X0:
3498 case ATH10K_HW_QCA9984:
3499 ar->regs = &qca99x0_regs;
3500 ar->hw_ce_regs = &qcax_ce_regs;
3501 ar->hw_values = &qca99x0_values;
3502 break;
3503 case ATH10K_HW_QCA9888:
3504 ar->regs = &qca99x0_regs;
3505 ar->hw_ce_regs = &qcax_ce_regs;
3506 ar->hw_values = &qca9888_values;
3507 break;
3508 case ATH10K_HW_QCA4019:
3509 ar->regs = &qca4019_regs;
3510 ar->hw_ce_regs = &qcax_ce_regs;
3511 ar->hw_values = &qca4019_values;
3512 break;
3513 case ATH10K_HW_WCN3990:
3514 ar->regs = &wcn3990_regs;
3515 ar->hw_ce_regs = &wcn3990_ce_regs;
3516 ar->hw_values = &wcn3990_values;
3517 break;
3518 default:
3519 ath10k_err(ar, "unsupported core hardware revision %d\n",
3520 hw_rev);
3521 ret = -ENOTSUPP;
3522 goto err_free_mac;
3523 }
3524
3525 init_completion(&ar->scan.started);
3526 init_completion(&ar->scan.completed);
3527 init_completion(&ar->scan.on_channel);
3528 init_completion(&ar->target_suspend);
3529 init_completion(&ar->driver_recovery);
3530 init_completion(&ar->wow.wakeup_completed);
3531
3532 init_completion(&ar->install_key_done);
3533 init_completion(&ar->vdev_setup_done);
3534 init_completion(&ar->vdev_delete_done);
3535 init_completion(&ar->thermal.wmi_sync);
3536 init_completion(&ar->bss_survey_done);
3537 init_completion(&ar->peer_delete_done);
3538 init_completion(&ar->peer_stats_info_complete);
3539
3540 INIT_DELAYED_WORK(&ar->scan.timeout, ath10k_scan_timeout_work);
3541
3542 ar->workqueue = create_singlethread_workqueue("ath10k_wq");
3543 if (!ar->workqueue)
3544 goto err_free_mac;
3545
3546 ar->workqueue_aux = create_singlethread_workqueue("ath10k_aux_wq");
3547 if (!ar->workqueue_aux)
3548 goto err_free_wq;
3549
3550 ar->workqueue_tx_complete =
3551 create_singlethread_workqueue("ath10k_tx_complete_wq");
3552 if (!ar->workqueue_tx_complete)
3553 goto err_free_aux_wq;
3554
3555 mutex_init(&ar->conf_mutex);
3556 mutex_init(&ar->dump_mutex);
3557 spin_lock_init(&ar->data_lock);
3558
3559 INIT_LIST_HEAD(&ar->peers);
3560 init_waitqueue_head(&ar->peer_mapping_wq);
3561 init_waitqueue_head(&ar->htt.empty_tx_wq);
3562 init_waitqueue_head(&ar->wmi.tx_credits_wq);
3563
3564 skb_queue_head_init(&ar->htt.rx_indication_head);
3565
3566 init_completion(&ar->offchan_tx_completed);
3567 INIT_WORK(&ar->offchan_tx_work, ath10k_offchan_tx_work);
3568 skb_queue_head_init(&ar->offchan_tx_queue);
3569
3570 INIT_WORK(&ar->wmi_mgmt_tx_work, ath10k_mgmt_over_wmi_tx_work);
3571 skb_queue_head_init(&ar->wmi_mgmt_tx_queue);
3572
3573 INIT_WORK(&ar->register_work, ath10k_core_register_work);
3574 INIT_WORK(&ar->restart_work, ath10k_core_restart);
3575 INIT_WORK(&ar->set_coverage_class_work,
3576 ath10k_core_set_coverage_class_work);
3577
3578 init_dummy_netdev(&ar->napi_dev);
3579
3580 ret = ath10k_coredump_create(ar);
3581 if (ret)
3582 goto err_free_tx_complete;
3583
3584 ret = ath10k_debug_create(ar);
3585 if (ret)
3586 goto err_free_coredump;
3587
3588 return ar;
3589
3590err_free_coredump:
3591 ath10k_coredump_destroy(ar);
3592err_free_tx_complete:
3593 destroy_workqueue(ar->workqueue_tx_complete);
3594err_free_aux_wq:
3595 destroy_workqueue(ar->workqueue_aux);
3596err_free_wq:
3597 destroy_workqueue(ar->workqueue);
3598err_free_mac:
3599 ath10k_mac_destroy(ar);
3600
3601 return NULL;
3602}
3603EXPORT_SYMBOL(ath10k_core_create);
3604
3605void ath10k_core_destroy(struct ath10k *ar)
3606{
3607 destroy_workqueue(ar->workqueue);
3608
3609 destroy_workqueue(ar->workqueue_aux);
3610
3611 destroy_workqueue(ar->workqueue_tx_complete);
3612
3613 ath10k_debug_destroy(ar);
3614 ath10k_coredump_destroy(ar);
3615 ath10k_htt_tx_destroy(&ar->htt);
3616 ath10k_wmi_free_host_mem(ar);
3617 ath10k_mac_destroy(ar);
3618}
3619EXPORT_SYMBOL(ath10k_core_destroy);
3620
3621MODULE_AUTHOR("Qualcomm Atheros");
3622MODULE_DESCRIPTION("Core module for Qualcomm Atheros 802.11ac wireless LAN cards.");
3623MODULE_LICENSE("Dual BSD/GPL");
3624
