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2
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4
5#ifndef __RTK_MAIN_H_
6#define __RTK_MAIN_H_
7
8#include <net/mac80211.h>
9#include <linux/vmalloc.h>
10#include <linux/firmware.h>
11#include <linux/average.h>
12#include <linux/bitops.h>
13#include <linux/bitfield.h>
14#include <linux/iopoll.h>
15#include <linux/interrupt.h>
16#include <linux/workqueue.h>
17
18#include "util.h"
19
20#define RTW_NAPI_WEIGHT_NUM 64
21#define RTW_MAX_MAC_ID_NUM 32
22#define RTW_MAX_SEC_CAM_NUM 32
23#define MAX_PG_CAM_BACKUP_NUM 8
24
25#define RTW_SCAN_MAX_SSIDS 4
26#define RTW_SCAN_MAX_IE_LEN 128
27
28#define RTW_MAX_PATTERN_NUM 12
29#define RTW_MAX_PATTERN_MASK_SIZE 16
30#define RTW_MAX_PATTERN_SIZE 128
31
32#define RTW_WATCH_DOG_DELAY_TIME round_jiffies_relative(HZ * 2)
33
34#define RFREG_MASK 0xfffff
35#define INV_RF_DATA 0xffffffff
36#define TX_PAGE_SIZE_SHIFT 7
37
38#define RTW_CHANNEL_WIDTH_MAX 3
39#define RTW_RF_PATH_MAX 4
40#define HW_FEATURE_LEN 13
41
42#define RTW_TP_SHIFT 18
43
44extern bool rtw_bf_support;
45extern bool rtw_disable_lps_deep_mode;
46extern unsigned int rtw_debug_mask;
47extern bool rtw_edcca_enabled;
48extern const struct ieee80211_ops rtw_ops;
49
50#define RTW_MAX_CHANNEL_NUM_2G 14
51#define RTW_MAX_CHANNEL_NUM_5G 49
52
53struct rtw_dev;
54
55enum rtw_hci_type {
56 RTW_HCI_TYPE_PCIE,
57 RTW_HCI_TYPE_USB,
58 RTW_HCI_TYPE_SDIO,
59
60 RTW_HCI_TYPE_UNDEFINE,
61};
62
63struct rtw_hci {
64 struct rtw_hci_ops *ops;
65 enum rtw_hci_type type;
66
67 u32 rpwm_addr;
68 u32 cpwm_addr;
69
70 u8 bulkout_num;
71};
72
73#define IS_CH_5G_BAND_1(channel) ((channel) >= 36 && (channel <= 48))
74#define IS_CH_5G_BAND_2(channel) ((channel) >= 52 && (channel <= 64))
75#define IS_CH_5G_BAND_3(channel) ((channel) >= 100 && (channel <= 144))
76#define IS_CH_5G_BAND_4(channel) ((channel) >= 149 && (channel <= 177))
77
78#define IS_CH_5G_BAND_MID(channel) \
79 (IS_CH_5G_BAND_2(channel) || IS_CH_5G_BAND_3(channel))
80
81#define IS_CH_2G_BAND(channel) ((channel) <= 14)
82#define IS_CH_5G_BAND(channel) \
83 (IS_CH_5G_BAND_1(channel) || IS_CH_5G_BAND_2(channel) || \
84 IS_CH_5G_BAND_3(channel) || IS_CH_5G_BAND_4(channel))
85
86enum rtw_supported_band {
87 RTW_BAND_2G = BIT(NL80211_BAND_2GHZ),
88 RTW_BAND_5G = BIT(NL80211_BAND_5GHZ),
89 RTW_BAND_60G = BIT(NL80211_BAND_60GHZ),
90};
91
92
93#define RTW_MAX_CHANNEL_WIDTH RTW_CHANNEL_WIDTH_80
94
95enum rtw_bandwidth {
96 RTW_CHANNEL_WIDTH_20 = 0,
97 RTW_CHANNEL_WIDTH_40 = 1,
98 RTW_CHANNEL_WIDTH_80 = 2,
99 RTW_CHANNEL_WIDTH_160 = 3,
100 RTW_CHANNEL_WIDTH_80_80 = 4,
101 RTW_CHANNEL_WIDTH_5 = 5,
102 RTW_CHANNEL_WIDTH_10 = 6,
103};
104
105enum rtw_sc_offset {
106 RTW_SC_DONT_CARE = 0,
107 RTW_SC_20_UPPER = 1,
108 RTW_SC_20_LOWER = 2,
109 RTW_SC_20_UPMOST = 3,
110 RTW_SC_20_LOWEST = 4,
111 RTW_SC_40_UPPER = 9,
112 RTW_SC_40_LOWER = 10,
113};
114
115enum rtw_net_type {
116 RTW_NET_NO_LINK = 0,
117 RTW_NET_AD_HOC = 1,
118 RTW_NET_MGD_LINKED = 2,
119 RTW_NET_AP_MODE = 3,
120};
121
122enum rtw_rf_type {
123 RF_1T1R = 0,
124 RF_1T2R = 1,
125 RF_2T2R = 2,
126 RF_2T3R = 3,
127 RF_2T4R = 4,
128 RF_3T3R = 5,
129 RF_3T4R = 6,
130 RF_4T4R = 7,
131 RF_TYPE_MAX,
132};
133
134enum rtw_rf_path {
135 RF_PATH_A = 0,
136 RF_PATH_B = 1,
137 RF_PATH_C = 2,
138 RF_PATH_D = 3,
139};
140
141enum rtw_bb_path {
142 BB_PATH_A = BIT(0),
143 BB_PATH_B = BIT(1),
144 BB_PATH_C = BIT(2),
145 BB_PATH_D = BIT(3),
146
147 BB_PATH_AB = (BB_PATH_A | BB_PATH_B),
148 BB_PATH_AC = (BB_PATH_A | BB_PATH_C),
149 BB_PATH_AD = (BB_PATH_A | BB_PATH_D),
150 BB_PATH_BC = (BB_PATH_B | BB_PATH_C),
151 BB_PATH_BD = (BB_PATH_B | BB_PATH_D),
152 BB_PATH_CD = (BB_PATH_C | BB_PATH_D),
153
154 BB_PATH_ABC = (BB_PATH_A | BB_PATH_B | BB_PATH_C),
155 BB_PATH_ABD = (BB_PATH_A | BB_PATH_B | BB_PATH_D),
156 BB_PATH_ACD = (BB_PATH_A | BB_PATH_C | BB_PATH_D),
157 BB_PATH_BCD = (BB_PATH_B | BB_PATH_C | BB_PATH_D),
158
159 BB_PATH_ABCD = (BB_PATH_A | BB_PATH_B | BB_PATH_C | BB_PATH_D),
160};
161
162enum rtw_rate_section {
163 RTW_RATE_SECTION_CCK = 0,
164 RTW_RATE_SECTION_OFDM,
165 RTW_RATE_SECTION_HT_1S,
166 RTW_RATE_SECTION_HT_2S,
167 RTW_RATE_SECTION_VHT_1S,
168 RTW_RATE_SECTION_VHT_2S,
169
170
171 RTW_RATE_SECTION_MAX,
172};
173
174enum rtw_wireless_set {
175 WIRELESS_CCK = 0x00000001,
176 WIRELESS_OFDM = 0x00000002,
177 WIRELESS_HT = 0x00000004,
178 WIRELESS_VHT = 0x00000008,
179};
180
181#define HT_STBC_EN BIT(0)
182#define VHT_STBC_EN BIT(1)
183#define HT_LDPC_EN BIT(0)
184#define VHT_LDPC_EN BIT(1)
185
186enum rtw_chip_type {
187 RTW_CHIP_TYPE_8822B,
188 RTW_CHIP_TYPE_8822C,
189 RTW_CHIP_TYPE_8723D,
190 RTW_CHIP_TYPE_8821C,
191};
192
193enum rtw_tx_queue_type {
194
195 RTW_TX_QUEUE_BK = 0x0,
196 RTW_TX_QUEUE_BE = 0x1,
197 RTW_TX_QUEUE_VI = 0x2,
198 RTW_TX_QUEUE_VO = 0x3,
199
200 RTW_TX_QUEUE_BCN = 0x4,
201 RTW_TX_QUEUE_MGMT = 0x5,
202 RTW_TX_QUEUE_HI0 = 0x6,
203 RTW_TX_QUEUE_H2C = 0x7,
204
205 RTK_MAX_TX_QUEUE_NUM
206};
207
208enum rtw_rx_queue_type {
209 RTW_RX_QUEUE_MPDU = 0x0,
210 RTW_RX_QUEUE_C2H = 0x1,
211
212 RTK_MAX_RX_QUEUE_NUM
213};
214
215enum rtw_fw_type {
216 RTW_NORMAL_FW = 0x0,
217 RTW_WOWLAN_FW = 0x1,
218};
219
220enum rtw_rate_index {
221 RTW_RATEID_BGN_40M_2SS = 0,
222 RTW_RATEID_BGN_40M_1SS = 1,
223 RTW_RATEID_BGN_20M_2SS = 2,
224 RTW_RATEID_BGN_20M_1SS = 3,
225 RTW_RATEID_GN_N2SS = 4,
226 RTW_RATEID_GN_N1SS = 5,
227 RTW_RATEID_BG = 6,
228 RTW_RATEID_G = 7,
229 RTW_RATEID_B_20M = 8,
230 RTW_RATEID_ARFR0_AC_2SS = 9,
231 RTW_RATEID_ARFR1_AC_1SS = 10,
232 RTW_RATEID_ARFR2_AC_2G_1SS = 11,
233 RTW_RATEID_ARFR3_AC_2G_2SS = 12,
234 RTW_RATEID_ARFR4_AC_3SS = 13,
235 RTW_RATEID_ARFR5_N_3SS = 14,
236 RTW_RATEID_ARFR7_N_4SS = 15,
237 RTW_RATEID_ARFR6_AC_4SS = 16
238};
239
240enum rtw_trx_desc_rate {
241 DESC_RATE1M = 0x00,
242 DESC_RATE2M = 0x01,
243 DESC_RATE5_5M = 0x02,
244 DESC_RATE11M = 0x03,
245
246 DESC_RATE6M = 0x04,
247 DESC_RATE9M = 0x05,
248 DESC_RATE12M = 0x06,
249 DESC_RATE18M = 0x07,
250 DESC_RATE24M = 0x08,
251 DESC_RATE36M = 0x09,
252 DESC_RATE48M = 0x0a,
253 DESC_RATE54M = 0x0b,
254
255 DESC_RATEMCS0 = 0x0c,
256 DESC_RATEMCS1 = 0x0d,
257 DESC_RATEMCS2 = 0x0e,
258 DESC_RATEMCS3 = 0x0f,
259 DESC_RATEMCS4 = 0x10,
260 DESC_RATEMCS5 = 0x11,
261 DESC_RATEMCS6 = 0x12,
262 DESC_RATEMCS7 = 0x13,
263 DESC_RATEMCS8 = 0x14,
264 DESC_RATEMCS9 = 0x15,
265 DESC_RATEMCS10 = 0x16,
266 DESC_RATEMCS11 = 0x17,
267 DESC_RATEMCS12 = 0x18,
268 DESC_RATEMCS13 = 0x19,
269 DESC_RATEMCS14 = 0x1a,
270 DESC_RATEMCS15 = 0x1b,
271 DESC_RATEMCS16 = 0x1c,
272 DESC_RATEMCS17 = 0x1d,
273 DESC_RATEMCS18 = 0x1e,
274 DESC_RATEMCS19 = 0x1f,
275 DESC_RATEMCS20 = 0x20,
276 DESC_RATEMCS21 = 0x21,
277 DESC_RATEMCS22 = 0x22,
278 DESC_RATEMCS23 = 0x23,
279 DESC_RATEMCS24 = 0x24,
280 DESC_RATEMCS25 = 0x25,
281 DESC_RATEMCS26 = 0x26,
282 DESC_RATEMCS27 = 0x27,
283 DESC_RATEMCS28 = 0x28,
284 DESC_RATEMCS29 = 0x29,
285 DESC_RATEMCS30 = 0x2a,
286 DESC_RATEMCS31 = 0x2b,
287
288 DESC_RATEVHT1SS_MCS0 = 0x2c,
289 DESC_RATEVHT1SS_MCS1 = 0x2d,
290 DESC_RATEVHT1SS_MCS2 = 0x2e,
291 DESC_RATEVHT1SS_MCS3 = 0x2f,
292 DESC_RATEVHT1SS_MCS4 = 0x30,
293 DESC_RATEVHT1SS_MCS5 = 0x31,
294 DESC_RATEVHT1SS_MCS6 = 0x32,
295 DESC_RATEVHT1SS_MCS7 = 0x33,
296 DESC_RATEVHT1SS_MCS8 = 0x34,
297 DESC_RATEVHT1SS_MCS9 = 0x35,
298
299 DESC_RATEVHT2SS_MCS0 = 0x36,
300 DESC_RATEVHT2SS_MCS1 = 0x37,
301 DESC_RATEVHT2SS_MCS2 = 0x38,
302 DESC_RATEVHT2SS_MCS3 = 0x39,
303 DESC_RATEVHT2SS_MCS4 = 0x3a,
304 DESC_RATEVHT2SS_MCS5 = 0x3b,
305 DESC_RATEVHT2SS_MCS6 = 0x3c,
306 DESC_RATEVHT2SS_MCS7 = 0x3d,
307 DESC_RATEVHT2SS_MCS8 = 0x3e,
308 DESC_RATEVHT2SS_MCS9 = 0x3f,
309
310 DESC_RATEVHT3SS_MCS0 = 0x40,
311 DESC_RATEVHT3SS_MCS1 = 0x41,
312 DESC_RATEVHT3SS_MCS2 = 0x42,
313 DESC_RATEVHT3SS_MCS3 = 0x43,
314 DESC_RATEVHT3SS_MCS4 = 0x44,
315 DESC_RATEVHT3SS_MCS5 = 0x45,
316 DESC_RATEVHT3SS_MCS6 = 0x46,
317 DESC_RATEVHT3SS_MCS7 = 0x47,
318 DESC_RATEVHT3SS_MCS8 = 0x48,
319 DESC_RATEVHT3SS_MCS9 = 0x49,
320
321 DESC_RATEVHT4SS_MCS0 = 0x4a,
322 DESC_RATEVHT4SS_MCS1 = 0x4b,
323 DESC_RATEVHT4SS_MCS2 = 0x4c,
324 DESC_RATEVHT4SS_MCS3 = 0x4d,
325 DESC_RATEVHT4SS_MCS4 = 0x4e,
326 DESC_RATEVHT4SS_MCS5 = 0x4f,
327 DESC_RATEVHT4SS_MCS6 = 0x50,
328 DESC_RATEVHT4SS_MCS7 = 0x51,
329 DESC_RATEVHT4SS_MCS8 = 0x52,
330 DESC_RATEVHT4SS_MCS9 = 0x53,
331
332 DESC_RATE_MAX,
333};
334
335enum rtw_regulatory_domains {
336 RTW_REGD_FCC = 0,
337 RTW_REGD_MKK = 1,
338 RTW_REGD_ETSI = 2,
339 RTW_REGD_IC = 3,
340 RTW_REGD_KCC = 4,
341 RTW_REGD_ACMA = 5,
342 RTW_REGD_CHILE = 6,
343 RTW_REGD_UKRAINE = 7,
344 RTW_REGD_MEXICO = 8,
345 RTW_REGD_CN = 9,
346 RTW_REGD_WW,
347
348 RTW_REGD_MAX
349};
350
351enum rtw_txq_flags {
352 RTW_TXQ_AMPDU,
353 RTW_TXQ_BLOCK_BA,
354};
355
356enum rtw_flags {
357 RTW_FLAG_RUNNING,
358 RTW_FLAG_FW_RUNNING,
359 RTW_FLAG_SCANNING,
360 RTW_FLAG_INACTIVE_PS,
361 RTW_FLAG_LEISURE_PS,
362 RTW_FLAG_LEISURE_PS_DEEP,
363 RTW_FLAG_DIG_DISABLE,
364 RTW_FLAG_BUSY_TRAFFIC,
365 RTW_FLAG_WOWLAN,
366 RTW_FLAG_RESTARTING,
367 RTW_FLAG_RESTART_TRIGGERING,
368 RTW_FLAG_FORCE_LOWEST_RATE,
369
370 NUM_OF_RTW_FLAGS,
371};
372
373enum rtw_evm {
374 RTW_EVM_OFDM = 0,
375 RTW_EVM_1SS,
376 RTW_EVM_2SS_A,
377 RTW_EVM_2SS_B,
378
379 RTW_EVM_NUM
380};
381
382enum rtw_snr {
383 RTW_SNR_OFDM_A = 0,
384 RTW_SNR_OFDM_B,
385 RTW_SNR_OFDM_C,
386 RTW_SNR_OFDM_D,
387 RTW_SNR_1SS_A,
388 RTW_SNR_1SS_B,
389 RTW_SNR_1SS_C,
390 RTW_SNR_1SS_D,
391 RTW_SNR_2SS_A,
392 RTW_SNR_2SS_B,
393 RTW_SNR_2SS_C,
394 RTW_SNR_2SS_D,
395
396 RTW_SNR_NUM
397};
398
399enum rtw_wow_flags {
400 RTW_WOW_FLAG_EN_MAGIC_PKT,
401 RTW_WOW_FLAG_EN_REKEY_PKT,
402 RTW_WOW_FLAG_EN_DISCONNECT,
403
404
405 RTW_WOW_FLAG_MAX,
406};
407
408
409
410
411struct rtw_2g_1s_pwr_idx_diff {
412#ifdef __LITTLE_ENDIAN
413 s8 ofdm:4;
414 s8 bw20:4;
415#else
416 s8 bw20:4;
417 s8 ofdm:4;
418#endif
419} __packed;
420
421struct rtw_2g_ns_pwr_idx_diff {
422#ifdef __LITTLE_ENDIAN
423 s8 bw20:4;
424 s8 bw40:4;
425 s8 cck:4;
426 s8 ofdm:4;
427#else
428 s8 ofdm:4;
429 s8 cck:4;
430 s8 bw40:4;
431 s8 bw20:4;
432#endif
433} __packed;
434
435struct rtw_2g_txpwr_idx {
436 u8 cck_base[6];
437 u8 bw40_base[5];
438 struct rtw_2g_1s_pwr_idx_diff ht_1s_diff;
439 struct rtw_2g_ns_pwr_idx_diff ht_2s_diff;
440 struct rtw_2g_ns_pwr_idx_diff ht_3s_diff;
441 struct rtw_2g_ns_pwr_idx_diff ht_4s_diff;
442};
443
444struct rtw_5g_ht_1s_pwr_idx_diff {
445#ifdef __LITTLE_ENDIAN
446 s8 ofdm:4;
447 s8 bw20:4;
448#else
449 s8 bw20:4;
450 s8 ofdm:4;
451#endif
452} __packed;
453
454struct rtw_5g_ht_ns_pwr_idx_diff {
455#ifdef __LITTLE_ENDIAN
456 s8 bw20:4;
457 s8 bw40:4;
458#else
459 s8 bw40:4;
460 s8 bw20:4;
461#endif
462} __packed;
463
464struct rtw_5g_ofdm_ns_pwr_idx_diff {
465#ifdef __LITTLE_ENDIAN
466 s8 ofdm_3s:4;
467 s8 ofdm_2s:4;
468 s8 ofdm_4s:4;
469 s8 res:4;
470#else
471 s8 res:4;
472 s8 ofdm_4s:4;
473 s8 ofdm_2s:4;
474 s8 ofdm_3s:4;
475#endif
476} __packed;
477
478struct rtw_5g_vht_ns_pwr_idx_diff {
479#ifdef __LITTLE_ENDIAN
480 s8 bw160:4;
481 s8 bw80:4;
482#else
483 s8 bw80:4;
484 s8 bw160:4;
485#endif
486} __packed;
487
488struct rtw_5g_txpwr_idx {
489 u8 bw40_base[14];
490 struct rtw_5g_ht_1s_pwr_idx_diff ht_1s_diff;
491 struct rtw_5g_ht_ns_pwr_idx_diff ht_2s_diff;
492 struct rtw_5g_ht_ns_pwr_idx_diff ht_3s_diff;
493 struct rtw_5g_ht_ns_pwr_idx_diff ht_4s_diff;
494 struct rtw_5g_ofdm_ns_pwr_idx_diff ofdm_diff;
495 struct rtw_5g_vht_ns_pwr_idx_diff vht_1s_diff;
496 struct rtw_5g_vht_ns_pwr_idx_diff vht_2s_diff;
497 struct rtw_5g_vht_ns_pwr_idx_diff vht_3s_diff;
498 struct rtw_5g_vht_ns_pwr_idx_diff vht_4s_diff;
499};
500
501struct rtw_txpwr_idx {
502 struct rtw_2g_txpwr_idx pwr_idx_2g;
503 struct rtw_5g_txpwr_idx pwr_idx_5g;
504};
505
506struct rtw_timer_list {
507 struct timer_list timer;
508 void (*function)(void *data);
509 void *args;
510};
511
512struct rtw_channel_params {
513 u8 center_chan;
514 u8 bandwidth;
515 u8 primary_chan_idx;
516
517
518
519 u8 cch_by_bw[RTW_MAX_CHANNEL_WIDTH + 1];
520};
521
522struct rtw_hw_reg {
523 u32 addr;
524 u32 mask;
525};
526
527struct rtw_ltecoex_addr {
528 u32 ctrl;
529 u32 wdata;
530 u32 rdata;
531};
532
533struct rtw_reg_domain {
534 u32 addr;
535 u32 mask;
536#define RTW_REG_DOMAIN_MAC32 0
537#define RTW_REG_DOMAIN_MAC16 1
538#define RTW_REG_DOMAIN_MAC8 2
539#define RTW_REG_DOMAIN_RF_A 3
540#define RTW_REG_DOMAIN_RF_B 4
541#define RTW_REG_DOMAIN_NL 0xFF
542 u8 domain;
543};
544
545struct rtw_rf_sipi_addr {
546 u32 hssi_1;
547 u32 hssi_2;
548 u32 lssi_read;
549 u32 lssi_read_pi;
550};
551
552struct rtw_hw_reg_offset {
553 struct rtw_hw_reg hw_reg;
554 u8 offset;
555};
556
557struct rtw_backup_info {
558 u8 len;
559 u32 reg;
560 u32 val;
561};
562
563enum rtw_vif_port_set {
564 PORT_SET_MAC_ADDR = BIT(0),
565 PORT_SET_BSSID = BIT(1),
566 PORT_SET_NET_TYPE = BIT(2),
567 PORT_SET_AID = BIT(3),
568 PORT_SET_BCN_CTRL = BIT(4),
569};
570
571struct rtw_vif_port {
572 struct rtw_hw_reg mac_addr;
573 struct rtw_hw_reg bssid;
574 struct rtw_hw_reg net_type;
575 struct rtw_hw_reg aid;
576 struct rtw_hw_reg bcn_ctrl;
577};
578
579struct rtw_tx_pkt_info {
580 u32 tx_pkt_size;
581 u8 offset;
582 u8 pkt_offset;
583 u8 mac_id;
584 u8 rate_id;
585 u8 rate;
586 u8 qsel;
587 u8 bw;
588 u8 sec_type;
589 u8 sn;
590 bool ampdu_en;
591 u8 ampdu_factor;
592 u8 ampdu_density;
593 u16 seq;
594 bool stbc;
595 bool ldpc;
596 bool dis_rate_fallback;
597 bool bmc;
598 bool use_rate;
599 bool ls;
600 bool fs;
601 bool short_gi;
602 bool report;
603 bool rts;
604 bool dis_qselseq;
605 bool en_hwseq;
606 u8 hw_ssn_sel;
607 bool nav_use_hdr;
608 bool bt_null;
609};
610
611struct rtw_rx_pkt_stat {
612 bool phy_status;
613 bool icv_err;
614 bool crc_err;
615 bool decrypted;
616 bool is_c2h;
617
618 s32 signal_power;
619 u16 pkt_len;
620 u8 bw;
621 u8 drv_info_sz;
622 u8 shift;
623 u8 rate;
624 u8 mac_id;
625 u8 cam_id;
626 u8 ppdu_cnt;
627 u32 tsf_low;
628 s8 rx_power[RTW_RF_PATH_MAX];
629 u8 rssi;
630 u8 rxsc;
631 s8 rx_snr[RTW_RF_PATH_MAX];
632 u8 rx_evm[RTW_RF_PATH_MAX];
633 s8 cfo_tail[RTW_RF_PATH_MAX];
634 u16 freq;
635 u8 band;
636
637 struct rtw_sta_info *si;
638 struct ieee80211_vif *vif;
639 struct ieee80211_hdr *hdr;
640};
641
642DECLARE_EWMA(tp, 10, 2);
643
644struct rtw_traffic_stats {
645
646 u64 tx_unicast;
647 u64 rx_unicast;
648
649
650 u64 tx_cnt;
651 u64 rx_cnt;
652
653
654 u32 tx_throughput;
655 u32 rx_throughput;
656 struct ewma_tp tx_ewma_tp;
657 struct ewma_tp rx_ewma_tp;
658};
659
660enum rtw_lps_mode {
661 RTW_MODE_ACTIVE = 0,
662 RTW_MODE_LPS = 1,
663 RTW_MODE_WMM_PS = 2,
664};
665
666enum rtw_lps_deep_mode {
667 LPS_DEEP_MODE_NONE = 0,
668 LPS_DEEP_MODE_LCLK = 1,
669 LPS_DEEP_MODE_PG = 2,
670};
671
672enum rtw_pwr_state {
673 RTW_RF_OFF = 0x0,
674 RTW_RF_ON = 0x4,
675 RTW_ALL_ON = 0xc,
676};
677
678struct rtw_lps_conf {
679 enum rtw_lps_mode mode;
680 enum rtw_lps_deep_mode deep_mode;
681 enum rtw_lps_deep_mode wow_deep_mode;
682 enum rtw_pwr_state state;
683 u8 awake_interval;
684 u8 rlbm;
685 u8 smart_ps;
686 u8 port_id;
687 bool sec_cam_backup;
688 bool pattern_cam_backup;
689};
690
691enum rtw_hw_key_type {
692 RTW_CAM_NONE = 0,
693 RTW_CAM_WEP40 = 1,
694 RTW_CAM_TKIP = 2,
695 RTW_CAM_AES = 4,
696 RTW_CAM_WEP104 = 5,
697};
698
699struct rtw_cam_entry {
700 bool valid;
701 bool group;
702 u8 addr[ETH_ALEN];
703 u8 hw_key_type;
704 struct ieee80211_key_conf *key;
705};
706
707struct rtw_sec_desc {
708
709 bool default_key_search;
710
711 u32 total_cam_num;
712 struct rtw_cam_entry cam_table[RTW_MAX_SEC_CAM_NUM];
713 DECLARE_BITMAP(cam_map, RTW_MAX_SEC_CAM_NUM);
714};
715
716struct rtw_tx_report {
717
718 spinlock_t q_lock;
719 struct sk_buff_head queue;
720 atomic_t sn;
721 struct timer_list purge_timer;
722};
723
724struct rtw_ra_report {
725 struct rate_info txrate;
726 u32 bit_rate;
727 u8 desc_rate;
728};
729
730struct rtw_txq {
731 struct list_head list;
732
733 unsigned long flags;
734 unsigned long last_push;
735};
736
737#define RTW_BC_MC_MACID 1
738DECLARE_EWMA(rssi, 10, 16);
739
740struct rtw_sta_info {
741 struct ieee80211_sta *sta;
742 struct ieee80211_vif *vif;
743
744 struct ewma_rssi avg_rssi;
745 u8 rssi_level;
746
747 u8 mac_id;
748 u8 rate_id;
749 enum rtw_bandwidth bw_mode;
750 enum rtw_rf_type rf_type;
751 enum rtw_wireless_set wireless_set;
752 u8 stbc_en:2;
753 u8 ldpc_en:2;
754 bool sgi_enable;
755 bool vht_enable;
756 bool updated;
757 u8 init_ra_lv;
758 u64 ra_mask;
759
760 DECLARE_BITMAP(tid_ba, IEEE80211_NUM_TIDS);
761
762 struct rtw_ra_report ra_report;
763
764 bool use_cfg_mask;
765 struct cfg80211_bitrate_mask *mask;
766};
767
768enum rtw_bfee_role {
769 RTW_BFEE_NONE,
770 RTW_BFEE_SU,
771 RTW_BFEE_MU
772};
773
774struct rtw_bfee {
775 enum rtw_bfee_role role;
776
777 u16 p_aid;
778 u8 g_id;
779 u8 mac_addr[ETH_ALEN];
780 u8 sound_dim;
781
782
783 u8 su_reg_index;
784
785
786 u16 aid;
787};
788
789struct rtw_bf_info {
790 u8 bfer_mu_cnt;
791 u8 bfer_su_cnt;
792 DECLARE_BITMAP(bfer_su_reg_maping, 2);
793 u8 cur_csi_rpt_rate;
794};
795
796struct rtw_vif {
797 enum rtw_net_type net_type;
798 u16 aid;
799 u8 mac_addr[ETH_ALEN];
800 u8 bssid[ETH_ALEN];
801 u8 port;
802 u8 bcn_ctrl;
803 struct list_head rsvd_page_list;
804 struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS];
805 const struct rtw_vif_port *conf;
806 struct cfg80211_scan_request *scan_req;
807 struct ieee80211_scan_ies *scan_ies;
808
809 struct rtw_traffic_stats stats;
810
811 struct rtw_bfee bfee;
812};
813
814struct rtw_regulatory {
815 char alpha2[2];
816 u8 txpwr_regd_2g;
817 u8 txpwr_regd_5g;
818};
819
820enum rtw_regd_state {
821 RTW_REGD_STATE_WORLDWIDE,
822 RTW_REGD_STATE_PROGRAMMED,
823 RTW_REGD_STATE_SETTING,
824
825 RTW_REGD_STATE_NR,
826};
827
828struct rtw_regd {
829 enum rtw_regd_state state;
830 const struct rtw_regulatory *regulatory;
831 enum nl80211_dfs_regions dfs_region;
832};
833
834struct rtw_chip_ops {
835 int (*mac_init)(struct rtw_dev *rtwdev);
836 int (*dump_fw_crash)(struct rtw_dev *rtwdev);
837 void (*shutdown)(struct rtw_dev *rtwdev);
838 int (*read_efuse)(struct rtw_dev *rtwdev, u8 *map);
839 void (*phy_set_param)(struct rtw_dev *rtwdev);
840 void (*set_channel)(struct rtw_dev *rtwdev, u8 channel,
841 u8 bandwidth, u8 primary_chan_idx);
842 void (*query_rx_desc)(struct rtw_dev *rtwdev, u8 *rx_desc,
843 struct rtw_rx_pkt_stat *pkt_stat,
844 struct ieee80211_rx_status *rx_status);
845 u32 (*read_rf)(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
846 u32 addr, u32 mask);
847 bool (*write_rf)(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
848 u32 addr, u32 mask, u32 data);
849 void (*set_tx_power_index)(struct rtw_dev *rtwdev);
850 int (*rsvd_page_dump)(struct rtw_dev *rtwdev, u8 *buf, u32 offset,
851 u32 size);
852 int (*set_antenna)(struct rtw_dev *rtwdev,
853 u32 antenna_tx,
854 u32 antenna_rx);
855 void (*cfg_ldo25)(struct rtw_dev *rtwdev, bool enable);
856 void (*efuse_grant)(struct rtw_dev *rtwdev, bool enable);
857 void (*false_alarm_statistics)(struct rtw_dev *rtwdev);
858 void (*phy_calibration)(struct rtw_dev *rtwdev);
859 void (*dpk_track)(struct rtw_dev *rtwdev);
860 void (*cck_pd_set)(struct rtw_dev *rtwdev, u8 level);
861 void (*pwr_track)(struct rtw_dev *rtwdev);
862 void (*config_bfee)(struct rtw_dev *rtwdev, struct rtw_vif *vif,
863 struct rtw_bfee *bfee, bool enable);
864 void (*set_gid_table)(struct rtw_dev *rtwdev,
865 struct ieee80211_vif *vif,
866 struct ieee80211_bss_conf *conf);
867 void (*cfg_csi_rate)(struct rtw_dev *rtwdev, u8 rssi, u8 cur_rate,
868 u8 fixrate_en, u8 *new_rate);
869 void (*adaptivity_init)(struct rtw_dev *rtwdev);
870 void (*adaptivity)(struct rtw_dev *rtwdev);
871 void (*cfo_init)(struct rtw_dev *rtwdev);
872 void (*cfo_track)(struct rtw_dev *rtwdev);
873 void (*config_tx_path)(struct rtw_dev *rtwdev, u8 tx_path,
874 enum rtw_bb_path tx_path_1ss,
875 enum rtw_bb_path tx_path_cck,
876 bool is_tx2_path);
877
878
879 void (*coex_set_init)(struct rtw_dev *rtwdev);
880 void (*coex_set_ant_switch)(struct rtw_dev *rtwdev,
881 u8 ctrl_type, u8 pos_type);
882 void (*coex_set_gnt_fix)(struct rtw_dev *rtwdev);
883 void (*coex_set_gnt_debug)(struct rtw_dev *rtwdev);
884 void (*coex_set_rfe_type)(struct rtw_dev *rtwdev);
885 void (*coex_set_wl_tx_power)(struct rtw_dev *rtwdev, u8 wl_pwr);
886 void (*coex_set_wl_rx_gain)(struct rtw_dev *rtwdev, bool low_gain);
887};
888
889#define RTW_PWR_POLLING_CNT 20000
890
891#define RTW_PWR_CMD_READ 0x00
892#define RTW_PWR_CMD_WRITE 0x01
893#define RTW_PWR_CMD_POLLING 0x02
894#define RTW_PWR_CMD_DELAY 0x03
895#define RTW_PWR_CMD_END 0x04
896
897
898#define RTW_PWR_ADDR_MAC 0x00
899#define RTW_PWR_ADDR_USB 0x01
900#define RTW_PWR_ADDR_PCIE 0x02
901#define RTW_PWR_ADDR_SDIO 0x03
902
903#define RTW_PWR_INTF_SDIO_MSK BIT(0)
904#define RTW_PWR_INTF_USB_MSK BIT(1)
905#define RTW_PWR_INTF_PCI_MSK BIT(2)
906#define RTW_PWR_INTF_ALL_MSK (BIT(0) | BIT(1) | BIT(2) | BIT(3))
907
908#define RTW_PWR_CUT_TEST_MSK BIT(0)
909#define RTW_PWR_CUT_A_MSK BIT(1)
910#define RTW_PWR_CUT_B_MSK BIT(2)
911#define RTW_PWR_CUT_C_MSK BIT(3)
912#define RTW_PWR_CUT_D_MSK BIT(4)
913#define RTW_PWR_CUT_E_MSK BIT(5)
914#define RTW_PWR_CUT_F_MSK BIT(6)
915#define RTW_PWR_CUT_G_MSK BIT(7)
916#define RTW_PWR_CUT_ALL_MSK 0xFF
917
918enum rtw_pwr_seq_cmd_delay_unit {
919 RTW_PWR_DELAY_US,
920 RTW_PWR_DELAY_MS,
921};
922
923struct rtw_pwr_seq_cmd {
924 u16 offset;
925 u8 cut_mask;
926 u8 intf_mask;
927 u8 base:4;
928 u8 cmd:4;
929 u8 mask;
930 u8 value;
931};
932
933enum rtw_chip_ver {
934 RTW_CHIP_VER_CUT_A = 0x00,
935 RTW_CHIP_VER_CUT_B = 0x01,
936 RTW_CHIP_VER_CUT_C = 0x02,
937 RTW_CHIP_VER_CUT_D = 0x03,
938 RTW_CHIP_VER_CUT_E = 0x04,
939 RTW_CHIP_VER_CUT_F = 0x05,
940 RTW_CHIP_VER_CUT_G = 0x06,
941};
942
943#define RTW_INTF_PHY_PLATFORM_ALL 0
944
945enum rtw_intf_phy_cut {
946 RTW_INTF_PHY_CUT_A = BIT(0),
947 RTW_INTF_PHY_CUT_B = BIT(1),
948 RTW_INTF_PHY_CUT_C = BIT(2),
949 RTW_INTF_PHY_CUT_D = BIT(3),
950 RTW_INTF_PHY_CUT_E = BIT(4),
951 RTW_INTF_PHY_CUT_F = BIT(5),
952 RTW_INTF_PHY_CUT_G = BIT(6),
953 RTW_INTF_PHY_CUT_ALL = 0xFFFF,
954};
955
956enum rtw_ip_sel {
957 RTW_IP_SEL_PHY = 0,
958 RTW_IP_SEL_MAC = 1,
959 RTW_IP_SEL_DBI = 2,
960
961 RTW_IP_SEL_UNDEF = 0xFFFF
962};
963
964enum rtw_pq_map_id {
965 RTW_PQ_MAP_VO = 0x0,
966 RTW_PQ_MAP_VI = 0x1,
967 RTW_PQ_MAP_BE = 0x2,
968 RTW_PQ_MAP_BK = 0x3,
969 RTW_PQ_MAP_MG = 0x4,
970 RTW_PQ_MAP_HI = 0x5,
971 RTW_PQ_MAP_NUM = 0x6,
972
973 RTW_PQ_MAP_UNDEF,
974};
975
976enum rtw_dma_mapping {
977 RTW_DMA_MAPPING_EXTRA = 0,
978 RTW_DMA_MAPPING_LOW = 1,
979 RTW_DMA_MAPPING_NORMAL = 2,
980 RTW_DMA_MAPPING_HIGH = 3,
981
982 RTW_DMA_MAPPING_MAX,
983 RTW_DMA_MAPPING_UNDEF,
984};
985
986struct rtw_rqpn {
987 enum rtw_dma_mapping dma_map_vo;
988 enum rtw_dma_mapping dma_map_vi;
989 enum rtw_dma_mapping dma_map_be;
990 enum rtw_dma_mapping dma_map_bk;
991 enum rtw_dma_mapping dma_map_mg;
992 enum rtw_dma_mapping dma_map_hi;
993};
994
995struct rtw_prioq_addr {
996 u32 rsvd;
997 u32 avail;
998};
999
1000struct rtw_prioq_addrs {
1001 struct rtw_prioq_addr prio[RTW_DMA_MAPPING_MAX];
1002 bool wsize;
1003};
1004
1005struct rtw_page_table {
1006 u16 hq_num;
1007 u16 nq_num;
1008 u16 lq_num;
1009 u16 exq_num;
1010 u16 gapq_num;
1011};
1012
1013struct rtw_intf_phy_para {
1014 u16 offset;
1015 u16 value;
1016 u16 ip_sel;
1017 u16 cut_mask;
1018 u16 platform;
1019};
1020
1021struct rtw_wow_pattern {
1022 u16 crc;
1023 u8 type;
1024 u8 valid;
1025 u8 mask[RTW_MAX_PATTERN_MASK_SIZE];
1026};
1027
1028struct rtw_pno_request {
1029 bool inited;
1030 u32 match_set_cnt;
1031 struct cfg80211_match_set *match_sets;
1032 u8 channel_cnt;
1033 struct ieee80211_channel *channels;
1034 struct cfg80211_sched_scan_plan scan_plan;
1035};
1036
1037struct rtw_wow_param {
1038 struct ieee80211_vif *wow_vif;
1039 DECLARE_BITMAP(flags, RTW_WOW_FLAG_MAX);
1040 u8 txpause;
1041 u8 pattern_cnt;
1042 struct rtw_wow_pattern patterns[RTW_MAX_PATTERN_NUM];
1043
1044 bool ips_enabled;
1045 struct rtw_pno_request pno_req;
1046};
1047
1048struct rtw_intf_phy_para_table {
1049 const struct rtw_intf_phy_para *usb2_para;
1050 const struct rtw_intf_phy_para *usb3_para;
1051 const struct rtw_intf_phy_para *gen1_para;
1052 const struct rtw_intf_phy_para *gen2_para;
1053 u8 n_usb2_para;
1054 u8 n_usb3_para;
1055 u8 n_gen1_para;
1056 u8 n_gen2_para;
1057};
1058
1059struct rtw_table {
1060 const void *data;
1061 const u32 size;
1062 void (*parse)(struct rtw_dev *rtwdev, const struct rtw_table *tbl);
1063 void (*do_cfg)(struct rtw_dev *rtwdev, const struct rtw_table *tbl,
1064 u32 addr, u32 data);
1065 enum rtw_rf_path rf_path;
1066};
1067
1068static inline void rtw_load_table(struct rtw_dev *rtwdev,
1069 const struct rtw_table *tbl)
1070{
1071 (*tbl->parse)(rtwdev, tbl);
1072}
1073
1074enum rtw_rfe_fem {
1075 RTW_RFE_IFEM,
1076 RTW_RFE_EFEM,
1077 RTW_RFE_IFEM2G_EFEM5G,
1078 RTW_RFE_NUM,
1079};
1080
1081struct rtw_rfe_def {
1082 const struct rtw_table *phy_pg_tbl;
1083 const struct rtw_table *txpwr_lmt_tbl;
1084 const struct rtw_table *agc_btg_tbl;
1085};
1086
1087#define RTW_DEF_RFE(chip, bb_pg, pwrlmt) { \
1088 .phy_pg_tbl = &rtw ## chip ## _bb_pg_type ## bb_pg ## _tbl, \
1089 .txpwr_lmt_tbl = &rtw ## chip ## _txpwr_lmt_type ## pwrlmt ## _tbl, \
1090 }
1091
1092#define RTW_DEF_RFE_EXT(chip, bb_pg, pwrlmt, btg) { \
1093 .phy_pg_tbl = &rtw ## chip ## _bb_pg_type ## bb_pg ## _tbl, \
1094 .txpwr_lmt_tbl = &rtw ## chip ## _txpwr_lmt_type ## pwrlmt ## _tbl, \
1095 .agc_btg_tbl = &rtw ## chip ## _agc_btg_type ## btg ## _tbl, \
1096 }
1097
1098#define RTW_PWR_TRK_5G_1 0
1099#define RTW_PWR_TRK_5G_2 1
1100#define RTW_PWR_TRK_5G_3 2
1101#define RTW_PWR_TRK_5G_NUM 3
1102
1103#define RTW_PWR_TRK_TBL_SZ 30
1104
1105
1106
1107
1108
1109
1110
1111struct rtw_pwr_track_tbl {
1112 const u8 *pwrtrk_5gb_n[RTW_PWR_TRK_5G_NUM];
1113 const u8 *pwrtrk_5gb_p[RTW_PWR_TRK_5G_NUM];
1114 const u8 *pwrtrk_5ga_n[RTW_PWR_TRK_5G_NUM];
1115 const u8 *pwrtrk_5ga_p[RTW_PWR_TRK_5G_NUM];
1116 const u8 *pwrtrk_2gb_n;
1117 const u8 *pwrtrk_2gb_p;
1118 const u8 *pwrtrk_2ga_n;
1119 const u8 *pwrtrk_2ga_p;
1120 const u8 *pwrtrk_2g_cckb_n;
1121 const u8 *pwrtrk_2g_cckb_p;
1122 const u8 *pwrtrk_2g_ccka_n;
1123 const u8 *pwrtrk_2g_ccka_p;
1124 const s8 *pwrtrk_xtal_n;
1125 const s8 *pwrtrk_xtal_p;
1126};
1127
1128enum rtw_wlan_cpu {
1129 RTW_WCPU_11AC,
1130 RTW_WCPU_11N,
1131};
1132
1133enum rtw_fw_fifo_sel {
1134 RTW_FW_FIFO_SEL_TX,
1135 RTW_FW_FIFO_SEL_RX,
1136 RTW_FW_FIFO_SEL_RSVD_PAGE,
1137 RTW_FW_FIFO_SEL_REPORT,
1138 RTW_FW_FIFO_SEL_LLT,
1139 RTW_FW_FIFO_SEL_RXBUF_FW,
1140
1141 RTW_FW_FIFO_MAX,
1142};
1143
1144enum rtw_fwcd_item {
1145 RTW_FWCD_TLV,
1146 RTW_FWCD_REG,
1147 RTW_FWCD_ROM,
1148 RTW_FWCD_IMEM,
1149 RTW_FWCD_DMEM,
1150 RTW_FWCD_EMEM,
1151};
1152
1153
1154struct rtw_chip_info {
1155 struct rtw_chip_ops *ops;
1156 u8 id;
1157
1158 const char *fw_name;
1159 enum rtw_wlan_cpu wlan_cpu;
1160 u8 tx_pkt_desc_sz;
1161 u8 tx_buf_desc_sz;
1162 u8 rx_pkt_desc_sz;
1163 u8 rx_buf_desc_sz;
1164 u32 phy_efuse_size;
1165 u32 log_efuse_size;
1166 u32 ptct_efuse_size;
1167 u32 txff_size;
1168 u32 rxff_size;
1169 u32 fw_rxff_size;
1170 u8 band;
1171 u8 page_size;
1172 u8 csi_buf_pg_num;
1173 u8 dig_max;
1174 u8 dig_min;
1175 u8 txgi_factor;
1176 bool is_pwr_by_rate_dec;
1177 bool rx_ldpc;
1178 bool tx_stbc;
1179 u8 max_power_index;
1180
1181 u16 fw_fifo_addr[RTW_FW_FIFO_MAX];
1182 const struct rtw_fwcd_segs *fwcd_segs;
1183
1184 u8 default_1ss_tx_path;
1185
1186 bool path_div_supported;
1187 bool ht_supported;
1188 bool vht_supported;
1189 u8 lps_deep_mode_supported;
1190
1191
1192 u8 sys_func_en;
1193 const struct rtw_pwr_seq_cmd **pwr_on_seq;
1194 const struct rtw_pwr_seq_cmd **pwr_off_seq;
1195 const struct rtw_rqpn *rqpn_table;
1196 const struct rtw_prioq_addrs *prioq_addrs;
1197 const struct rtw_page_table *page_table;
1198 const struct rtw_intf_phy_para_table *intf_table;
1199
1200 const struct rtw_hw_reg *dig;
1201 const struct rtw_hw_reg *dig_cck;
1202 u32 rf_base_addr[2];
1203 u32 rf_sipi_addr[2];
1204 const struct rtw_rf_sipi_addr *rf_sipi_read_addr;
1205 u8 fix_rf_phy_num;
1206 const struct rtw_ltecoex_addr *ltecoex_addr;
1207
1208 const struct rtw_table *mac_tbl;
1209 const struct rtw_table *agc_tbl;
1210 const struct rtw_table *bb_tbl;
1211 const struct rtw_table *rf_tbl[RTW_RF_PATH_MAX];
1212 const struct rtw_table *rfk_init_tbl;
1213
1214 const struct rtw_rfe_def *rfe_defs;
1215 u32 rfe_defs_size;
1216
1217 bool en_dis_dpd;
1218 u16 dpd_ratemask;
1219 u8 iqk_threshold;
1220 u8 lck_threshold;
1221 const struct rtw_pwr_track_tbl *pwr_track_tbl;
1222
1223 u8 bfer_su_max_num;
1224 u8 bfer_mu_max_num;
1225
1226 struct rtw_hw_reg_offset *edcca_th;
1227 s8 l2h_th_ini_cs;
1228 s8 l2h_th_ini_ad;
1229
1230 const char *wow_fw_name;
1231 const struct wiphy_wowlan_support *wowlan_stub;
1232 const u8 max_sched_scan_ssids;
1233
1234
1235 u32 ch_param[3];
1236
1237
1238 u32 coex_para_ver;
1239 u8 bt_desired_ver;
1240 bool scbd_support;
1241 bool new_scbd10_def;
1242 bool ble_hid_profile_support;
1243 u8 pstdma_type;
1244 u8 bt_rssi_type;
1245 u8 ant_isolation;
1246 u8 rssi_tolerance;
1247 u8 table_sant_num;
1248 u8 table_nsant_num;
1249 u8 tdma_sant_num;
1250 u8 tdma_nsant_num;
1251 u8 bt_afh_span_bw20;
1252 u8 bt_afh_span_bw40;
1253 u8 afh_5g_num;
1254 u8 wl_rf_para_num;
1255 u8 coex_info_hw_regs_num;
1256 const u8 *bt_rssi_step;
1257 const u8 *wl_rssi_step;
1258 const struct coex_table_para *table_nsant;
1259 const struct coex_table_para *table_sant;
1260 const struct coex_tdma_para *tdma_sant;
1261 const struct coex_tdma_para *tdma_nsant;
1262 const struct coex_rf_para *wl_rf_para_tx;
1263 const struct coex_rf_para *wl_rf_para_rx;
1264 const struct coex_5g_afh_map *afh_5g;
1265 const struct rtw_hw_reg *btg_reg;
1266 const struct rtw_reg_domain *coex_info_hw_regs;
1267 u32 wl_fw_desired_ver;
1268};
1269
1270enum rtw_coex_bt_state_cnt {
1271 COEX_CNT_BT_RETRY,
1272 COEX_CNT_BT_REINIT,
1273 COEX_CNT_BT_REENABLE,
1274 COEX_CNT_BT_POPEVENT,
1275 COEX_CNT_BT_SETUPLINK,
1276 COEX_CNT_BT_IGNWLANACT,
1277 COEX_CNT_BT_INQ,
1278 COEX_CNT_BT_PAGE,
1279 COEX_CNT_BT_ROLESWITCH,
1280 COEX_CNT_BT_AFHUPDATE,
1281 COEX_CNT_BT_INFOUPDATE,
1282 COEX_CNT_BT_IQK,
1283 COEX_CNT_BT_IQKFAIL,
1284
1285 COEX_CNT_BT_MAX
1286};
1287
1288enum rtw_coex_wl_state_cnt {
1289 COEX_CNT_WL_SCANAP,
1290 COEX_CNT_WL_CONNPKT,
1291 COEX_CNT_WL_COEXRUN,
1292 COEX_CNT_WL_NOISY0,
1293 COEX_CNT_WL_NOISY1,
1294 COEX_CNT_WL_NOISY2,
1295 COEX_CNT_WL_5MS_NOEXTEND,
1296 COEX_CNT_WL_FW_NOTIFY,
1297
1298 COEX_CNT_WL_MAX
1299};
1300
1301struct rtw_coex_rfe {
1302 bool ant_switch_exist;
1303 bool ant_switch_diversity;
1304 bool ant_switch_with_bt;
1305 u8 rfe_module_type;
1306 u8 ant_switch_polarity;
1307
1308
1309 bool wlg_at_btg;
1310};
1311
1312#define COEX_WL_TDMA_PARA_LENGTH 5
1313
1314struct rtw_coex_dm {
1315 bool cur_ps_tdma_on;
1316 bool cur_wl_rx_low_gain_en;
1317 bool ignore_wl_act;
1318
1319 u8 reason;
1320 u8 bt_rssi_state[4];
1321 u8 wl_rssi_state[4];
1322 u8 wl_ch_info[3];
1323 u8 cur_ps_tdma;
1324 u8 cur_table;
1325 u8 ps_tdma_para[5];
1326 u8 cur_bt_pwr_lvl;
1327 u8 cur_bt_lna_lvl;
1328 u8 cur_wl_pwr_lvl;
1329 u8 bt_status;
1330 u32 cur_ant_pos_type;
1331 u32 cur_switch_status;
1332 u32 setting_tdma;
1333 u8 fw_tdma_para[COEX_WL_TDMA_PARA_LENGTH];
1334};
1335
1336#define COEX_BTINFO_SRC_WL_FW 0x0
1337#define COEX_BTINFO_SRC_BT_RSP 0x1
1338#define COEX_BTINFO_SRC_BT_ACT 0x2
1339#define COEX_BTINFO_SRC_BT_IQK 0x3
1340#define COEX_BTINFO_SRC_BT_SCBD 0x4
1341#define COEX_BTINFO_SRC_H2C60 0x5
1342#define COEX_BTINFO_SRC_MAX 0x6
1343
1344#define COEX_INFO_FTP BIT(7)
1345#define COEX_INFO_A2DP BIT(6)
1346#define COEX_INFO_HID BIT(5)
1347#define COEX_INFO_SCO_BUSY BIT(4)
1348#define COEX_INFO_ACL_BUSY BIT(3)
1349#define COEX_INFO_INQ_PAGE BIT(2)
1350#define COEX_INFO_SCO_ESCO BIT(1)
1351#define COEX_INFO_CONNECTION BIT(0)
1352#define COEX_BTINFO_LENGTH_MAX 10
1353#define COEX_BTINFO_LENGTH 7
1354
1355struct rtw_coex_stat {
1356 bool bt_disabled;
1357 bool bt_disabled_pre;
1358 bool bt_link_exist;
1359 bool bt_whck_test;
1360 bool bt_inq_page;
1361 bool bt_inq_remain;
1362 bool bt_inq;
1363 bool bt_page;
1364 bool bt_ble_voice;
1365 bool bt_ble_exist;
1366 bool bt_hfp_exist;
1367 bool bt_a2dp_exist;
1368 bool bt_hid_exist;
1369 bool bt_pan_exist;
1370 bool bt_opp_exist;
1371 bool bt_acl_busy;
1372 bool bt_fix_2M;
1373 bool bt_setup_link;
1374 bool bt_multi_link;
1375 bool bt_multi_link_pre;
1376 bool bt_multi_link_remain;
1377 bool bt_a2dp_sink;
1378 bool bt_a2dp_active;
1379 bool bt_reenable;
1380 bool bt_ble_scan_en;
1381 bool bt_init_scan;
1382 bool bt_slave;
1383 bool bt_418_hid_exist;
1384 bool bt_ble_hid_exist;
1385 bool bt_mailbox_reply;
1386
1387 bool wl_under_lps;
1388 bool wl_under_ips;
1389 bool wl_hi_pri_task1;
1390 bool wl_hi_pri_task2;
1391 bool wl_force_lps_ctrl;
1392 bool wl_gl_busy;
1393 bool wl_linkscan_proc;
1394 bool wl_ps_state_fail;
1395 bool wl_tx_limit_en;
1396 bool wl_ampdu_limit_en;
1397 bool wl_connected;
1398 bool wl_slot_extend;
1399 bool wl_cck_lock;
1400 bool wl_cck_lock_pre;
1401 bool wl_cck_lock_ever;
1402 bool wl_connecting;
1403 bool wl_slot_toggle;
1404 bool wl_slot_toggle_change;
1405
1406 u32 bt_supported_version;
1407 u32 bt_supported_feature;
1408 u32 hi_pri_tx;
1409 u32 hi_pri_rx;
1410 u32 lo_pri_tx;
1411 u32 lo_pri_rx;
1412 u32 patch_ver;
1413 u16 bt_reg_vendor_ae;
1414 u16 bt_reg_vendor_ac;
1415 s8 bt_rssi;
1416 u8 kt_ver;
1417 u8 gnt_workaround_state;
1418 u8 tdma_timer_base;
1419 u8 bt_profile_num;
1420 u8 bt_info_c2h[COEX_BTINFO_SRC_MAX][COEX_BTINFO_LENGTH_MAX];
1421 u8 bt_info_lb2;
1422 u8 bt_info_lb3;
1423 u8 bt_info_hb0;
1424 u8 bt_info_hb1;
1425 u8 bt_info_hb2;
1426 u8 bt_info_hb3;
1427 u8 bt_ble_scan_type;
1428 u8 bt_hid_pair_num;
1429 u8 bt_hid_slot;
1430 u8 bt_a2dp_bitpool;
1431 u8 bt_iqk_state;
1432
1433 u16 wl_beacon_interval;
1434 u8 wl_noisy_level;
1435 u8 wl_fw_dbg_info[10];
1436 u8 wl_fw_dbg_info_pre[10];
1437 u8 wl_rx_rate;
1438 u8 wl_tx_rate;
1439 u8 wl_rts_rx_rate;
1440 u8 wl_coex_mode;
1441 u8 wl_iot_peer;
1442 u8 ampdu_max_time;
1443 u8 wl_tput_dir;
1444
1445 u8 wl_toggle_para[6];
1446 u8 wl_toggle_interval;
1447
1448 u16 score_board;
1449 u16 retry_limit;
1450
1451
1452 u32 cnt_bt[COEX_CNT_BT_MAX];
1453
1454
1455 u32 cnt_wl[COEX_CNT_WL_MAX];
1456
1457
1458 u32 cnt_bt_info_c2h[COEX_BTINFO_SRC_MAX];
1459
1460 u32 darfrc;
1461 u32 darfrch;
1462};
1463
1464struct rtw_coex {
1465
1466 struct mutex mutex;
1467 struct sk_buff_head queue;
1468 wait_queue_head_t wait;
1469
1470 bool under_5g;
1471 bool stop_dm;
1472 bool freeze;
1473 bool freerun;
1474 bool wl_rf_off;
1475 bool manual_control;
1476
1477 struct rtw_coex_stat stat;
1478 struct rtw_coex_dm dm;
1479 struct rtw_coex_rfe rfe;
1480
1481 struct delayed_work bt_relink_work;
1482 struct delayed_work bt_reenable_work;
1483 struct delayed_work defreeze_work;
1484 struct delayed_work wl_remain_work;
1485 struct delayed_work bt_remain_work;
1486 struct delayed_work wl_connecting_work;
1487 struct delayed_work bt_multi_link_remain_work;
1488 struct delayed_work wl_ccklock_work;
1489
1490};
1491
1492#define DPK_RF_REG_NUM 7
1493#define DPK_RF_PATH_NUM 2
1494#define DPK_BB_REG_NUM 18
1495#define DPK_CHANNEL_WIDTH_80 1
1496
1497DECLARE_EWMA(thermal, 10, 4);
1498
1499struct rtw_dpk_info {
1500 bool is_dpk_pwr_on;
1501 bool is_reload;
1502
1503 DECLARE_BITMAP(dpk_path_ok, DPK_RF_PATH_NUM);
1504
1505 u8 thermal_dpk[DPK_RF_PATH_NUM];
1506 struct ewma_thermal avg_thermal[DPK_RF_PATH_NUM];
1507
1508 u32 gnt_control;
1509 u32 gnt_value;
1510
1511 u8 result[RTW_RF_PATH_MAX];
1512 u8 dpk_txagc[RTW_RF_PATH_MAX];
1513 u32 coef[RTW_RF_PATH_MAX][20];
1514 u16 dpk_gs[RTW_RF_PATH_MAX];
1515 u8 thermal_dpk_delta[RTW_RF_PATH_MAX];
1516 u8 pre_pwsf[RTW_RF_PATH_MAX];
1517
1518 u8 dpk_band;
1519 u8 dpk_ch;
1520 u8 dpk_bw;
1521};
1522
1523struct rtw_phy_cck_pd_reg {
1524 u32 reg_pd;
1525 u32 mask_pd;
1526 u32 reg_cs;
1527 u32 mask_cs;
1528};
1529
1530#define DACK_MSBK_BACKUP_NUM 0xf
1531#define DACK_DCK_BACKUP_NUM 0x2
1532
1533struct rtw_swing_table {
1534 const u8 *p[RTW_RF_PATH_MAX];
1535 const u8 *n[RTW_RF_PATH_MAX];
1536};
1537
1538struct rtw_pkt_count {
1539 u16 num_bcn_pkt;
1540 u16 num_qry_pkt[DESC_RATE_MAX];
1541};
1542
1543DECLARE_EWMA(evm, 10, 4);
1544DECLARE_EWMA(snr, 10, 4);
1545
1546struct rtw_iqk_info {
1547 bool done;
1548 struct {
1549 u32 s1_x;
1550 u32 s1_y;
1551 u32 s0_x;
1552 u32 s0_y;
1553 } result;
1554};
1555
1556enum rtw_rf_band {
1557 RF_BAND_2G_CCK,
1558 RF_BAND_2G_OFDM,
1559 RF_BAND_5G_L,
1560 RF_BAND_5G_M,
1561 RF_BAND_5G_H,
1562 RF_BAND_MAX
1563};
1564
1565#define RF_GAIN_NUM 11
1566#define RF_HW_OFFSET_NUM 10
1567
1568struct rtw_gapk_info {
1569 u32 rf3f_bp[RF_BAND_MAX][RF_GAIN_NUM][RTW_RF_PATH_MAX];
1570 u32 rf3f_fs[RTW_RF_PATH_MAX][RF_GAIN_NUM];
1571 bool txgapk_bp_done;
1572 s8 offset[RF_GAIN_NUM][RTW_RF_PATH_MAX];
1573 s8 fianl_offset[RF_GAIN_NUM][RTW_RF_PATH_MAX];
1574 u8 read_txgain;
1575 u8 channel;
1576};
1577
1578#define EDCCA_TH_L2H_IDX 0
1579#define EDCCA_TH_H2L_IDX 1
1580#define EDCCA_TH_L2H_LB 48
1581#define EDCCA_ADC_BACKOFF 12
1582#define EDCCA_IGI_BASE 50
1583#define EDCCA_IGI_L2H_DIFF 8
1584#define EDCCA_L2H_H2L_DIFF 7
1585#define EDCCA_L2H_H2L_DIFF_NORMAL 8
1586
1587enum rtw_edcca_mode {
1588 RTW_EDCCA_NORMAL = 0,
1589 RTW_EDCCA_ADAPTIVITY = 1,
1590};
1591
1592struct rtw_cfo_track {
1593 bool is_adjust;
1594 u8 crystal_cap;
1595 s32 cfo_tail[RTW_RF_PATH_MAX];
1596 s32 cfo_cnt[RTW_RF_PATH_MAX];
1597 u32 packet_count;
1598 u32 packet_count_pre;
1599};
1600
1601#define RRSR_INIT_2G 0x15f
1602#define RRSR_INIT_5G 0x150
1603
1604enum rtw_dm_cap {
1605 RTW_DM_CAP_NA,
1606 RTW_DM_CAP_TXGAPK,
1607 RTW_DM_CAP_NUM
1608};
1609
1610struct rtw_dm_info {
1611 u32 cck_fa_cnt;
1612 u32 ofdm_fa_cnt;
1613 u32 total_fa_cnt;
1614 u32 cck_cca_cnt;
1615 u32 ofdm_cca_cnt;
1616 u32 total_cca_cnt;
1617
1618 u32 cck_ok_cnt;
1619 u32 cck_err_cnt;
1620 u32 ofdm_ok_cnt;
1621 u32 ofdm_err_cnt;
1622 u32 ht_ok_cnt;
1623 u32 ht_err_cnt;
1624 u32 vht_ok_cnt;
1625 u32 vht_err_cnt;
1626
1627 u8 min_rssi;
1628 u8 pre_min_rssi;
1629 u16 fa_history[4];
1630 u8 igi_history[4];
1631 u8 igi_bitmap;
1632 bool damping;
1633 u8 damping_cnt;
1634 u8 damping_rssi;
1635
1636 u8 cck_gi_u_bnd;
1637 u8 cck_gi_l_bnd;
1638
1639 u8 fix_rate;
1640 u8 tx_rate;
1641 u32 rrsr_val_init;
1642 u32 rrsr_mask_min;
1643 u8 thermal_avg[RTW_RF_PATH_MAX];
1644 u8 thermal_meter_k;
1645 u8 thermal_meter_lck;
1646 s8 delta_power_index[RTW_RF_PATH_MAX];
1647 s8 delta_power_index_last[RTW_RF_PATH_MAX];
1648 u8 default_ofdm_index;
1649 bool pwr_trk_triggered;
1650 bool pwr_trk_init_trigger;
1651 struct ewma_thermal avg_thermal[RTW_RF_PATH_MAX];
1652 s8 txagc_remnant_cck;
1653 s8 txagc_remnant_ofdm;
1654
1655
1656 u32 dack_adck[RTW_RF_PATH_MAX];
1657 u16 dack_msbk[RTW_RF_PATH_MAX][2][DACK_MSBK_BACKUP_NUM];
1658 u8 dack_dck[RTW_RF_PATH_MAX][2][DACK_DCK_BACKUP_NUM];
1659
1660 struct rtw_dpk_info dpk_info;
1661 struct rtw_cfo_track cfo_track;
1662
1663
1664 u8 cck_pd_lv[2][RTW_RF_PATH_MAX];
1665 u32 cck_fa_avg;
1666 u8 cck_pd_default;
1667
1668
1669 s8 rx_snr[RTW_RF_PATH_MAX];
1670 u8 rx_evm_dbm[RTW_RF_PATH_MAX];
1671 s16 cfo_tail[RTW_RF_PATH_MAX];
1672 u8 rssi[RTW_RF_PATH_MAX];
1673 u8 curr_rx_rate;
1674 struct rtw_pkt_count cur_pkt_count;
1675 struct rtw_pkt_count last_pkt_count;
1676 struct ewma_evm ewma_evm[RTW_EVM_NUM];
1677 struct ewma_snr ewma_snr[RTW_SNR_NUM];
1678
1679 u32 dm_flags;
1680 struct rtw_iqk_info iqk;
1681 struct rtw_gapk_info gapk;
1682 bool is_bt_iqk_timeout;
1683
1684 s8 l2h_th_ini;
1685 enum rtw_edcca_mode edcca_mode;
1686 u8 scan_density;
1687};
1688
1689struct rtw_efuse {
1690 u32 size;
1691 u32 physical_size;
1692 u32 logical_size;
1693 u32 protect_size;
1694
1695 u8 addr[ETH_ALEN];
1696 u8 channel_plan;
1697 u8 country_code[2];
1698 u8 rf_board_option;
1699 u8 rfe_option;
1700 u8 power_track_type;
1701 u8 thermal_meter[RTW_RF_PATH_MAX];
1702 u8 thermal_meter_k;
1703 u8 crystal_cap;
1704 u8 ant_div_cfg;
1705 u8 ant_div_type;
1706 u8 regd;
1707 u8 afe;
1708
1709 u8 lna_type_2g;
1710 u8 lna_type_5g;
1711 u8 glna_type;
1712 u8 alna_type;
1713 bool ext_lna_2g;
1714 bool ext_lna_5g;
1715 u8 pa_type_2g;
1716 u8 pa_type_5g;
1717 u8 gpa_type;
1718 u8 apa_type;
1719 bool ext_pa_2g;
1720 bool ext_pa_5g;
1721 u8 tx_bb_swing_setting_2g;
1722 u8 tx_bb_swing_setting_5g;
1723
1724 bool btcoex;
1725
1726 bool share_ant;
1727 u8 bt_setting;
1728
1729 struct {
1730 u8 hci;
1731 u8 bw;
1732 u8 ptcl;
1733 u8 nss;
1734 u8 ant_num;
1735 } hw_cap;
1736
1737 struct rtw_txpwr_idx txpwr_idx_table[4];
1738};
1739
1740struct rtw_phy_cond {
1741#ifdef __LITTLE_ENDIAN
1742 u32 rfe:8;
1743 u32 intf:4;
1744 u32 pkg:4;
1745 u32 plat:4;
1746 u32 intf_rsvd:4;
1747 u32 cut:4;
1748 u32 branch:2;
1749 u32 neg:1;
1750 u32 pos:1;
1751#else
1752 u32 pos:1;
1753 u32 neg:1;
1754 u32 branch:2;
1755 u32 cut:4;
1756 u32 intf_rsvd:4;
1757 u32 plat:4;
1758 u32 pkg:4;
1759 u32 intf:4;
1760 u32 rfe:8;
1761#endif
1762
1763 #define INTF_PCIE BIT(0)
1764 #define INTF_USB BIT(1)
1765 #define INTF_SDIO BIT(2)
1766
1767 #define BRANCH_IF 0
1768 #define BRANCH_ELIF 1
1769 #define BRANCH_ELSE 2
1770 #define BRANCH_ENDIF 3
1771};
1772
1773struct rtw_fifo_conf {
1774
1775 u16 rsvd_boundary;
1776 u16 rsvd_pg_num;
1777 u16 rsvd_drv_pg_num;
1778 u16 txff_pg_num;
1779 u16 acq_pg_num;
1780 u16 rsvd_drv_addr;
1781 u16 rsvd_h2c_info_addr;
1782 u16 rsvd_h2c_sta_info_addr;
1783 u16 rsvd_h2cq_addr;
1784 u16 rsvd_cpu_instr_addr;
1785 u16 rsvd_fw_txbuf_addr;
1786 u16 rsvd_csibuf_addr;
1787 const struct rtw_rqpn *rqpn;
1788};
1789
1790struct rtw_fwcd_desc {
1791 u32 size;
1792 u8 *next;
1793 u8 *data;
1794};
1795
1796struct rtw_fwcd_segs {
1797 const u32 *segs;
1798 u8 num;
1799};
1800
1801#define FW_CD_TYPE 0xffff
1802#define FW_CD_LEN 4
1803#define FW_CD_VAL 0xaabbccdd
1804struct rtw_fw_state {
1805 const struct firmware *firmware;
1806 struct rtw_dev *rtwdev;
1807 struct completion completion;
1808 struct rtw_fwcd_desc fwcd_desc;
1809 u16 version;
1810 u8 sub_version;
1811 u8 sub_index;
1812 u16 h2c_version;
1813 u32 feature;
1814};
1815
1816enum rtw_sar_sources {
1817 RTW_SAR_SOURCE_NONE,
1818 RTW_SAR_SOURCE_COMMON,
1819};
1820
1821enum rtw_sar_bands {
1822 RTW_SAR_BAND_0,
1823 RTW_SAR_BAND_1,
1824
1825 RTW_SAR_BAND_3,
1826 RTW_SAR_BAND_4,
1827
1828 RTW_SAR_BAND_NR,
1829};
1830
1831
1832
1833
1834union rtw_sar_cfg {
1835 s8 common[RTW_SAR_BAND_NR];
1836};
1837
1838struct rtw_sar {
1839 enum rtw_sar_sources src;
1840 union rtw_sar_cfg cfg[RTW_RF_PATH_MAX][RTW_RATE_SECTION_MAX];
1841};
1842
1843struct rtw_hal {
1844 u32 rcr;
1845
1846 u32 chip_version;
1847 u8 cut_version;
1848 u8 mp_chip;
1849 u8 oem_id;
1850 struct rtw_phy_cond phy_cond;
1851
1852 u8 ps_mode;
1853 u8 current_channel;
1854 u8 current_primary_channel_index;
1855 u8 current_band_width;
1856 u8 current_band_type;
1857
1858
1859
1860
1861 u8 cch_by_bw[RTW_MAX_CHANNEL_WIDTH + 1];
1862
1863 u8 sec_ch_offset;
1864 u8 rf_type;
1865 u8 rf_path_num;
1866 u8 rf_phy_num;
1867 u32 antenna_tx;
1868 u32 antenna_rx;
1869 u8 bfee_sts_cap;
1870
1871
1872 struct mutex tx_power_mutex;
1873 s8 tx_pwr_by_rate_offset_2g[RTW_RF_PATH_MAX]
1874 [DESC_RATE_MAX];
1875 s8 tx_pwr_by_rate_offset_5g[RTW_RF_PATH_MAX]
1876 [DESC_RATE_MAX];
1877 s8 tx_pwr_by_rate_base_2g[RTW_RF_PATH_MAX]
1878 [RTW_RATE_SECTION_MAX];
1879 s8 tx_pwr_by_rate_base_5g[RTW_RF_PATH_MAX]
1880 [RTW_RATE_SECTION_MAX];
1881 s8 tx_pwr_limit_2g[RTW_REGD_MAX]
1882 [RTW_CHANNEL_WIDTH_MAX]
1883 [RTW_RATE_SECTION_MAX]
1884 [RTW_MAX_CHANNEL_NUM_2G];
1885 s8 tx_pwr_limit_5g[RTW_REGD_MAX]
1886 [RTW_CHANNEL_WIDTH_MAX]
1887 [RTW_RATE_SECTION_MAX]
1888 [RTW_MAX_CHANNEL_NUM_5G];
1889 s8 tx_pwr_tbl[RTW_RF_PATH_MAX]
1890 [DESC_RATE_MAX];
1891
1892 enum rtw_sar_bands sar_band;
1893 struct rtw_sar sar;
1894};
1895
1896struct rtw_path_div {
1897 enum rtw_bb_path current_tx_path;
1898 u32 path_a_sum;
1899 u32 path_b_sum;
1900 u16 path_a_cnt;
1901 u16 path_b_cnt;
1902};
1903
1904struct rtw_chan_info {
1905 int pri_ch_idx;
1906 int action_id;
1907 int bw;
1908 u8 extra_info;
1909 u8 channel;
1910 u16 timeout;
1911};
1912
1913struct rtw_chan_list {
1914 u32 buf_size;
1915 u32 ch_num;
1916 u32 size;
1917 u16 addr;
1918};
1919
1920struct rtw_hw_scan_info {
1921 struct ieee80211_vif *scanning_vif;
1922 u8 probe_pg_size;
1923 u8 op_pri_ch_idx;
1924 u8 op_chan;
1925 u8 op_bw;
1926};
1927
1928struct rtw_dev {
1929 struct ieee80211_hw *hw;
1930 struct device *dev;
1931
1932 struct rtw_hci hci;
1933
1934 struct rtw_hw_scan_info scan_info;
1935 struct rtw_chip_info *chip;
1936 struct rtw_hal hal;
1937 struct rtw_fifo_conf fifo;
1938 struct rtw_fw_state fw;
1939 struct rtw_efuse efuse;
1940 struct rtw_sec_desc sec;
1941 struct rtw_traffic_stats stats;
1942 struct rtw_regd regd;
1943 struct rtw_bf_info bf_info;
1944
1945 struct rtw_dm_info dm_info;
1946 struct rtw_coex coex;
1947
1948
1949 struct mutex mutex;
1950
1951
1952 spinlock_t rf_lock;
1953
1954
1955 struct delayed_work watch_dog_work;
1956 u32 watch_dog_cnt;
1957
1958 struct list_head rsvd_page_list;
1959
1960
1961 struct sk_buff_head c2h_queue;
1962 struct work_struct c2h_work;
1963 struct work_struct fw_recovery_work;
1964
1965
1966 spinlock_t txq_lock;
1967 struct list_head txqs;
1968 struct workqueue_struct *tx_wq;
1969 struct work_struct tx_work;
1970 struct work_struct ba_work;
1971
1972 struct rtw_tx_report tx_report;
1973
1974 struct {
1975
1976 u8 last_box_num;
1977
1978 spinlock_t lock;
1979 u32 seq;
1980 } h2c;
1981
1982
1983 struct rtw_lps_conf lps_conf;
1984 bool ps_enabled;
1985 bool beacon_loss;
1986 struct completion lps_leave_check;
1987
1988 struct dentry *debugfs;
1989
1990 u8 sta_cnt;
1991 u32 rts_threshold;
1992
1993 DECLARE_BITMAP(mac_id_map, RTW_MAX_MAC_ID_NUM);
1994 DECLARE_BITMAP(flags, NUM_OF_RTW_FLAGS);
1995
1996 u8 mp_mode;
1997 struct rtw_path_div dm_path_div;
1998
1999 struct rtw_fw_state wow_fw;
2000 struct rtw_wow_param wow;
2001
2002 bool need_rfk;
2003 struct completion fw_scan_density;
2004
2005
2006 u8 priv[] __aligned(sizeof(void *));
2007};
2008
2009#include "hci.h"
2010
2011static inline bool rtw_is_assoc(struct rtw_dev *rtwdev)
2012{
2013 return !!rtwdev->sta_cnt;
2014}
2015
2016static inline struct ieee80211_txq *rtwtxq_to_txq(struct rtw_txq *rtwtxq)
2017{
2018 void *p = rtwtxq;
2019
2020 return container_of(p, struct ieee80211_txq, drv_priv);
2021}
2022
2023static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw_vif *rtwvif)
2024{
2025 void *p = rtwvif;
2026
2027 return container_of(p, struct ieee80211_vif, drv_priv);
2028}
2029
2030static inline bool rtw_ssid_equal(struct cfg80211_ssid *a,
2031 struct cfg80211_ssid *b)
2032{
2033 if (!a || !b || a->ssid_len != b->ssid_len)
2034 return false;
2035
2036 if (memcmp(a->ssid, b->ssid, a->ssid_len))
2037 return false;
2038
2039 return true;
2040}
2041
2042static inline void rtw_chip_efuse_grant_on(struct rtw_dev *rtwdev)
2043{
2044 if (rtwdev->chip->ops->efuse_grant)
2045 rtwdev->chip->ops->efuse_grant(rtwdev, true);
2046}
2047
2048static inline void rtw_chip_efuse_grant_off(struct rtw_dev *rtwdev)
2049{
2050 if (rtwdev->chip->ops->efuse_grant)
2051 rtwdev->chip->ops->efuse_grant(rtwdev, false);
2052}
2053
2054static inline bool rtw_chip_wcpu_11n(struct rtw_dev *rtwdev)
2055{
2056 return rtwdev->chip->wlan_cpu == RTW_WCPU_11N;
2057}
2058
2059static inline bool rtw_chip_wcpu_11ac(struct rtw_dev *rtwdev)
2060{
2061 return rtwdev->chip->wlan_cpu == RTW_WCPU_11AC;
2062}
2063
2064static inline bool rtw_chip_has_rx_ldpc(struct rtw_dev *rtwdev)
2065{
2066 return rtwdev->chip->rx_ldpc;
2067}
2068
2069static inline bool rtw_chip_has_tx_stbc(struct rtw_dev *rtwdev)
2070{
2071 return rtwdev->chip->tx_stbc;
2072}
2073
2074static inline void rtw_release_macid(struct rtw_dev *rtwdev, u8 mac_id)
2075{
2076 clear_bit(mac_id, rtwdev->mac_id_map);
2077}
2078
2079static inline int rtw_chip_dump_fw_crash(struct rtw_dev *rtwdev)
2080{
2081 if (rtwdev->chip->ops->dump_fw_crash)
2082 return rtwdev->chip->ops->dump_fw_crash(rtwdev);
2083
2084 return 0;
2085}
2086
2087void rtw_set_rx_freq_band(struct rtw_rx_pkt_stat *pkt_stat, u8 channel);
2088void rtw_get_channel_params(struct cfg80211_chan_def *chandef,
2089 struct rtw_channel_params *ch_param);
2090bool check_hw_ready(struct rtw_dev *rtwdev, u32 addr, u32 mask, u32 target);
2091bool ltecoex_read_reg(struct rtw_dev *rtwdev, u16 offset, u32 *val);
2092bool ltecoex_reg_write(struct rtw_dev *rtwdev, u16 offset, u32 value);
2093void rtw_restore_reg(struct rtw_dev *rtwdev,
2094 struct rtw_backup_info *bckp, u32 num);
2095void rtw_desc_to_mcsrate(u16 rate, u8 *mcs, u8 *nss);
2096void rtw_set_channel(struct rtw_dev *rtwdev);
2097void rtw_chip_prepare_tx(struct rtw_dev *rtwdev);
2098void rtw_vif_port_config(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif,
2099 u32 config);
2100void rtw_tx_report_purge_timer(struct timer_list *t);
2101void rtw_update_sta_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si);
2102void rtw_core_scan_start(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif,
2103 const u8 *mac_addr, bool hw_scan);
2104void rtw_core_scan_complete(struct rtw_dev *rtwdev, struct ieee80211_vif *vif);
2105int rtw_core_start(struct rtw_dev *rtwdev);
2106void rtw_core_stop(struct rtw_dev *rtwdev);
2107int rtw_chip_info_setup(struct rtw_dev *rtwdev);
2108int rtw_core_init(struct rtw_dev *rtwdev);
2109void rtw_core_deinit(struct rtw_dev *rtwdev);
2110int rtw_register_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw);
2111void rtw_unregister_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw);
2112u16 rtw_desc_to_bitrate(u8 desc_rate);
2113void rtw_vif_assoc_changed(struct rtw_vif *rtwvif,
2114 struct ieee80211_bss_conf *conf);
2115int rtw_sta_add(struct rtw_dev *rtwdev, struct ieee80211_sta *sta,
2116 struct ieee80211_vif *vif);
2117void rtw_sta_remove(struct rtw_dev *rtwdev, struct ieee80211_sta *sta,
2118 bool fw_exist);
2119void rtw_fw_recovery(struct rtw_dev *rtwdev);
2120void rtw_core_fw_scan_notify(struct rtw_dev *rtwdev, bool start);
2121int rtw_dump_fw(struct rtw_dev *rtwdev, const u32 ocp_src, u32 size,
2122 u32 fwcd_item);
2123int rtw_dump_reg(struct rtw_dev *rtwdev, const u32 addr, const u32 size);
2124
2125#endif
2126
