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11#include <linux/bitfield.h>
12#include <linux/clk.h>
13#include <linux/delay.h>
14#include <linux/gpio.h>
15#include <linux/kernel.h>
16#include <linux/mfd/syscon.h>
17#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
18#include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
19#include <linux/module.h>
20#include <linux/of_gpio.h>
21#include <linux/of_device.h>
22#include <linux/of_address.h>
23#include <linux/pci.h>
24#include <linux/platform_device.h>
25#include <linux/regmap.h>
26#include <linux/regulator/consumer.h>
27#include <linux/resource.h>
28#include <linux/signal.h>
29#include <linux/types.h>
30#include <linux/interrupt.h>
31#include <linux/reset.h>
32#include <linux/phy/phy.h>
33#include <linux/pm_domain.h>
34#include <linux/pm_runtime.h>
35
36#include "pcie-designware.h"
37
38#define IMX8MQ_GPR_PCIE_REF_USE_PAD BIT(9)
39#define IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN BIT(10)
40#define IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE BIT(11)
41#define IMX8MQ_GPR_PCIE_VREG_BYPASS BIT(12)
42#define IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE GENMASK(11, 8)
43#define IMX8MQ_PCIE2_BASE_ADDR 0x33c00000
44
45#define to_imx6_pcie(x) dev_get_drvdata((x)->dev)
46
47enum imx6_pcie_variants {
48 IMX6Q,
49 IMX6SX,
50 IMX6QP,
51 IMX7D,
52 IMX8MQ,
53 IMX8MM,
54};
55
56#define IMX6_PCIE_FLAG_IMX6_PHY BIT(0)
57#define IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE BIT(1)
58#define IMX6_PCIE_FLAG_SUPPORTS_SUSPEND BIT(2)
59
60struct imx6_pcie_drvdata {
61 enum imx6_pcie_variants variant;
62 u32 flags;
63 int dbi_length;
64};
65
66struct imx6_pcie {
67 struct dw_pcie *pci;
68 int reset_gpio;
69 bool gpio_active_high;
70 struct clk *pcie_bus;
71 struct clk *pcie_phy;
72 struct clk *pcie_inbound_axi;
73 struct clk *pcie;
74 struct clk *pcie_aux;
75 struct regmap *iomuxc_gpr;
76 u32 controller_id;
77 struct reset_control *pciephy_reset;
78 struct reset_control *apps_reset;
79 struct reset_control *turnoff_reset;
80 u32 tx_deemph_gen1;
81 u32 tx_deemph_gen2_3p5db;
82 u32 tx_deemph_gen2_6db;
83 u32 tx_swing_full;
84 u32 tx_swing_low;
85 struct regulator *vpcie;
86 struct regulator *vph;
87 void __iomem *phy_base;
88
89
90 struct device *pd_pcie;
91
92 struct device *pd_pcie_phy;
93 struct phy *phy;
94 const struct imx6_pcie_drvdata *drvdata;
95};
96
97
98#define PHY_PLL_LOCK_WAIT_USLEEP_MAX 200
99#define PHY_PLL_LOCK_WAIT_TIMEOUT (2000 * PHY_PLL_LOCK_WAIT_USLEEP_MAX)
100
101
102#define PL_OFFSET 0x700
103
104#define PCIE_PHY_CTRL (PL_OFFSET + 0x114)
105#define PCIE_PHY_CTRL_DATA(x) FIELD_PREP(GENMASK(15, 0), (x))
106#define PCIE_PHY_CTRL_CAP_ADR BIT(16)
107#define PCIE_PHY_CTRL_CAP_DAT BIT(17)
108#define PCIE_PHY_CTRL_WR BIT(18)
109#define PCIE_PHY_CTRL_RD BIT(19)
110
111#define PCIE_PHY_STAT (PL_OFFSET + 0x110)
112#define PCIE_PHY_STAT_ACK BIT(16)
113
114
115#define PCIE_PHY_ATEOVRD 0x10
116#define PCIE_PHY_ATEOVRD_EN BIT(2)
117#define PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT 0
118#define PCIE_PHY_ATEOVRD_REF_CLKDIV_MASK 0x1
119
120#define PCIE_PHY_MPLL_OVRD_IN_LO 0x11
121#define PCIE_PHY_MPLL_MULTIPLIER_SHIFT 2
122#define PCIE_PHY_MPLL_MULTIPLIER_MASK 0x7f
123#define PCIE_PHY_MPLL_MULTIPLIER_OVRD BIT(9)
124
125#define PCIE_PHY_RX_ASIC_OUT 0x100D
126#define PCIE_PHY_RX_ASIC_OUT_VALID (1 << 0)
127
128
129#define PCIE_PHY_CMN_REG4 0x14
130
131#define PCIE_PHY_CMN_REG4_DCC_FB_EN 0x29
132
133#define PCIE_PHY_CMN_REG15 0x54
134#define PCIE_PHY_CMN_REG15_DLY_4 BIT(2)
135#define PCIE_PHY_CMN_REG15_PLL_PD BIT(5)
136#define PCIE_PHY_CMN_REG15_OVRD_PLL_PD BIT(7)
137
138#define PCIE_PHY_CMN_REG24 0x90
139#define PCIE_PHY_CMN_REG24_RX_EQ BIT(6)
140#define PCIE_PHY_CMN_REG24_RX_EQ_SEL BIT(3)
141
142#define PCIE_PHY_CMN_REG26 0x98
143#define PCIE_PHY_CMN_REG26_ATT_MODE 0xBC
144
145#define PHY_RX_OVRD_IN_LO 0x1005
146#define PHY_RX_OVRD_IN_LO_RX_DATA_EN BIT(5)
147#define PHY_RX_OVRD_IN_LO_RX_PLL_EN BIT(3)
148
149static int pcie_phy_poll_ack(struct imx6_pcie *imx6_pcie, bool exp_val)
150{
151 struct dw_pcie *pci = imx6_pcie->pci;
152 bool val;
153 u32 max_iterations = 10;
154 u32 wait_counter = 0;
155
156 do {
157 val = dw_pcie_readl_dbi(pci, PCIE_PHY_STAT) &
158 PCIE_PHY_STAT_ACK;
159 wait_counter++;
160
161 if (val == exp_val)
162 return 0;
163
164 udelay(1);
165 } while (wait_counter < max_iterations);
166
167 return -ETIMEDOUT;
168}
169
170static int pcie_phy_wait_ack(struct imx6_pcie *imx6_pcie, int addr)
171{
172 struct dw_pcie *pci = imx6_pcie->pci;
173 u32 val;
174 int ret;
175
176 val = PCIE_PHY_CTRL_DATA(addr);
177 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val);
178
179 val |= PCIE_PHY_CTRL_CAP_ADR;
180 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val);
181
182 ret = pcie_phy_poll_ack(imx6_pcie, true);
183 if (ret)
184 return ret;
185
186 val = PCIE_PHY_CTRL_DATA(addr);
187 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val);
188
189 return pcie_phy_poll_ack(imx6_pcie, false);
190}
191
192
193static int pcie_phy_read(struct imx6_pcie *imx6_pcie, int addr, u16 *data)
194{
195 struct dw_pcie *pci = imx6_pcie->pci;
196 u32 phy_ctl;
197 int ret;
198
199 ret = pcie_phy_wait_ack(imx6_pcie, addr);
200 if (ret)
201 return ret;
202
203
204 phy_ctl = PCIE_PHY_CTRL_RD;
205 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, phy_ctl);
206
207 ret = pcie_phy_poll_ack(imx6_pcie, true);
208 if (ret)
209 return ret;
210
211 *data = dw_pcie_readl_dbi(pci, PCIE_PHY_STAT);
212
213
214 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, 0x00);
215
216 return pcie_phy_poll_ack(imx6_pcie, false);
217}
218
219static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, u16 data)
220{
221 struct dw_pcie *pci = imx6_pcie->pci;
222 u32 var;
223 int ret;
224
225
226
227 ret = pcie_phy_wait_ack(imx6_pcie, addr);
228 if (ret)
229 return ret;
230
231 var = PCIE_PHY_CTRL_DATA(data);
232 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
233
234
235 var |= PCIE_PHY_CTRL_CAP_DAT;
236 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
237
238 ret = pcie_phy_poll_ack(imx6_pcie, true);
239 if (ret)
240 return ret;
241
242
243 var = PCIE_PHY_CTRL_DATA(data);
244 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
245
246
247 ret = pcie_phy_poll_ack(imx6_pcie, false);
248 if (ret)
249 return ret;
250
251
252 var = PCIE_PHY_CTRL_WR;
253 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
254
255
256 ret = pcie_phy_poll_ack(imx6_pcie, true);
257 if (ret)
258 return ret;
259
260
261 var = PCIE_PHY_CTRL_DATA(data);
262 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
263
264
265 ret = pcie_phy_poll_ack(imx6_pcie, false);
266 if (ret)
267 return ret;
268
269 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, 0x0);
270
271 return 0;
272}
273
274static void imx6_pcie_reset_phy(struct imx6_pcie *imx6_pcie)
275{
276 u16 tmp;
277
278 if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_IMX6_PHY))
279 return;
280
281 pcie_phy_read(imx6_pcie, PHY_RX_OVRD_IN_LO, &tmp);
282 tmp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN |
283 PHY_RX_OVRD_IN_LO_RX_PLL_EN);
284 pcie_phy_write(imx6_pcie, PHY_RX_OVRD_IN_LO, tmp);
285
286 usleep_range(2000, 3000);
287
288 pcie_phy_read(imx6_pcie, PHY_RX_OVRD_IN_LO, &tmp);
289 tmp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN |
290 PHY_RX_OVRD_IN_LO_RX_PLL_EN);
291 pcie_phy_write(imx6_pcie, PHY_RX_OVRD_IN_LO, tmp);
292}
293
294#ifdef CONFIG_ARM
295
296static int imx6q_pcie_abort_handler(unsigned long addr,
297 unsigned int fsr, struct pt_regs *regs)
298{
299 unsigned long pc = instruction_pointer(regs);
300 unsigned long instr = *(unsigned long *)pc;
301 int reg = (instr >> 12) & 15;
302
303
304
305
306
307 if ((instr & 0x0c100000) == 0x04100000) {
308 unsigned long val;
309
310 if (instr & 0x00400000)
311 val = 255;
312 else
313 val = -1;
314
315 regs->uregs[reg] = val;
316 regs->ARM_pc += 4;
317 return 0;
318 }
319
320 if ((instr & 0x0e100090) == 0x00100090) {
321 regs->uregs[reg] = -1;
322 regs->ARM_pc += 4;
323 return 0;
324 }
325
326 return 1;
327}
328#endif
329
330static int imx6_pcie_attach_pd(struct device *dev)
331{
332 struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
333 struct device_link *link;
334
335
336 if (dev->pm_domain)
337 return 0;
338
339 imx6_pcie->pd_pcie = dev_pm_domain_attach_by_name(dev, "pcie");
340 if (IS_ERR(imx6_pcie->pd_pcie))
341 return PTR_ERR(imx6_pcie->pd_pcie);
342
343 if (!imx6_pcie->pd_pcie)
344 return 0;
345 link = device_link_add(dev, imx6_pcie->pd_pcie,
346 DL_FLAG_STATELESS |
347 DL_FLAG_PM_RUNTIME |
348 DL_FLAG_RPM_ACTIVE);
349 if (!link) {
350 dev_err(dev, "Failed to add device_link to pcie pd.\n");
351 return -EINVAL;
352 }
353
354 imx6_pcie->pd_pcie_phy = dev_pm_domain_attach_by_name(dev, "pcie_phy");
355 if (IS_ERR(imx6_pcie->pd_pcie_phy))
356 return PTR_ERR(imx6_pcie->pd_pcie_phy);
357
358 link = device_link_add(dev, imx6_pcie->pd_pcie_phy,
359 DL_FLAG_STATELESS |
360 DL_FLAG_PM_RUNTIME |
361 DL_FLAG_RPM_ACTIVE);
362 if (!link) {
363 dev_err(dev, "Failed to add device_link to pcie_phy pd.\n");
364 return -EINVAL;
365 }
366
367 return 0;
368}
369
370static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie)
371{
372 struct device *dev = imx6_pcie->pci->dev;
373
374 switch (imx6_pcie->drvdata->variant) {
375 case IMX7D:
376 case IMX8MQ:
377 reset_control_assert(imx6_pcie->pciephy_reset);
378 fallthrough;
379 case IMX8MM:
380 reset_control_assert(imx6_pcie->apps_reset);
381 break;
382 case IMX6SX:
383 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
384 IMX6SX_GPR12_PCIE_TEST_POWERDOWN,
385 IMX6SX_GPR12_PCIE_TEST_POWERDOWN);
386
387 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5,
388 IMX6SX_GPR5_PCIE_BTNRST_RESET,
389 IMX6SX_GPR5_PCIE_BTNRST_RESET);
390 break;
391 case IMX6QP:
392 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
393 IMX6Q_GPR1_PCIE_SW_RST,
394 IMX6Q_GPR1_PCIE_SW_RST);
395 break;
396 case IMX6Q:
397 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
398 IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18);
399 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
400 IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16);
401 break;
402 }
403
404 if (imx6_pcie->vpcie && regulator_is_enabled(imx6_pcie->vpcie) > 0) {
405 int ret = regulator_disable(imx6_pcie->vpcie);
406
407 if (ret)
408 dev_err(dev, "failed to disable vpcie regulator: %d\n",
409 ret);
410 }
411}
412
413static unsigned int imx6_pcie_grp_offset(const struct imx6_pcie *imx6_pcie)
414{
415 WARN_ON(imx6_pcie->drvdata->variant != IMX8MQ &&
416 imx6_pcie->drvdata->variant != IMX8MM);
417 return imx6_pcie->controller_id == 1 ? IOMUXC_GPR16 : IOMUXC_GPR14;
418}
419
420static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
421{
422 struct dw_pcie *pci = imx6_pcie->pci;
423 struct device *dev = pci->dev;
424 unsigned int offset;
425 int ret = 0;
426
427 switch (imx6_pcie->drvdata->variant) {
428 case IMX6SX:
429 ret = clk_prepare_enable(imx6_pcie->pcie_inbound_axi);
430 if (ret) {
431 dev_err(dev, "unable to enable pcie_axi clock\n");
432 break;
433 }
434
435 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
436 IMX6SX_GPR12_PCIE_TEST_POWERDOWN, 0);
437 break;
438 case IMX6QP:
439 case IMX6Q:
440
441 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
442 IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18);
443
444
445
446
447
448
449 usleep_range(10, 100);
450 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
451 IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);
452 break;
453 case IMX7D:
454 break;
455 case IMX8MM:
456 ret = clk_prepare_enable(imx6_pcie->pcie_aux);
457 if (ret)
458 dev_err(dev, "unable to enable pcie_aux clock\n");
459 break;
460 case IMX8MQ:
461 ret = clk_prepare_enable(imx6_pcie->pcie_aux);
462 if (ret) {
463 dev_err(dev, "unable to enable pcie_aux clock\n");
464 break;
465 }
466
467 offset = imx6_pcie_grp_offset(imx6_pcie);
468
469
470
471
472 regmap_update_bits(imx6_pcie->iomuxc_gpr, offset,
473 IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE,
474 0);
475 regmap_update_bits(imx6_pcie->iomuxc_gpr, offset,
476 IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN,
477 IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN);
478 break;
479 }
480
481 return ret;
482}
483
484static void imx7d_pcie_wait_for_phy_pll_lock(struct imx6_pcie *imx6_pcie)
485{
486 u32 val;
487 struct device *dev = imx6_pcie->pci->dev;
488
489 if (regmap_read_poll_timeout(imx6_pcie->iomuxc_gpr,
490 IOMUXC_GPR22, val,
491 val & IMX7D_GPR22_PCIE_PHY_PLL_LOCKED,
492 PHY_PLL_LOCK_WAIT_USLEEP_MAX,
493 PHY_PLL_LOCK_WAIT_TIMEOUT))
494 dev_err(dev, "PCIe PLL lock timeout\n");
495}
496
497static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
498{
499 struct dw_pcie *pci = imx6_pcie->pci;
500 struct device *dev = pci->dev;
501 int ret;
502
503 if (imx6_pcie->vpcie && !regulator_is_enabled(imx6_pcie->vpcie)) {
504 ret = regulator_enable(imx6_pcie->vpcie);
505 if (ret) {
506 dev_err(dev, "failed to enable vpcie regulator: %d\n",
507 ret);
508 return;
509 }
510 }
511
512 ret = clk_prepare_enable(imx6_pcie->pcie_phy);
513 if (ret) {
514 dev_err(dev, "unable to enable pcie_phy clock\n");
515 goto err_pcie_phy;
516 }
517
518 ret = clk_prepare_enable(imx6_pcie->pcie_bus);
519 if (ret) {
520 dev_err(dev, "unable to enable pcie_bus clock\n");
521 goto err_pcie_bus;
522 }
523
524 ret = clk_prepare_enable(imx6_pcie->pcie);
525 if (ret) {
526 dev_err(dev, "unable to enable pcie clock\n");
527 goto err_pcie;
528 }
529
530 ret = imx6_pcie_enable_ref_clk(imx6_pcie);
531 if (ret) {
532 dev_err(dev, "unable to enable pcie ref clock\n");
533 goto err_ref_clk;
534 }
535
536 switch (imx6_pcie->drvdata->variant) {
537 case IMX8MM:
538 if (phy_power_on(imx6_pcie->phy))
539 dev_err(dev, "unable to power on PHY\n");
540 break;
541 default:
542 break;
543 }
544
545 usleep_range(200, 500);
546
547
548 if (gpio_is_valid(imx6_pcie->reset_gpio)) {
549 gpio_set_value_cansleep(imx6_pcie->reset_gpio,
550 imx6_pcie->gpio_active_high);
551 msleep(100);
552 gpio_set_value_cansleep(imx6_pcie->reset_gpio,
553 !imx6_pcie->gpio_active_high);
554 }
555
556 switch (imx6_pcie->drvdata->variant) {
557 case IMX8MQ:
558 reset_control_deassert(imx6_pcie->pciephy_reset);
559 break;
560 case IMX8MM:
561 if (phy_init(imx6_pcie->phy))
562 dev_err(dev, "waiting for phy ready timeout!\n");
563 break;
564 case IMX7D:
565 reset_control_deassert(imx6_pcie->pciephy_reset);
566
567
568
569
570
571 if (likely(imx6_pcie->phy_base)) {
572
573 writel(PCIE_PHY_CMN_REG4_DCC_FB_EN,
574 imx6_pcie->phy_base + PCIE_PHY_CMN_REG4);
575
576 writel(PCIE_PHY_CMN_REG24_RX_EQ_SEL
577 | PCIE_PHY_CMN_REG24_RX_EQ,
578 imx6_pcie->phy_base + PCIE_PHY_CMN_REG24);
579
580 writel(PCIE_PHY_CMN_REG26_ATT_MODE,
581 imx6_pcie->phy_base + PCIE_PHY_CMN_REG26);
582 } else {
583 dev_warn(dev, "Unable to apply ERR010728 workaround. DT missing fsl,imx7d-pcie-phy phandle ?\n");
584 }
585
586 imx7d_pcie_wait_for_phy_pll_lock(imx6_pcie);
587 break;
588 case IMX6SX:
589 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5,
590 IMX6SX_GPR5_PCIE_BTNRST_RESET, 0);
591 break;
592 case IMX6QP:
593 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
594 IMX6Q_GPR1_PCIE_SW_RST, 0);
595
596 usleep_range(200, 500);
597 break;
598 case IMX6Q:
599 break;
600 }
601
602 return;
603
604err_ref_clk:
605 clk_disable_unprepare(imx6_pcie->pcie);
606err_pcie:
607 clk_disable_unprepare(imx6_pcie->pcie_bus);
608err_pcie_bus:
609 clk_disable_unprepare(imx6_pcie->pcie_phy);
610err_pcie_phy:
611 if (imx6_pcie->vpcie && regulator_is_enabled(imx6_pcie->vpcie) > 0) {
612 ret = regulator_disable(imx6_pcie->vpcie);
613 if (ret)
614 dev_err(dev, "failed to disable vpcie regulator: %d\n",
615 ret);
616 }
617}
618
619static void imx6_pcie_configure_type(struct imx6_pcie *imx6_pcie)
620{
621 unsigned int mask, val;
622
623 if (imx6_pcie->drvdata->variant == IMX8MQ &&
624 imx6_pcie->controller_id == 1) {
625 mask = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE;
626 val = FIELD_PREP(IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE,
627 PCI_EXP_TYPE_ROOT_PORT);
628 } else {
629 mask = IMX6Q_GPR12_DEVICE_TYPE;
630 val = FIELD_PREP(IMX6Q_GPR12_DEVICE_TYPE,
631 PCI_EXP_TYPE_ROOT_PORT);
632 }
633
634 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, mask, val);
635}
636
637static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
638{
639 switch (imx6_pcie->drvdata->variant) {
640 case IMX8MM:
641
642
643
644
645 break;
646 case IMX8MQ:
647
648
649
650
651 regmap_update_bits(imx6_pcie->iomuxc_gpr,
652 imx6_pcie_grp_offset(imx6_pcie),
653 IMX8MQ_GPR_PCIE_REF_USE_PAD,
654 IMX8MQ_GPR_PCIE_REF_USE_PAD);
655
656
657
658
659
660 if (imx6_pcie->vph &&
661 regulator_get_voltage(imx6_pcie->vph) > 3000000)
662 regmap_update_bits(imx6_pcie->iomuxc_gpr,
663 imx6_pcie_grp_offset(imx6_pcie),
664 IMX8MQ_GPR_PCIE_VREG_BYPASS,
665 0);
666 break;
667 case IMX7D:
668 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
669 IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, 0);
670 break;
671 case IMX6SX:
672 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
673 IMX6SX_GPR12_PCIE_RX_EQ_MASK,
674 IMX6SX_GPR12_PCIE_RX_EQ_2);
675 fallthrough;
676 default:
677 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
678 IMX6Q_GPR12_PCIE_CTL_2, 0 << 10);
679
680
681 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
682 IMX6Q_GPR12_LOS_LEVEL, 9 << 4);
683
684 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
685 IMX6Q_GPR8_TX_DEEMPH_GEN1,
686 imx6_pcie->tx_deemph_gen1 << 0);
687 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
688 IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB,
689 imx6_pcie->tx_deemph_gen2_3p5db << 6);
690 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
691 IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB,
692 imx6_pcie->tx_deemph_gen2_6db << 12);
693 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
694 IMX6Q_GPR8_TX_SWING_FULL,
695 imx6_pcie->tx_swing_full << 18);
696 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
697 IMX6Q_GPR8_TX_SWING_LOW,
698 imx6_pcie->tx_swing_low << 25);
699 break;
700 }
701
702 imx6_pcie_configure_type(imx6_pcie);
703}
704
705static int imx6_setup_phy_mpll(struct imx6_pcie *imx6_pcie)
706{
707 unsigned long phy_rate = clk_get_rate(imx6_pcie->pcie_phy);
708 int mult, div;
709 u16 val;
710
711 if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_IMX6_PHY))
712 return 0;
713
714 switch (phy_rate) {
715 case 125000000:
716
717
718
719
720 return 0;
721 case 100000000:
722 mult = 25;
723 div = 0;
724 break;
725 case 200000000:
726 mult = 25;
727 div = 1;
728 break;
729 default:
730 dev_err(imx6_pcie->pci->dev,
731 "Unsupported PHY reference clock rate %lu\n", phy_rate);
732 return -EINVAL;
733 }
734
735 pcie_phy_read(imx6_pcie, PCIE_PHY_MPLL_OVRD_IN_LO, &val);
736 val &= ~(PCIE_PHY_MPLL_MULTIPLIER_MASK <<
737 PCIE_PHY_MPLL_MULTIPLIER_SHIFT);
738 val |= mult << PCIE_PHY_MPLL_MULTIPLIER_SHIFT;
739 val |= PCIE_PHY_MPLL_MULTIPLIER_OVRD;
740 pcie_phy_write(imx6_pcie, PCIE_PHY_MPLL_OVRD_IN_LO, val);
741
742 pcie_phy_read(imx6_pcie, PCIE_PHY_ATEOVRD, &val);
743 val &= ~(PCIE_PHY_ATEOVRD_REF_CLKDIV_MASK <<
744 PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT);
745 val |= div << PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT;
746 val |= PCIE_PHY_ATEOVRD_EN;
747 pcie_phy_write(imx6_pcie, PCIE_PHY_ATEOVRD, val);
748
749 return 0;
750}
751
752static int imx6_pcie_wait_for_speed_change(struct imx6_pcie *imx6_pcie)
753{
754 struct dw_pcie *pci = imx6_pcie->pci;
755 struct device *dev = pci->dev;
756 u32 tmp;
757 unsigned int retries;
758
759 for (retries = 0; retries < 200; retries++) {
760 tmp = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
761
762 if (!(tmp & PORT_LOGIC_SPEED_CHANGE))
763 return 0;
764 usleep_range(100, 1000);
765 }
766
767 dev_err(dev, "Speed change timeout\n");
768 return -ETIMEDOUT;
769}
770
771static void imx6_pcie_ltssm_enable(struct device *dev)
772{
773 struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
774
775 switch (imx6_pcie->drvdata->variant) {
776 case IMX6Q:
777 case IMX6SX:
778 case IMX6QP:
779 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
780 IMX6Q_GPR12_PCIE_CTL_2,
781 IMX6Q_GPR12_PCIE_CTL_2);
782 break;
783 case IMX7D:
784 case IMX8MQ:
785 case IMX8MM:
786 reset_control_deassert(imx6_pcie->apps_reset);
787 break;
788 }
789}
790
791static int imx6_pcie_start_link(struct dw_pcie *pci)
792{
793 struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci);
794 struct device *dev = pci->dev;
795 u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
796 u32 tmp;
797 int ret;
798
799
800
801
802
803
804 tmp = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
805 tmp &= ~PCI_EXP_LNKCAP_SLS;
806 tmp |= PCI_EXP_LNKCAP_SLS_2_5GB;
807 dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, tmp);
808
809
810 imx6_pcie_ltssm_enable(dev);
811
812 ret = dw_pcie_wait_for_link(pci);
813 if (ret)
814 goto err_reset_phy;
815
816 if (pci->link_gen == 2) {
817
818 tmp = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
819 tmp &= ~PCI_EXP_LNKCAP_SLS;
820 tmp |= PCI_EXP_LNKCAP_SLS_5_0GB;
821 dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, tmp);
822
823
824
825
826
827 tmp = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
828 tmp |= PORT_LOGIC_SPEED_CHANGE;
829 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, tmp);
830
831 if (imx6_pcie->drvdata->flags &
832 IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE) {
833
834
835
836
837
838
839
840
841
842 ret = imx6_pcie_wait_for_speed_change(imx6_pcie);
843 if (ret) {
844 dev_err(dev, "Failed to bring link up!\n");
845 goto err_reset_phy;
846 }
847 }
848
849
850 ret = dw_pcie_wait_for_link(pci);
851 if (ret) {
852 dev_err(dev, "Failed to bring link up!\n");
853 goto err_reset_phy;
854 }
855 } else {
856 dev_info(dev, "Link: Gen2 disabled\n");
857 }
858
859 tmp = dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKSTA);
860 dev_info(dev, "Link up, Gen%i\n", tmp & PCI_EXP_LNKSTA_CLS);
861 return 0;
862
863err_reset_phy:
864 dev_dbg(dev, "PHY DEBUG_R0=0x%08x DEBUG_R1=0x%08x\n",
865 dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG0),
866 dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG1));
867 imx6_pcie_reset_phy(imx6_pcie);
868 return ret;
869}
870
871static int imx6_pcie_host_init(struct pcie_port *pp)
872{
873 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
874 struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci);
875
876 imx6_pcie_assert_core_reset(imx6_pcie);
877 imx6_pcie_init_phy(imx6_pcie);
878 imx6_pcie_deassert_core_reset(imx6_pcie);
879 imx6_setup_phy_mpll(imx6_pcie);
880
881 return 0;
882}
883
884static const struct dw_pcie_host_ops imx6_pcie_host_ops = {
885 .host_init = imx6_pcie_host_init,
886};
887
888static const struct dw_pcie_ops dw_pcie_ops = {
889 .start_link = imx6_pcie_start_link,
890};
891
892#ifdef CONFIG_PM_SLEEP
893static void imx6_pcie_ltssm_disable(struct device *dev)
894{
895 struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
896
897 switch (imx6_pcie->drvdata->variant) {
898 case IMX6SX:
899 case IMX6QP:
900 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
901 IMX6Q_GPR12_PCIE_CTL_2, 0);
902 break;
903 case IMX7D:
904 case IMX8MM:
905 reset_control_assert(imx6_pcie->apps_reset);
906 break;
907 default:
908 dev_err(dev, "ltssm_disable not supported\n");
909 }
910}
911
912static void imx6_pcie_pm_turnoff(struct imx6_pcie *imx6_pcie)
913{
914 struct device *dev = imx6_pcie->pci->dev;
915
916
917 if (imx6_pcie->turnoff_reset) {
918 reset_control_assert(imx6_pcie->turnoff_reset);
919 reset_control_deassert(imx6_pcie->turnoff_reset);
920 goto pm_turnoff_sleep;
921 }
922
923
924 switch (imx6_pcie->drvdata->variant) {
925 case IMX6SX:
926 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
927 IMX6SX_GPR12_PCIE_PM_TURN_OFF,
928 IMX6SX_GPR12_PCIE_PM_TURN_OFF);
929 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
930 IMX6SX_GPR12_PCIE_PM_TURN_OFF, 0);
931 break;
932 default:
933 dev_err(dev, "PME_Turn_Off not implemented\n");
934 return;
935 }
936
937
938
939
940
941
942
943
944pm_turnoff_sleep:
945 usleep_range(1000, 10000);
946}
947
948static void imx6_pcie_clk_disable(struct imx6_pcie *imx6_pcie)
949{
950 clk_disable_unprepare(imx6_pcie->pcie);
951 clk_disable_unprepare(imx6_pcie->pcie_phy);
952 clk_disable_unprepare(imx6_pcie->pcie_bus);
953
954 switch (imx6_pcie->drvdata->variant) {
955 case IMX6SX:
956 clk_disable_unprepare(imx6_pcie->pcie_inbound_axi);
957 break;
958 case IMX7D:
959 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
960 IMX7D_GPR12_PCIE_PHY_REFCLK_SEL,
961 IMX7D_GPR12_PCIE_PHY_REFCLK_SEL);
962 break;
963 case IMX8MQ:
964 case IMX8MM:
965 clk_disable_unprepare(imx6_pcie->pcie_aux);
966 break;
967 default:
968 break;
969 }
970}
971
972static int imx6_pcie_suspend_noirq(struct device *dev)
973{
974 struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
975
976 if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_SUPPORTS_SUSPEND))
977 return 0;
978
979 imx6_pcie_pm_turnoff(imx6_pcie);
980 imx6_pcie_ltssm_disable(dev);
981 imx6_pcie_clk_disable(imx6_pcie);
982 switch (imx6_pcie->drvdata->variant) {
983 case IMX8MM:
984 if (phy_power_off(imx6_pcie->phy))
985 dev_err(dev, "unable to power off PHY\n");
986 break;
987 default:
988 break;
989 }
990
991 return 0;
992}
993
994static int imx6_pcie_resume_noirq(struct device *dev)
995{
996 int ret;
997 struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
998 struct pcie_port *pp = &imx6_pcie->pci->pp;
999
1000 if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_SUPPORTS_SUSPEND))
1001 return 0;
1002
1003 imx6_pcie_assert_core_reset(imx6_pcie);
1004 imx6_pcie_init_phy(imx6_pcie);
1005 imx6_pcie_deassert_core_reset(imx6_pcie);
1006 dw_pcie_setup_rc(pp);
1007
1008 ret = imx6_pcie_start_link(imx6_pcie->pci);
1009 if (ret < 0)
1010 dev_info(dev, "pcie link is down after resume.\n");
1011
1012 return 0;
1013}
1014#endif
1015
1016static const struct dev_pm_ops imx6_pcie_pm_ops = {
1017 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(imx6_pcie_suspend_noirq,
1018 imx6_pcie_resume_noirq)
1019};
1020
1021static int imx6_pcie_probe(struct platform_device *pdev)
1022{
1023 struct device *dev = &pdev->dev;
1024 struct dw_pcie *pci;
1025 struct imx6_pcie *imx6_pcie;
1026 struct device_node *np;
1027 struct resource *dbi_base;
1028 struct device_node *node = dev->of_node;
1029 int ret;
1030 u16 val;
1031
1032 imx6_pcie = devm_kzalloc(dev, sizeof(*imx6_pcie), GFP_KERNEL);
1033 if (!imx6_pcie)
1034 return -ENOMEM;
1035
1036 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
1037 if (!pci)
1038 return -ENOMEM;
1039
1040 pci->dev = dev;
1041 pci->ops = &dw_pcie_ops;
1042 pci->pp.ops = &imx6_pcie_host_ops;
1043
1044 imx6_pcie->pci = pci;
1045 imx6_pcie->drvdata = of_device_get_match_data(dev);
1046
1047
1048 np = of_parse_phandle(node, "fsl,imx7d-pcie-phy", 0);
1049 if (np) {
1050 struct resource res;
1051
1052 ret = of_address_to_resource(np, 0, &res);
1053 if (ret) {
1054 dev_err(dev, "Unable to map PCIe PHY\n");
1055 return ret;
1056 }
1057 imx6_pcie->phy_base = devm_ioremap_resource(dev, &res);
1058 if (IS_ERR(imx6_pcie->phy_base))
1059 return PTR_ERR(imx6_pcie->phy_base);
1060 }
1061
1062 dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1063 pci->dbi_base = devm_ioremap_resource(dev, dbi_base);
1064 if (IS_ERR(pci->dbi_base))
1065 return PTR_ERR(pci->dbi_base);
1066
1067
1068 imx6_pcie->reset_gpio = of_get_named_gpio(node, "reset-gpio", 0);
1069 imx6_pcie->gpio_active_high = of_property_read_bool(node,
1070 "reset-gpio-active-high");
1071 if (gpio_is_valid(imx6_pcie->reset_gpio)) {
1072 ret = devm_gpio_request_one(dev, imx6_pcie->reset_gpio,
1073 imx6_pcie->gpio_active_high ?
1074 GPIOF_OUT_INIT_HIGH :
1075 GPIOF_OUT_INIT_LOW,
1076 "PCIe reset");
1077 if (ret) {
1078 dev_err(dev, "unable to get reset gpio\n");
1079 return ret;
1080 }
1081 } else if (imx6_pcie->reset_gpio == -EPROBE_DEFER) {
1082 return imx6_pcie->reset_gpio;
1083 }
1084
1085
1086 imx6_pcie->pcie_bus = devm_clk_get(dev, "pcie_bus");
1087 if (IS_ERR(imx6_pcie->pcie_bus))
1088 return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_bus),
1089 "pcie_bus clock source missing or invalid\n");
1090
1091 imx6_pcie->pcie = devm_clk_get(dev, "pcie");
1092 if (IS_ERR(imx6_pcie->pcie))
1093 return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie),
1094 "pcie clock source missing or invalid\n");
1095
1096 switch (imx6_pcie->drvdata->variant) {
1097 case IMX6SX:
1098 imx6_pcie->pcie_inbound_axi = devm_clk_get(dev,
1099 "pcie_inbound_axi");
1100 if (IS_ERR(imx6_pcie->pcie_inbound_axi))
1101 return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_inbound_axi),
1102 "pcie_inbound_axi clock missing or invalid\n");
1103 break;
1104 case IMX8MQ:
1105 imx6_pcie->pcie_aux = devm_clk_get(dev, "pcie_aux");
1106 if (IS_ERR(imx6_pcie->pcie_aux))
1107 return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_aux),
1108 "pcie_aux clock source missing or invalid\n");
1109 fallthrough;
1110 case IMX7D:
1111 if (dbi_base->start == IMX8MQ_PCIE2_BASE_ADDR)
1112 imx6_pcie->controller_id = 1;
1113
1114 imx6_pcie->pciephy_reset = devm_reset_control_get_exclusive(dev,
1115 "pciephy");
1116 if (IS_ERR(imx6_pcie->pciephy_reset)) {
1117 dev_err(dev, "Failed to get PCIEPHY reset control\n");
1118 return PTR_ERR(imx6_pcie->pciephy_reset);
1119 }
1120
1121 imx6_pcie->apps_reset = devm_reset_control_get_exclusive(dev,
1122 "apps");
1123 if (IS_ERR(imx6_pcie->apps_reset)) {
1124 dev_err(dev, "Failed to get PCIE APPS reset control\n");
1125 return PTR_ERR(imx6_pcie->apps_reset);
1126 }
1127 break;
1128 case IMX8MM:
1129 imx6_pcie->pcie_aux = devm_clk_get(dev, "pcie_aux");
1130 if (IS_ERR(imx6_pcie->pcie_aux))
1131 return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_aux),
1132 "pcie_aux clock source missing or invalid\n");
1133 imx6_pcie->apps_reset = devm_reset_control_get_exclusive(dev,
1134 "apps");
1135 if (IS_ERR(imx6_pcie->apps_reset))
1136 return dev_err_probe(dev, PTR_ERR(imx6_pcie->apps_reset),
1137 "failed to get pcie apps reset control\n");
1138
1139 imx6_pcie->phy = devm_phy_get(dev, "pcie-phy");
1140 if (IS_ERR(imx6_pcie->phy))
1141 return dev_err_probe(dev, PTR_ERR(imx6_pcie->phy),
1142 "failed to get pcie phy\n");
1143
1144 break;
1145 default:
1146 break;
1147 }
1148
1149 if (imx6_pcie->phy == NULL) {
1150 imx6_pcie->pcie_phy = devm_clk_get(dev, "pcie_phy");
1151 if (IS_ERR(imx6_pcie->pcie_phy))
1152 return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_phy),
1153 "pcie_phy clock source missing or invalid\n");
1154 }
1155
1156
1157
1158 imx6_pcie->turnoff_reset = devm_reset_control_get_optional_exclusive(dev, "turnoff");
1159 if (IS_ERR(imx6_pcie->turnoff_reset)) {
1160 dev_err(dev, "Failed to get TURNOFF reset control\n");
1161 return PTR_ERR(imx6_pcie->turnoff_reset);
1162 }
1163
1164
1165 imx6_pcie->iomuxc_gpr =
1166 syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
1167 if (IS_ERR(imx6_pcie->iomuxc_gpr)) {
1168 dev_err(dev, "unable to find iomuxc registers\n");
1169 return PTR_ERR(imx6_pcie->iomuxc_gpr);
1170 }
1171
1172
1173 if (of_property_read_u32(node, "fsl,tx-deemph-gen1",
1174 &imx6_pcie->tx_deemph_gen1))
1175 imx6_pcie->tx_deemph_gen1 = 0;
1176
1177 if (of_property_read_u32(node, "fsl,tx-deemph-gen2-3p5db",
1178 &imx6_pcie->tx_deemph_gen2_3p5db))
1179 imx6_pcie->tx_deemph_gen2_3p5db = 0;
1180
1181 if (of_property_read_u32(node, "fsl,tx-deemph-gen2-6db",
1182 &imx6_pcie->tx_deemph_gen2_6db))
1183 imx6_pcie->tx_deemph_gen2_6db = 20;
1184
1185 if (of_property_read_u32(node, "fsl,tx-swing-full",
1186 &imx6_pcie->tx_swing_full))
1187 imx6_pcie->tx_swing_full = 127;
1188
1189 if (of_property_read_u32(node, "fsl,tx-swing-low",
1190 &imx6_pcie->tx_swing_low))
1191 imx6_pcie->tx_swing_low = 127;
1192
1193
1194 pci->link_gen = 1;
1195 of_property_read_u32(node, "fsl,max-link-speed", &pci->link_gen);
1196
1197 imx6_pcie->vpcie = devm_regulator_get_optional(&pdev->dev, "vpcie");
1198 if (IS_ERR(imx6_pcie->vpcie)) {
1199 if (PTR_ERR(imx6_pcie->vpcie) != -ENODEV)
1200 return PTR_ERR(imx6_pcie->vpcie);
1201 imx6_pcie->vpcie = NULL;
1202 }
1203
1204 imx6_pcie->vph = devm_regulator_get_optional(&pdev->dev, "vph");
1205 if (IS_ERR(imx6_pcie->vph)) {
1206 if (PTR_ERR(imx6_pcie->vph) != -ENODEV)
1207 return PTR_ERR(imx6_pcie->vph);
1208 imx6_pcie->vph = NULL;
1209 }
1210
1211 platform_set_drvdata(pdev, imx6_pcie);
1212
1213 ret = imx6_pcie_attach_pd(dev);
1214 if (ret)
1215 return ret;
1216
1217 ret = dw_pcie_host_init(&pci->pp);
1218 if (ret < 0)
1219 return ret;
1220
1221 if (pci_msi_enabled()) {
1222 u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_MSI);
1223 val = dw_pcie_readw_dbi(pci, offset + PCI_MSI_FLAGS);
1224 val |= PCI_MSI_FLAGS_ENABLE;
1225 dw_pcie_writew_dbi(pci, offset + PCI_MSI_FLAGS, val);
1226 }
1227
1228 return 0;
1229}
1230
1231static void imx6_pcie_shutdown(struct platform_device *pdev)
1232{
1233 struct imx6_pcie *imx6_pcie = platform_get_drvdata(pdev);
1234
1235
1236 imx6_pcie_assert_core_reset(imx6_pcie);
1237}
1238
1239static const struct imx6_pcie_drvdata drvdata[] = {
1240 [IMX6Q] = {
1241 .variant = IMX6Q,
1242 .flags = IMX6_PCIE_FLAG_IMX6_PHY |
1243 IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE,
1244 .dbi_length = 0x200,
1245 },
1246 [IMX6SX] = {
1247 .variant = IMX6SX,
1248 .flags = IMX6_PCIE_FLAG_IMX6_PHY |
1249 IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE |
1250 IMX6_PCIE_FLAG_SUPPORTS_SUSPEND,
1251 },
1252 [IMX6QP] = {
1253 .variant = IMX6QP,
1254 .flags = IMX6_PCIE_FLAG_IMX6_PHY |
1255 IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE,
1256 .dbi_length = 0x200,
1257 },
1258 [IMX7D] = {
1259 .variant = IMX7D,
1260 .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND,
1261 },
1262 [IMX8MQ] = {
1263 .variant = IMX8MQ,
1264 },
1265 [IMX8MM] = {
1266 .variant = IMX8MM,
1267 .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND,
1268 },
1269};
1270
1271static const struct of_device_id imx6_pcie_of_match[] = {
1272 { .compatible = "fsl,imx6q-pcie", .data = &drvdata[IMX6Q], },
1273 { .compatible = "fsl,imx6sx-pcie", .data = &drvdata[IMX6SX], },
1274 { .compatible = "fsl,imx6qp-pcie", .data = &drvdata[IMX6QP], },
1275 { .compatible = "fsl,imx7d-pcie", .data = &drvdata[IMX7D], },
1276 { .compatible = "fsl,imx8mq-pcie", .data = &drvdata[IMX8MQ], },
1277 { .compatible = "fsl,imx8mm-pcie", .data = &drvdata[IMX8MM], },
1278 {},
1279};
1280
1281static struct platform_driver imx6_pcie_driver = {
1282 .driver = {
1283 .name = "imx6q-pcie",
1284 .of_match_table = imx6_pcie_of_match,
1285 .suppress_bind_attrs = true,
1286 .pm = &imx6_pcie_pm_ops,
1287 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1288 },
1289 .probe = imx6_pcie_probe,
1290 .shutdown = imx6_pcie_shutdown,
1291};
1292
1293static void imx6_pcie_quirk(struct pci_dev *dev)
1294{
1295 struct pci_bus *bus = dev->bus;
1296 struct pcie_port *pp = bus->sysdata;
1297
1298
1299 if (!bus->dev.parent || !bus->dev.parent->parent)
1300 return;
1301
1302
1303 if (bus->dev.parent->parent->driver != &imx6_pcie_driver.driver)
1304 return;
1305
1306 if (pci_is_root_bus(bus)) {
1307 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
1308 struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci);
1309
1310
1311
1312
1313
1314 if (imx6_pcie->drvdata->dbi_length) {
1315 dev->cfg_size = imx6_pcie->drvdata->dbi_length;
1316 dev_info(&dev->dev, "Limiting cfg_size to %d\n",
1317 dev->cfg_size);
1318 }
1319 }
1320}
1321DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_SYNOPSYS, 0xabcd,
1322 PCI_CLASS_BRIDGE_PCI, 8, imx6_pcie_quirk);
1323
1324static int __init imx6_pcie_init(void)
1325{
1326#ifdef CONFIG_ARM
1327
1328
1329
1330
1331
1332
1333
1334 hook_fault_code(8, imx6q_pcie_abort_handler, SIGBUS, 0,
1335 "external abort on non-linefetch");
1336#endif
1337
1338 return platform_driver_register(&imx6_pcie_driver);
1339}
1340device_initcall(imx6_pcie_init);
1341
