LXR linux/drivers/phy/samsung/phy-exynos-pcie.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Samsung Exynos SoC series PCIe PHY driver
   4 *
   5 * Phy provider for PCIe controller on Exynos SoC series
   6 *
   7 * Copyright (C) 2017-2020 Samsung Electronics Co., Ltd.
   8 * Jaehoon Chung <jh80.chung@samsung.com>
   9 */
  10
  11#include <linux/io.h>
  12#include <linux/mfd/syscon.h>
  13#include <linux/of_platform.h>
  14#include <linux/platform_device.h>
  15#include <linux/phy/phy.h>
  16#include <linux/regmap.h>
  17
  18#define PCIE_PHY_OFFSET(x)              ((x) * 0x4)
  19
  20/* Sysreg FSYS register offsets and bits for Exynos5433 */
  21#define PCIE_EXYNOS5433_PHY_MAC_RESET           0x0208
  22#define PCIE_MAC_RESET_MASK                     0xFF
  23#define PCIE_MAC_RESET                          BIT(4)
  24#define PCIE_EXYNOS5433_PHY_L1SUB_CM_CON        0x1010
  25#define PCIE_REFCLK_GATING_EN                   BIT(0)
  26#define PCIE_EXYNOS5433_PHY_COMMON_RESET        0x1020
  27#define PCIE_PHY_RESET                          BIT(0)
  28#define PCIE_EXYNOS5433_PHY_GLOBAL_RESET        0x1040
  29#define PCIE_GLOBAL_RESET                       BIT(0)
  30#define PCIE_REFCLK                             BIT(1)
  31#define PCIE_REFCLK_MASK                        0x16
  32#define PCIE_APP_REQ_EXIT_L1_MODE               BIT(5)
  33
  34/* PMU PCIE PHY isolation control */
  35#define EXYNOS5433_PMU_PCIE_PHY_OFFSET          0x730
  36
  37/* For Exynos pcie phy */
  38struct exynos_pcie_phy {
  39        void __iomem *base;
  40        struct regmap *pmureg;
  41        struct regmap *fsysreg;
  42};
  43
  44static void exynos_pcie_phy_writel(void __iomem *base, u32 val, u32 offset)
  45{
  46        writel(val, base + offset);
  47}
  48
  49/* Exynos5433 specific functions */
  50static int exynos5433_pcie_phy_init(struct phy *phy)
  51{
  52        struct exynos_pcie_phy *ep = phy_get_drvdata(phy);
  53
  54        regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_COMMON_RESET,
  55                           PCIE_PHY_RESET, 1);
  56        regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_MAC_RESET,
  57                           PCIE_MAC_RESET, 0);
  58
  59        /* PHY refclk 24MHz */
  60        regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_GLOBAL_RESET,
  61                           PCIE_REFCLK_MASK, PCIE_REFCLK);
  62        regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_GLOBAL_RESET,
  63                           PCIE_GLOBAL_RESET, 0);
  64
  65
  66        exynos_pcie_phy_writel(ep->base, 0x11, PCIE_PHY_OFFSET(0x3));
  67
  68        /* band gap reference on */
  69        exynos_pcie_phy_writel(ep->base, 0, PCIE_PHY_OFFSET(0x20));
  70        exynos_pcie_phy_writel(ep->base, 0, PCIE_PHY_OFFSET(0x4b));
  71
  72        /* jitter tuning */
  73        exynos_pcie_phy_writel(ep->base, 0x34, PCIE_PHY_OFFSET(0x4));
  74        exynos_pcie_phy_writel(ep->base, 0x02, PCIE_PHY_OFFSET(0x7));
  75        exynos_pcie_phy_writel(ep->base, 0x41, PCIE_PHY_OFFSET(0x21));
  76        exynos_pcie_phy_writel(ep->base, 0x7F, PCIE_PHY_OFFSET(0x14));
  77        exynos_pcie_phy_writel(ep->base, 0xC0, PCIE_PHY_OFFSET(0x15));
  78        exynos_pcie_phy_writel(ep->base, 0x61, PCIE_PHY_OFFSET(0x36));
  79
  80        /* D0 uninit.. */
  81        exynos_pcie_phy_writel(ep->base, 0x44, PCIE_PHY_OFFSET(0x3D));
  82
  83        /* 24MHz */
  84        exynos_pcie_phy_writel(ep->base, 0x94, PCIE_PHY_OFFSET(0x8));
  85        exynos_pcie_phy_writel(ep->base, 0xA7, PCIE_PHY_OFFSET(0x9));
  86        exynos_pcie_phy_writel(ep->base, 0x93, PCIE_PHY_OFFSET(0xA));
  87        exynos_pcie_phy_writel(ep->base, 0x6B, PCIE_PHY_OFFSET(0xC));
  88        exynos_pcie_phy_writel(ep->base, 0xA5, PCIE_PHY_OFFSET(0xF));
  89        exynos_pcie_phy_writel(ep->base, 0x34, PCIE_PHY_OFFSET(0x16));
  90        exynos_pcie_phy_writel(ep->base, 0xA3, PCIE_PHY_OFFSET(0x17));
  91        exynos_pcie_phy_writel(ep->base, 0xA7, PCIE_PHY_OFFSET(0x1A));
  92        exynos_pcie_phy_writel(ep->base, 0x71, PCIE_PHY_OFFSET(0x23));
  93        exynos_pcie_phy_writel(ep->base, 0x4C, PCIE_PHY_OFFSET(0x24));
  94
  95        exynos_pcie_phy_writel(ep->base, 0x0E, PCIE_PHY_OFFSET(0x26));
  96        exynos_pcie_phy_writel(ep->base, 0x14, PCIE_PHY_OFFSET(0x7));
  97        exynos_pcie_phy_writel(ep->base, 0x48, PCIE_PHY_OFFSET(0x43));
  98        exynos_pcie_phy_writel(ep->base, 0x44, PCIE_PHY_OFFSET(0x44));
  99        exynos_pcie_phy_writel(ep->base, 0x03, PCIE_PHY_OFFSET(0x45));
 100        exynos_pcie_phy_writel(ep->base, 0xA7, PCIE_PHY_OFFSET(0x48));
 101        exynos_pcie_phy_writel(ep->base, 0x13, PCIE_PHY_OFFSET(0x54));
 102        exynos_pcie_phy_writel(ep->base, 0x04, PCIE_PHY_OFFSET(0x31));
 103        exynos_pcie_phy_writel(ep->base, 0, PCIE_PHY_OFFSET(0x32));
 104
 105        regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_COMMON_RESET,
 106                           PCIE_PHY_RESET, 0);
 107        regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_MAC_RESET,
 108                           PCIE_MAC_RESET_MASK, PCIE_MAC_RESET);
 109        return 0;
 110}
 111
 112static int exynos5433_pcie_phy_power_on(struct phy *phy)
 113{
 114        struct exynos_pcie_phy *ep = phy_get_drvdata(phy);
 115
 116        regmap_update_bits(ep->pmureg, EXYNOS5433_PMU_PCIE_PHY_OFFSET,
 117                           BIT(0), 1);
 118        regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_GLOBAL_RESET,
 119                           PCIE_APP_REQ_EXIT_L1_MODE, 0);
 120        regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_L1SUB_CM_CON,
 121                           PCIE_REFCLK_GATING_EN, 0);
 122        return 0;
 123}
 124
 125static int exynos5433_pcie_phy_power_off(struct phy *phy)
 126{
 127        struct exynos_pcie_phy *ep = phy_get_drvdata(phy);
 128
 129        regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_L1SUB_CM_CON,
 130                           PCIE_REFCLK_GATING_EN, PCIE_REFCLK_GATING_EN);
 131        regmap_update_bits(ep->pmureg, EXYNOS5433_PMU_PCIE_PHY_OFFSET,
 132                           BIT(0), 0);
 133        return 0;
 134}
 135
 136static const struct phy_ops exynos5433_phy_ops = {
 137        .init           = exynos5433_pcie_phy_init,
 138        .power_on       = exynos5433_pcie_phy_power_on,
 139        .power_off      = exynos5433_pcie_phy_power_off,
 140        .owner          = THIS_MODULE,
 141};
 142
 143static const struct of_device_id exynos_pcie_phy_match[] = {
 144        {
 145                .compatible = "samsung,exynos5433-pcie-phy",
 146        },
 147        {},
 148};
 149
 150static int exynos_pcie_phy_probe(struct platform_device *pdev)
 151{
 152        struct device *dev = &pdev->dev;
 153        struct exynos_pcie_phy *exynos_phy;
 154        struct phy *generic_phy;
 155        struct phy_provider *phy_provider;
 156
 157        exynos_phy = devm_kzalloc(dev, sizeof(*exynos_phy), GFP_KERNEL);
 158        if (!exynos_phy)
 159                return -ENOMEM;
 160
 161        exynos_phy->base = devm_platform_ioremap_resource(pdev, 0);
 162        if (IS_ERR(exynos_phy->base))
 163                return PTR_ERR(exynos_phy->base);
 164
 165        exynos_phy->pmureg = syscon_regmap_lookup_by_phandle(dev->of_node,
 166                                                        "samsung,pmu-syscon");
 167        if (IS_ERR(exynos_phy->pmureg)) {
 168                dev_err(&pdev->dev, "PMU regmap lookup failed.\n");
 169                return PTR_ERR(exynos_phy->pmureg);
 170        }
 171
 172        exynos_phy->fsysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
 173                                                         "samsung,fsys-sysreg");
 174        if (IS_ERR(exynos_phy->fsysreg)) {
 175                dev_err(&pdev->dev, "FSYS sysreg regmap lookup failed.\n");
 176                return PTR_ERR(exynos_phy->fsysreg);
 177        }
 178
 179        generic_phy = devm_phy_create(dev, dev->of_node, &exynos5433_phy_ops);
 180        if (IS_ERR(generic_phy)) {
 181                dev_err(dev, "failed to create PHY\n");
 182                return PTR_ERR(generic_phy);
 183        }
 184
 185        phy_set_drvdata(generic_phy, exynos_phy);
 186        phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
 187
 188        return PTR_ERR_OR_ZERO(phy_provider);
 189}
 190
 191static struct platform_driver exynos_pcie_phy_driver = {
 192        .probe  = exynos_pcie_phy_probe,
 193        .driver = {
 194                .of_match_table = exynos_pcie_phy_match,
 195                .name           = "exynos_pcie_phy",
 196                .suppress_bind_attrs = true,
 197        }
 198};
 199builtin_platform_driver(exynos_pcie_phy_driver);
 200