LXR linux/drivers/scsi/mpi3mr/mpi3mr.h

   1/* SPDX-License-Identifier: GPL-2.0-or-later */
   2/*
   3 * Driver for Broadcom MPI3 Storage Controllers
   4 *
   5 * Copyright (C) 2017-2021 Broadcom Inc.
   6 *  (mailto: mpi3mr-linuxdrv.pdl@broadcom.com)
   7 *
   8 */
   9
  10#ifndef MPI3MR_H_INCLUDED
  11#define MPI3MR_H_INCLUDED
  12
  13#include <linux/blkdev.h>
  14#include <linux/blk-mq.h>
  15#include <linux/blk-mq-pci.h>
  16#include <linux/delay.h>
  17#include <linux/dmapool.h>
  18#include <linux/errno.h>
  19#include <linux/init.h>
  20#include <linux/io.h>
  21#include <linux/interrupt.h>
  22#include <linux/kernel.h>
  23#include <linux/miscdevice.h>
  24#include <linux/module.h>
  25#include <linux/pci.h>
  26#include <linux/poll.h>
  27#include <linux/sched.h>
  28#include <linux/slab.h>
  29#include <linux/types.h>
  30#include <linux/uaccess.h>
  31#include <linux/utsname.h>
  32#include <linux/version.h>
  33#include <linux/workqueue.h>
  34#include <asm/unaligned.h>
  35#include <scsi/scsi.h>
  36#include <scsi/scsi_cmnd.h>
  37#include <scsi/scsi_dbg.h>
  38#include <scsi/scsi_device.h>
  39#include <scsi/scsi_host.h>
  40#include <scsi/scsi_tcq.h>
  41
  42#include "mpi/mpi30_transport.h"
  43#include "mpi/mpi30_cnfg.h"
  44#include "mpi/mpi30_image.h"
  45#include "mpi/mpi30_init.h"
  46#include "mpi/mpi30_ioc.h"
  47#include "mpi/mpi30_sas.h"
  48#include "mpi/mpi30_pci.h"
  49#include "mpi3mr_debug.h"
  50
  51/* Global list and lock for storing multiple adapters managed by the driver */
  52extern spinlock_t mrioc_list_lock;
  53extern struct list_head mrioc_list;
  54extern int prot_mask;
  55
  56#define MPI3MR_DRIVER_VERSION   "8.0.0.61.0"
  57#define MPI3MR_DRIVER_RELDATE   "20-December-2021"
  58
  59#define MPI3MR_DRIVER_NAME      "mpi3mr"
  60#define MPI3MR_DRIVER_LICENSE   "GPL"
  61#define MPI3MR_DRIVER_AUTHOR    "Broadcom Inc. <mpi3mr-linuxdrv.pdl@broadcom.com>"
  62#define MPI3MR_DRIVER_DESC      "MPI3 Storage Controller Device Driver"
  63
  64#define MPI3MR_NAME_LENGTH      32
  65#define IOCNAME                 "%s: "
  66
  67/* Definitions for internal SGL and Chain SGL buffers */
  68#define MPI3MR_PAGE_SIZE_4K             4096
  69#define MPI3MR_SG_DEPTH         (MPI3MR_PAGE_SIZE_4K / sizeof(struct mpi3_sge_common))
  70
  71/* Definitions for MAX values for shost */
  72#define MPI3MR_MAX_CMDS_LUN     7
  73#define MPI3MR_MAX_CDB_LENGTH   32
  74
  75/* Admin queue management definitions */
  76#define MPI3MR_ADMIN_REQ_Q_SIZE         (2 * MPI3MR_PAGE_SIZE_4K)
  77#define MPI3MR_ADMIN_REPLY_Q_SIZE       (4 * MPI3MR_PAGE_SIZE_4K)
  78#define MPI3MR_ADMIN_REQ_FRAME_SZ       128
  79#define MPI3MR_ADMIN_REPLY_FRAME_SZ     16
  80
  81/* Operational queue management definitions */
  82#define MPI3MR_OP_REQ_Q_QD              512
  83#define MPI3MR_OP_REP_Q_QD              1024
  84#define MPI3MR_OP_REP_Q_QD4K            4096
  85#define MPI3MR_OP_REQ_Q_SEG_SIZE        4096
  86#define MPI3MR_OP_REP_Q_SEG_SIZE        4096
  87#define MPI3MR_MAX_SEG_LIST_SIZE        4096
  88
  89/* Reserved Host Tag definitions */
  90#define MPI3MR_HOSTTAG_INVALID          0xFFFF
  91#define MPI3MR_HOSTTAG_INITCMDS         1
  92#define MPI3MR_HOSTTAG_IOCTLCMDS        2
  93#define MPI3MR_HOSTTAG_BLK_TMS          5
  94
  95#define MPI3MR_NUM_DEVRMCMD             16
  96#define MPI3MR_HOSTTAG_DEVRMCMD_MIN     (MPI3MR_HOSTTAG_BLK_TMS + 1)
  97#define MPI3MR_HOSTTAG_DEVRMCMD_MAX     (MPI3MR_HOSTTAG_DEVRMCMD_MIN + \
  98                                                MPI3MR_NUM_DEVRMCMD - 1)
  99
 100#define MPI3MR_INTERNAL_CMDS_RESVD      MPI3MR_HOSTTAG_DEVRMCMD_MAX
 101#define MPI3MR_NUM_EVTACKCMD            4
 102#define MPI3MR_HOSTTAG_EVTACKCMD_MIN    (MPI3MR_HOSTTAG_DEVRMCMD_MAX + 1)
 103#define MPI3MR_HOSTTAG_EVTACKCMD_MAX    (MPI3MR_HOSTTAG_EVTACKCMD_MIN + \
 104                                        MPI3MR_NUM_EVTACKCMD - 1)
 105
 106/* Reduced resource count definition for crash kernel */
 107#define MPI3MR_HOST_IOS_KDUMP           128
 108
 109/* command/controller interaction timeout definitions in seconds */
 110#define MPI3MR_INTADMCMD_TIMEOUT                60
 111#define MPI3MR_PORTENABLE_TIMEOUT               300
 112#define MPI3MR_ABORTTM_TIMEOUT                  60
 113#define MPI3MR_RESETTM_TIMEOUT                  60
 114#define MPI3MR_RESET_HOST_IOWAIT_TIMEOUT        5
 115#define MPI3MR_TSUPDATE_INTERVAL                900
 116#define MPI3MR_DEFAULT_SHUTDOWN_TIME            120
 117#define MPI3MR_RAID_ERRREC_RESET_TIMEOUT        180
 118#define MPI3MR_PREPARE_FOR_RESET_TIMEOUT        180
 119#define MPI3MR_RESET_ACK_TIMEOUT                30
 120
 121#define MPI3MR_WATCHDOG_INTERVAL                1000 /* in milli seconds */
 122
 123/* Internal admin command state definitions*/
 124#define MPI3MR_CMD_NOTUSED      0x8000
 125#define MPI3MR_CMD_COMPLETE     0x0001
 126#define MPI3MR_CMD_PENDING      0x0002
 127#define MPI3MR_CMD_REPLY_VALID  0x0004
 128#define MPI3MR_CMD_RESET        0x0008
 129
 130/* Definitions for Event replies and sense buffer allocated per controller */
 131#define MPI3MR_NUM_EVT_REPLIES  64
 132#define MPI3MR_SENSE_BUF_SZ     256
 133#define MPI3MR_SENSEBUF_FACTOR  3
 134#define MPI3MR_CHAINBUF_FACTOR  3
 135#define MPI3MR_CHAINBUFDIX_FACTOR       2
 136
 137/* Invalid target device handle */
 138#define MPI3MR_INVALID_DEV_HANDLE       0xFFFF
 139
 140/* Controller Reset related definitions */
 141#define MPI3MR_HOSTDIAG_UNLOCK_RETRY_COUNT      5
 142#define MPI3MR_MAX_RESET_RETRY_COUNT            3
 143
 144/* ResponseCode definitions */
 145#define MPI3MR_RI_MASK_RESPCODE         (0x000000FF)
 146#define MPI3MR_RSP_IO_QUEUED_ON_IOC \
 147                        MPI3_SCSITASKMGMT_RSPCODE_IO_QUEUED_ON_IOC
 148
 149#define MPI3MR_DEFAULT_MDTS     (128 * 1024)
 150#define MPI3MR_DEFAULT_PGSZEXP         (12)
 151/* Command retry count definitions */
 152#define MPI3MR_DEV_RMHS_RETRY_COUNT 3
 153
 154/* Default target device queue depth */
 155#define MPI3MR_DEFAULT_SDEV_QD  32
 156
 157/* Definitions for Threaded IRQ poll*/
 158#define MPI3MR_IRQ_POLL_SLEEP                   2
 159#define MPI3MR_IRQ_POLL_TRIGGER_IOCOUNT         8
 160
 161/* Definitions for the controller security status*/
 162#define MPI3MR_CTLR_SECURITY_STATUS_MASK        0x0C
 163#define MPI3MR_CTLR_SECURE_DBG_STATUS_MASK      0x02
 164
 165#define MPI3MR_INVALID_DEVICE                   0x00
 166#define MPI3MR_CONFIG_SECURE_DEVICE             0x04
 167#define MPI3MR_HARD_SECURE_DEVICE               0x08
 168#define MPI3MR_TAMPERED_DEVICE                  0x0C
 169
 170/* SGE Flag definition */
 171#define MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST \
 172        (MPI3_SGE_FLAGS_ELEMENT_TYPE_SIMPLE | MPI3_SGE_FLAGS_DLAS_SYSTEM | \
 173        MPI3_SGE_FLAGS_END_OF_LIST)
 174
 175/* MSI Index from Reply Queue Index */
 176#define REPLY_QUEUE_IDX_TO_MSIX_IDX(qidx, offset)       (qidx + offset)
 177
 178/* IOC State definitions */
 179enum mpi3mr_iocstate {
 180        MRIOC_STATE_READY = 1,
 181        MRIOC_STATE_RESET,
 182        MRIOC_STATE_FAULT,
 183        MRIOC_STATE_BECOMING_READY,
 184        MRIOC_STATE_RESET_REQUESTED,
 185        MRIOC_STATE_UNRECOVERABLE,
 186};
 187
 188/* Reset reason code definitions*/
 189enum mpi3mr_reset_reason {
 190        MPI3MR_RESET_FROM_BRINGUP = 1,
 191        MPI3MR_RESET_FROM_FAULT_WATCH = 2,
 192        MPI3MR_RESET_FROM_IOCTL = 3,
 193        MPI3MR_RESET_FROM_EH_HOS = 4,
 194        MPI3MR_RESET_FROM_TM_TIMEOUT = 5,
 195        MPI3MR_RESET_FROM_IOCTL_TIMEOUT = 6,
 196        MPI3MR_RESET_FROM_MUR_FAILURE = 7,
 197        MPI3MR_RESET_FROM_CTLR_CLEANUP = 8,
 198        MPI3MR_RESET_FROM_CIACTIV_FAULT = 9,
 199        MPI3MR_RESET_FROM_PE_TIMEOUT = 10,
 200        MPI3MR_RESET_FROM_TSU_TIMEOUT = 11,
 201        MPI3MR_RESET_FROM_DELREQQ_TIMEOUT = 12,
 202        MPI3MR_RESET_FROM_DELREPQ_TIMEOUT = 13,
 203        MPI3MR_RESET_FROM_CREATEREPQ_TIMEOUT = 14,
 204        MPI3MR_RESET_FROM_CREATEREQQ_TIMEOUT = 15,
 205        MPI3MR_RESET_FROM_IOCFACTS_TIMEOUT = 16,
 206        MPI3MR_RESET_FROM_IOCINIT_TIMEOUT = 17,
 207        MPI3MR_RESET_FROM_EVTNOTIFY_TIMEOUT = 18,
 208        MPI3MR_RESET_FROM_EVTACK_TIMEOUT = 19,
 209        MPI3MR_RESET_FROM_CIACTVRST_TIMER = 20,
 210        MPI3MR_RESET_FROM_GETPKGVER_TIMEOUT = 21,
 211        MPI3MR_RESET_FROM_PELABORT_TIMEOUT = 22,
 212        MPI3MR_RESET_FROM_SYSFS = 23,
 213        MPI3MR_RESET_FROM_SYSFS_TIMEOUT = 24,
 214        MPI3MR_RESET_FROM_FIRMWARE = 27,
 215};
 216
 217/* Queue type definitions */
 218enum queue_type {
 219        MPI3MR_DEFAULT_QUEUE = 0,
 220        MPI3MR_POLL_QUEUE,
 221};
 222
 223/**
 224 * struct mpi3mr_compimg_ver - replica of component image
 225 * version defined in mpi30_image.h in host endianness
 226 *
 227 */
 228struct mpi3mr_compimg_ver {
 229        u16 build_num;
 230        u16 cust_id;
 231        u8 ph_minor;
 232        u8 ph_major;
 233        u8 gen_minor;
 234        u8 gen_major;
 235};
 236
 237/**
 238 * struct mpi3mr_ioc_facs - replica of component image version
 239 * defined in mpi30_ioc.h in host endianness
 240 *
 241 */
 242struct mpi3mr_ioc_facts {
 243        u32 ioc_capabilities;
 244        struct mpi3mr_compimg_ver fw_ver;
 245        u32 mpi_version;
 246        u16 max_reqs;
 247        u16 product_id;
 248        u16 op_req_sz;
 249        u16 reply_sz;
 250        u16 exceptions;
 251        u16 max_perids;
 252        u16 max_pds;
 253        u16 max_sasexpanders;
 254        u16 max_sasinitiators;
 255        u16 max_enclosures;
 256        u16 max_pcie_switches;
 257        u16 max_nvme;
 258        u16 max_vds;
 259        u16 max_hpds;
 260        u16 max_advhpds;
 261        u16 max_raid_pds;
 262        u16 min_devhandle;
 263        u16 max_devhandle;
 264        u16 max_op_req_q;
 265        u16 max_op_reply_q;
 266        u16 shutdown_timeout;
 267        u8 ioc_num;
 268        u8 who_init;
 269        u16 max_msix_vectors;
 270        u8 personality;
 271        u8 dma_mask;
 272        u8 protocol_flags;
 273        u8 sge_mod_mask;
 274        u8 sge_mod_value;
 275        u8 sge_mod_shift;
 276};
 277
 278/**
 279 * struct segments - memory descriptor structure to store
 280 * virtual and dma addresses for operational queue segments.
 281 *
 282 * @segment: virtual address
 283 * @segment_dma: dma address
 284 */
 285struct segments {
 286        void *segment;
 287        dma_addr_t segment_dma;
 288};
 289
 290/**
 291 * struct op_req_qinfo -  Operational Request Queue Information
 292 *
 293 * @ci: consumer index
 294 * @pi: producer index
 295 * @num_request: Maximum number of entries in the queue
 296 * @qid: Queue Id starting from 1
 297 * @reply_qid: Associated reply queue Id
 298 * @num_segments: Number of discontiguous memory segments
 299 * @segment_qd: Depth of each segments
 300 * @q_lock: Concurrent queue access lock
 301 * @q_segments: Segment descriptor pointer
 302 * @q_segment_list: Segment list base virtual address
 303 * @q_segment_list_dma: Segment list base DMA address
 304 */
 305struct op_req_qinfo {
 306        u16 ci;
 307        u16 pi;
 308        u16 num_requests;
 309        u16 qid;
 310        u16 reply_qid;
 311        u16 num_segments;
 312        u16 segment_qd;
 313        spinlock_t q_lock;
 314        struct segments *q_segments;
 315        void *q_segment_list;
 316        dma_addr_t q_segment_list_dma;
 317};
 318
 319/**
 320 * struct op_reply_qinfo -  Operational Reply Queue Information
 321 *
 322 * @ci: consumer index
 323 * @qid: Queue Id starting from 1
 324 * @num_replies: Maximum number of entries in the queue
 325 * @num_segments: Number of discontiguous memory segments
 326 * @segment_qd: Depth of each segments
 327 * @q_segments: Segment descriptor pointer
 328 * @q_segment_list: Segment list base virtual address
 329 * @q_segment_list_dma: Segment list base DMA address
 330 * @ephase: Expected phased identifier for the reply queue
 331 * @pend_ios: Number of IOs pending in HW for this queue
 332 * @enable_irq_poll: Flag to indicate polling is enabled
 333 * @in_use: Queue is handled by poll/ISR
 334 * @qtype: Type of queue (types defined in enum queue_type)
 335 */
 336struct op_reply_qinfo {
 337        u16 ci;
 338        u16 qid;
 339        u16 num_replies;
 340        u16 num_segments;
 341        u16 segment_qd;
 342        struct segments *q_segments;
 343        void *q_segment_list;
 344        dma_addr_t q_segment_list_dma;
 345        u8 ephase;
 346        atomic_t pend_ios;
 347        bool enable_irq_poll;
 348        atomic_t in_use;
 349        enum queue_type qtype;
 350};
 351
 352/**
 353 * struct mpi3mr_intr_info -  Interrupt cookie information
 354 *
 355 * @mrioc: Adapter instance reference
 356 * @msix_index: MSIx index
 357 * @op_reply_q: Associated operational reply queue
 358 * @name: Dev name for the irq claiming device
 359 */
 360struct mpi3mr_intr_info {
 361        struct mpi3mr_ioc *mrioc;
 362        u16 msix_index;
 363        struct op_reply_qinfo *op_reply_q;
 364        char name[MPI3MR_NAME_LENGTH];
 365};
 366
 367/**
 368 * struct tgt_dev_sas_sata - SAS/SATA device specific
 369 * information cached from firmware given data
 370 *
 371 * @sas_address: World wide unique SAS address
 372 * @dev_info: Device information bits
 373 */
 374struct tgt_dev_sas_sata {
 375        u64 sas_address;
 376        u16 dev_info;
 377};
 378
 379/**
 380 * struct tgt_dev_pcie - PCIe device specific information cached
 381 * from firmware given data
 382 *
 383 * @mdts: Maximum data transfer size
 384 * @capb: Device capabilities
 385 * @pgsz: Device page size
 386 * @abort_to: Timeout for abort TM
 387 * @reset_to: Timeout for Target/LUN reset TM
 388 * @dev_info: Device information bits
 389 */
 390struct tgt_dev_pcie {
 391        u32 mdts;
 392        u16 capb;
 393        u8 pgsz;
 394        u8 abort_to;
 395        u8 reset_to;
 396        u16 dev_info;
 397};
 398
 399/**
 400 * struct tgt_dev_volume - virtual device specific information
 401 * cached from firmware given data
 402 *
 403 * @state: State of the VD
 404 */
 405struct tgt_dev_volume {
 406        u8 state;
 407};
 408
 409/**
 410 * union _form_spec_inf - union of device specific information
 411 */
 412union _form_spec_inf {
 413        struct tgt_dev_sas_sata sas_sata_inf;
 414        struct tgt_dev_pcie pcie_inf;
 415        struct tgt_dev_volume vol_inf;
 416};
 417
 418
 419
 420/**
 421 * struct mpi3mr_tgt_dev - target device data structure
 422 *
 423 * @list: List pointer
 424 * @starget: Scsi_target pointer
 425 * @dev_handle: FW device handle
 426 * @parent_handle: FW parent device handle
 427 * @slot: Slot number
 428 * @encl_handle: FW enclosure handle
 429 * @perst_id: FW assigned Persistent ID
 430 * @dev_type: SAS/SATA/PCIE device type
 431 * @is_hidden: Should be exposed to upper layers or not
 432 * @host_exposed: Already exposed to host or not
 433 * @q_depth: Device specific Queue Depth
 434 * @wwid: World wide ID
 435 * @dev_spec: Device type specific information
 436 * @ref_count: Reference count
 437 */
 438struct mpi3mr_tgt_dev {
 439        struct list_head list;
 440        struct scsi_target *starget;
 441        u16 dev_handle;
 442        u16 parent_handle;
 443        u16 slot;
 444        u16 encl_handle;
 445        u16 perst_id;
 446        u8 dev_type;
 447        u8 is_hidden;
 448        u8 host_exposed;
 449        u16 q_depth;
 450        u64 wwid;
 451        union _form_spec_inf dev_spec;
 452        struct kref ref_count;
 453};
 454
 455/**
 456 * mpi3mr_tgtdev_get - k reference incrementor
 457 * @s: Target device reference
 458 *
 459 * Increment target device reference count.
 460 */
 461static inline void mpi3mr_tgtdev_get(struct mpi3mr_tgt_dev *s)
 462{
 463        kref_get(&s->ref_count);
 464}
 465
 466/**
 467 * mpi3mr_free_tgtdev - target device memory dealloctor
 468 * @r: k reference pointer of the target device
 469 *
 470 * Free target device memory when no reference.
 471 */
 472static inline void mpi3mr_free_tgtdev(struct kref *r)
 473{
 474        kfree(container_of(r, struct mpi3mr_tgt_dev, ref_count));
 475}
 476
 477/**
 478 * mpi3mr_tgtdev_put - k reference decrementor
 479 * @s: Target device reference
 480 *
 481 * Decrement target device reference count.
 482 */
 483static inline void mpi3mr_tgtdev_put(struct mpi3mr_tgt_dev *s)
 484{
 485        kref_put(&s->ref_count, mpi3mr_free_tgtdev);
 486}
 487
 488
 489/**
 490 * struct mpi3mr_stgt_priv_data - SCSI target private structure
 491 *
 492 * @starget: Scsi_target pointer
 493 * @dev_handle: FW device handle
 494 * @perst_id: FW assigned Persistent ID
 495 * @num_luns: Number of Logical Units
 496 * @block_io: I/O blocked to the device or not
 497 * @dev_removed: Device removed in the Firmware
 498 * @dev_removedelay: Device is waiting to be removed in FW
 499 * @dev_type: Device type
 500 * @tgt_dev: Internal target device pointer
 501 * @pend_count: Counter to track pending I/Os during error
 502 *              handling
 503 */
 504struct mpi3mr_stgt_priv_data {
 505        struct scsi_target *starget;
 506        u16 dev_handle;
 507        u16 perst_id;
 508        u32 num_luns;
 509        atomic_t block_io;
 510        u8 dev_removed;
 511        u8 dev_removedelay;
 512        u8 dev_type;
 513        struct mpi3mr_tgt_dev *tgt_dev;
 514        u32 pend_count;
 515};
 516
 517/**
 518 * struct mpi3mr_stgt_priv_data - SCSI device private structure
 519 *
 520 * @tgt_priv_data: Scsi_target private data pointer
 521 * @lun_id: LUN ID of the device
 522 * @ncq_prio_enable: NCQ priority enable for SATA device
 523 * @pend_count: Counter to track pending I/Os during error
 524 *              handling
 525 */
 526struct mpi3mr_sdev_priv_data {
 527        struct mpi3mr_stgt_priv_data *tgt_priv_data;
 528        u32 lun_id;
 529        u8 ncq_prio_enable;
 530        u32 pend_count;
 531};
 532
 533/**
 534 * struct mpi3mr_drv_cmd - Internal command tracker
 535 *
 536 * @mutex: Command mutex
 537 * @done: Completeor for wakeup
 538 * @reply: Firmware reply for internal commands
 539 * @sensebuf: Sensebuf for SCSI IO commands
 540 * @iou_rc: IO Unit control reason code
 541 * @state: Command State
 542 * @dev_handle: Firmware handle for device specific commands
 543 * @ioc_status: IOC status from the firmware
 544 * @ioc_loginfo:IOC log info from the firmware
 545 * @is_waiting: Is the command issued in block mode
 546 * @retry_count: Retry count for retriable commands
 547 * @host_tag: Host tag used by the command
 548 * @callback: Callback for non blocking commands
 549 */
 550struct mpi3mr_drv_cmd {
 551        struct mutex mutex;
 552        struct completion done;
 553        void *reply;
 554        u8 *sensebuf;
 555        u8 iou_rc;
 556        u16 state;
 557        u16 dev_handle;
 558        u16 ioc_status;
 559        u32 ioc_loginfo;
 560        u8 is_waiting;
 561        u8 retry_count;
 562        u16 host_tag;
 563
 564        void (*callback)(struct mpi3mr_ioc *mrioc,
 565            struct mpi3mr_drv_cmd *drv_cmd);
 566};
 567
 568
 569/**
 570 * struct chain_element - memory descriptor structure to store
 571 * virtual and dma addresses for chain elements.
 572 *
 573 * @addr: virtual address
 574 * @dma_addr: dma address
 575 */
 576struct chain_element {
 577        void *addr;
 578        dma_addr_t dma_addr;
 579};
 580
 581/**
 582 * struct scmd_priv - SCSI command private data
 583 *
 584 * @host_tag: Host tag specific to operational queue
 585 * @in_lld_scope: Command in LLD scope or not
 586 * @meta_sg_valid: DIX command with meta data SGL or not
 587 * @scmd: SCSI Command pointer
 588 * @req_q_idx: Operational request queue index
 589 * @chain_idx: Chain frame index
 590 * @meta_chain_idx: Chain frame index of meta data SGL
 591 * @mpi3mr_scsiio_req: MPI SCSI IO request
 592 */
 593struct scmd_priv {
 594        u16 host_tag;
 595        u8 in_lld_scope;
 596        u8 meta_sg_valid;
 597        struct scsi_cmnd *scmd;
 598        u16 req_q_idx;
 599        int chain_idx;
 600        int meta_chain_idx;
 601        u8 mpi3mr_scsiio_req[MPI3MR_ADMIN_REQ_FRAME_SZ];
 602};
 603
 604/**
 605 * struct mpi3mr_ioc - Adapter anchor structure stored in shost
 606 * private data
 607 *
 608 * @list: List pointer
 609 * @pdev: PCI device pointer
 610 * @shost: Scsi_Host pointer
 611 * @id: Controller ID
 612 * @cpu_count: Number of online CPUs
 613 * @irqpoll_sleep: usleep unit used in threaded isr irqpoll
 614 * @name: Controller ASCII name
 615 * @driver_name: Driver ASCII name
 616 * @sysif_regs: System interface registers virtual address
 617 * @sysif_regs_phys: System interface registers physical address
 618 * @bars: PCI BARS
 619 * @dma_mask: DMA mask
 620 * @msix_count: Number of MSIX vectors used
 621 * @intr_enabled: Is interrupts enabled
 622 * @num_admin_req: Number of admin requests
 623 * @admin_req_q_sz: Admin request queue size
 624 * @admin_req_pi: Admin request queue producer index
 625 * @admin_req_ci: Admin request queue consumer index
 626 * @admin_req_base: Admin request queue base virtual address
 627 * @admin_req_dma: Admin request queue base dma address
 628 * @admin_req_lock: Admin queue access lock
 629 * @num_admin_replies: Number of admin replies
 630 * @admin_reply_q_sz: Admin reply queue size
 631 * @admin_reply_ci: Admin reply queue consumer index
 632 * @admin_reply_ephase:Admin reply queue expected phase
 633 * @admin_reply_base: Admin reply queue base virtual address
 634 * @admin_reply_dma: Admin reply queue base dma address
 635 * @ready_timeout: Controller ready timeout
 636 * @intr_info: Interrupt cookie pointer
 637 * @intr_info_count: Number of interrupt cookies
 638 * @is_intr_info_set: Flag to indicate intr info is setup
 639 * @num_queues: Number of operational queues
 640 * @num_op_req_q: Number of operational request queues
 641 * @req_qinfo: Operational request queue info pointer
 642 * @num_op_reply_q: Number of operational reply queues
 643 * @op_reply_qinfo: Operational reply queue info pointer
 644 * @init_cmds: Command tracker for initialization commands
 645 * @facts: Cached IOC facts data
 646 * @op_reply_desc_sz: Operational reply descriptor size
 647 * @num_reply_bufs: Number of reply buffers allocated
 648 * @reply_buf_pool: Reply buffer pool
 649 * @reply_buf: Reply buffer base virtual address
 650 * @reply_buf_dma: Reply buffer DMA address
 651 * @reply_buf_dma_max_address: Reply DMA address max limit
 652 * @reply_free_qsz: Reply free queue size
 653 * @reply_free_q_pool: Reply free queue pool
 654 * @reply_free_q: Reply free queue base virtual address
 655 * @reply_free_q_dma: Reply free queue base DMA address
 656 * @reply_free_queue_lock: Reply free queue lock
 657 * @reply_free_queue_host_index: Reply free queue host index
 658 * @num_sense_bufs: Number of sense buffers
 659 * @sense_buf_pool: Sense buffer pool
 660 * @sense_buf: Sense buffer base virtual address
 661 * @sense_buf_dma: Sense buffer base DMA address
 662 * @sense_buf_q_sz: Sense buffer queue size
 663 * @sense_buf_q_pool: Sense buffer queue pool
 664 * @sense_buf_q: Sense buffer queue virtual address
 665 * @sense_buf_q_dma: Sense buffer queue DMA address
 666 * @sbq_lock: Sense buffer queue lock
 667 * @sbq_host_index: Sense buffer queuehost index
 668 * @event_masks: Event mask bitmap
 669 * @fwevt_worker_name: Firmware event worker thread name
 670 * @fwevt_worker_thread: Firmware event worker thread
 671 * @fwevt_lock: Firmware event lock
 672 * @fwevt_list: Firmware event list
 673 * @watchdog_work_q_name: Fault watchdog worker thread name
 674 * @watchdog_work_q: Fault watchdog worker thread
 675 * @watchdog_work: Fault watchdog work
 676 * @watchdog_lock: Fault watchdog lock
 677 * @is_driver_loading: Is driver still loading
 678 * @scan_started: Async scan started
 679 * @scan_failed: Asycn scan failed
 680 * @stop_drv_processing: Stop all command processing
 681 * @max_host_ios: Maximum host I/O count
 682 * @chain_buf_count: Chain buffer count
 683 * @chain_buf_pool: Chain buffer pool
 684 * @chain_sgl_list: Chain SGL list
 685 * @chain_bitmap_sz: Chain buffer allocator bitmap size
 686 * @chain_bitmap: Chain buffer allocator bitmap
 687 * @chain_buf_lock: Chain buffer list lock
 688 * @host_tm_cmds: Command tracker for task management commands
 689 * @dev_rmhs_cmds: Command tracker for device removal commands
 690 * @evtack_cmds: Command tracker for event ack commands
 691 * @devrem_bitmap_sz: Device removal bitmap size
 692 * @devrem_bitmap: Device removal bitmap
 693 * @dev_handle_bitmap_sz: Device handle bitmap size
 694 * @removepend_bitmap: Remove pending bitmap
 695 * @delayed_rmhs_list: Delayed device removal list
 696 * @evtack_cmds_bitmap_sz: Event Ack bitmap size
 697 * @evtack_cmds_bitmap: Event Ack bitmap
 698 * @delayed_evtack_cmds_list: Delayed event acknowledgment list
 699 * @ts_update_counter: Timestamp update counter
 700 * @reset_in_progress: Reset in progress flag
 701 * @unrecoverable: Controller unrecoverable flag
 702 * @prev_reset_result: Result of previous reset
 703 * @reset_mutex: Controller reset mutex
 704 * @reset_waitq: Controller reset  wait queue
 705 * @prepare_for_reset: Prepare for reset event received
 706 * @prepare_for_reset_timeout_counter: Prepare for reset timeout
 707 * @diagsave_timeout: Diagnostic information save timeout
 708 * @logging_level: Controller debug logging level
 709 * @flush_io_count: I/O count to flush after reset
 710 * @current_event: Firmware event currently in process
 711 * @driver_info: Driver, Kernel, OS information to firmware
 712 * @change_count: Topology change count
 713 * @op_reply_q_offset: Operational reply queue offset with MSIx
 714 * @default_qcount: Total Default queues
 715 * @active_poll_qcount: Currently active poll queue count
 716 * @requested_poll_qcount: User requested poll queue count
 717 */
 718struct mpi3mr_ioc {
 719        struct list_head list;
 720        struct pci_dev *pdev;
 721        struct Scsi_Host *shost;
 722        u8 id;
 723        int cpu_count;
 724        bool enable_segqueue;
 725        u32 irqpoll_sleep;
 726
 727        char name[MPI3MR_NAME_LENGTH];
 728        char driver_name[MPI3MR_NAME_LENGTH];
 729
 730        volatile struct mpi3_sysif_registers __iomem *sysif_regs;
 731        resource_size_t sysif_regs_phys;
 732        int bars;
 733        u64 dma_mask;
 734
 735        u16 msix_count;
 736        u8 intr_enabled;
 737
 738        u16 num_admin_req;
 739        u32 admin_req_q_sz;
 740        u16 admin_req_pi;
 741        u16 admin_req_ci;
 742        void *admin_req_base;
 743        dma_addr_t admin_req_dma;
 744        spinlock_t admin_req_lock;
 745
 746        u16 num_admin_replies;
 747        u32 admin_reply_q_sz;
 748        u16 admin_reply_ci;
 749        u8 admin_reply_ephase;
 750        void *admin_reply_base;
 751        dma_addr_t admin_reply_dma;
 752
 753        u32 ready_timeout;
 754
 755        struct mpi3mr_intr_info *intr_info;
 756        u16 intr_info_count;
 757        bool is_intr_info_set;
 758
 759        u16 num_queues;
 760        u16 num_op_req_q;
 761        struct op_req_qinfo *req_qinfo;
 762
 763        u16 num_op_reply_q;
 764        struct op_reply_qinfo *op_reply_qinfo;
 765
 766        struct mpi3mr_drv_cmd init_cmds;
 767        struct mpi3mr_ioc_facts facts;
 768        u16 op_reply_desc_sz;
 769
 770        u32 num_reply_bufs;
 771        struct dma_pool *reply_buf_pool;
 772        u8 *reply_buf;
 773        dma_addr_t reply_buf_dma;
 774        dma_addr_t reply_buf_dma_max_address;
 775
 776        u16 reply_free_qsz;
 777        u16 reply_sz;
 778        struct dma_pool *reply_free_q_pool;
 779        __le64 *reply_free_q;
 780        dma_addr_t reply_free_q_dma;
 781        spinlock_t reply_free_queue_lock;
 782        u32 reply_free_queue_host_index;
 783
 784        u32 num_sense_bufs;
 785        struct dma_pool *sense_buf_pool;
 786        u8 *sense_buf;
 787        dma_addr_t sense_buf_dma;
 788
 789        u16 sense_buf_q_sz;
 790        struct dma_pool *sense_buf_q_pool;
 791        __le64 *sense_buf_q;
 792        dma_addr_t sense_buf_q_dma;
 793        spinlock_t sbq_lock;
 794        u32 sbq_host_index;
 795        u32 event_masks[MPI3_EVENT_NOTIFY_EVENTMASK_WORDS];
 796
 797        char fwevt_worker_name[MPI3MR_NAME_LENGTH];
 798        struct workqueue_struct *fwevt_worker_thread;
 799        spinlock_t fwevt_lock;
 800        struct list_head fwevt_list;
 801
 802        char watchdog_work_q_name[20];
 803        struct workqueue_struct *watchdog_work_q;
 804        struct delayed_work watchdog_work;
 805        spinlock_t watchdog_lock;
 806
 807        u8 is_driver_loading;
 808        u8 scan_started;
 809        u16 scan_failed;
 810        u8 stop_drv_processing;
 811
 812        u16 max_host_ios;
 813        spinlock_t tgtdev_lock;
 814        struct list_head tgtdev_list;
 815
 816        u32 chain_buf_count;
 817        struct dma_pool *chain_buf_pool;
 818        struct chain_element *chain_sgl_list;
 819        u16  chain_bitmap_sz;
 820        void *chain_bitmap;
 821        spinlock_t chain_buf_lock;
 822
 823        struct mpi3mr_drv_cmd host_tm_cmds;
 824        struct mpi3mr_drv_cmd dev_rmhs_cmds[MPI3MR_NUM_DEVRMCMD];
 825        struct mpi3mr_drv_cmd evtack_cmds[MPI3MR_NUM_EVTACKCMD];
 826        u16 devrem_bitmap_sz;
 827        void *devrem_bitmap;
 828        u16 dev_handle_bitmap_sz;
 829        void *removepend_bitmap;
 830        struct list_head delayed_rmhs_list;
 831        u16 evtack_cmds_bitmap_sz;
 832        void *evtack_cmds_bitmap;
 833        struct list_head delayed_evtack_cmds_list;
 834
 835        u32 ts_update_counter;
 836        u8 reset_in_progress;
 837        u8 unrecoverable;
 838        int prev_reset_result;
 839        struct mutex reset_mutex;
 840        wait_queue_head_t reset_waitq;
 841
 842        u8 prepare_for_reset;
 843        u16 prepare_for_reset_timeout_counter;
 844
 845        u16 diagsave_timeout;
 846        int logging_level;
 847        u16 flush_io_count;
 848
 849        struct mpi3mr_fwevt *current_event;
 850        struct mpi3_driver_info_layout driver_info;
 851        u16 change_count;
 852        u16 op_reply_q_offset;
 853
 854        u16 default_qcount;
 855        u16 active_poll_qcount;
 856        u16 requested_poll_qcount;
 857};
 858
 859/**
 860 * struct mpi3mr_fwevt - Firmware event structure.
 861 *
 862 * @list: list head
 863 * @work: Work structure
 864 * @mrioc: Adapter instance reference
 865 * @event_id: MPI3 firmware event ID
 866 * @send_ack: Event acknowledgment required or not
 867 * @process_evt: Bottomhalf processing required or not
 868 * @evt_ctx: Event context to send in Ack
 869 * @ref_count: kref count
 870 * @event_data: Actual MPI3 event data
 871 */
 872struct mpi3mr_fwevt {
 873        struct list_head list;
 874        struct work_struct work;
 875        struct mpi3mr_ioc *mrioc;
 876        u16 event_id;
 877        bool send_ack;
 878        bool process_evt;
 879        u32 evt_ctx;
 880        struct kref ref_count;
 881        char event_data[0] __aligned(4);
 882};
 883
 884
 885/**
 886 * struct delayed_dev_rmhs_node - Delayed device removal node
 887 *
 888 * @list: list head
 889 * @handle: Device handle
 890 * @iou_rc: IO Unit Control Reason Code
 891 */
 892struct delayed_dev_rmhs_node {
 893        struct list_head list;
 894        u16 handle;
 895        u8 iou_rc;
 896};
 897
 898/**
 899 * struct delayed_evt_ack_node - Delayed event ack node
 900 * @list: list head
 901 * @event: MPI3 event ID
 902 * @event_ctx: event context
 903 */
 904struct delayed_evt_ack_node {
 905        struct list_head list;
 906        u8 event;
 907        u32 event_ctx;
 908};
 909
 910int mpi3mr_setup_resources(struct mpi3mr_ioc *mrioc);
 911void mpi3mr_cleanup_resources(struct mpi3mr_ioc *mrioc);
 912int mpi3mr_init_ioc(struct mpi3mr_ioc *mrioc);
 913int mpi3mr_reinit_ioc(struct mpi3mr_ioc *mrioc, u8 is_resume);
 914void mpi3mr_cleanup_ioc(struct mpi3mr_ioc *mrioc);
 915int mpi3mr_issue_port_enable(struct mpi3mr_ioc *mrioc, u8 async);
 916int mpi3mr_admin_request_post(struct mpi3mr_ioc *mrioc, void *admin_req,
 917u16 admin_req_sz, u8 ignore_reset);
 918int mpi3mr_op_request_post(struct mpi3mr_ioc *mrioc,
 919                           struct op_req_qinfo *opreqq, u8 *req);
 920void mpi3mr_add_sg_single(void *paddr, u8 flags, u32 length,
 921                          dma_addr_t dma_addr);
 922void mpi3mr_build_zero_len_sge(void *paddr);
 923void *mpi3mr_get_sensebuf_virt_addr(struct mpi3mr_ioc *mrioc,
 924                                     dma_addr_t phys_addr);
 925void *mpi3mr_get_reply_virt_addr(struct mpi3mr_ioc *mrioc,
 926                                     dma_addr_t phys_addr);
 927void mpi3mr_repost_sense_buf(struct mpi3mr_ioc *mrioc,
 928                                     u64 sense_buf_dma);
 929
 930void mpi3mr_memset_buffers(struct mpi3mr_ioc *mrioc);
 931void mpi3mr_free_mem(struct mpi3mr_ioc *mrioc);
 932void mpi3mr_os_handle_events(struct mpi3mr_ioc *mrioc,
 933                             struct mpi3_event_notification_reply *event_reply);
 934void mpi3mr_process_op_reply_desc(struct mpi3mr_ioc *mrioc,
 935                                  struct mpi3_default_reply_descriptor *reply_desc,
 936                                  u64 *reply_dma, u16 qidx);
 937void mpi3mr_start_watchdog(struct mpi3mr_ioc *mrioc);
 938void mpi3mr_stop_watchdog(struct mpi3mr_ioc *mrioc);
 939
 940int mpi3mr_soft_reset_handler(struct mpi3mr_ioc *mrioc,
 941                              u32 reset_reason, u8 snapdump);
 942void mpi3mr_ioc_disable_intr(struct mpi3mr_ioc *mrioc);
 943void mpi3mr_ioc_enable_intr(struct mpi3mr_ioc *mrioc);
 944
 945enum mpi3mr_iocstate mpi3mr_get_iocstate(struct mpi3mr_ioc *mrioc);
 946int mpi3mr_process_event_ack(struct mpi3mr_ioc *mrioc, u8 event,
 947                          u32 event_ctx);
 948
 949void mpi3mr_wait_for_host_io(struct mpi3mr_ioc *mrioc, u32 timeout);
 950void mpi3mr_cleanup_fwevt_list(struct mpi3mr_ioc *mrioc);
 951void mpi3mr_flush_host_io(struct mpi3mr_ioc *mrioc);
 952void mpi3mr_invalidate_devhandles(struct mpi3mr_ioc *mrioc);
 953void mpi3mr_rfresh_tgtdevs(struct mpi3mr_ioc *mrioc);
 954void mpi3mr_flush_delayed_cmd_lists(struct mpi3mr_ioc *mrioc);
 955void mpi3mr_check_rh_fault_ioc(struct mpi3mr_ioc *mrioc, u32 reason_code);
 956void mpi3mr_print_fault_info(struct mpi3mr_ioc *mrioc);
 957void mpi3mr_check_rh_fault_ioc(struct mpi3mr_ioc *mrioc, u32 reason_code);
 958int mpi3mr_process_op_reply_q(struct mpi3mr_ioc *mrioc,
 959        struct op_reply_qinfo *op_reply_q);
 960int mpi3mr_blk_mq_poll(struct Scsi_Host *shost, unsigned int queue_num);
 961
 962#endif /*MPI3MR_H_INCLUDED*/
 963