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12#define pr_fmt(fmt) "tegra-pmc: " fmt
13
14#include <linux/arm-smccc.h>
15#include <linux/clk.h>
16#include <linux/clk-provider.h>
17#include <linux/clkdev.h>
18#include <linux/clk/clk-conf.h>
19#include <linux/clk/tegra.h>
20#include <linux/debugfs.h>
21#include <linux/delay.h>
22#include <linux/device.h>
23#include <linux/err.h>
24#include <linux/export.h>
25#include <linux/init.h>
26#include <linux/io.h>
27#include <linux/iopoll.h>
28#include <linux/irqdomain.h>
29#include <linux/irq.h>
30#include <linux/kernel.h>
31#include <linux/of_address.h>
32#include <linux/of_clk.h>
33#include <linux/of.h>
34#include <linux/of_irq.h>
35#include <linux/of_platform.h>
36#include <linux/pinctrl/pinconf-generic.h>
37#include <linux/pinctrl/pinconf.h>
38#include <linux/pinctrl/pinctrl.h>
39#include <linux/platform_device.h>
40#include <linux/pm_domain.h>
41#include <linux/pm_opp.h>
42#include <linux/reboot.h>
43#include <linux/regmap.h>
44#include <linux/reset.h>
45#include <linux/seq_file.h>
46#include <linux/slab.h>
47#include <linux/spinlock.h>
48
49#include <soc/tegra/common.h>
50#include <soc/tegra/fuse.h>
51#include <soc/tegra/pmc.h>
52
53#include <dt-bindings/interrupt-controller/arm-gic.h>
54#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
55#include <dt-bindings/gpio/tegra186-gpio.h>
56#include <dt-bindings/gpio/tegra194-gpio.h>
57#include <dt-bindings/soc/tegra-pmc.h>
58
59#define PMC_CNTRL 0x0
60#define PMC_CNTRL_INTR_POLARITY BIT(17)
61#define PMC_CNTRL_CPU_PWRREQ_OE BIT(16)
62#define PMC_CNTRL_CPU_PWRREQ_POLARITY BIT(15)
63#define PMC_CNTRL_SIDE_EFFECT_LP0 BIT(14)
64#define PMC_CNTRL_SYSCLK_OE BIT(11)
65#define PMC_CNTRL_SYSCLK_POLARITY BIT(10)
66#define PMC_CNTRL_PWRREQ_POLARITY BIT(8)
67#define PMC_CNTRL_BLINK_EN 7
68#define PMC_CNTRL_MAIN_RST BIT(4)
69
70#define PMC_WAKE_MASK 0x0c
71#define PMC_WAKE_LEVEL 0x10
72#define PMC_WAKE_STATUS 0x14
73#define PMC_SW_WAKE_STATUS 0x18
74#define PMC_DPD_PADS_ORIDE 0x1c
75#define PMC_DPD_PADS_ORIDE_BLINK 20
76
77#define DPD_SAMPLE 0x020
78#define DPD_SAMPLE_ENABLE BIT(0)
79#define DPD_SAMPLE_DISABLE (0 << 0)
80
81#define PWRGATE_TOGGLE 0x30
82#define PWRGATE_TOGGLE_START BIT(8)
83
84#define REMOVE_CLAMPING 0x34
85
86#define PWRGATE_STATUS 0x38
87
88#define PMC_BLINK_TIMER 0x40
89#define PMC_IMPL_E_33V_PWR 0x40
90
91#define PMC_PWR_DET 0x48
92
93#define PMC_SCRATCH0_MODE_RECOVERY BIT(31)
94#define PMC_SCRATCH0_MODE_BOOTLOADER BIT(30)
95#define PMC_SCRATCH0_MODE_RCM BIT(1)
96#define PMC_SCRATCH0_MODE_MASK (PMC_SCRATCH0_MODE_RECOVERY | \
97 PMC_SCRATCH0_MODE_BOOTLOADER | \
98 PMC_SCRATCH0_MODE_RCM)
99
100#define PMC_CPUPWRGOOD_TIMER 0xc8
101#define PMC_CPUPWROFF_TIMER 0xcc
102#define PMC_COREPWRGOOD_TIMER 0x3c
103#define PMC_COREPWROFF_TIMER 0xe0
104
105#define PMC_PWR_DET_VALUE 0xe4
106
107#define PMC_USB_DEBOUNCE_DEL 0xec
108#define PMC_USB_AO 0xf0
109
110#define PMC_SCRATCH41 0x140
111
112#define PMC_WAKE2_MASK 0x160
113#define PMC_WAKE2_LEVEL 0x164
114#define PMC_WAKE2_STATUS 0x168
115#define PMC_SW_WAKE2_STATUS 0x16c
116
117#define PMC_CLK_OUT_CNTRL 0x1a8
118#define PMC_CLK_OUT_MUX_MASK GENMASK(1, 0)
119#define PMC_SENSOR_CTRL 0x1b0
120#define PMC_SENSOR_CTRL_SCRATCH_WRITE BIT(2)
121#define PMC_SENSOR_CTRL_ENABLE_RST BIT(1)
122
123#define PMC_RST_STATUS_POR 0
124#define PMC_RST_STATUS_WATCHDOG 1
125#define PMC_RST_STATUS_SENSOR 2
126#define PMC_RST_STATUS_SW_MAIN 3
127#define PMC_RST_STATUS_LP0 4
128#define PMC_RST_STATUS_AOTAG 5
129
130#define IO_DPD_REQ 0x1b8
131#define IO_DPD_REQ_CODE_IDLE (0U << 30)
132#define IO_DPD_REQ_CODE_OFF (1U << 30)
133#define IO_DPD_REQ_CODE_ON (2U << 30)
134#define IO_DPD_REQ_CODE_MASK (3U << 30)
135
136#define IO_DPD_STATUS 0x1bc
137#define IO_DPD2_REQ 0x1c0
138#define IO_DPD2_STATUS 0x1c4
139#define SEL_DPD_TIM 0x1c8
140
141#define PMC_UTMIP_UHSIC_TRIGGERS 0x1ec
142#define PMC_UTMIP_UHSIC_SAVED_STATE 0x1f0
143
144#define PMC_UTMIP_TERM_PAD_CFG 0x1f8
145#define PMC_UTMIP_UHSIC_SLEEP_CFG 0x1fc
146#define PMC_UTMIP_UHSIC_FAKE 0x218
147
148#define PMC_SCRATCH54 0x258
149#define PMC_SCRATCH54_DATA_SHIFT 8
150#define PMC_SCRATCH54_ADDR_SHIFT 0
151
152#define PMC_SCRATCH55 0x25c
153#define PMC_SCRATCH55_RESET_TEGRA BIT(31)
154#define PMC_SCRATCH55_CNTRL_ID_SHIFT 27
155#define PMC_SCRATCH55_PINMUX_SHIFT 24
156#define PMC_SCRATCH55_16BITOP BIT(15)
157#define PMC_SCRATCH55_CHECKSUM_SHIFT 16
158#define PMC_SCRATCH55_I2CSLV1_SHIFT 0
159
160#define PMC_UTMIP_UHSIC_LINE_WAKEUP 0x26c
161
162#define PMC_UTMIP_BIAS_MASTER_CNTRL 0x270
163#define PMC_UTMIP_MASTER_CONFIG 0x274
164#define PMC_UTMIP_UHSIC2_TRIGGERS 0x27c
165#define PMC_UTMIP_MASTER2_CONFIG 0x29c
166
167#define GPU_RG_CNTRL 0x2d4
168
169#define PMC_UTMIP_PAD_CFG0 0x4c0
170#define PMC_UTMIP_UHSIC_SLEEP_CFG1 0x4d0
171#define PMC_UTMIP_SLEEPWALK_P3 0x4e0
172
173#define WAKE_AOWAKE_CNTRL(x) (0x000 + ((x) << 2))
174#define WAKE_AOWAKE_CNTRL_LEVEL (1 << 3)
175#define WAKE_AOWAKE_MASK_W(x) (0x180 + ((x) << 2))
176#define WAKE_AOWAKE_MASK_R(x) (0x300 + ((x) << 2))
177#define WAKE_AOWAKE_STATUS_W(x) (0x30c + ((x) << 2))
178#define WAKE_AOWAKE_STATUS_R(x) (0x48c + ((x) << 2))
179#define WAKE_AOWAKE_TIER0_ROUTING(x) (0x4b4 + ((x) << 2))
180#define WAKE_AOWAKE_TIER1_ROUTING(x) (0x4c0 + ((x) << 2))
181#define WAKE_AOWAKE_TIER2_ROUTING(x) (0x4cc + ((x) << 2))
182
183#define WAKE_AOWAKE_CTRL 0x4f4
184#define WAKE_AOWAKE_CTRL_INTR_POLARITY BIT(0)
185
186
187#define TEGRA_SMC_PMC 0xc2fffe00
188#define TEGRA_SMC_PMC_READ 0xaa
189#define TEGRA_SMC_PMC_WRITE 0xbb
190
191struct pmc_clk {
192 struct clk_hw hw;
193 unsigned long offs;
194 u32 mux_shift;
195 u32 force_en_shift;
196};
197
198#define to_pmc_clk(_hw) container_of(_hw, struct pmc_clk, hw)
199
200struct pmc_clk_gate {
201 struct clk_hw hw;
202 unsigned long offs;
203 u32 shift;
204};
205
206#define to_pmc_clk_gate(_hw) container_of(_hw, struct pmc_clk_gate, hw)
207
208struct pmc_clk_init_data {
209 char *name;
210 const char *const *parents;
211 int num_parents;
212 int clk_id;
213 u8 mux_shift;
214 u8 force_en_shift;
215};
216
217static const char * const clk_out1_parents[] = { "osc", "osc_div2",
218 "osc_div4", "extern1",
219};
220
221static const char * const clk_out2_parents[] = { "osc", "osc_div2",
222 "osc_div4", "extern2",
223};
224
225static const char * const clk_out3_parents[] = { "osc", "osc_div2",
226 "osc_div4", "extern3",
227};
228
229static const struct pmc_clk_init_data tegra_pmc_clks_data[] = {
230 {
231 .name = "pmc_clk_out_1",
232 .parents = clk_out1_parents,
233 .num_parents = ARRAY_SIZE(clk_out1_parents),
234 .clk_id = TEGRA_PMC_CLK_OUT_1,
235 .mux_shift = 6,
236 .force_en_shift = 2,
237 },
238 {
239 .name = "pmc_clk_out_2",
240 .parents = clk_out2_parents,
241 .num_parents = ARRAY_SIZE(clk_out2_parents),
242 .clk_id = TEGRA_PMC_CLK_OUT_2,
243 .mux_shift = 14,
244 .force_en_shift = 10,
245 },
246 {
247 .name = "pmc_clk_out_3",
248 .parents = clk_out3_parents,
249 .num_parents = ARRAY_SIZE(clk_out3_parents),
250 .clk_id = TEGRA_PMC_CLK_OUT_3,
251 .mux_shift = 22,
252 .force_en_shift = 18,
253 },
254};
255
256struct tegra_powergate {
257 struct generic_pm_domain genpd;
258 struct tegra_pmc *pmc;
259 unsigned int id;
260 struct clk **clks;
261 unsigned int num_clks;
262 unsigned long *clk_rates;
263 struct reset_control *reset;
264};
265
266struct tegra_io_pad_soc {
267 enum tegra_io_pad id;
268 unsigned int dpd;
269 unsigned int voltage;
270 const char *name;
271};
272
273struct tegra_pmc_regs {
274 unsigned int scratch0;
275 unsigned int dpd_req;
276 unsigned int dpd_status;
277 unsigned int dpd2_req;
278 unsigned int dpd2_status;
279 unsigned int rst_status;
280 unsigned int rst_source_shift;
281 unsigned int rst_source_mask;
282 unsigned int rst_level_shift;
283 unsigned int rst_level_mask;
284};
285
286struct tegra_wake_event {
287 const char *name;
288 unsigned int id;
289 unsigned int irq;
290 struct {
291 unsigned int instance;
292 unsigned int pin;
293 } gpio;
294};
295
296#define TEGRA_WAKE_IRQ(_name, _id, _irq) \
297 { \
298 .name = _name, \
299 .id = _id, \
300 .irq = _irq, \
301 .gpio = { \
302 .instance = UINT_MAX, \
303 .pin = UINT_MAX, \
304 }, \
305 }
306
307#define TEGRA_WAKE_GPIO(_name, _id, _instance, _pin) \
308 { \
309 .name = _name, \
310 .id = _id, \
311 .irq = 0, \
312 .gpio = { \
313 .instance = _instance, \
314 .pin = _pin, \
315 }, \
316 }
317
318struct tegra_pmc_soc {
319 unsigned int num_powergates;
320 const char *const *powergates;
321 unsigned int num_cpu_powergates;
322 const u8 *cpu_powergates;
323
324 bool has_tsense_reset;
325 bool has_gpu_clamps;
326 bool needs_mbist_war;
327 bool has_impl_33v_pwr;
328 bool maybe_tz_only;
329
330 const struct tegra_io_pad_soc *io_pads;
331 unsigned int num_io_pads;
332
333 const struct pinctrl_pin_desc *pin_descs;
334 unsigned int num_pin_descs;
335
336 const struct tegra_pmc_regs *regs;
337 void (*init)(struct tegra_pmc *pmc);
338 void (*setup_irq_polarity)(struct tegra_pmc *pmc,
339 struct device_node *np,
340 bool invert);
341 int (*irq_set_wake)(struct irq_data *data, unsigned int on);
342 int (*irq_set_type)(struct irq_data *data, unsigned int type);
343 int (*powergate_set)(struct tegra_pmc *pmc, unsigned int id,
344 bool new_state);
345
346 const char * const *reset_sources;
347 unsigned int num_reset_sources;
348 const char * const *reset_levels;
349 unsigned int num_reset_levels;
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355
356 const struct tegra_wake_event *wake_events;
357 unsigned int num_wake_events;
358
359 const struct pmc_clk_init_data *pmc_clks_data;
360 unsigned int num_pmc_clks;
361 bool has_blink_output;
362 bool has_usb_sleepwalk;
363 bool supports_core_domain;
364};
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397struct tegra_pmc {
398 struct device *dev;
399 void __iomem *base;
400 void __iomem *wake;
401 void __iomem *aotag;
402 void __iomem *scratch;
403 struct clk *clk;
404 struct dentry *debugfs;
405
406 const struct tegra_pmc_soc *soc;
407 bool tz_only;
408
409 unsigned long rate;
410
411 enum tegra_suspend_mode suspend_mode;
412 u32 cpu_good_time;
413 u32 cpu_off_time;
414 u32 core_osc_time;
415 u32 core_pmu_time;
416 u32 core_off_time;
417 bool corereq_high;
418 bool sysclkreq_high;
419 bool combined_req;
420 bool cpu_pwr_good_en;
421 u32 lp0_vec_phys;
422 u32 lp0_vec_size;
423 DECLARE_BITMAP(powergates_available, TEGRA_POWERGATE_MAX);
424
425 struct mutex powergates_lock;
426
427 struct pinctrl_dev *pctl_dev;
428
429 struct irq_domain *domain;
430 struct irq_chip irq;
431
432 struct notifier_block clk_nb;
433
434 bool core_domain_state_synced;
435 bool core_domain_registered;
436};
437
438static struct tegra_pmc *pmc = &(struct tegra_pmc) {
439 .base = NULL,
440 .suspend_mode = TEGRA_SUSPEND_NOT_READY,
441};
442
443static inline struct tegra_powergate *
444to_powergate(struct generic_pm_domain *domain)
445{
446 return container_of(domain, struct tegra_powergate, genpd);
447}
448
449static u32 tegra_pmc_readl(struct tegra_pmc *pmc, unsigned long offset)
450{
451 struct arm_smccc_res res;
452
453 if (pmc->tz_only) {
454 arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_READ, offset, 0, 0,
455 0, 0, 0, &res);
456 if (res.a0) {
457 if (pmc->dev)
458 dev_warn(pmc->dev, "%s(): SMC failed: %lu\n",
459 __func__, res.a0);
460 else
461 pr_warn("%s(): SMC failed: %lu\n", __func__,
462 res.a0);
463 }
464
465 return res.a1;
466 }
467
468 return readl(pmc->base + offset);
469}
470
471static void tegra_pmc_writel(struct tegra_pmc *pmc, u32 value,
472 unsigned long offset)
473{
474 struct arm_smccc_res res;
475
476 if (pmc->tz_only) {
477 arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_WRITE, offset,
478 value, 0, 0, 0, 0, &res);
479 if (res.a0) {
480 if (pmc->dev)
481 dev_warn(pmc->dev, "%s(): SMC failed: %lu\n",
482 __func__, res.a0);
483 else
484 pr_warn("%s(): SMC failed: %lu\n", __func__,
485 res.a0);
486 }
487 } else {
488 writel(value, pmc->base + offset);
489 }
490}
491
492static u32 tegra_pmc_scratch_readl(struct tegra_pmc *pmc, unsigned long offset)
493{
494 if (pmc->tz_only)
495 return tegra_pmc_readl(pmc, offset);
496
497 return readl(pmc->scratch + offset);
498}
499
500static void tegra_pmc_scratch_writel(struct tegra_pmc *pmc, u32 value,
501 unsigned long offset)
502{
503 if (pmc->tz_only)
504 tegra_pmc_writel(pmc, value, offset);
505 else
506 writel(value, pmc->scratch + offset);
507}
508
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513
514static inline bool tegra_powergate_state(int id)
515{
516 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps)
517 return (tegra_pmc_readl(pmc, GPU_RG_CNTRL) & 0x1) == 0;
518 else
519 return (tegra_pmc_readl(pmc, PWRGATE_STATUS) & BIT(id)) != 0;
520}
521
522static inline bool tegra_powergate_is_valid(struct tegra_pmc *pmc, int id)
523{
524 return (pmc->soc && pmc->soc->powergates[id]);
525}
526
527static inline bool tegra_powergate_is_available(struct tegra_pmc *pmc, int id)
528{
529 return test_bit(id, pmc->powergates_available);
530}
531
532static int tegra_powergate_lookup(struct tegra_pmc *pmc, const char *name)
533{
534 unsigned int i;
535
536 if (!pmc || !pmc->soc || !name)
537 return -EINVAL;
538
539 for (i = 0; i < pmc->soc->num_powergates; i++) {
540 if (!tegra_powergate_is_valid(pmc, i))
541 continue;
542
543 if (!strcmp(name, pmc->soc->powergates[i]))
544 return i;
545 }
546
547 return -ENODEV;
548}
549
550static int tegra20_powergate_set(struct tegra_pmc *pmc, unsigned int id,
551 bool new_state)
552{
553 unsigned int retries = 100;
554 bool status;
555 int ret;
556
557
558
559
560
561
562 do {
563 tegra_pmc_writel(pmc, PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);
564
565
566 ret = readx_poll_timeout(tegra_powergate_state, id, status,
567 status == new_state, 1, 10);
568 } while (ret == -ETIMEDOUT && retries--);
569
570 return ret;
571}
572
573static inline bool tegra_powergate_toggle_ready(struct tegra_pmc *pmc)
574{
575 return !(tegra_pmc_readl(pmc, PWRGATE_TOGGLE) & PWRGATE_TOGGLE_START);
576}
577
578static int tegra114_powergate_set(struct tegra_pmc *pmc, unsigned int id,
579 bool new_state)
580{
581 bool status;
582 int err;
583
584
585 err = readx_poll_timeout(tegra_powergate_toggle_ready, pmc, status,
586 status == true, 1, 100);
587 if (err)
588 return err;
589
590 tegra_pmc_writel(pmc, PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);
591
592
593 err = readx_poll_timeout(tegra_powergate_toggle_ready, pmc, status,
594 status == true, 1, 100);
595 if (err)
596 return err;
597
598
599 err = readx_poll_timeout(tegra_powergate_state, id, status,
600 status == new_state, 10, 100000);
601 if (err)
602 return err;
603
604 return 0;
605}
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610
611
612
613static int tegra_powergate_set(struct tegra_pmc *pmc, unsigned int id,
614 bool new_state)
615{
616 int err;
617
618 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps)
619 return -EINVAL;
620
621 mutex_lock(&pmc->powergates_lock);
622
623 if (tegra_powergate_state(id) == new_state) {
624 mutex_unlock(&pmc->powergates_lock);
625 return 0;
626 }
627
628 err = pmc->soc->powergate_set(pmc, id, new_state);
629
630 mutex_unlock(&pmc->powergates_lock);
631
632 return err;
633}
634
635static int __tegra_powergate_remove_clamping(struct tegra_pmc *pmc,
636 unsigned int id)
637{
638 u32 mask;
639
640 mutex_lock(&pmc->powergates_lock);
641
642
643
644
645
646 if (id == TEGRA_POWERGATE_3D) {
647 if (pmc->soc->has_gpu_clamps) {
648 tegra_pmc_writel(pmc, 0, GPU_RG_CNTRL);
649 goto out;
650 }
651 }
652
653
654
655
656
657 if (id == TEGRA_POWERGATE_VDEC)
658 mask = (1 << TEGRA_POWERGATE_PCIE);
659 else if (id == TEGRA_POWERGATE_PCIE)
660 mask = (1 << TEGRA_POWERGATE_VDEC);
661 else
662 mask = (1 << id);
663
664 tegra_pmc_writel(pmc, mask, REMOVE_CLAMPING);
665
666out:
667 mutex_unlock(&pmc->powergates_lock);
668
669 return 0;
670}
671
672static int tegra_powergate_prepare_clocks(struct tegra_powergate *pg)
673{
674 unsigned long safe_rate = 100 * 1000 * 1000;
675 unsigned int i;
676 int err;
677
678 for (i = 0; i < pg->num_clks; i++) {
679 pg->clk_rates[i] = clk_get_rate(pg->clks[i]);
680
681 if (!pg->clk_rates[i]) {
682 err = -EINVAL;
683 goto out;
684 }
685
686 if (pg->clk_rates[i] <= safe_rate)
687 continue;
688
689
690
691
692
693
694
695 err = clk_set_rate(pg->clks[i], safe_rate);
696 if (err)
697 goto out;
698 }
699
700 return 0;
701
702out:
703 while (i--)
704 clk_set_rate(pg->clks[i], pg->clk_rates[i]);
705
706 return err;
707}
708
709static int tegra_powergate_unprepare_clocks(struct tegra_powergate *pg)
710{
711 unsigned int i;
712 int err;
713
714 for (i = 0; i < pg->num_clks; i++) {
715 err = clk_set_rate(pg->clks[i], pg->clk_rates[i]);
716 if (err)
717 return err;
718 }
719
720 return 0;
721}
722
723static void tegra_powergate_disable_clocks(struct tegra_powergate *pg)
724{
725 unsigned int i;
726
727 for (i = 0; i < pg->num_clks; i++)
728 clk_disable_unprepare(pg->clks[i]);
729}
730
731static int tegra_powergate_enable_clocks(struct tegra_powergate *pg)
732{
733 unsigned int i;
734 int err;
735
736 for (i = 0; i < pg->num_clks; i++) {
737 err = clk_prepare_enable(pg->clks[i]);
738 if (err)
739 goto out;
740 }
741
742 return 0;
743
744out:
745 while (i--)
746 clk_disable_unprepare(pg->clks[i]);
747
748 return err;
749}
750
751static int tegra_powergate_power_up(struct tegra_powergate *pg,
752 bool disable_clocks)
753{
754 int err;
755
756 err = reset_control_assert(pg->reset);
757 if (err)
758 return err;
759
760 usleep_range(10, 20);
761
762 err = tegra_powergate_set(pg->pmc, pg->id, true);
763 if (err < 0)
764 return err;
765
766 usleep_range(10, 20);
767
768 err = tegra_powergate_prepare_clocks(pg);
769 if (err)
770 goto powergate_off;
771
772 err = tegra_powergate_enable_clocks(pg);
773 if (err)
774 goto unprepare_clks;
775
776 usleep_range(10, 20);
777
778 err = __tegra_powergate_remove_clamping(pg->pmc, pg->id);
779 if (err)
780 goto disable_clks;
781
782 usleep_range(10, 20);
783
784 err = reset_control_deassert(pg->reset);
785 if (err)
786 goto disable_clks;
787
788 usleep_range(10, 20);
789
790 if (pg->pmc->soc->needs_mbist_war)
791 err = tegra210_clk_handle_mbist_war(pg->id);
792 if (err)
793 goto disable_clks;
794
795 if (disable_clocks)
796 tegra_powergate_disable_clocks(pg);
797
798 err = tegra_powergate_unprepare_clocks(pg);
799 if (err)
800 return err;
801
802 return 0;
803
804disable_clks:
805 tegra_powergate_disable_clocks(pg);
806 usleep_range(10, 20);
807
808unprepare_clks:
809 tegra_powergate_unprepare_clocks(pg);
810
811powergate_off:
812 tegra_powergate_set(pg->pmc, pg->id, false);
813
814 return err;
815}
816
817static int tegra_powergate_power_down(struct tegra_powergate *pg)
818{
819 int err;
820
821 err = tegra_powergate_prepare_clocks(pg);
822 if (err)
823 return err;
824
825 err = tegra_powergate_enable_clocks(pg);
826 if (err)
827 goto unprepare_clks;
828
829 usleep_range(10, 20);
830
831 err = reset_control_assert(pg->reset);
832 if (err)
833 goto disable_clks;
834
835 usleep_range(10, 20);
836
837 tegra_powergate_disable_clocks(pg);
838
839 usleep_range(10, 20);
840
841 err = tegra_powergate_set(pg->pmc, pg->id, false);
842 if (err)
843 goto assert_resets;
844
845 err = tegra_powergate_unprepare_clocks(pg);
846 if (err)
847 return err;
848
849 return 0;
850
851assert_resets:
852 tegra_powergate_enable_clocks(pg);
853 usleep_range(10, 20);
854 reset_control_deassert(pg->reset);
855 usleep_range(10, 20);
856
857disable_clks:
858 tegra_powergate_disable_clocks(pg);
859
860unprepare_clks:
861 tegra_powergate_unprepare_clocks(pg);
862
863 return err;
864}
865
866static int tegra_genpd_power_on(struct generic_pm_domain *domain)
867{
868 struct tegra_powergate *pg = to_powergate(domain);
869 struct device *dev = pg->pmc->dev;
870 int err;
871
872 err = tegra_powergate_power_up(pg, true);
873 if (err) {
874 dev_err(dev, "failed to turn on PM domain %s: %d\n",
875 pg->genpd.name, err);
876 goto out;
877 }
878
879 reset_control_release(pg->reset);
880
881out:
882 return err;
883}
884
885static int tegra_genpd_power_off(struct generic_pm_domain *domain)
886{
887 struct tegra_powergate *pg = to_powergate(domain);
888 struct device *dev = pg->pmc->dev;
889 int err;
890
891 err = reset_control_acquire(pg->reset);
892 if (err < 0) {
893 dev_err(dev, "failed to acquire resets for PM domain %s: %d\n",
894 pg->genpd.name, err);
895 return err;
896 }
897
898 err = tegra_powergate_power_down(pg);
899 if (err) {
900 dev_err(dev, "failed to turn off PM domain %s: %d\n",
901 pg->genpd.name, err);
902 reset_control_release(pg->reset);
903 }
904
905 return err;
906}
907
908
909
910
911
912int tegra_powergate_power_on(unsigned int id)
913{
914 if (!tegra_powergate_is_available(pmc, id))
915 return -EINVAL;
916
917 return tegra_powergate_set(pmc, id, true);
918}
919EXPORT_SYMBOL(tegra_powergate_power_on);
920
921
922
923
924
925int tegra_powergate_power_off(unsigned int id)
926{
927 if (!tegra_powergate_is_available(pmc, id))
928 return -EINVAL;
929
930 return tegra_powergate_set(pmc, id, false);
931}
932EXPORT_SYMBOL(tegra_powergate_power_off);
933
934
935
936
937
938
939static int tegra_powergate_is_powered(struct tegra_pmc *pmc, unsigned int id)
940{
941 if (!tegra_powergate_is_valid(pmc, id))
942 return -EINVAL;
943
944 return tegra_powergate_state(id);
945}
946
947
948
949
950
951int tegra_powergate_remove_clamping(unsigned int id)
952{
953 if (!tegra_powergate_is_available(pmc, id))
954 return -EINVAL;
955
956 return __tegra_powergate_remove_clamping(pmc, id);
957}
958EXPORT_SYMBOL(tegra_powergate_remove_clamping);
959
960
961
962
963
964
965
966
967
968int tegra_powergate_sequence_power_up(unsigned int id, struct clk *clk,
969 struct reset_control *rst)
970{
971 struct tegra_powergate *pg;
972 int err;
973
974 if (!tegra_powergate_is_available(pmc, id))
975 return -EINVAL;
976
977 pg = kzalloc(sizeof(*pg), GFP_KERNEL);
978 if (!pg)
979 return -ENOMEM;
980
981 pg->clk_rates = kzalloc(sizeof(*pg->clk_rates), GFP_KERNEL);
982 if (!pg->clk_rates) {
983 kfree(pg->clks);
984 return -ENOMEM;
985 }
986
987 pg->id = id;
988 pg->clks = &clk;
989 pg->num_clks = 1;
990 pg->reset = rst;
991 pg->pmc = pmc;
992
993 err = tegra_powergate_power_up(pg, false);
994 if (err)
995 dev_err(pmc->dev, "failed to turn on partition %d: %d\n", id,
996 err);
997
998 kfree(pg->clk_rates);
999 kfree(pg);
1000
1001 return err;
1002}
1003EXPORT_SYMBOL(tegra_powergate_sequence_power_up);
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013static int tegra_get_cpu_powergate_id(struct tegra_pmc *pmc,
1014 unsigned int cpuid)
1015{
1016 if (pmc->soc && cpuid < pmc->soc->num_cpu_powergates)
1017 return pmc->soc->cpu_powergates[cpuid];
1018
1019 return -EINVAL;
1020}
1021
1022
1023
1024
1025
1026bool tegra_pmc_cpu_is_powered(unsigned int cpuid)
1027{
1028 int id;
1029
1030 id = tegra_get_cpu_powergate_id(pmc, cpuid);
1031 if (id < 0)
1032 return false;
1033
1034 return tegra_powergate_is_powered(pmc, id);
1035}
1036
1037
1038
1039
1040
1041int tegra_pmc_cpu_power_on(unsigned int cpuid)
1042{
1043 int id;
1044
1045 id = tegra_get_cpu_powergate_id(pmc, cpuid);
1046 if (id < 0)
1047 return id;
1048
1049 return tegra_powergate_set(pmc, id, true);
1050}
1051
1052
1053
1054
1055
1056int tegra_pmc_cpu_remove_clamping(unsigned int cpuid)
1057{
1058 int id;
1059
1060 id = tegra_get_cpu_powergate_id(pmc, cpuid);
1061 if (id < 0)
1062 return id;
1063
1064 return tegra_powergate_remove_clamping(id);
1065}
1066
1067static void tegra_pmc_program_reboot_reason(const char *cmd)
1068{
1069 u32 value;
1070
1071 value = tegra_pmc_scratch_readl(pmc, pmc->soc->regs->scratch0);
1072 value &= ~PMC_SCRATCH0_MODE_MASK;
1073
1074 if (cmd) {
1075 if (strcmp(cmd, "recovery") == 0)
1076 value |= PMC_SCRATCH0_MODE_RECOVERY;
1077
1078 if (strcmp(cmd, "bootloader") == 0)
1079 value |= PMC_SCRATCH0_MODE_BOOTLOADER;
1080
1081 if (strcmp(cmd, "forced-recovery") == 0)
1082 value |= PMC_SCRATCH0_MODE_RCM;
1083 }
1084
1085 tegra_pmc_scratch_writel(pmc, value, pmc->soc->regs->scratch0);
1086}
1087
1088static int tegra_pmc_reboot_notify(struct notifier_block *this,
1089 unsigned long action, void *data)
1090{
1091 if (action == SYS_RESTART)
1092 tegra_pmc_program_reboot_reason(data);
1093
1094 return NOTIFY_DONE;
1095}
1096
1097static struct notifier_block tegra_pmc_reboot_notifier = {
1098 .notifier_call = tegra_pmc_reboot_notify,
1099};
1100
1101static int tegra_pmc_restart_notify(struct notifier_block *this,
1102 unsigned long action, void *data)
1103{
1104 u32 value;
1105
1106
1107 value = tegra_pmc_readl(pmc, PMC_CNTRL);
1108 value |= PMC_CNTRL_MAIN_RST;
1109 tegra_pmc_writel(pmc, value, PMC_CNTRL);
1110
1111 return NOTIFY_DONE;
1112}
1113
1114static struct notifier_block tegra_pmc_restart_handler = {
1115 .notifier_call = tegra_pmc_restart_notify,
1116 .priority = 128,
1117};
1118
1119static int powergate_show(struct seq_file *s, void *data)
1120{
1121 unsigned int i;
1122 int status;
1123
1124 seq_printf(s, " powergate powered\n");
1125 seq_printf(s, "------------------\n");
1126
1127 for (i = 0; i < pmc->soc->num_powergates; i++) {
1128 status = tegra_powergate_is_powered(pmc, i);
1129 if (status < 0)
1130 continue;
1131
1132 seq_printf(s, " %9s %7s\n", pmc->soc->powergates[i],
1133 status ? "yes" : "no");
1134 }
1135
1136 return 0;
1137}
1138
1139DEFINE_SHOW_ATTRIBUTE(powergate);
1140
1141static int tegra_powergate_debugfs_init(void)
1142{
1143 pmc->debugfs = debugfs_create_file("powergate", S_IRUGO, NULL, NULL,
1144 &powergate_fops);
1145 if (!pmc->debugfs)
1146 return -ENOMEM;
1147
1148 return 0;
1149}
1150
1151static int tegra_powergate_of_get_clks(struct tegra_powergate *pg,
1152 struct device_node *np)
1153{
1154 struct clk *clk;
1155 unsigned int i, count;
1156 int err;
1157
1158 count = of_clk_get_parent_count(np);
1159 if (count == 0)
1160 return -ENODEV;
1161
1162 pg->clks = kcalloc(count, sizeof(clk), GFP_KERNEL);
1163 if (!pg->clks)
1164 return -ENOMEM;
1165
1166 pg->clk_rates = kcalloc(count, sizeof(*pg->clk_rates), GFP_KERNEL);
1167 if (!pg->clk_rates) {
1168 kfree(pg->clks);
1169 return -ENOMEM;
1170 }
1171
1172 for (i = 0; i < count; i++) {
1173 pg->clks[i] = of_clk_get(np, i);
1174 if (IS_ERR(pg->clks[i])) {
1175 err = PTR_ERR(pg->clks[i]);
1176 goto err;
1177 }
1178 }
1179
1180 pg->num_clks = count;
1181
1182 return 0;
1183
1184err:
1185 while (i--)
1186 clk_put(pg->clks[i]);
1187
1188 kfree(pg->clk_rates);
1189 kfree(pg->clks);
1190
1191 return err;
1192}
1193
1194static int tegra_powergate_of_get_resets(struct tegra_powergate *pg,
1195 struct device_node *np, bool off)
1196{
1197 struct device *dev = pg->pmc->dev;
1198 int err;
1199
1200 pg->reset = of_reset_control_array_get_exclusive_released(np);
1201 if (IS_ERR(pg->reset)) {
1202 err = PTR_ERR(pg->reset);
1203 dev_err(dev, "failed to get device resets: %d\n", err);
1204 return err;
1205 }
1206
1207 err = reset_control_acquire(pg->reset);
1208 if (err < 0) {
1209 pr_err("failed to acquire resets: %d\n", err);
1210 goto out;
1211 }
1212
1213 if (off) {
1214 err = reset_control_assert(pg->reset);
1215 } else {
1216 err = reset_control_deassert(pg->reset);
1217 if (err < 0)
1218 goto out;
1219
1220 reset_control_release(pg->reset);
1221 }
1222
1223out:
1224 if (err) {
1225 reset_control_release(pg->reset);
1226 reset_control_put(pg->reset);
1227 }
1228
1229 return err;
1230}
1231
1232static int tegra_powergate_add(struct tegra_pmc *pmc, struct device_node *np)
1233{
1234 struct device *dev = pmc->dev;
1235 struct tegra_powergate *pg;
1236 int id, err = 0;
1237 bool off;
1238
1239 pg = kzalloc(sizeof(*pg), GFP_KERNEL);
1240 if (!pg)
1241 return -ENOMEM;
1242
1243 id = tegra_powergate_lookup(pmc, np->name);
1244 if (id < 0) {
1245 dev_err(dev, "powergate lookup failed for %pOFn: %d\n", np, id);
1246 err = -ENODEV;
1247 goto free_mem;
1248 }
1249
1250
1251
1252
1253
1254 clear_bit(id, pmc->powergates_available);
1255
1256 pg->id = id;
1257 pg->genpd.name = np->name;
1258 pg->genpd.power_off = tegra_genpd_power_off;
1259 pg->genpd.power_on = tegra_genpd_power_on;
1260 pg->pmc = pmc;
1261
1262 off = !tegra_powergate_is_powered(pmc, pg->id);
1263
1264 err = tegra_powergate_of_get_clks(pg, np);
1265 if (err < 0) {
1266 dev_err(dev, "failed to get clocks for %pOFn: %d\n", np, err);
1267 goto set_available;
1268 }
1269
1270 err = tegra_powergate_of_get_resets(pg, np, off);
1271 if (err < 0) {
1272 dev_err(dev, "failed to get resets for %pOFn: %d\n", np, err);
1273 goto remove_clks;
1274 }
1275
1276 if (!IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS)) {
1277 if (off)
1278 WARN_ON(tegra_powergate_power_up(pg, true));
1279
1280 goto remove_resets;
1281 }
1282
1283 err = pm_genpd_init(&pg->genpd, NULL, off);
1284 if (err < 0) {
1285 dev_err(dev, "failed to initialise PM domain %pOFn: %d\n", np,
1286 err);
1287 goto remove_resets;
1288 }
1289
1290 err = of_genpd_add_provider_simple(np, &pg->genpd);
1291 if (err < 0) {
1292 dev_err(dev, "failed to add PM domain provider for %pOFn: %d\n",
1293 np, err);
1294 goto remove_genpd;
1295 }
1296
1297 dev_dbg(dev, "added PM domain %s\n", pg->genpd.name);
1298
1299 return 0;
1300
1301remove_genpd:
1302 pm_genpd_remove(&pg->genpd);
1303
1304remove_resets:
1305 reset_control_put(pg->reset);
1306
1307remove_clks:
1308 while (pg->num_clks--)
1309 clk_put(pg->clks[pg->num_clks]);
1310
1311 kfree(pg->clks);
1312
1313set_available:
1314 set_bit(id, pmc->powergates_available);
1315
1316free_mem:
1317 kfree(pg);
1318
1319 return err;
1320}
1321
1322bool tegra_pmc_core_domain_state_synced(void)
1323{
1324 return pmc->core_domain_state_synced;
1325}
1326
1327static int
1328tegra_pmc_core_pd_set_performance_state(struct generic_pm_domain *genpd,
1329 unsigned int level)
1330{
1331 struct dev_pm_opp *opp;
1332 int err;
1333
1334 opp = dev_pm_opp_find_level_ceil(&genpd->dev, &level);
1335 if (IS_ERR(opp)) {
1336 dev_err(&genpd->dev, "failed to find OPP for level %u: %pe\n",
1337 level, opp);
1338 return PTR_ERR(opp);
1339 }
1340
1341 mutex_lock(&pmc->powergates_lock);
1342 err = dev_pm_opp_set_opp(pmc->dev, opp);
1343 mutex_unlock(&pmc->powergates_lock);
1344
1345 dev_pm_opp_put(opp);
1346
1347 if (err) {
1348 dev_err(&genpd->dev, "failed to set voltage to %duV: %d\n",
1349 level, err);
1350 return err;
1351 }
1352
1353 return 0;
1354}
1355
1356static unsigned int
1357tegra_pmc_core_pd_opp_to_performance_state(struct generic_pm_domain *genpd,
1358 struct dev_pm_opp *opp)
1359{
1360 return dev_pm_opp_get_level(opp);
1361}
1362
1363static int tegra_pmc_core_pd_add(struct tegra_pmc *pmc, struct device_node *np)
1364{
1365 struct generic_pm_domain *genpd;
1366 const char *rname = "core";
1367 int err;
1368
1369 genpd = devm_kzalloc(pmc->dev, sizeof(*genpd), GFP_KERNEL);
1370 if (!genpd)
1371 return -ENOMEM;
1372
1373 genpd->name = "core";
1374 genpd->set_performance_state = tegra_pmc_core_pd_set_performance_state;
1375 genpd->opp_to_performance_state = tegra_pmc_core_pd_opp_to_performance_state;
1376
1377 err = devm_pm_opp_set_regulators(pmc->dev, &rname, 1);
1378 if (err)
1379 return dev_err_probe(pmc->dev, err,
1380 "failed to set core OPP regulator\n");
1381
1382 err = pm_genpd_init(genpd, NULL, false);
1383 if (err) {
1384 dev_err(pmc->dev, "failed to init core genpd: %d\n", err);
1385 return err;
1386 }
1387
1388 err = of_genpd_add_provider_simple(np, genpd);
1389 if (err) {
1390 dev_err(pmc->dev, "failed to add core genpd: %d\n", err);
1391 goto remove_genpd;
1392 }
1393
1394 pmc->core_domain_registered = true;
1395
1396 return 0;
1397
1398remove_genpd:
1399 pm_genpd_remove(genpd);
1400
1401 return err;
1402}
1403
1404static int tegra_powergate_init(struct tegra_pmc *pmc,
1405 struct device_node *parent)
1406{
1407 struct of_phandle_args child_args, parent_args;
1408 struct device_node *np, *child;
1409 int err = 0;
1410
1411
1412
1413
1414
1415 np = of_get_child_by_name(parent, "core-domain");
1416 if (np) {
1417 err = tegra_pmc_core_pd_add(pmc, np);
1418 of_node_put(np);
1419 if (err)
1420 return err;
1421 }
1422
1423 np = of_get_child_by_name(parent, "powergates");
1424 if (!np)
1425 return 0;
1426
1427 for_each_child_of_node(np, child) {
1428 err = tegra_powergate_add(pmc, child);
1429 if (err < 0) {
1430 of_node_put(child);
1431 break;
1432 }
1433
1434 if (of_parse_phandle_with_args(child, "power-domains",
1435 "#power-domain-cells",
1436 0, &parent_args))
1437 continue;
1438
1439 child_args.np = child;
1440 child_args.args_count = 0;
1441
1442 err = of_genpd_add_subdomain(&parent_args, &child_args);
1443 of_node_put(parent_args.np);
1444 if (err) {
1445 of_node_put(child);
1446 break;
1447 }
1448 }
1449
1450 of_node_put(np);
1451
1452 return err;
1453}
1454
1455static void tegra_powergate_remove(struct generic_pm_domain *genpd)
1456{
1457 struct tegra_powergate *pg = to_powergate(genpd);
1458
1459 reset_control_put(pg->reset);
1460
1461 while (pg->num_clks--)
1462 clk_put(pg->clks[pg->num_clks]);
1463
1464 kfree(pg->clks);
1465
1466 set_bit(pg->id, pmc->powergates_available);
1467
1468 kfree(pg);
1469}
1470
1471static void tegra_powergate_remove_all(struct device_node *parent)
1472{
1473 struct generic_pm_domain *genpd;
1474 struct device_node *np, *child;
1475
1476 np = of_get_child_by_name(parent, "powergates");
1477 if (!np)
1478 return;
1479
1480 for_each_child_of_node(np, child) {
1481 of_genpd_del_provider(child);
1482
1483 genpd = of_genpd_remove_last(child);
1484 if (IS_ERR(genpd))
1485 continue;
1486
1487 tegra_powergate_remove(genpd);
1488 }
1489
1490 of_node_put(np);
1491
1492 np = of_get_child_by_name(parent, "core-domain");
1493 if (np) {
1494 of_genpd_del_provider(np);
1495 of_genpd_remove_last(np);
1496 }
1497}
1498
1499static const struct tegra_io_pad_soc *
1500tegra_io_pad_find(struct tegra_pmc *pmc, enum tegra_io_pad id)
1501{
1502 unsigned int i;
1503
1504 for (i = 0; i < pmc->soc->num_io_pads; i++)
1505 if (pmc->soc->io_pads[i].id == id)
1506 return &pmc->soc->io_pads[i];
1507
1508 return NULL;
1509}
1510
1511static int tegra_io_pad_get_dpd_register_bit(struct tegra_pmc *pmc,
1512 enum tegra_io_pad id,
1513 unsigned long *request,
1514 unsigned long *status,
1515 u32 *mask)
1516{
1517 const struct tegra_io_pad_soc *pad;
1518
1519 pad = tegra_io_pad_find(pmc, id);
1520 if (!pad) {
1521 dev_err(pmc->dev, "invalid I/O pad ID %u\n", id);
1522 return -ENOENT;
1523 }
1524
1525 if (pad->dpd == UINT_MAX)
1526 return -ENOTSUPP;
1527
1528 *mask = BIT(pad->dpd % 32);
1529
1530 if (pad->dpd < 32) {
1531 *status = pmc->soc->regs->dpd_status;
1532 *request = pmc->soc->regs->dpd_req;
1533 } else {
1534 *status = pmc->soc->regs->dpd2_status;
1535 *request = pmc->soc->regs->dpd2_req;
1536 }
1537
1538 return 0;
1539}
1540
1541static int tegra_io_pad_prepare(struct tegra_pmc *pmc, enum tegra_io_pad id,
1542 unsigned long *request, unsigned long *status,
1543 u32 *mask)
1544{
1545 unsigned long rate, value;
1546 int err;
1547
1548 err = tegra_io_pad_get_dpd_register_bit(pmc, id, request, status, mask);
1549 if (err)
1550 return err;
1551
1552 if (pmc->clk) {
1553 rate = pmc->rate;
1554 if (!rate) {
1555 dev_err(pmc->dev, "failed to get clock rate\n");
1556 return -ENODEV;
1557 }
1558
1559 tegra_pmc_writel(pmc, DPD_SAMPLE_ENABLE, DPD_SAMPLE);
1560
1561
1562 value = DIV_ROUND_UP(1000000000, rate);
1563 value = DIV_ROUND_UP(200, value);
1564 tegra_pmc_writel(pmc, value, SEL_DPD_TIM);
1565 }
1566
1567 return 0;
1568}
1569
1570static int tegra_io_pad_poll(struct tegra_pmc *pmc, unsigned long offset,
1571 u32 mask, u32 val, unsigned long timeout)
1572{
1573 u32 value;
1574
1575 timeout = jiffies + msecs_to_jiffies(timeout);
1576
1577 while (time_after(timeout, jiffies)) {
1578 value = tegra_pmc_readl(pmc, offset);
1579 if ((value & mask) == val)
1580 return 0;
1581
1582 usleep_range(250, 1000);
1583 }
1584
1585 return -ETIMEDOUT;
1586}
1587
1588static void tegra_io_pad_unprepare(struct tegra_pmc *pmc)
1589{
1590 if (pmc->clk)
1591 tegra_pmc_writel(pmc, DPD_SAMPLE_DISABLE, DPD_SAMPLE);
1592}
1593
1594
1595
1596
1597
1598
1599
1600int tegra_io_pad_power_enable(enum tegra_io_pad id)
1601{
1602 unsigned long request, status;
1603 u32 mask;
1604 int err;
1605
1606 mutex_lock(&pmc->powergates_lock);
1607
1608 err = tegra_io_pad_prepare(pmc, id, &request, &status, &mask);
1609 if (err < 0) {
1610 dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err);
1611 goto unlock;
1612 }
1613
1614 tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_OFF | mask, request);
1615
1616 err = tegra_io_pad_poll(pmc, status, mask, 0, 250);
1617 if (err < 0) {
1618 dev_err(pmc->dev, "failed to enable I/O pad: %d\n", err);
1619 goto unlock;
1620 }
1621
1622 tegra_io_pad_unprepare(pmc);
1623
1624unlock:
1625 mutex_unlock(&pmc->powergates_lock);
1626 return err;
1627}
1628EXPORT_SYMBOL(tegra_io_pad_power_enable);
1629
1630
1631
1632
1633
1634
1635
1636int tegra_io_pad_power_disable(enum tegra_io_pad id)
1637{
1638 unsigned long request, status;
1639 u32 mask;
1640 int err;
1641
1642 mutex_lock(&pmc->powergates_lock);
1643
1644 err = tegra_io_pad_prepare(pmc, id, &request, &status, &mask);
1645 if (err < 0) {
1646 dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err);
1647 goto unlock;
1648 }
1649
1650 tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_ON | mask, request);
1651
1652 err = tegra_io_pad_poll(pmc, status, mask, mask, 250);
1653 if (err < 0) {
1654 dev_err(pmc->dev, "failed to disable I/O pad: %d\n", err);
1655 goto unlock;
1656 }
1657
1658 tegra_io_pad_unprepare(pmc);
1659
1660unlock:
1661 mutex_unlock(&pmc->powergates_lock);
1662 return err;
1663}
1664EXPORT_SYMBOL(tegra_io_pad_power_disable);
1665
1666static int tegra_io_pad_is_powered(struct tegra_pmc *pmc, enum tegra_io_pad id)
1667{
1668 unsigned long request, status;
1669 u32 mask, value;
1670 int err;
1671
1672 err = tegra_io_pad_get_dpd_register_bit(pmc, id, &request, &status,
1673 &mask);
1674 if (err)
1675 return err;
1676
1677 value = tegra_pmc_readl(pmc, status);
1678
1679 return !(value & mask);
1680}
1681
1682static int tegra_io_pad_set_voltage(struct tegra_pmc *pmc, enum tegra_io_pad id,
1683 int voltage)
1684{
1685 const struct tegra_io_pad_soc *pad;
1686 u32 value;
1687
1688 pad = tegra_io_pad_find(pmc, id);
1689 if (!pad)
1690 return -ENOENT;
1691
1692 if (pad->voltage == UINT_MAX)
1693 return -ENOTSUPP;
1694
1695 mutex_lock(&pmc->powergates_lock);
1696
1697 if (pmc->soc->has_impl_33v_pwr) {
1698 value = tegra_pmc_readl(pmc, PMC_IMPL_E_33V_PWR);
1699
1700 if (voltage == TEGRA_IO_PAD_VOLTAGE_1V8)
1701 value &= ~BIT(pad->voltage);
1702 else
1703 value |= BIT(pad->voltage);
1704
1705 tegra_pmc_writel(pmc, value, PMC_IMPL_E_33V_PWR);
1706 } else {
1707
1708 value = tegra_pmc_readl(pmc, PMC_PWR_DET);
1709 value |= BIT(pad->voltage);
1710 tegra_pmc_writel(pmc, value, PMC_PWR_DET);
1711
1712
1713 value = tegra_pmc_readl(pmc, PMC_PWR_DET_VALUE);
1714
1715 if (voltage == TEGRA_IO_PAD_VOLTAGE_1V8)
1716 value &= ~BIT(pad->voltage);
1717 else
1718 value |= BIT(pad->voltage);
1719
1720 tegra_pmc_writel(pmc, value, PMC_PWR_DET_VALUE);
1721 }
1722
1723 mutex_unlock(&pmc->powergates_lock);
1724
1725 usleep_range(100, 250);
1726
1727 return 0;
1728}
1729
1730static int tegra_io_pad_get_voltage(struct tegra_pmc *pmc, enum tegra_io_pad id)
1731{
1732 const struct tegra_io_pad_soc *pad;
1733 u32 value;
1734
1735 pad = tegra_io_pad_find(pmc, id);
1736 if (!pad)
1737 return -ENOENT;
1738
1739 if (pad->voltage == UINT_MAX)
1740 return -ENOTSUPP;
1741
1742 if (pmc->soc->has_impl_33v_pwr)
1743 value = tegra_pmc_readl(pmc, PMC_IMPL_E_33V_PWR);
1744 else
1745 value = tegra_pmc_readl(pmc, PMC_PWR_DET_VALUE);
1746
1747 if ((value & BIT(pad->voltage)) == 0)
1748 return TEGRA_IO_PAD_VOLTAGE_1V8;
1749
1750 return TEGRA_IO_PAD_VOLTAGE_3V3;
1751}
1752
1753
1754
1755
1756
1757
1758
1759int tegra_io_rail_power_on(unsigned int id)
1760{
1761 return tegra_io_pad_power_enable(id);
1762}
1763EXPORT_SYMBOL(tegra_io_rail_power_on);
1764
1765
1766
1767
1768
1769
1770
1771int tegra_io_rail_power_off(unsigned int id)
1772{
1773 return tegra_io_pad_power_disable(id);
1774}
1775EXPORT_SYMBOL(tegra_io_rail_power_off);
1776
1777#ifdef CONFIG_PM_SLEEP
1778enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void)
1779{
1780 return pmc->suspend_mode;
1781}
1782
1783void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode)
1784{
1785 if (mode < TEGRA_SUSPEND_NONE || mode >= TEGRA_MAX_SUSPEND_MODE)
1786 return;
1787
1788 pmc->suspend_mode = mode;
1789}
1790
1791void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode)
1792{
1793 unsigned long long rate = 0;
1794 u64 ticks;
1795 u32 value;
1796
1797 switch (mode) {
1798 case TEGRA_SUSPEND_LP1:
1799 rate = 32768;
1800 break;
1801
1802 case TEGRA_SUSPEND_LP2:
1803 rate = pmc->rate;
1804 break;
1805
1806 default:
1807 break;
1808 }
1809
1810 if (WARN_ON_ONCE(rate == 0))
1811 rate = 100000000;
1812
1813 ticks = pmc->cpu_good_time * rate + USEC_PER_SEC - 1;
1814 do_div(ticks, USEC_PER_SEC);
1815 tegra_pmc_writel(pmc, ticks, PMC_CPUPWRGOOD_TIMER);
1816
1817 ticks = pmc->cpu_off_time * rate + USEC_PER_SEC - 1;
1818 do_div(ticks, USEC_PER_SEC);
1819 tegra_pmc_writel(pmc, ticks, PMC_CPUPWROFF_TIMER);
1820
1821 value = tegra_pmc_readl(pmc, PMC_CNTRL);
1822 value &= ~PMC_CNTRL_SIDE_EFFECT_LP0;
1823 value |= PMC_CNTRL_CPU_PWRREQ_OE;
1824 tegra_pmc_writel(pmc, value, PMC_CNTRL);
1825}
1826#endif
1827
1828static int tegra_pmc_parse_dt(struct tegra_pmc *pmc, struct device_node *np)
1829{
1830 u32 value, values[2];
1831
1832 if (of_property_read_u32(np, "nvidia,suspend-mode", &value)) {
1833 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1834 } else {
1835 switch (value) {
1836 case 0:
1837 pmc->suspend_mode = TEGRA_SUSPEND_LP0;
1838 break;
1839
1840 case 1:
1841 pmc->suspend_mode = TEGRA_SUSPEND_LP1;
1842 break;
1843
1844 case 2:
1845 pmc->suspend_mode = TEGRA_SUSPEND_LP2;
1846 break;
1847
1848 default:
1849 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1850 break;
1851 }
1852 }
1853
1854 pmc->suspend_mode = tegra_pm_validate_suspend_mode(pmc->suspend_mode);
1855
1856 if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &value))
1857 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1858
1859 pmc->cpu_good_time = value;
1860
1861 if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &value))
1862 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1863
1864 pmc->cpu_off_time = value;
1865
1866 if (of_property_read_u32_array(np, "nvidia,core-pwr-good-time",
1867 values, ARRAY_SIZE(values)))
1868 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1869
1870 pmc->core_osc_time = values[0];
1871 pmc->core_pmu_time = values[1];
1872
1873 if (of_property_read_u32(np, "nvidia,core-pwr-off-time", &value))
1874 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1875
1876 pmc->core_off_time = value;
1877
1878 pmc->corereq_high = of_property_read_bool(np,
1879 "nvidia,core-power-req-active-high");
1880
1881 pmc->sysclkreq_high = of_property_read_bool(np,
1882 "nvidia,sys-clock-req-active-high");
1883
1884 pmc->combined_req = of_property_read_bool(np,
1885 "nvidia,combined-power-req");
1886
1887 pmc->cpu_pwr_good_en = of_property_read_bool(np,
1888 "nvidia,cpu-pwr-good-en");
1889
1890 if (of_property_read_u32_array(np, "nvidia,lp0-vec", values,
1891 ARRAY_SIZE(values)))
1892 if (pmc->suspend_mode == TEGRA_SUSPEND_LP0)
1893 pmc->suspend_mode = TEGRA_SUSPEND_LP1;
1894
1895 pmc->lp0_vec_phys = values[0];
1896 pmc->lp0_vec_size = values[1];
1897
1898 return 0;
1899}
1900
1901static void tegra_pmc_init(struct tegra_pmc *pmc)
1902{
1903 if (pmc->soc->init)
1904 pmc->soc->init(pmc);
1905}
1906
1907static void tegra_pmc_init_tsense_reset(struct tegra_pmc *pmc)
1908{
1909 static const char disabled[] = "emergency thermal reset disabled";
1910 u32 pmu_addr, ctrl_id, reg_addr, reg_data, pinmux;
1911 struct device *dev = pmc->dev;
1912 struct device_node *np;
1913 u32 value, checksum;
1914
1915 if (!pmc->soc->has_tsense_reset)
1916 return;
1917
1918 np = of_get_child_by_name(pmc->dev->of_node, "i2c-thermtrip");
1919 if (!np) {
1920 dev_warn(dev, "i2c-thermtrip node not found, %s.\n", disabled);
1921 return;
1922 }
1923
1924 if (of_property_read_u32(np, "nvidia,i2c-controller-id", &ctrl_id)) {
1925 dev_err(dev, "I2C controller ID missing, %s.\n", disabled);
1926 goto out;
1927 }
1928
1929 if (of_property_read_u32(np, "nvidia,bus-addr", &pmu_addr)) {
1930 dev_err(dev, "nvidia,bus-addr missing, %s.\n", disabled);
1931 goto out;
1932 }
1933
1934 if (of_property_read_u32(np, "nvidia,reg-addr", ®_addr)) {
1935 dev_err(dev, "nvidia,reg-addr missing, %s.\n", disabled);
1936 goto out;
1937 }
1938
1939 if (of_property_read_u32(np, "nvidia,reg-data", ®_data)) {
1940 dev_err(dev, "nvidia,reg-data missing, %s.\n", disabled);
1941 goto out;
1942 }
1943
1944 if (of_property_read_u32(np, "nvidia,pinmux-id", &pinmux))
1945 pinmux = 0;
1946
1947 value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL);
1948 value |= PMC_SENSOR_CTRL_SCRATCH_WRITE;
1949 tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL);
1950
1951 value = (reg_data << PMC_SCRATCH54_DATA_SHIFT) |
1952 (reg_addr << PMC_SCRATCH54_ADDR_SHIFT);
1953 tegra_pmc_writel(pmc, value, PMC_SCRATCH54);
1954
1955 value = PMC_SCRATCH55_RESET_TEGRA;
1956 value |= ctrl_id << PMC_SCRATCH55_CNTRL_ID_SHIFT;
1957 value |= pinmux << PMC_SCRATCH55_PINMUX_SHIFT;
1958 value |= pmu_addr << PMC_SCRATCH55_I2CSLV1_SHIFT;
1959
1960
1961
1962
1963
1964 checksum = reg_addr + reg_data + (value & 0xff) + ((value >> 8) & 0xff)
1965 + ((value >> 24) & 0xff);
1966 checksum &= 0xff;
1967 checksum = 0x100 - checksum;
1968
1969 value |= checksum << PMC_SCRATCH55_CHECKSUM_SHIFT;
1970
1971 tegra_pmc_writel(pmc, value, PMC_SCRATCH55);
1972
1973 value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL);
1974 value |= PMC_SENSOR_CTRL_ENABLE_RST;
1975 tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL);
1976
1977 dev_info(pmc->dev, "emergency thermal reset enabled\n");
1978
1979out:
1980 of_node_put(np);
1981}
1982
1983static int tegra_io_pad_pinctrl_get_groups_count(struct pinctrl_dev *pctl_dev)
1984{
1985 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);
1986
1987 return pmc->soc->num_io_pads;
1988}
1989
1990static const char *tegra_io_pad_pinctrl_get_group_name(struct pinctrl_dev *pctl,
1991 unsigned int group)
1992{
1993 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl);
1994
1995 return pmc->soc->io_pads[group].name;
1996}
1997
1998static int tegra_io_pad_pinctrl_get_group_pins(struct pinctrl_dev *pctl_dev,
1999 unsigned int group,
2000 const unsigned int **pins,
2001 unsigned int *num_pins)
2002{
2003 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);
2004
2005 *pins = &pmc->soc->io_pads[group].id;
2006 *num_pins = 1;
2007
2008 return 0;
2009}
2010
2011static const struct pinctrl_ops tegra_io_pad_pinctrl_ops = {
2012 .get_groups_count = tegra_io_pad_pinctrl_get_groups_count,
2013 .get_group_name = tegra_io_pad_pinctrl_get_group_name,
2014 .get_group_pins = tegra_io_pad_pinctrl_get_group_pins,
2015 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
2016 .dt_free_map = pinconf_generic_dt_free_map,
2017};
2018
2019static int tegra_io_pad_pinconf_get(struct pinctrl_dev *pctl_dev,
2020 unsigned int pin, unsigned long *config)
2021{
2022 enum pin_config_param param = pinconf_to_config_param(*config);
2023 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);
2024 const struct tegra_io_pad_soc *pad;
2025 int ret;
2026 u32 arg;
2027
2028 pad = tegra_io_pad_find(pmc, pin);
2029 if (!pad)
2030 return -EINVAL;
2031
2032 switch (param) {
2033 case PIN_CONFIG_POWER_SOURCE:
2034 ret = tegra_io_pad_get_voltage(pmc, pad->id);
2035 if (ret < 0)
2036 return ret;
2037
2038 arg = ret;
2039 break;
2040
2041 case PIN_CONFIG_MODE_LOW_POWER:
2042 ret = tegra_io_pad_is_powered(pmc, pad->id);
2043 if (ret < 0)
2044 return ret;
2045
2046 arg = !ret;
2047 break;
2048
2049 default:
2050 return -EINVAL;
2051 }
2052
2053 *config = pinconf_to_config_packed(param, arg);
2054
2055 return 0;
2056}
2057
2058static int tegra_io_pad_pinconf_set(struct pinctrl_dev *pctl_dev,
2059 unsigned int pin, unsigned long *configs,
2060 unsigned int num_configs)
2061{
2062 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);
2063 const struct tegra_io_pad_soc *pad;
2064 enum pin_config_param param;
2065 unsigned int i;
2066 int err;
2067 u32 arg;
2068
2069 pad = tegra_io_pad_find(pmc, pin);
2070 if (!pad)
2071 return -EINVAL;
2072
2073 for (i = 0; i < num_configs; ++i) {
2074 param = pinconf_to_config_param(configs[i]);
2075 arg = pinconf_to_config_argument(configs[i]);
2076
2077 switch (param) {
2078 case PIN_CONFIG_MODE_LOW_POWER:
2079 if (arg)
2080 err = tegra_io_pad_power_disable(pad->id);
2081 else
2082 err = tegra_io_pad_power_enable(pad->id);
2083 if (err)
2084 return err;
2085 break;
2086 case PIN_CONFIG_POWER_SOURCE:
2087 if (arg != TEGRA_IO_PAD_VOLTAGE_1V8 &&
2088 arg != TEGRA_IO_PAD_VOLTAGE_3V3)
2089 return -EINVAL;
2090 err = tegra_io_pad_set_voltage(pmc, pad->id, arg);
2091 if (err)
2092 return err;
2093 break;
2094 default:
2095 return -EINVAL;
2096 }
2097 }
2098
2099 return 0;
2100}
2101
2102static const struct pinconf_ops tegra_io_pad_pinconf_ops = {
2103 .pin_config_get = tegra_io_pad_pinconf_get,
2104 .pin_config_set = tegra_io_pad_pinconf_set,
2105 .is_generic = true,
2106};
2107
2108static struct pinctrl_desc tegra_pmc_pctl_desc = {
2109 .pctlops = &tegra_io_pad_pinctrl_ops,
2110 .confops = &tegra_io_pad_pinconf_ops,
2111};
2112
2113static int tegra_pmc_pinctrl_init(struct tegra_pmc *pmc)
2114{
2115 int err;
2116
2117 if (!pmc->soc->num_pin_descs)
2118 return 0;
2119
2120 tegra_pmc_pctl_desc.name = dev_name(pmc->dev);
2121 tegra_pmc_pctl_desc.pins = pmc->soc->pin_descs;
2122 tegra_pmc_pctl_desc.npins = pmc->soc->num_pin_descs;
2123
2124 pmc->pctl_dev = devm_pinctrl_register(pmc->dev, &tegra_pmc_pctl_desc,
2125 pmc);
2126 if (IS_ERR(pmc->pctl_dev)) {
2127 err = PTR_ERR(pmc->pctl_dev);
2128 dev_err(pmc->dev, "failed to register pin controller: %d\n",
2129 err);
2130 return err;
2131 }
2132
2133 return 0;
2134}
2135
2136static ssize_t reset_reason_show(struct device *dev,
2137 struct device_attribute *attr, char *buf)
2138{
2139 u32 value;
2140
2141 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status);
2142 value &= pmc->soc->regs->rst_source_mask;
2143 value >>= pmc->soc->regs->rst_source_shift;
2144
2145 if (WARN_ON(value >= pmc->soc->num_reset_sources))
2146 return sprintf(buf, "%s\n", "UNKNOWN");
2147
2148 return sprintf(buf, "%s\n", pmc->soc->reset_sources[value]);
2149}
2150
2151static DEVICE_ATTR_RO(reset_reason);
2152
2153static ssize_t reset_level_show(struct device *dev,
2154 struct device_attribute *attr, char *buf)
2155{
2156 u32 value;
2157
2158 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status);
2159 value &= pmc->soc->regs->rst_level_mask;
2160 value >>= pmc->soc->regs->rst_level_shift;
2161
2162 if (WARN_ON(value >= pmc->soc->num_reset_levels))
2163 return sprintf(buf, "%s\n", "UNKNOWN");
2164
2165 return sprintf(buf, "%s\n", pmc->soc->reset_levels[value]);
2166}
2167
2168static DEVICE_ATTR_RO(reset_level);
2169
2170static void tegra_pmc_reset_sysfs_init(struct tegra_pmc *pmc)
2171{
2172 struct device *dev = pmc->dev;
2173 int err = 0;
2174
2175 if (pmc->soc->reset_sources) {
2176 err = device_create_file(dev, &dev_attr_reset_reason);
2177 if (err < 0)
2178 dev_warn(dev,
2179 "failed to create attr \"reset_reason\": %d\n",
2180 err);
2181 }
2182
2183 if (pmc->soc->reset_levels) {
2184 err = device_create_file(dev, &dev_attr_reset_level);
2185 if (err < 0)
2186 dev_warn(dev,
2187 "failed to create attr \"reset_level\": %d\n",
2188 err);
2189 }
2190}
2191
2192static int tegra_pmc_irq_translate(struct irq_domain *domain,
2193 struct irq_fwspec *fwspec,
2194 unsigned long *hwirq,
2195 unsigned int *type)
2196{
2197 if (WARN_ON(fwspec->param_count < 2))
2198 return -EINVAL;
2199
2200 *hwirq = fwspec->param[0];
2201 *type = fwspec->param[1];
2202
2203 return 0;
2204}
2205
2206static int tegra_pmc_irq_alloc(struct irq_domain *domain, unsigned int virq,
2207 unsigned int num_irqs, void *data)
2208{
2209 struct tegra_pmc *pmc = domain->host_data;
2210 const struct tegra_pmc_soc *soc = pmc->soc;
2211 struct irq_fwspec *fwspec = data;
2212 unsigned int i;
2213 int err = 0;
2214
2215 if (WARN_ON(num_irqs > 1))
2216 return -EINVAL;
2217
2218 for (i = 0; i < soc->num_wake_events; i++) {
2219 const struct tegra_wake_event *event = &soc->wake_events[i];
2220
2221 if (fwspec->param_count == 2) {
2222 struct irq_fwspec spec;
2223
2224 if (event->id != fwspec->param[0])
2225 continue;
2226
2227 err = irq_domain_set_hwirq_and_chip(domain, virq,
2228 event->id,
2229 &pmc->irq, pmc);
2230 if (err < 0)
2231 break;
2232
2233 spec.fwnode = &pmc->dev->of_node->fwnode;
2234 spec.param_count = 3;
2235 spec.param[0] = GIC_SPI;
2236 spec.param[1] = event->irq;
2237 spec.param[2] = fwspec->param[1];
2238
2239 err = irq_domain_alloc_irqs_parent(domain, virq,
2240 num_irqs, &spec);
2241
2242 break;
2243 }
2244
2245 if (fwspec->param_count == 3) {
2246 if (event->gpio.instance != fwspec->param[0] ||
2247 event->gpio.pin != fwspec->param[1])
2248 continue;
2249
2250 err = irq_domain_set_hwirq_and_chip(domain, virq,
2251 event->id,
2252 &pmc->irq, pmc);
2253
2254
2255 if (!err && domain->parent)
2256 err = irq_domain_disconnect_hierarchy(domain->parent,
2257 virq);
2258 break;
2259 }
2260 }
2261
2262
2263 if (i == soc->num_wake_events)
2264 err = irq_domain_disconnect_hierarchy(domain, virq);
2265
2266 return err;
2267}
2268
2269static const struct irq_domain_ops tegra_pmc_irq_domain_ops = {
2270 .translate = tegra_pmc_irq_translate,
2271 .alloc = tegra_pmc_irq_alloc,
2272};
2273
2274static int tegra210_pmc_irq_set_wake(struct irq_data *data, unsigned int on)
2275{
2276 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);
2277 unsigned int offset, bit;
2278 u32 value;
2279
2280 offset = data->hwirq / 32;
2281 bit = data->hwirq % 32;
2282
2283
2284 tegra_pmc_writel(pmc, 0, PMC_SW_WAKE_STATUS);
2285 tegra_pmc_writel(pmc, 0, PMC_SW_WAKE2_STATUS);
2286
2287 tegra_pmc_writel(pmc, 0, PMC_WAKE_STATUS);
2288 tegra_pmc_writel(pmc, 0, PMC_WAKE2_STATUS);
2289
2290
2291 if (data->hwirq >= 32)
2292 offset = PMC_WAKE2_MASK;
2293 else
2294 offset = PMC_WAKE_MASK;
2295
2296 value = tegra_pmc_readl(pmc, offset);
2297
2298 if (on)
2299 value |= BIT(bit);
2300 else
2301 value &= ~BIT(bit);
2302
2303 tegra_pmc_writel(pmc, value, offset);
2304
2305 return 0;
2306}
2307
2308static int tegra210_pmc_irq_set_type(struct irq_data *data, unsigned int type)
2309{
2310 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);
2311 unsigned int offset, bit;
2312 u32 value;
2313
2314 offset = data->hwirq / 32;
2315 bit = data->hwirq % 32;
2316
2317 if (data->hwirq >= 32)
2318 offset = PMC_WAKE2_LEVEL;
2319 else
2320 offset = PMC_WAKE_LEVEL;
2321
2322 value = tegra_pmc_readl(pmc, offset);
2323
2324 switch (type) {
2325 case IRQ_TYPE_EDGE_RISING:
2326 case IRQ_TYPE_LEVEL_HIGH:
2327 value |= BIT(bit);
2328 break;
2329
2330 case IRQ_TYPE_EDGE_FALLING:
2331 case IRQ_TYPE_LEVEL_LOW:
2332 value &= ~BIT(bit);
2333 break;
2334
2335 case IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING:
2336 value ^= BIT(bit);
2337 break;
2338
2339 default:
2340 return -EINVAL;
2341 }
2342
2343 tegra_pmc_writel(pmc, value, offset);
2344
2345 return 0;
2346}
2347
2348static int tegra186_pmc_irq_set_wake(struct irq_data *data, unsigned int on)
2349{
2350 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);
2351 unsigned int offset, bit;
2352 u32 value;
2353
2354 offset = data->hwirq / 32;
2355 bit = data->hwirq % 32;
2356
2357
2358 writel(0x1, pmc->wake + WAKE_AOWAKE_STATUS_W(data->hwirq));
2359
2360
2361 value = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset));
2362
2363 if (!on)
2364 value &= ~(1 << bit);
2365 else
2366 value |= 1 << bit;
2367
2368 writel(value, pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset));
2369
2370
2371 writel(!!on, pmc->wake + WAKE_AOWAKE_MASK_W(data->hwirq));
2372
2373 return 0;
2374}
2375
2376static int tegra186_pmc_irq_set_type(struct irq_data *data, unsigned int type)
2377{
2378 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);
2379 u32 value;
2380
2381 value = readl(pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq));
2382
2383 switch (type) {
2384 case IRQ_TYPE_EDGE_RISING:
2385 case IRQ_TYPE_LEVEL_HIGH:
2386 value |= WAKE_AOWAKE_CNTRL_LEVEL;
2387 break;
2388
2389 case IRQ_TYPE_EDGE_FALLING:
2390 case IRQ_TYPE_LEVEL_LOW:
2391 value &= ~WAKE_AOWAKE_CNTRL_LEVEL;
2392 break;
2393
2394 case IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING:
2395 value ^= WAKE_AOWAKE_CNTRL_LEVEL;
2396 break;
2397
2398 default:
2399 return -EINVAL;
2400 }
2401
2402 writel(value, pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq));
2403
2404 return 0;
2405}
2406
2407static void tegra_irq_mask_parent(struct irq_data *data)
2408{
2409 if (data->parent_data)
2410 irq_chip_mask_parent(data);
2411}
2412
2413static void tegra_irq_unmask_parent(struct irq_data *data)
2414{
2415 if (data->parent_data)
2416 irq_chip_unmask_parent(data);
2417}
2418
2419static void tegra_irq_eoi_parent(struct irq_data *data)
2420{
2421 if (data->parent_data)
2422 irq_chip_eoi_parent(data);
2423}
2424
2425static int tegra_irq_set_affinity_parent(struct irq_data *data,
2426 const struct cpumask *dest,
2427 bool force)
2428{
2429 if (data->parent_data)
2430 return irq_chip_set_affinity_parent(data, dest, force);
2431
2432 return -EINVAL;
2433}
2434
2435static int tegra_pmc_irq_init(struct tegra_pmc *pmc)
2436{
2437 struct irq_domain *parent = NULL;
2438 struct device_node *np;
2439
2440 np = of_irq_find_parent(pmc->dev->of_node);
2441 if (np) {
2442 parent = irq_find_host(np);
2443 of_node_put(np);
2444 }
2445
2446 if (!parent)
2447 return 0;
2448
2449 pmc->irq.name = dev_name(pmc->dev);
2450 pmc->irq.irq_mask = tegra_irq_mask_parent;
2451 pmc->irq.irq_unmask = tegra_irq_unmask_parent;
2452 pmc->irq.irq_eoi = tegra_irq_eoi_parent;
2453 pmc->irq.irq_set_affinity = tegra_irq_set_affinity_parent;
2454 pmc->irq.irq_set_type = pmc->soc->irq_set_type;
2455 pmc->irq.irq_set_wake = pmc->soc->irq_set_wake;
2456
2457 pmc->domain = irq_domain_add_hierarchy(parent, 0, 96, pmc->dev->of_node,
2458 &tegra_pmc_irq_domain_ops, pmc);
2459 if (!pmc->domain) {
2460 dev_err(pmc->dev, "failed to allocate domain\n");
2461 return -ENOMEM;
2462 }
2463
2464 return 0;
2465}
2466
2467static int tegra_pmc_clk_notify_cb(struct notifier_block *nb,
2468 unsigned long action, void *ptr)
2469{
2470 struct tegra_pmc *pmc = container_of(nb, struct tegra_pmc, clk_nb);
2471 struct clk_notifier_data *data = ptr;
2472
2473 switch (action) {
2474 case PRE_RATE_CHANGE:
2475 mutex_lock(&pmc->powergates_lock);
2476 break;
2477
2478 case POST_RATE_CHANGE:
2479 pmc->rate = data->new_rate;
2480 fallthrough;
2481
2482 case ABORT_RATE_CHANGE:
2483 mutex_unlock(&pmc->powergates_lock);
2484 break;
2485
2486 default:
2487 WARN_ON_ONCE(1);
2488 return notifier_from_errno(-EINVAL);
2489 }
2490
2491 return NOTIFY_OK;
2492}
2493
2494static void pmc_clk_fence_udelay(u32 offset)
2495{
2496 tegra_pmc_readl(pmc, offset);
2497
2498 udelay(2);
2499}
2500
2501static u8 pmc_clk_mux_get_parent(struct clk_hw *hw)
2502{
2503 struct pmc_clk *clk = to_pmc_clk(hw);
2504 u32 val;
2505
2506 val = tegra_pmc_readl(pmc, clk->offs) >> clk->mux_shift;
2507 val &= PMC_CLK_OUT_MUX_MASK;
2508
2509 return val;
2510}
2511
2512static int pmc_clk_mux_set_parent(struct clk_hw *hw, u8 index)
2513{
2514 struct pmc_clk *clk = to_pmc_clk(hw);
2515 u32 val;
2516
2517 val = tegra_pmc_readl(pmc, clk->offs);
2518 val &= ~(PMC_CLK_OUT_MUX_MASK << clk->mux_shift);
2519 val |= index << clk->mux_shift;
2520 tegra_pmc_writel(pmc, val, clk->offs);
2521 pmc_clk_fence_udelay(clk->offs);
2522
2523 return 0;
2524}
2525
2526static int pmc_clk_is_enabled(struct clk_hw *hw)
2527{
2528 struct pmc_clk *clk = to_pmc_clk(hw);
2529 u32 val;
2530
2531 val = tegra_pmc_readl(pmc, clk->offs) & BIT(clk->force_en_shift);
2532
2533 return val ? 1 : 0;
2534}
2535
2536static void pmc_clk_set_state(unsigned long offs, u32 shift, int state)
2537{
2538 u32 val;
2539
2540 val = tegra_pmc_readl(pmc, offs);
2541 val = state ? (val | BIT(shift)) : (val & ~BIT(shift));
2542 tegra_pmc_writel(pmc, val, offs);
2543 pmc_clk_fence_udelay(offs);
2544}
2545
2546static int pmc_clk_enable(struct clk_hw *hw)
2547{
2548 struct pmc_clk *clk = to_pmc_clk(hw);
2549
2550 pmc_clk_set_state(clk->offs, clk->force_en_shift, 1);
2551
2552 return 0;
2553}
2554
2555static void pmc_clk_disable(struct clk_hw *hw)
2556{
2557 struct pmc_clk *clk = to_pmc_clk(hw);
2558
2559 pmc_clk_set_state(clk->offs, clk->force_en_shift, 0);
2560}
2561
2562static const struct clk_ops pmc_clk_ops = {
2563 .get_parent = pmc_clk_mux_get_parent,
2564 .set_parent = pmc_clk_mux_set_parent,
2565 .determine_rate = __clk_mux_determine_rate,
2566 .is_enabled = pmc_clk_is_enabled,
2567 .enable = pmc_clk_enable,
2568 .disable = pmc_clk_disable,
2569};
2570
2571static struct clk *
2572tegra_pmc_clk_out_register(struct tegra_pmc *pmc,
2573 const struct pmc_clk_init_data *data,
2574 unsigned long offset)
2575{
2576 struct clk_init_data init;
2577 struct pmc_clk *pmc_clk;
2578
2579 pmc_clk = devm_kzalloc(pmc->dev, sizeof(*pmc_clk), GFP_KERNEL);
2580 if (!pmc_clk)
2581 return ERR_PTR(-ENOMEM);
2582
2583 init.name = data->name;
2584 init.ops = &pmc_clk_ops;
2585 init.parent_names = data->parents;
2586 init.num_parents = data->num_parents;
2587 init.flags = CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT |
2588 CLK_SET_PARENT_GATE;
2589
2590 pmc_clk->hw.init = &init;
2591 pmc_clk->offs = offset;
2592 pmc_clk->mux_shift = data->mux_shift;
2593 pmc_clk->force_en_shift = data->force_en_shift;
2594
2595 return clk_register(NULL, &pmc_clk->hw);
2596}
2597
2598static int pmc_clk_gate_is_enabled(struct clk_hw *hw)
2599{
2600 struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);
2601
2602 return tegra_pmc_readl(pmc, gate->offs) & BIT(gate->shift) ? 1 : 0;
2603}
2604
2605static int pmc_clk_gate_enable(struct clk_hw *hw)
2606{
2607 struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);
2608
2609 pmc_clk_set_state(gate->offs, gate->shift, 1);
2610
2611 return 0;
2612}
2613
2614static void pmc_clk_gate_disable(struct clk_hw *hw)
2615{
2616 struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);
2617
2618 pmc_clk_set_state(gate->offs, gate->shift, 0);
2619}
2620
2621static const struct clk_ops pmc_clk_gate_ops = {
2622 .is_enabled = pmc_clk_gate_is_enabled,
2623 .enable = pmc_clk_gate_enable,
2624 .disable = pmc_clk_gate_disable,
2625};
2626
2627static struct clk *
2628tegra_pmc_clk_gate_register(struct tegra_pmc *pmc, const char *name,
2629 const char *parent_name, unsigned long offset,
2630 u32 shift)
2631{
2632 struct clk_init_data init;
2633 struct pmc_clk_gate *gate;
2634
2635 gate = devm_kzalloc(pmc->dev, sizeof(*gate), GFP_KERNEL);
2636 if (!gate)
2637 return ERR_PTR(-ENOMEM);
2638
2639 init.name = name;
2640 init.ops = &pmc_clk_gate_ops;
2641 init.parent_names = &parent_name;
2642 init.num_parents = 1;
2643 init.flags = 0;
2644
2645 gate->hw.init = &init;
2646 gate->offs = offset;
2647 gate->shift = shift;
2648
2649 return clk_register(NULL, &gate->hw);
2650}
2651
2652static void tegra_pmc_clock_register(struct tegra_pmc *pmc,
2653 struct device_node *np)
2654{
2655 struct clk *clk;
2656 struct clk_onecell_data *clk_data;
2657 unsigned int num_clks;
2658 int i, err;
2659
2660 num_clks = pmc->soc->num_pmc_clks;
2661 if (pmc->soc->has_blink_output)
2662 num_clks += 1;
2663
2664 if (!num_clks)
2665 return;
2666
2667 clk_data = devm_kmalloc(pmc->dev, sizeof(*clk_data), GFP_KERNEL);
2668 if (!clk_data)
2669 return;
2670
2671 clk_data->clks = devm_kcalloc(pmc->dev, TEGRA_PMC_CLK_MAX,
2672 sizeof(*clk_data->clks), GFP_KERNEL);
2673 if (!clk_data->clks)
2674 return;
2675
2676 clk_data->clk_num = TEGRA_PMC_CLK_MAX;
2677
2678 for (i = 0; i < TEGRA_PMC_CLK_MAX; i++)
2679 clk_data->clks[i] = ERR_PTR(-ENOENT);
2680
2681 for (i = 0; i < pmc->soc->num_pmc_clks; i++) {
2682 const struct pmc_clk_init_data *data;
2683
2684 data = pmc->soc->pmc_clks_data + i;
2685
2686 clk = tegra_pmc_clk_out_register(pmc, data, PMC_CLK_OUT_CNTRL);
2687 if (IS_ERR(clk)) {
2688 dev_warn(pmc->dev, "unable to register clock %s: %d\n",
2689 data->name, PTR_ERR_OR_ZERO(clk));
2690 return;
2691 }
2692
2693 err = clk_register_clkdev(clk, data->name, NULL);
2694 if (err) {
2695 dev_warn(pmc->dev,
2696 "unable to register %s clock lookup: %d\n",
2697 data->name, err);
2698 return;
2699 }
2700
2701 clk_data->clks[data->clk_id] = clk;
2702 }
2703
2704 if (pmc->soc->has_blink_output) {
2705 tegra_pmc_writel(pmc, 0x0, PMC_BLINK_TIMER);
2706 clk = tegra_pmc_clk_gate_register(pmc,
2707 "pmc_blink_override",
2708 "clk_32k",
2709 PMC_DPD_PADS_ORIDE,
2710 PMC_DPD_PADS_ORIDE_BLINK);
2711 if (IS_ERR(clk)) {
2712 dev_warn(pmc->dev,
2713 "unable to register pmc_blink_override: %d\n",
2714 PTR_ERR_OR_ZERO(clk));
2715 return;
2716 }
2717
2718 clk = tegra_pmc_clk_gate_register(pmc, "pmc_blink",
2719 "pmc_blink_override",
2720 PMC_CNTRL,
2721 PMC_CNTRL_BLINK_EN);
2722 if (IS_ERR(clk)) {
2723 dev_warn(pmc->dev,
2724 "unable to register pmc_blink: %d\n",
2725 PTR_ERR_OR_ZERO(clk));
2726 return;
2727 }
2728
2729 err = clk_register_clkdev(clk, "pmc_blink", NULL);
2730 if (err) {
2731 dev_warn(pmc->dev,
2732 "unable to register pmc_blink lookup: %d\n",
2733 err);
2734 return;
2735 }
2736
2737 clk_data->clks[TEGRA_PMC_CLK_BLINK] = clk;
2738 }
2739
2740 err = of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
2741 if (err)
2742 dev_warn(pmc->dev, "failed to add pmc clock provider: %d\n",
2743 err);
2744}
2745
2746static const struct regmap_range pmc_usb_sleepwalk_ranges[] = {
2747 regmap_reg_range(PMC_USB_DEBOUNCE_DEL, PMC_USB_AO),
2748 regmap_reg_range(PMC_UTMIP_UHSIC_TRIGGERS, PMC_UTMIP_UHSIC_SAVED_STATE),
2749 regmap_reg_range(PMC_UTMIP_TERM_PAD_CFG, PMC_UTMIP_UHSIC_FAKE),
2750 regmap_reg_range(PMC_UTMIP_UHSIC_LINE_WAKEUP, PMC_UTMIP_UHSIC_LINE_WAKEUP),
2751 regmap_reg_range(PMC_UTMIP_BIAS_MASTER_CNTRL, PMC_UTMIP_MASTER_CONFIG),
2752 regmap_reg_range(PMC_UTMIP_UHSIC2_TRIGGERS, PMC_UTMIP_MASTER2_CONFIG),
2753 regmap_reg_range(PMC_UTMIP_PAD_CFG0, PMC_UTMIP_UHSIC_SLEEP_CFG1),
2754 regmap_reg_range(PMC_UTMIP_SLEEPWALK_P3, PMC_UTMIP_SLEEPWALK_P3),
2755};
2756
2757static const struct regmap_access_table pmc_usb_sleepwalk_table = {
2758 .yes_ranges = pmc_usb_sleepwalk_ranges,
2759 .n_yes_ranges = ARRAY_SIZE(pmc_usb_sleepwalk_ranges),
2760};
2761
2762static int tegra_pmc_regmap_readl(void *context, unsigned int offset, unsigned int *value)
2763{
2764 struct tegra_pmc *pmc = context;
2765
2766 *value = tegra_pmc_readl(pmc, offset);
2767 return 0;
2768}
2769
2770static int tegra_pmc_regmap_writel(void *context, unsigned int offset, unsigned int value)
2771{
2772 struct tegra_pmc *pmc = context;
2773
2774 tegra_pmc_writel(pmc, value, offset);
2775 return 0;
2776}
2777
2778static const struct regmap_config usb_sleepwalk_regmap_config = {
2779 .name = "usb_sleepwalk",
2780 .reg_bits = 32,
2781 .val_bits = 32,
2782 .reg_stride = 4,
2783 .fast_io = true,
2784 .rd_table = &pmc_usb_sleepwalk_table,
2785 .wr_table = &pmc_usb_sleepwalk_table,
2786 .reg_read = tegra_pmc_regmap_readl,
2787 .reg_write = tegra_pmc_regmap_writel,
2788};
2789
2790static int tegra_pmc_regmap_init(struct tegra_pmc *pmc)
2791{
2792 struct regmap *regmap;
2793 int err;
2794
2795 if (pmc->soc->has_usb_sleepwalk) {
2796 regmap = devm_regmap_init(pmc->dev, NULL, pmc, &usb_sleepwalk_regmap_config);
2797 if (IS_ERR(regmap)) {
2798 err = PTR_ERR(regmap);
2799 dev_err(pmc->dev, "failed to allocate register map (%d)\n", err);
2800 return err;
2801 }
2802 }
2803
2804 return 0;
2805}
2806
2807static void tegra_pmc_reset_suspend_mode(void *data)
2808{
2809 pmc->suspend_mode = TEGRA_SUSPEND_NOT_READY;
2810}
2811
2812static int tegra_pmc_probe(struct platform_device *pdev)
2813{
2814 void __iomem *base;
2815 struct resource *res;
2816 int err;
2817
2818
2819
2820
2821
2822
2823 if (WARN_ON(!pmc->base || !pmc->soc))
2824 return -ENODEV;
2825
2826 err = tegra_pmc_parse_dt(pmc, pdev->dev.of_node);
2827 if (err < 0)
2828 return err;
2829
2830 err = devm_add_action_or_reset(&pdev->dev, tegra_pmc_reset_suspend_mode,
2831 NULL);
2832 if (err)
2833 return err;
2834
2835
2836 base = devm_platform_ioremap_resource(pdev, 0);
2837 if (IS_ERR(base))
2838 return PTR_ERR(base);
2839
2840 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "wake");
2841 if (res) {
2842 pmc->wake = devm_ioremap_resource(&pdev->dev, res);
2843 if (IS_ERR(pmc->wake))
2844 return PTR_ERR(pmc->wake);
2845 } else {
2846 pmc->wake = base;
2847 }
2848
2849 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "aotag");
2850 if (res) {
2851 pmc->aotag = devm_ioremap_resource(&pdev->dev, res);
2852 if (IS_ERR(pmc->aotag))
2853 return PTR_ERR(pmc->aotag);
2854 } else {
2855 pmc->aotag = base;
2856 }
2857
2858 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "scratch");
2859 if (res) {
2860 pmc->scratch = devm_ioremap_resource(&pdev->dev, res);
2861 if (IS_ERR(pmc->scratch))
2862 return PTR_ERR(pmc->scratch);
2863 } else {
2864 pmc->scratch = base;
2865 }
2866
2867 pmc->clk = devm_clk_get(&pdev->dev, "pclk");
2868 if (IS_ERR(pmc->clk)) {
2869 err = PTR_ERR(pmc->clk);
2870
2871 if (err != -ENOENT) {
2872 dev_err(&pdev->dev, "failed to get pclk: %d\n", err);
2873 return err;
2874 }
2875
2876 pmc->clk = NULL;
2877 }
2878
2879
2880
2881
2882
2883
2884 if (pmc->clk) {
2885 pmc->clk_nb.notifier_call = tegra_pmc_clk_notify_cb;
2886 err = clk_notifier_register(pmc->clk, &pmc->clk_nb);
2887 if (err) {
2888 dev_err(&pdev->dev,
2889 "failed to register clk notifier\n");
2890 return err;
2891 }
2892
2893 pmc->rate = clk_get_rate(pmc->clk);
2894 }
2895
2896 pmc->dev = &pdev->dev;
2897
2898 tegra_pmc_init(pmc);
2899
2900 tegra_pmc_init_tsense_reset(pmc);
2901
2902 tegra_pmc_reset_sysfs_init(pmc);
2903
2904 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
2905 err = tegra_powergate_debugfs_init();
2906 if (err < 0)
2907 goto cleanup_sysfs;
2908 }
2909
2910 err = devm_register_reboot_notifier(&pdev->dev,
2911 &tegra_pmc_reboot_notifier);
2912 if (err) {
2913 dev_err(&pdev->dev, "unable to register reboot notifier, %d\n",
2914 err);
2915 goto cleanup_debugfs;
2916 }
2917
2918 err = register_restart_handler(&tegra_pmc_restart_handler);
2919 if (err) {
2920 dev_err(&pdev->dev, "unable to register restart handler, %d\n",
2921 err);
2922 goto cleanup_debugfs;
2923 }
2924
2925 err = tegra_pmc_pinctrl_init(pmc);
2926 if (err)
2927 goto cleanup_restart_handler;
2928
2929 err = tegra_pmc_regmap_init(pmc);
2930 if (err < 0)
2931 goto cleanup_restart_handler;
2932
2933 err = tegra_powergate_init(pmc, pdev->dev.of_node);
2934 if (err < 0)
2935 goto cleanup_powergates;
2936
2937 err = tegra_pmc_irq_init(pmc);
2938 if (err < 0)
2939 goto cleanup_powergates;
2940
2941 mutex_lock(&pmc->powergates_lock);
2942 iounmap(pmc->base);
2943 pmc->base = base;
2944 mutex_unlock(&pmc->powergates_lock);
2945
2946 tegra_pmc_clock_register(pmc, pdev->dev.of_node);
2947 platform_set_drvdata(pdev, pmc);
2948 tegra_pm_init_suspend();
2949
2950 return 0;
2951
2952cleanup_powergates:
2953 tegra_powergate_remove_all(pdev->dev.of_node);
2954cleanup_restart_handler:
2955 unregister_restart_handler(&tegra_pmc_restart_handler);
2956cleanup_debugfs:
2957 debugfs_remove(pmc->debugfs);
2958cleanup_sysfs:
2959 device_remove_file(&pdev->dev, &dev_attr_reset_reason);
2960 device_remove_file(&pdev->dev, &dev_attr_reset_level);
2961 clk_notifier_unregister(pmc->clk, &pmc->clk_nb);
2962
2963 return err;
2964}
2965
2966#if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM)
2967static int tegra_pmc_suspend(struct device *dev)
2968{
2969 struct tegra_pmc *pmc = dev_get_drvdata(dev);
2970
2971 tegra_pmc_writel(pmc, virt_to_phys(tegra_resume), PMC_SCRATCH41);
2972
2973 return 0;
2974}
2975
2976static int tegra_pmc_resume(struct device *dev)
2977{
2978 struct tegra_pmc *pmc = dev_get_drvdata(dev);
2979
2980 tegra_pmc_writel(pmc, 0x0, PMC_SCRATCH41);
2981
2982 return 0;
2983}
2984
2985static SIMPLE_DEV_PM_OPS(tegra_pmc_pm_ops, tegra_pmc_suspend, tegra_pmc_resume);
2986
2987#endif
2988
2989static const char * const tegra20_powergates[] = {
2990 [TEGRA_POWERGATE_CPU] = "cpu",
2991 [TEGRA_POWERGATE_3D] = "td",
2992 [TEGRA_POWERGATE_VENC] = "venc",
2993 [TEGRA_POWERGATE_VDEC] = "vdec",
2994 [TEGRA_POWERGATE_PCIE] = "pcie",
2995 [TEGRA_POWERGATE_L2] = "l2",
2996 [TEGRA_POWERGATE_MPE] = "mpe",
2997};
2998
2999static const struct tegra_pmc_regs tegra20_pmc_regs = {
3000 .scratch0 = 0x50,
3001 .dpd_req = 0x1b8,
3002 .dpd_status = 0x1bc,
3003 .dpd2_req = 0x1c0,
3004 .dpd2_status = 0x1c4,
3005 .rst_status = 0x1b4,
3006 .rst_source_shift = 0x0,
3007 .rst_source_mask = 0x7,
3008 .rst_level_shift = 0x0,
3009 .rst_level_mask = 0x0,
3010};
3011
3012static void tegra20_pmc_init(struct tegra_pmc *pmc)
3013{
3014 u32 value, osc, pmu, off;
3015
3016
3017 value = tegra_pmc_readl(pmc, PMC_CNTRL);
3018 value |= PMC_CNTRL_CPU_PWRREQ_OE;
3019 tegra_pmc_writel(pmc, value, PMC_CNTRL);
3020
3021 value = tegra_pmc_readl(pmc, PMC_CNTRL);
3022
3023 if (pmc->sysclkreq_high)
3024 value &= ~PMC_CNTRL_SYSCLK_POLARITY;
3025 else
3026 value |= PMC_CNTRL_SYSCLK_POLARITY;
3027
3028 if (pmc->corereq_high)
3029 value &= ~PMC_CNTRL_PWRREQ_POLARITY;
3030 else
3031 value |= PMC_CNTRL_PWRREQ_POLARITY;
3032
3033
3034 tegra_pmc_writel(pmc, value, PMC_CNTRL);
3035
3036
3037 value = tegra_pmc_readl(pmc, PMC_CNTRL);
3038 value |= PMC_CNTRL_SYSCLK_OE;
3039 tegra_pmc_writel(pmc, value, PMC_CNTRL);
3040
3041
3042 if (pmc->suspend_mode != TEGRA_SUSPEND_NONE) {
3043 osc = DIV_ROUND_UP(pmc->core_osc_time * 8192, 1000000);
3044 pmu = DIV_ROUND_UP(pmc->core_pmu_time * 32768, 1000000);
3045 off = DIV_ROUND_UP(pmc->core_off_time * 32768, 1000000);
3046 tegra_pmc_writel(pmc, ((osc << 8) & 0xff00) | (pmu & 0xff),
3047 PMC_COREPWRGOOD_TIMER);
3048 tegra_pmc_writel(pmc, off, PMC_COREPWROFF_TIMER);
3049 }
3050}
3051
3052static void tegra20_pmc_setup_irq_polarity(struct tegra_pmc *pmc,
3053 struct device_node *np,
3054 bool invert)
3055{
3056 u32 value;
3057
3058 value = tegra_pmc_readl(pmc, PMC_CNTRL);
3059
3060 if (invert)
3061 value |= PMC_CNTRL_INTR_POLARITY;
3062 else
3063 value &= ~PMC_CNTRL_INTR_POLARITY;
3064
3065 tegra_pmc_writel(pmc, value, PMC_CNTRL);
3066}
3067
3068static const struct tegra_pmc_soc tegra20_pmc_soc = {
3069 .supports_core_domain = false,
3070 .num_powergates = ARRAY_SIZE(tegra20_powergates),
3071 .powergates = tegra20_powergates,
3072 .num_cpu_powergates = 0,
3073 .cpu_powergates = NULL,
3074 .has_tsense_reset = false,
3075 .has_gpu_clamps = false,
3076 .needs_mbist_war = false,
3077 .has_impl_33v_pwr = false,
3078 .maybe_tz_only = false,
3079 .num_io_pads = 0,
3080 .io_pads = NULL,
3081 .num_pin_descs = 0,
3082 .pin_descs = NULL,
3083 .regs = &tegra20_pmc_regs,
3084 .init = tegra20_pmc_init,
3085 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
3086 .powergate_set = tegra20_powergate_set,
3087 .reset_sources = NULL,
3088 .num_reset_sources = 0,
3089 .reset_levels = NULL,
3090 .num_reset_levels = 0,
3091 .pmc_clks_data = NULL,
3092 .num_pmc_clks = 0,
3093 .has_blink_output = true,
3094 .has_usb_sleepwalk = true,
3095};
3096
3097static const char * const tegra30_powergates[] = {
3098 [TEGRA_POWERGATE_CPU] = "cpu0",
3099 [TEGRA_POWERGATE_3D] = "td",
3100 [TEGRA_POWERGATE_VENC] = "venc",
3101 [TEGRA_POWERGATE_VDEC] = "vdec",
3102 [TEGRA_POWERGATE_PCIE] = "pcie",
3103 [TEGRA_POWERGATE_L2] = "l2",
3104 [TEGRA_POWERGATE_MPE] = "mpe",
3105 [TEGRA_POWERGATE_HEG] = "heg",
3106 [TEGRA_POWERGATE_SATA] = "sata",
3107 [TEGRA_POWERGATE_CPU1] = "cpu1",
3108 [TEGRA_POWERGATE_CPU2] = "cpu2",
3109 [TEGRA_POWERGATE_CPU3] = "cpu3",
3110 [TEGRA_POWERGATE_CELP] = "celp",
3111 [TEGRA_POWERGATE_3D1] = "td2",
3112};
3113
3114static const u8 tegra30_cpu_powergates[] = {
3115 TEGRA_POWERGATE_CPU,
3116 TEGRA_POWERGATE_CPU1,
3117 TEGRA_POWERGATE_CPU2,
3118 TEGRA_POWERGATE_CPU3,
3119};
3120
3121static const char * const tegra30_reset_sources[] = {
3122 "POWER_ON_RESET",
3123 "WATCHDOG",
3124 "SENSOR",
3125 "SW_MAIN",
3126 "LP0"
3127};
3128
3129static const struct tegra_pmc_soc tegra30_pmc_soc = {
3130 .supports_core_domain = false,
3131 .num_powergates = ARRAY_SIZE(tegra30_powergates),
3132 .powergates = tegra30_powergates,
3133 .num_cpu_powergates = ARRAY_SIZE(tegra30_cpu_powergates),
3134 .cpu_powergates = tegra30_cpu_powergates,
3135 .has_tsense_reset = true,
3136 .has_gpu_clamps = false,
3137 .needs_mbist_war = false,
3138 .has_impl_33v_pwr = false,
3139 .maybe_tz_only = false,
3140 .num_io_pads = 0,
3141 .io_pads = NULL,
3142 .num_pin_descs = 0,
3143 .pin_descs = NULL,
3144 .regs = &tegra20_pmc_regs,
3145 .init = tegra20_pmc_init,
3146 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
3147 .powergate_set = tegra20_powergate_set,
3148 .reset_sources = tegra30_reset_sources,
3149 .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources),
3150 .reset_levels = NULL,
3151 .num_reset_levels = 0,
3152 .pmc_clks_data = tegra_pmc_clks_data,
3153 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),
3154 .has_blink_output = true,
3155 .has_usb_sleepwalk = true,
3156};
3157
3158static const char * const tegra114_powergates[] = {
3159 [TEGRA_POWERGATE_CPU] = "crail",
3160 [TEGRA_POWERGATE_3D] = "td",
3161 [TEGRA_POWERGATE_VENC] = "venc",
3162 [TEGRA_POWERGATE_VDEC] = "vdec",
3163 [TEGRA_POWERGATE_MPE] = "mpe",
3164 [TEGRA_POWERGATE_HEG] = "heg",
3165 [TEGRA_POWERGATE_CPU1] = "cpu1",
3166 [TEGRA_POWERGATE_CPU2] = "cpu2",
3167 [TEGRA_POWERGATE_CPU3] = "cpu3",
3168 [TEGRA_POWERGATE_CELP] = "celp",
3169 [TEGRA_POWERGATE_CPU0] = "cpu0",
3170 [TEGRA_POWERGATE_C0NC] = "c0nc",
3171 [TEGRA_POWERGATE_C1NC] = "c1nc",
3172 [TEGRA_POWERGATE_DIS] = "dis",
3173 [TEGRA_POWERGATE_DISB] = "disb",
3174 [TEGRA_POWERGATE_XUSBA] = "xusba",
3175 [TEGRA_POWERGATE_XUSBB] = "xusbb",
3176 [TEGRA_POWERGATE_XUSBC] = "xusbc",
3177};
3178
3179static const u8 tegra114_cpu_powergates[] = {
3180 TEGRA_POWERGATE_CPU0,
3181 TEGRA_POWERGATE_CPU1,
3182 TEGRA_POWERGATE_CPU2,
3183 TEGRA_POWERGATE_CPU3,
3184};
3185
3186static const struct tegra_pmc_soc tegra114_pmc_soc = {
3187 .supports_core_domain = false,
3188 .num_powergates = ARRAY_SIZE(tegra114_powergates),
3189 .powergates = tegra114_powergates,
3190 .num_cpu_powergates = ARRAY_SIZE(tegra114_cpu_powergates),
3191 .cpu_powergates = tegra114_cpu_powergates,
3192 .has_tsense_reset = true,
3193 .has_gpu_clamps = false,
3194 .needs_mbist_war = false,
3195 .has_impl_33v_pwr = false,
3196 .maybe_tz_only = false,
3197 .num_io_pads = 0,
3198 .io_pads = NULL,
3199 .num_pin_descs = 0,
3200 .pin_descs = NULL,
3201 .regs = &tegra20_pmc_regs,
3202 .init = tegra20_pmc_init,
3203 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
3204 .powergate_set = tegra114_powergate_set,
3205 .reset_sources = tegra30_reset_sources,
3206 .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources),
3207 .reset_levels = NULL,
3208 .num_reset_levels = 0,
3209 .pmc_clks_data = tegra_pmc_clks_data,
3210 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),
3211 .has_blink_output = true,
3212 .has_usb_sleepwalk = true,
3213};
3214
3215static const char * const tegra124_powergates[] = {
3216 [TEGRA_POWERGATE_CPU] = "crail",
3217 [TEGRA_POWERGATE_3D] = "3d",
3218 [TEGRA_POWERGATE_VENC] = "venc",
3219 [TEGRA_POWERGATE_PCIE] = "pcie",
3220 [TEGRA_POWERGATE_VDEC] = "vdec",
3221 [TEGRA_POWERGATE_MPE] = "mpe",
3222 [TEGRA_POWERGATE_HEG] = "heg",
3223 [TEGRA_POWERGATE_SATA] = "sata",
3224 [TEGRA_POWERGATE_CPU1] = "cpu1",
3225 [TEGRA_POWERGATE_CPU2] = "cpu2",
3226 [TEGRA_POWERGATE_CPU3] = "cpu3",
3227 [TEGRA_POWERGATE_CELP] = "celp",
3228 [TEGRA_POWERGATE_CPU0] = "cpu0",
3229 [TEGRA_POWERGATE_C0NC] = "c0nc",
3230 [TEGRA_POWERGATE_C1NC] = "c1nc",
3231 [TEGRA_POWERGATE_SOR] = "sor",
3232 [TEGRA_POWERGATE_DIS] = "dis",
3233 [TEGRA_POWERGATE_DISB] = "disb",
3234 [TEGRA_POWERGATE_XUSBA] = "xusba",
3235 [TEGRA_POWERGATE_XUSBB] = "xusbb",
3236 [TEGRA_POWERGATE_XUSBC] = "xusbc",
3237 [TEGRA_POWERGATE_VIC] = "vic",
3238 [TEGRA_POWERGATE_IRAM] = "iram",
3239};
3240
3241static const u8 tegra124_cpu_powergates[] = {
3242 TEGRA_POWERGATE_CPU0,
3243 TEGRA_POWERGATE_CPU1,
3244 TEGRA_POWERGATE_CPU2,
3245 TEGRA_POWERGATE_CPU3,
3246};
3247
3248#define TEGRA_IO_PAD(_id, _dpd, _voltage, _name) \
3249 ((struct tegra_io_pad_soc) { \
3250 .id = (_id), \
3251 .dpd = (_dpd), \
3252 .voltage = (_voltage), \
3253 .name = (_name), \
3254 })
3255
3256#define TEGRA_IO_PIN_DESC(_id, _dpd, _voltage, _name) \
3257 ((struct pinctrl_pin_desc) { \
3258 .number = (_id), \
3259 .name = (_name) \
3260 })
3261
3262#define TEGRA124_IO_PAD_TABLE(_pad) \
3263 \
3264 _pad(TEGRA_IO_PAD_AUDIO, 17, UINT_MAX, "audio"), \
3265 _pad(TEGRA_IO_PAD_BB, 15, UINT_MAX, "bb"), \
3266 _pad(TEGRA_IO_PAD_CAM, 36, UINT_MAX, "cam"), \
3267 _pad(TEGRA_IO_PAD_COMP, 22, UINT_MAX, "comp"), \
3268 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \
3269 _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csb"), \
3270 _pad(TEGRA_IO_PAD_CSIE, 44, UINT_MAX, "cse"), \
3271 _pad(TEGRA_IO_PAD_DSI, 2, UINT_MAX, "dsi"), \
3272 _pad(TEGRA_IO_PAD_DSIB, 39, UINT_MAX, "dsib"), \
3273 _pad(TEGRA_IO_PAD_DSIC, 40, UINT_MAX, "dsic"), \
3274 _pad(TEGRA_IO_PAD_DSID, 41, UINT_MAX, "dsid"), \
3275 _pad(TEGRA_IO_PAD_HDMI, 28, UINT_MAX, "hdmi"), \
3276 _pad(TEGRA_IO_PAD_HSIC, 19, UINT_MAX, "hsic"), \
3277 _pad(TEGRA_IO_PAD_HV, 38, UINT_MAX, "hv"), \
3278 _pad(TEGRA_IO_PAD_LVDS, 57, UINT_MAX, "lvds"), \
3279 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \
3280 _pad(TEGRA_IO_PAD_NAND, 13, UINT_MAX, "nand"), \
3281 _pad(TEGRA_IO_PAD_PEX_BIAS, 4, UINT_MAX, "pex-bias"), \
3282 _pad(TEGRA_IO_PAD_PEX_CLK1, 5, UINT_MAX, "pex-clk1"), \
3283 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \
3284 _pad(TEGRA_IO_PAD_PEX_CNTRL, 32, UINT_MAX, "pex-cntrl"), \
3285 _pad(TEGRA_IO_PAD_SDMMC1, 33, UINT_MAX, "sdmmc1"), \
3286 _pad(TEGRA_IO_PAD_SDMMC3, 34, UINT_MAX, "sdmmc3"), \
3287 _pad(TEGRA_IO_PAD_SDMMC4, 35, UINT_MAX, "sdmmc4"), \
3288 _pad(TEGRA_IO_PAD_SYS_DDC, 58, UINT_MAX, "sys_ddc"), \
3289 _pad(TEGRA_IO_PAD_UART, 14, UINT_MAX, "uart"), \
3290 _pad(TEGRA_IO_PAD_USB0, 9, UINT_MAX, "usb0"), \
3291 _pad(TEGRA_IO_PAD_USB1, 10, UINT_MAX, "usb1"), \
3292 _pad(TEGRA_IO_PAD_USB2, 11, UINT_MAX, "usb2"), \
3293 _pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb_bias")
3294
3295static const struct tegra_io_pad_soc tegra124_io_pads[] = {
3296 TEGRA124_IO_PAD_TABLE(TEGRA_IO_PAD)
3297};
3298
3299static const struct pinctrl_pin_desc tegra124_pin_descs[] = {
3300 TEGRA124_IO_PAD_TABLE(TEGRA_IO_PIN_DESC)
3301};
3302
3303static const struct tegra_pmc_soc tegra124_pmc_soc = {
3304 .supports_core_domain = false,
3305 .num_powergates = ARRAY_SIZE(tegra124_powergates),
3306 .powergates = tegra124_powergates,
3307 .num_cpu_powergates = ARRAY_SIZE(tegra124_cpu_powergates),
3308 .cpu_powergates = tegra124_cpu_powergates,
3309 .has_tsense_reset = true,
3310 .has_gpu_clamps = true,
3311 .needs_mbist_war = false,
3312 .has_impl_33v_pwr = false,
3313 .maybe_tz_only = false,
3314 .num_io_pads = ARRAY_SIZE(tegra124_io_pads),
3315 .io_pads = tegra124_io_pads,
3316 .num_pin_descs = ARRAY_SIZE(tegra124_pin_descs),
3317 .pin_descs = tegra124_pin_descs,
3318 .regs = &tegra20_pmc_regs,
3319 .init = tegra20_pmc_init,
3320 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
3321 .powergate_set = tegra114_powergate_set,
3322 .reset_sources = tegra30_reset_sources,
3323 .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources),
3324 .reset_levels = NULL,
3325 .num_reset_levels = 0,
3326 .pmc_clks_data = tegra_pmc_clks_data,
3327 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),
3328 .has_blink_output = true,
3329 .has_usb_sleepwalk = true,
3330};
3331
3332static const char * const tegra210_powergates[] = {
3333 [TEGRA_POWERGATE_CPU] = "crail",
3334 [TEGRA_POWERGATE_3D] = "3d",
3335 [TEGRA_POWERGATE_VENC] = "venc",
3336 [TEGRA_POWERGATE_PCIE] = "pcie",
3337 [TEGRA_POWERGATE_MPE] = "mpe",
3338 [TEGRA_POWERGATE_SATA] = "sata",
3339 [TEGRA_POWERGATE_CPU1] = "cpu1",
3340 [TEGRA_POWERGATE_CPU2] = "cpu2",
3341 [TEGRA_POWERGATE_CPU3] = "cpu3",
3342 [TEGRA_POWERGATE_CPU0] = "cpu0",
3343 [TEGRA_POWERGATE_C0NC] = "c0nc",
3344 [TEGRA_POWERGATE_SOR] = "sor",
3345 [TEGRA_POWERGATE_DIS] = "dis",
3346 [TEGRA_POWERGATE_DISB] = "disb",
3347 [TEGRA_POWERGATE_XUSBA] = "xusba",
3348 [TEGRA_POWERGATE_XUSBB] = "xusbb",
3349 [TEGRA_POWERGATE_XUSBC] = "xusbc",
3350 [TEGRA_POWERGATE_VIC] = "vic",
3351 [TEGRA_POWERGATE_IRAM] = "iram",
3352 [TEGRA_POWERGATE_NVDEC] = "nvdec",
3353 [TEGRA_POWERGATE_NVJPG] = "nvjpg",
3354 [TEGRA_POWERGATE_AUD] = "aud",
3355 [TEGRA_POWERGATE_DFD] = "dfd",
3356 [TEGRA_POWERGATE_VE2] = "ve2",
3357};
3358
3359static const u8 tegra210_cpu_powergates[] = {
3360 TEGRA_POWERGATE_CPU0,
3361 TEGRA_POWERGATE_CPU1,
3362 TEGRA_POWERGATE_CPU2,
3363 TEGRA_POWERGATE_CPU3,
3364};
3365
3366#define TEGRA210_IO_PAD_TABLE(_pad) \
3367 \
3368 _pad(TEGRA_IO_PAD_AUDIO, 17, 5, "audio"), \
3369 _pad(TEGRA_IO_PAD_AUDIO_HV, 61, 18, "audio-hv"), \
3370 _pad(TEGRA_IO_PAD_CAM, 36, 10, "cam"), \
3371 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \
3372 _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csib"), \
3373 _pad(TEGRA_IO_PAD_CSIC, 42, UINT_MAX, "csic"), \
3374 _pad(TEGRA_IO_PAD_CSID, 43, UINT_MAX, "csid"), \
3375 _pad(TEGRA_IO_PAD_CSIE, 44, UINT_MAX, "csie"), \
3376 _pad(TEGRA_IO_PAD_CSIF, 45, UINT_MAX, "csif"), \
3377 _pad(TEGRA_IO_PAD_DBG, 25, 19, "dbg"), \
3378 _pad(TEGRA_IO_PAD_DEBUG_NONAO, 26, UINT_MAX, "debug-nonao"), \
3379 _pad(TEGRA_IO_PAD_DMIC, 50, 20, "dmic"), \
3380 _pad(TEGRA_IO_PAD_DP, 51, UINT_MAX, "dp"), \
3381 _pad(TEGRA_IO_PAD_DSI, 2, UINT_MAX, "dsi"), \
3382 _pad(TEGRA_IO_PAD_DSIB, 39, UINT_MAX, "dsib"), \
3383 _pad(TEGRA_IO_PAD_DSIC, 40, UINT_MAX, "dsic"), \
3384 _pad(TEGRA_IO_PAD_DSID, 41, UINT_MAX, "dsid"), \
3385 _pad(TEGRA_IO_PAD_EMMC, 35, UINT_MAX, "emmc"), \
3386 _pad(TEGRA_IO_PAD_EMMC2, 37, UINT_MAX, "emmc2"), \
3387 _pad(TEGRA_IO_PAD_GPIO, 27, 21, "gpio"), \
3388 _pad(TEGRA_IO_PAD_HDMI, 28, UINT_MAX, "hdmi"), \
3389 _pad(TEGRA_IO_PAD_HSIC, 19, UINT_MAX, "hsic"), \
3390 _pad(TEGRA_IO_PAD_LVDS, 57, UINT_MAX, "lvds"), \
3391 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \
3392 _pad(TEGRA_IO_PAD_PEX_BIAS, 4, UINT_MAX, "pex-bias"), \
3393 _pad(TEGRA_IO_PAD_PEX_CLK1, 5, UINT_MAX, "pex-clk1"), \
3394 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \
3395 _pad(TEGRA_IO_PAD_PEX_CNTRL, UINT_MAX, 11, "pex-cntrl"), \
3396 _pad(TEGRA_IO_PAD_SDMMC1, 33, 12, "sdmmc1"), \
3397 _pad(TEGRA_IO_PAD_SDMMC3, 34, 13, "sdmmc3"), \
3398 _pad(TEGRA_IO_PAD_SPI, 46, 22, "spi"), \
3399 _pad(TEGRA_IO_PAD_SPI_HV, 47, 23, "spi-hv"), \
3400 _pad(TEGRA_IO_PAD_UART, 14, 2, "uart"), \
3401 _pad(TEGRA_IO_PAD_USB0, 9, UINT_MAX, "usb0"), \
3402 _pad(TEGRA_IO_PAD_USB1, 10, UINT_MAX, "usb1"), \
3403 _pad(TEGRA_IO_PAD_USB2, 11, UINT_MAX, "usb2"), \
3404 _pad(TEGRA_IO_PAD_USB3, 18, UINT_MAX, "usb3"), \
3405 _pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb-bias")
3406
3407static const struct tegra_io_pad_soc tegra210_io_pads[] = {
3408 TEGRA210_IO_PAD_TABLE(TEGRA_IO_PAD)
3409};
3410
3411static const struct pinctrl_pin_desc tegra210_pin_descs[] = {
3412 TEGRA210_IO_PAD_TABLE(TEGRA_IO_PIN_DESC)
3413};
3414
3415static const char * const tegra210_reset_sources[] = {
3416 "POWER_ON_RESET",
3417 "WATCHDOG",
3418 "SENSOR",
3419 "SW_MAIN",
3420 "LP0",
3421 "AOTAG"
3422};
3423
3424static const struct tegra_wake_event tegra210_wake_events[] = {
3425 TEGRA_WAKE_IRQ("rtc", 16, 2),
3426 TEGRA_WAKE_IRQ("pmu", 51, 86),
3427};
3428
3429static const struct tegra_pmc_soc tegra210_pmc_soc = {
3430 .supports_core_domain = false,
3431 .num_powergates = ARRAY_SIZE(tegra210_powergates),
3432 .powergates = tegra210_powergates,
3433 .num_cpu_powergates = ARRAY_SIZE(tegra210_cpu_powergates),
3434 .cpu_powergates = tegra210_cpu_powergates,
3435 .has_tsense_reset = true,
3436 .has_gpu_clamps = true,
3437 .needs_mbist_war = true,
3438 .has_impl_33v_pwr = false,
3439 .maybe_tz_only = true,
3440 .num_io_pads = ARRAY_SIZE(tegra210_io_pads),
3441 .io_pads = tegra210_io_pads,
3442 .num_pin_descs = ARRAY_SIZE(tegra210_pin_descs),
3443 .pin_descs = tegra210_pin_descs,
3444 .regs = &tegra20_pmc_regs,
3445 .init = tegra20_pmc_init,
3446 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
3447 .powergate_set = tegra114_powergate_set,
3448 .irq_set_wake = tegra210_pmc_irq_set_wake,
3449 .irq_set_type = tegra210_pmc_irq_set_type,
3450 .reset_sources = tegra210_reset_sources,
3451 .num_reset_sources = ARRAY_SIZE(tegra210_reset_sources),
3452 .reset_levels = NULL,
3453 .num_reset_levels = 0,
3454 .num_wake_events = ARRAY_SIZE(tegra210_wake_events),
3455 .wake_events = tegra210_wake_events,
3456 .pmc_clks_data = tegra_pmc_clks_data,
3457 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),
3458 .has_blink_output = true,
3459 .has_usb_sleepwalk = true,
3460};
3461
3462#define TEGRA186_IO_PAD_TABLE(_pad) \
3463 \
3464 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \
3465 _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csib"), \
3466 _pad(TEGRA_IO_PAD_DSI, 2, UINT_MAX, "dsi"), \
3467 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \
3468 _pad(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, UINT_MAX, "pex-clk-bias"), \
3469 _pad(TEGRA_IO_PAD_PEX_CLK3, 5, UINT_MAX, "pex-clk3"), \
3470 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \
3471 _pad(TEGRA_IO_PAD_PEX_CLK1, 7, UINT_MAX, "pex-clk1"), \
3472 _pad(TEGRA_IO_PAD_USB0, 9, UINT_MAX, "usb0"), \
3473 _pad(TEGRA_IO_PAD_USB1, 10, UINT_MAX, "usb1"), \
3474 _pad(TEGRA_IO_PAD_USB2, 11, UINT_MAX, "usb2"), \
3475 _pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb-bias"), \
3476 _pad(TEGRA_IO_PAD_UART, 14, UINT_MAX, "uart"), \
3477 _pad(TEGRA_IO_PAD_AUDIO, 17, UINT_MAX, "audio"), \
3478 _pad(TEGRA_IO_PAD_HSIC, 19, UINT_MAX, "hsic"), \
3479 _pad(TEGRA_IO_PAD_DBG, 25, UINT_MAX, "dbg"), \
3480 _pad(TEGRA_IO_PAD_HDMI_DP0, 28, UINT_MAX, "hdmi-dp0"), \
3481 _pad(TEGRA_IO_PAD_HDMI_DP1, 29, UINT_MAX, "hdmi-dp1"), \
3482 _pad(TEGRA_IO_PAD_PEX_CNTRL, 32, UINT_MAX, "pex-cntrl"), \
3483 _pad(TEGRA_IO_PAD_SDMMC2_HV, 34, 5, "sdmmc2-hv"), \
3484 _pad(TEGRA_IO_PAD_SDMMC4, 36, UINT_MAX, "sdmmc4"), \
3485 _pad(TEGRA_IO_PAD_CAM, 38, UINT_MAX, "cam"), \
3486 _pad(TEGRA_IO_PAD_DSIB, 40, UINT_MAX, "dsib"), \
3487 _pad(TEGRA_IO_PAD_DSIC, 41, UINT_MAX, "dsic"), \
3488 _pad(TEGRA_IO_PAD_DSID, 42, UINT_MAX, "dsid"), \
3489 _pad(TEGRA_IO_PAD_CSIC, 43, UINT_MAX, "csic"), \
3490 _pad(TEGRA_IO_PAD_CSID, 44, UINT_MAX, "csid"), \
3491 _pad(TEGRA_IO_PAD_CSIE, 45, UINT_MAX, "csie"), \
3492 _pad(TEGRA_IO_PAD_CSIF, 46, UINT_MAX, "csif"), \
3493 _pad(TEGRA_IO_PAD_SPI, 47, UINT_MAX, "spi"), \
3494 _pad(TEGRA_IO_PAD_UFS, 49, UINT_MAX, "ufs"), \
3495 _pad(TEGRA_IO_PAD_DMIC_HV, 52, 2, "dmic-hv"), \
3496 _pad(TEGRA_IO_PAD_EDP, 53, UINT_MAX, "edp"), \
3497 _pad(TEGRA_IO_PAD_SDMMC1_HV, 55, 4, "sdmmc1-hv"), \
3498 _pad(TEGRA_IO_PAD_SDMMC3_HV, 56, 6, "sdmmc3-hv"), \
3499 _pad(TEGRA_IO_PAD_CONN, 60, UINT_MAX, "conn"), \
3500 _pad(TEGRA_IO_PAD_AUDIO_HV, 61, 1, "audio-hv"), \
3501 _pad(TEGRA_IO_PAD_AO_HV, UINT_MAX, 0, "ao-hv")
3502
3503static const struct tegra_io_pad_soc tegra186_io_pads[] = {
3504 TEGRA186_IO_PAD_TABLE(TEGRA_IO_PAD)
3505};
3506
3507static const struct pinctrl_pin_desc tegra186_pin_descs[] = {
3508 TEGRA186_IO_PAD_TABLE(TEGRA_IO_PIN_DESC)
3509};
3510
3511static const struct tegra_pmc_regs tegra186_pmc_regs = {
3512 .scratch0 = 0x2000,
3513 .dpd_req = 0x74,
3514 .dpd_status = 0x78,
3515 .dpd2_req = 0x7c,
3516 .dpd2_status = 0x80,
3517 .rst_status = 0x70,
3518 .rst_source_shift = 0x2,
3519 .rst_source_mask = 0x3c,
3520 .rst_level_shift = 0x0,
3521 .rst_level_mask = 0x3,
3522};
3523
3524static void tegra186_pmc_setup_irq_polarity(struct tegra_pmc *pmc,
3525 struct device_node *np,
3526 bool invert)
3527{
3528 struct resource regs;
3529 void __iomem *wake;
3530 u32 value;
3531 int index;
3532
3533 index = of_property_match_string(np, "reg-names", "wake");
3534 if (index < 0) {
3535 dev_err(pmc->dev, "failed to find PMC wake registers\n");
3536 return;
3537 }
3538
3539 of_address_to_resource(np, index, ®s);
3540
3541 wake = ioremap(regs.start, resource_size(®s));
3542 if (!wake) {
3543 dev_err(pmc->dev, "failed to map PMC wake registers\n");
3544 return;
3545 }
3546
3547 value = readl(wake + WAKE_AOWAKE_CTRL);
3548
3549 if (invert)
3550 value |= WAKE_AOWAKE_CTRL_INTR_POLARITY;
3551 else
3552 value &= ~WAKE_AOWAKE_CTRL_INTR_POLARITY;
3553
3554 writel(value, wake + WAKE_AOWAKE_CTRL);
3555
3556 iounmap(wake);
3557}
3558
3559static const char * const tegra186_reset_sources[] = {
3560 "SYS_RESET",
3561 "AOWDT",
3562 "MCCPLEXWDT",
3563 "BPMPWDT",
3564 "SCEWDT",
3565 "SPEWDT",
3566 "APEWDT",
3567 "BCCPLEXWDT",
3568 "SENSOR",
3569 "AOTAG",
3570 "VFSENSOR",
3571 "SWREST",
3572 "SC7",
3573 "HSM",
3574 "CORESIGHT"
3575};
3576
3577static const char * const tegra186_reset_levels[] = {
3578 "L0", "L1", "L2", "WARM"
3579};
3580
3581static const struct tegra_wake_event tegra186_wake_events[] = {
3582 TEGRA_WAKE_IRQ("pmu", 24, 209),
3583 TEGRA_WAKE_GPIO("power", 29, 1, TEGRA186_AON_GPIO(FF, 0)),
3584 TEGRA_WAKE_IRQ("rtc", 73, 10),
3585};
3586
3587static const struct tegra_pmc_soc tegra186_pmc_soc = {
3588 .supports_core_domain = false,
3589 .num_powergates = 0,
3590 .powergates = NULL,
3591 .num_cpu_powergates = 0,
3592 .cpu_powergates = NULL,
3593 .has_tsense_reset = false,
3594 .has_gpu_clamps = false,
3595 .needs_mbist_war = false,
3596 .has_impl_33v_pwr = true,
3597 .maybe_tz_only = false,
3598 .num_io_pads = ARRAY_SIZE(tegra186_io_pads),
3599 .io_pads = tegra186_io_pads,
3600 .num_pin_descs = ARRAY_SIZE(tegra186_pin_descs),
3601 .pin_descs = tegra186_pin_descs,
3602 .regs = &tegra186_pmc_regs,
3603 .init = NULL,
3604 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity,
3605 .irq_set_wake = tegra186_pmc_irq_set_wake,
3606 .irq_set_type = tegra186_pmc_irq_set_type,
3607 .reset_sources = tegra186_reset_sources,
3608 .num_reset_sources = ARRAY_SIZE(tegra186_reset_sources),
3609 .reset_levels = tegra186_reset_levels,
3610 .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels),
3611 .num_wake_events = ARRAY_SIZE(tegra186_wake_events),
3612 .wake_events = tegra186_wake_events,
3613 .pmc_clks_data = NULL,
3614 .num_pmc_clks = 0,
3615 .has_blink_output = false,
3616 .has_usb_sleepwalk = false,
3617};
3618
3619#define TEGRA194_IO_PAD_TABLE(_pad) \
3620 \
3621 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \
3622 _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csib"), \
3623 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \
3624 _pad(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, UINT_MAX, "pex-clk-bias"), \
3625 _pad(TEGRA_IO_PAD_PEX_CLK3, 5, UINT_MAX, "pex-clk3"), \
3626 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \
3627 _pad(TEGRA_IO_PAD_PEX_CLK1, 7, UINT_MAX, "pex-clk1"), \
3628 _pad(TEGRA_IO_PAD_EQOS, 8, UINT_MAX, "eqos"), \
3629 _pad(TEGRA_IO_PAD_PEX_CLK_2_BIAS, 9, UINT_MAX, "pex-clk-2-bias"), \
3630 _pad(TEGRA_IO_PAD_PEX_CLK_2, 10, UINT_MAX, "pex-clk-2"), \
3631 _pad(TEGRA_IO_PAD_DAP3, 11, UINT_MAX, "dap3"), \
3632 _pad(TEGRA_IO_PAD_DAP5, 12, UINT_MAX, "dap5"), \
3633 _pad(TEGRA_IO_PAD_UART, 14, UINT_MAX, "uart"), \
3634 _pad(TEGRA_IO_PAD_PWR_CTL, 15, UINT_MAX, "pwr-ctl"), \
3635 _pad(TEGRA_IO_PAD_SOC_GPIO53, 16, UINT_MAX, "soc-gpio53"), \
3636 _pad(TEGRA_IO_PAD_AUDIO, 17, UINT_MAX, "audio"), \
3637 _pad(TEGRA_IO_PAD_GP_PWM2, 18, UINT_MAX, "gp-pwm2"), \
3638 _pad(TEGRA_IO_PAD_GP_PWM3, 19, UINT_MAX, "gp-pwm3"), \
3639 _pad(TEGRA_IO_PAD_SOC_GPIO12, 20, UINT_MAX, "soc-gpio12"), \
3640 _pad(TEGRA_IO_PAD_SOC_GPIO13, 21, UINT_MAX, "soc-gpio13"), \
3641 _pad(TEGRA_IO_PAD_SOC_GPIO10, 22, UINT_MAX, "soc-gpio10"), \
3642 _pad(TEGRA_IO_PAD_UART4, 23, UINT_MAX, "uart4"), \
3643 _pad(TEGRA_IO_PAD_UART5, 24, UINT_MAX, "uart5"), \
3644 _pad(TEGRA_IO_PAD_DBG, 25, UINT_MAX, "dbg"), \
3645 _pad(TEGRA_IO_PAD_HDMI_DP3, 26, UINT_MAX, "hdmi-dp3"), \
3646 _pad(TEGRA_IO_PAD_HDMI_DP2, 27, UINT_MAX, "hdmi-dp2"), \
3647 _pad(TEGRA_IO_PAD_HDMI_DP0, 28, UINT_MAX, "hdmi-dp0"), \
3648 _pad(TEGRA_IO_PAD_HDMI_DP1, 29, UINT_MAX, "hdmi-dp1"), \
3649 _pad(TEGRA_IO_PAD_PEX_CNTRL, 32, UINT_MAX, "pex-cntrl"), \
3650 _pad(TEGRA_IO_PAD_PEX_CTL2, 33, UINT_MAX, "pex-ctl2"), \
3651 _pad(TEGRA_IO_PAD_PEX_L0_RST_N, 34, UINT_MAX, "pex-l0-rst"), \
3652 _pad(TEGRA_IO_PAD_PEX_L1_RST_N, 35, UINT_MAX, "pex-l1-rst"), \
3653 _pad(TEGRA_IO_PAD_SDMMC4, 36, UINT_MAX, "sdmmc4"), \
3654 _pad(TEGRA_IO_PAD_PEX_L5_RST_N, 37, UINT_MAX, "pex-l5-rst"), \
3655 _pad(TEGRA_IO_PAD_CAM, 38, UINT_MAX, "cam"), \
3656 _pad(TEGRA_IO_PAD_CSIC, 43, UINT_MAX, "csic"), \
3657 _pad(TEGRA_IO_PAD_CSID, 44, UINT_MAX, "csid"), \
3658 _pad(TEGRA_IO_PAD_CSIE, 45, UINT_MAX, "csie"), \
3659 _pad(TEGRA_IO_PAD_CSIF, 46, UINT_MAX, "csif"), \
3660 _pad(TEGRA_IO_PAD_SPI, 47, UINT_MAX, "spi"), \
3661 _pad(TEGRA_IO_PAD_UFS, 49, UINT_MAX, "ufs"), \
3662 _pad(TEGRA_IO_PAD_CSIG, 50, UINT_MAX, "csig"), \
3663 _pad(TEGRA_IO_PAD_CSIH, 51, UINT_MAX, "csih"), \
3664 _pad(TEGRA_IO_PAD_EDP, 53, UINT_MAX, "edp"), \
3665 _pad(TEGRA_IO_PAD_SDMMC1_HV, 55, 4, "sdmmc1-hv"), \
3666 _pad(TEGRA_IO_PAD_SDMMC3_HV, 56, 6, "sdmmc3-hv"), \
3667 _pad(TEGRA_IO_PAD_CONN, 60, UINT_MAX, "conn"), \
3668 _pad(TEGRA_IO_PAD_AUDIO_HV, 61, 1, "audio-hv"), \
3669 _pad(TEGRA_IO_PAD_AO_HV, UINT_MAX, 0, "ao-hv")
3670
3671static const struct tegra_io_pad_soc tegra194_io_pads[] = {
3672 TEGRA194_IO_PAD_TABLE(TEGRA_IO_PAD)
3673};
3674
3675static const struct pinctrl_pin_desc tegra194_pin_descs[] = {
3676 TEGRA194_IO_PAD_TABLE(TEGRA_IO_PIN_DESC)
3677};
3678
3679static const struct tegra_pmc_regs tegra194_pmc_regs = {
3680 .scratch0 = 0x2000,
3681 .dpd_req = 0x74,
3682 .dpd_status = 0x78,
3683 .dpd2_req = 0x7c,
3684 .dpd2_status = 0x80,
3685 .rst_status = 0x70,
3686 .rst_source_shift = 0x2,
3687 .rst_source_mask = 0x7c,
3688 .rst_level_shift = 0x0,
3689 .rst_level_mask = 0x3,
3690};
3691
3692static const char * const tegra194_reset_sources[] = {
3693 "SYS_RESET_N",
3694 "AOWDT",
3695 "BCCPLEXWDT",
3696 "BPMPWDT",
3697 "SCEWDT",
3698 "SPEWDT",
3699 "APEWDT",
3700 "LCCPLEXWDT",
3701 "SENSOR",
3702 "AOTAG",
3703 "VFSENSOR",
3704 "MAINSWRST",
3705 "SC7",
3706 "HSM",
3707 "CSITE",
3708 "RCEWDT",
3709 "PVA0WDT",
3710 "PVA1WDT",
3711 "L1A_ASYNC",
3712 "BPMPBOOT",
3713 "FUSECRC",
3714};
3715
3716static const struct tegra_wake_event tegra194_wake_events[] = {
3717 TEGRA_WAKE_IRQ("pmu", 24, 209),
3718 TEGRA_WAKE_GPIO("power", 29, 1, TEGRA194_AON_GPIO(EE, 4)),
3719 TEGRA_WAKE_IRQ("rtc", 73, 10),
3720};
3721
3722static const struct tegra_pmc_soc tegra194_pmc_soc = {
3723 .supports_core_domain = false,
3724 .num_powergates = 0,
3725 .powergates = NULL,
3726 .num_cpu_powergates = 0,
3727 .cpu_powergates = NULL,
3728 .has_tsense_reset = false,
3729 .has_gpu_clamps = false,
3730 .needs_mbist_war = false,
3731 .has_impl_33v_pwr = true,
3732 .maybe_tz_only = false,
3733 .num_io_pads = ARRAY_SIZE(tegra194_io_pads),
3734 .io_pads = tegra194_io_pads,
3735 .num_pin_descs = ARRAY_SIZE(tegra194_pin_descs),
3736 .pin_descs = tegra194_pin_descs,
3737 .regs = &tegra194_pmc_regs,
3738 .init = NULL,
3739 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity,
3740 .irq_set_wake = tegra186_pmc_irq_set_wake,
3741 .irq_set_type = tegra186_pmc_irq_set_type,
3742 .reset_sources = tegra194_reset_sources,
3743 .num_reset_sources = ARRAY_SIZE(tegra194_reset_sources),
3744 .reset_levels = tegra186_reset_levels,
3745 .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels),
3746 .num_wake_events = ARRAY_SIZE(tegra194_wake_events),
3747 .wake_events = tegra194_wake_events,
3748 .pmc_clks_data = NULL,
3749 .num_pmc_clks = 0,
3750 .has_blink_output = false,
3751 .has_usb_sleepwalk = false,
3752};
3753
3754static const struct tegra_pmc_regs tegra234_pmc_regs = {
3755 .scratch0 = 0x2000,
3756 .dpd_req = 0,
3757 .dpd_status = 0,
3758 .dpd2_req = 0,
3759 .dpd2_status = 0,
3760 .rst_status = 0x70,
3761 .rst_source_shift = 0x2,
3762 .rst_source_mask = 0xfc,
3763 .rst_level_shift = 0x0,
3764 .rst_level_mask = 0x3,
3765};
3766
3767static const char * const tegra234_reset_sources[] = {
3768 "SYS_RESET_N",
3769 "AOWDT",
3770 "BCCPLEXWDT",
3771 "BPMPWDT",
3772 "SCEWDT",
3773 "SPEWDT",
3774 "APEWDT",
3775 "LCCPLEXWDT",
3776 "SENSOR",
3777 "AOTAG",
3778 "VFSENSOR",
3779 "MAINSWRST",
3780 "SC7",
3781 "HSM",
3782 "CSITE",
3783 "RCEWDT",
3784 "PVA0WDT",
3785 "PVA1WDT",
3786 "L1A_ASYNC",
3787 "BPMPBOOT",
3788 "FUSECRC",
3789};
3790
3791static const struct tegra_pmc_soc tegra234_pmc_soc = {
3792 .supports_core_domain = false,
3793 .num_powergates = 0,
3794 .powergates = NULL,
3795 .num_cpu_powergates = 0,
3796 .cpu_powergates = NULL,
3797 .has_tsense_reset = false,
3798 .has_gpu_clamps = false,
3799 .needs_mbist_war = false,
3800 .has_impl_33v_pwr = true,
3801 .maybe_tz_only = false,
3802 .num_io_pads = 0,
3803 .io_pads = NULL,
3804 .num_pin_descs = 0,
3805 .pin_descs = NULL,
3806 .regs = &tegra234_pmc_regs,
3807 .init = NULL,
3808 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity,
3809 .irq_set_wake = tegra186_pmc_irq_set_wake,
3810 .irq_set_type = tegra186_pmc_irq_set_type,
3811 .reset_sources = tegra234_reset_sources,
3812 .num_reset_sources = ARRAY_SIZE(tegra234_reset_sources),
3813 .reset_levels = tegra186_reset_levels,
3814 .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels),
3815 .num_wake_events = 0,
3816 .wake_events = NULL,
3817 .pmc_clks_data = NULL,
3818 .num_pmc_clks = 0,
3819 .has_blink_output = false,
3820};
3821
3822static const struct of_device_id tegra_pmc_match[] = {
3823 { .compatible = "nvidia,tegra234-pmc", .data = &tegra234_pmc_soc },
3824 { .compatible = "nvidia,tegra194-pmc", .data = &tegra194_pmc_soc },
3825 { .compatible = "nvidia,tegra186-pmc", .data = &tegra186_pmc_soc },
3826 { .compatible = "nvidia,tegra210-pmc", .data = &tegra210_pmc_soc },
3827 { .compatible = "nvidia,tegra132-pmc", .data = &tegra124_pmc_soc },
3828 { .compatible = "nvidia,tegra124-pmc", .data = &tegra124_pmc_soc },
3829 { .compatible = "nvidia,tegra114-pmc", .data = &tegra114_pmc_soc },
3830 { .compatible = "nvidia,tegra30-pmc", .data = &tegra30_pmc_soc },
3831 { .compatible = "nvidia,tegra20-pmc", .data = &tegra20_pmc_soc },
3832 { }
3833};
3834
3835static void tegra_pmc_sync_state(struct device *dev)
3836{
3837 int err;
3838
3839
3840
3841
3842
3843
3844 if (!pmc->soc->supports_core_domain)
3845 return;
3846
3847
3848
3849
3850
3851
3852 if (!pmc->core_domain_registered)
3853 return;
3854
3855 pmc->core_domain_state_synced = true;
3856
3857
3858 mutex_lock(&pmc->powergates_lock);
3859 err = dev_pm_opp_sync_regulators(dev);
3860 mutex_unlock(&pmc->powergates_lock);
3861
3862 if (err)
3863 dev_err(dev, "failed to sync regulators: %d\n", err);
3864}
3865
3866static struct platform_driver tegra_pmc_driver = {
3867 .driver = {
3868 .name = "tegra-pmc",
3869 .suppress_bind_attrs = true,
3870 .of_match_table = tegra_pmc_match,
3871#if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM)
3872 .pm = &tegra_pmc_pm_ops,
3873#endif
3874 .sync_state = tegra_pmc_sync_state,
3875 },
3876 .probe = tegra_pmc_probe,
3877};
3878builtin_platform_driver(tegra_pmc_driver);
3879
3880static bool __init tegra_pmc_detect_tz_only(struct tegra_pmc *pmc)
3881{
3882 u32 value, saved;
3883
3884 saved = readl(pmc->base + pmc->soc->regs->scratch0);
3885 value = saved ^ 0xffffffff;
3886
3887 if (value == 0xffffffff)
3888 value = 0xdeadbeef;
3889
3890
3891 writel(value, pmc->base + pmc->soc->regs->scratch0);
3892 value = readl(pmc->base + pmc->soc->regs->scratch0);
3893
3894
3895 if (value == 0) {
3896 pr_info("access to PMC is restricted to TZ\n");
3897 return true;
3898 }
3899
3900
3901 writel(saved, pmc->base + pmc->soc->regs->scratch0);
3902
3903 return false;
3904}
3905
3906
3907
3908
3909
3910static int __init tegra_pmc_early_init(void)
3911{
3912 const struct of_device_id *match;
3913 struct device_node *np;
3914 struct resource regs;
3915 unsigned int i;
3916 bool invert;
3917
3918 mutex_init(&pmc->powergates_lock);
3919
3920 np = of_find_matching_node_and_match(NULL, tegra_pmc_match, &match);
3921 if (!np) {
3922
3923
3924
3925
3926
3927
3928
3929
3930
3931
3932 if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) {
3933 pr_warn("DT node not found, powergating disabled\n");
3934
3935 regs.start = 0x7000e400;
3936 regs.end = 0x7000e7ff;
3937 regs.flags = IORESOURCE_MEM;
3938
3939 pr_warn("Using memory region %pR\n", ®s);
3940 } else {
3941
3942
3943
3944
3945 return 0;
3946 }
3947 } else {
3948
3949
3950
3951
3952 if (of_address_to_resource(np, 0, ®s) < 0) {
3953 pr_err("failed to get PMC registers\n");
3954 of_node_put(np);
3955 return -ENXIO;
3956 }
3957 }
3958
3959 pmc->base = ioremap(regs.start, resource_size(®s));
3960 if (!pmc->base) {
3961 pr_err("failed to map PMC registers\n");
3962 of_node_put(np);
3963 return -ENXIO;
3964 }
3965
3966 if (np) {
3967 pmc->soc = match->data;
3968
3969 if (pmc->soc->maybe_tz_only)
3970 pmc->tz_only = tegra_pmc_detect_tz_only(pmc);
3971
3972
3973 for (i = 0; i < pmc->soc->num_powergates; i++)
3974 if (pmc->soc->powergates[i])
3975 set_bit(i, pmc->powergates_available);
3976
3977
3978
3979
3980
3981 invert = of_property_read_bool(np, "nvidia,invert-interrupt");
3982
3983 pmc->soc->setup_irq_polarity(pmc, np, invert);
3984
3985 of_node_put(np);
3986 }
3987
3988 return 0;
3989}
3990early_initcall(tegra_pmc_early_init);
3991