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11#include <linux/kernel.h>
12#include <linux/module.h>
13#include <linux/delay.h>
14#include <linux/spinlock.h>
15#include <linux/platform_device.h>
16#include <linux/io.h>
17#include <linux/spi/spi.h>
18#include <linux/spi/spi_bitbang.h>
19#include <linux/bitops.h>
20#include <linux/clk.h>
21#include <linux/err.h>
22
23#define DRV_NAME "ath79-spi"
24
25#define ATH79_SPI_RRW_DELAY_FACTOR 12000
26#define MHZ (1000 * 1000)
27
28#define AR71XX_SPI_REG_FS 0x00
29#define AR71XX_SPI_REG_CTRL 0x04
30#define AR71XX_SPI_REG_IOC 0x08
31#define AR71XX_SPI_REG_RDS 0x0c
32
33#define AR71XX_SPI_FS_GPIO BIT(0)
34
35#define AR71XX_SPI_IOC_DO BIT(0)
36#define AR71XX_SPI_IOC_CLK BIT(8)
37#define AR71XX_SPI_IOC_CS(n) BIT(16 + (n))
38
39struct ath79_spi {
40 struct spi_bitbang bitbang;
41 u32 ioc_base;
42 u32 reg_ctrl;
43 void __iomem *base;
44 struct clk *clk;
45 unsigned int rrw_delay;
46};
47
48static inline u32 ath79_spi_rr(struct ath79_spi *sp, unsigned int reg)
49{
50 return ioread32(sp->base + reg);
51}
52
53static inline void ath79_spi_wr(struct ath79_spi *sp, unsigned int reg, u32 val)
54{
55 iowrite32(val, sp->base + reg);
56}
57
58static inline struct ath79_spi *ath79_spidev_to_sp(struct spi_device *spi)
59{
60 return spi_master_get_devdata(spi->master);
61}
62
63static inline void ath79_spi_delay(struct ath79_spi *sp, unsigned int nsecs)
64{
65 if (nsecs > sp->rrw_delay)
66 ndelay(nsecs - sp->rrw_delay);
67}
68
69static void ath79_spi_chipselect(struct spi_device *spi, int is_active)
70{
71 struct ath79_spi *sp = ath79_spidev_to_sp(spi);
72 int cs_high = (spi->mode & SPI_CS_HIGH) ? is_active : !is_active;
73 u32 cs_bit = AR71XX_SPI_IOC_CS(spi->chip_select);
74
75 if (cs_high)
76 sp->ioc_base |= cs_bit;
77 else
78 sp->ioc_base &= ~cs_bit;
79
80 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
81}
82
83static void ath79_spi_enable(struct ath79_spi *sp)
84{
85
86 ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO);
87
88
89 sp->reg_ctrl = ath79_spi_rr(sp, AR71XX_SPI_REG_CTRL);
90 sp->ioc_base = ath79_spi_rr(sp, AR71XX_SPI_REG_IOC);
91
92
93 sp->ioc_base &= ~(AR71XX_SPI_IOC_DO | AR71XX_SPI_IOC_CLK);
94
95
96 ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, 0x43);
97}
98
99static void ath79_spi_disable(struct ath79_spi *sp)
100{
101
102 ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, sp->reg_ctrl);
103
104 ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0);
105}
106
107static u32 ath79_spi_txrx_mode0(struct spi_device *spi, unsigned int nsecs,
108 u32 word, u8 bits, unsigned flags)
109{
110 struct ath79_spi *sp = ath79_spidev_to_sp(spi);
111 u32 ioc = sp->ioc_base;
112
113
114 for (word <<= (32 - bits); likely(bits); bits--) {
115 u32 out;
116
117 if (word & (1 << 31))
118 out = ioc | AR71XX_SPI_IOC_DO;
119 else
120 out = ioc & ~AR71XX_SPI_IOC_DO;
121
122
123 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out);
124 ath79_spi_delay(sp, nsecs);
125 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out | AR71XX_SPI_IOC_CLK);
126 ath79_spi_delay(sp, nsecs);
127 if (bits == 1)
128 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out);
129
130 word <<= 1;
131 }
132
133 return ath79_spi_rr(sp, AR71XX_SPI_REG_RDS);
134}
135
136static int ath79_spi_probe(struct platform_device *pdev)
137{
138 struct spi_master *master;
139 struct ath79_spi *sp;
140 unsigned long rate;
141 int ret;
142
143 master = spi_alloc_master(&pdev->dev, sizeof(*sp));
144 if (master == NULL) {
145 dev_err(&pdev->dev, "failed to allocate spi master\n");
146 return -ENOMEM;
147 }
148
149 sp = spi_master_get_devdata(master);
150 master->dev.of_node = pdev->dev.of_node;
151 platform_set_drvdata(pdev, sp);
152
153 master->use_gpio_descriptors = true;
154 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
155 master->flags = SPI_MASTER_GPIO_SS;
156 master->num_chipselect = 3;
157
158 sp->bitbang.master = master;
159 sp->bitbang.chipselect = ath79_spi_chipselect;
160 sp->bitbang.txrx_word[SPI_MODE_0] = ath79_spi_txrx_mode0;
161 sp->bitbang.flags = SPI_CS_HIGH;
162
163 sp->base = devm_platform_ioremap_resource(pdev, 0);
164 if (IS_ERR(sp->base)) {
165 ret = PTR_ERR(sp->base);
166 goto err_put_master;
167 }
168
169 sp->clk = devm_clk_get(&pdev->dev, "ahb");
170 if (IS_ERR(sp->clk)) {
171 ret = PTR_ERR(sp->clk);
172 goto err_put_master;
173 }
174
175 ret = clk_prepare_enable(sp->clk);
176 if (ret)
177 goto err_put_master;
178
179 rate = DIV_ROUND_UP(clk_get_rate(sp->clk), MHZ);
180 if (!rate) {
181 ret = -EINVAL;
182 goto err_clk_disable;
183 }
184
185 sp->rrw_delay = ATH79_SPI_RRW_DELAY_FACTOR / rate;
186 dev_dbg(&pdev->dev, "register read/write delay is %u nsecs\n",
187 sp->rrw_delay);
188
189 ath79_spi_enable(sp);
190 ret = spi_bitbang_start(&sp->bitbang);
191 if (ret)
192 goto err_disable;
193
194 return 0;
195
196err_disable:
197 ath79_spi_disable(sp);
198err_clk_disable:
199 clk_disable_unprepare(sp->clk);
200err_put_master:
201 spi_master_put(sp->bitbang.master);
202
203 return ret;
204}
205
206static int ath79_spi_remove(struct platform_device *pdev)
207{
208 struct ath79_spi *sp = platform_get_drvdata(pdev);
209
210 spi_bitbang_stop(&sp->bitbang);
211 ath79_spi_disable(sp);
212 clk_disable_unprepare(sp->clk);
213 spi_master_put(sp->bitbang.master);
214
215 return 0;
216}
217
218static void ath79_spi_shutdown(struct platform_device *pdev)
219{
220 ath79_spi_remove(pdev);
221}
222
223static const struct of_device_id ath79_spi_of_match[] = {
224 { .compatible = "qca,ar7100-spi", },
225 { },
226};
227MODULE_DEVICE_TABLE(of, ath79_spi_of_match);
228
229static struct platform_driver ath79_spi_driver = {
230 .probe = ath79_spi_probe,
231 .remove = ath79_spi_remove,
232 .shutdown = ath79_spi_shutdown,
233 .driver = {
234 .name = DRV_NAME,
235 .of_match_table = ath79_spi_of_match,
236 },
237};
238module_platform_driver(ath79_spi_driver);
239
240MODULE_DESCRIPTION("SPI controller driver for Atheros AR71XX/AR724X/AR913X");
241MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
242MODULE_LICENSE("GPL v2");
243MODULE_ALIAS("platform:" DRV_NAME);
244
