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12#include <linux/module.h>
13#include <linux/kernel.h>
14#include <linux/sched.h>
15#include <linux/errno.h>
16#include <linux/interrupt.h>
17#include <linux/platform_device.h>
18#include <linux/io.h>
19#include <linux/clk.h>
20#include <linux/dmaengine.h>
21#include <linux/dma-mapping.h>
22#include <linux/of_device.h>
23#include <linux/pm_runtime.h>
24#include <linux/reset.h>
25#include <linux/sh_dma.h>
26#include <linux/spi/spi.h>
27#include <linux/spi/rspi.h>
28#include <linux/spinlock.h>
29
30#define RSPI_SPCR 0x00
31#define RSPI_SSLP 0x01
32#define RSPI_SPPCR 0x02
33#define RSPI_SPSR 0x03
34#define RSPI_SPDR 0x04
35#define RSPI_SPSCR 0x08
36#define RSPI_SPSSR 0x09
37#define RSPI_SPBR 0x0a
38#define RSPI_SPDCR 0x0b
39#define RSPI_SPCKD 0x0c
40#define RSPI_SSLND 0x0d
41#define RSPI_SPND 0x0e
42#define RSPI_SPCR2 0x0f
43#define RSPI_SPCMD0 0x10
44#define RSPI_SPCMD1 0x12
45#define RSPI_SPCMD2 0x14
46#define RSPI_SPCMD3 0x16
47#define RSPI_SPCMD4 0x18
48#define RSPI_SPCMD5 0x1a
49#define RSPI_SPCMD6 0x1c
50#define RSPI_SPCMD7 0x1e
51#define RSPI_SPCMD(i) (RSPI_SPCMD0 + (i) * 2)
52#define RSPI_NUM_SPCMD 8
53#define RSPI_RZ_NUM_SPCMD 4
54#define QSPI_NUM_SPCMD 4
55
56
57#define RSPI_SPBFCR 0x20
58#define RSPI_SPBFDR 0x22
59
60
61#define QSPI_SPBFCR 0x18
62#define QSPI_SPBDCR 0x1a
63#define QSPI_SPBMUL0 0x1c
64#define QSPI_SPBMUL1 0x20
65#define QSPI_SPBMUL2 0x24
66#define QSPI_SPBMUL3 0x28
67#define QSPI_SPBMUL(i) (QSPI_SPBMUL0 + (i) * 4)
68
69
70#define SPCR_SPRIE 0x80
71#define SPCR_SPE 0x40
72#define SPCR_SPTIE 0x20
73#define SPCR_SPEIE 0x10
74#define SPCR_MSTR 0x08
75#define SPCR_MODFEN 0x04
76
77#define SPCR_TXMD 0x02
78#define SPCR_SPMS 0x01
79
80#define SPCR_WSWAP 0x02
81#define SPCR_BSWAP 0x01
82
83
84#define SSLP_SSLP(i) BIT(i)
85
86
87#define SPPCR_MOIFE 0x20
88#define SPPCR_MOIFV 0x10
89#define SPPCR_SPOM 0x04
90#define SPPCR_SPLP2 0x02
91#define SPPCR_SPLP 0x01
92
93#define SPPCR_IO3FV 0x04
94#define SPPCR_IO2FV 0x04
95
96
97#define SPSR_SPRF 0x80
98#define SPSR_TEND 0x40
99#define SPSR_SPTEF 0x20
100#define SPSR_PERF 0x08
101#define SPSR_MODF 0x04
102#define SPSR_IDLNF 0x02
103#define SPSR_OVRF 0x01
104
105
106#define SPSCR_SPSLN_MASK 0x07
107
108
109#define SPSSR_SPECM_MASK 0x70
110#define SPSSR_SPCP_MASK 0x07
111
112
113#define SPDCR_TXDMY 0x80
114#define SPDCR_SPLW1 0x40
115#define SPDCR_SPLW0 0x20
116#define SPDCR_SPLLWORD (SPDCR_SPLW1 | SPDCR_SPLW0)
117#define SPDCR_SPLWORD SPDCR_SPLW1
118#define SPDCR_SPLBYTE SPDCR_SPLW0
119#define SPDCR_SPLW 0x20
120#define SPDCR_SPRDTD 0x10
121#define SPDCR_SLSEL1 0x08
122#define SPDCR_SLSEL0 0x04
123#define SPDCR_SLSEL_MASK 0x0c
124#define SPDCR_SPFC1 0x02
125#define SPDCR_SPFC0 0x01
126#define SPDCR_SPFC_MASK 0x03
127
128
129#define SPCKD_SCKDL_MASK 0x07
130
131
132#define SSLND_SLNDL_MASK 0x07
133
134
135#define SPND_SPNDL_MASK 0x07
136
137
138#define SPCR2_PTE 0x08
139#define SPCR2_SPIE 0x04
140#define SPCR2_SPOE 0x02
141#define SPCR2_SPPE 0x01
142
143
144#define SPCMD_SCKDEN 0x8000
145#define SPCMD_SLNDEN 0x4000
146#define SPCMD_SPNDEN 0x2000
147#define SPCMD_LSBF 0x1000
148#define SPCMD_SPB_MASK 0x0f00
149#define SPCMD_SPB_8_TO_16(bit) (((bit - 1) << 8) & SPCMD_SPB_MASK)
150#define SPCMD_SPB_8BIT 0x0000
151#define SPCMD_SPB_16BIT 0x0100
152#define SPCMD_SPB_20BIT 0x0000
153#define SPCMD_SPB_24BIT 0x0100
154#define SPCMD_SPB_32BIT 0x0200
155#define SPCMD_SSLKP 0x0080
156#define SPCMD_SPIMOD_MASK 0x0060
157#define SPCMD_SPIMOD1 0x0040
158#define SPCMD_SPIMOD0 0x0020
159#define SPCMD_SPIMOD_SINGLE 0
160#define SPCMD_SPIMOD_DUAL SPCMD_SPIMOD0
161#define SPCMD_SPIMOD_QUAD SPCMD_SPIMOD1
162#define SPCMD_SPRW 0x0010
163#define SPCMD_SSLA(i) ((i) << 4)
164#define SPCMD_BRDV_MASK 0x000c
165#define SPCMD_BRDV(brdv) ((brdv) << 2)
166#define SPCMD_CPOL 0x0002
167#define SPCMD_CPHA 0x0001
168
169
170#define SPBFCR_TXRST 0x80
171#define SPBFCR_RXRST 0x40
172#define SPBFCR_TXTRG_MASK 0x30
173#define SPBFCR_RXTRG_MASK 0x07
174
175#define SPBFCR_TXTRG_1B 0x00
176#define SPBFCR_TXTRG_32B 0x30
177#define SPBFCR_RXTRG_1B 0x00
178#define SPBFCR_RXTRG_32B 0x07
179
180#define QSPI_BUFFER_SIZE 32u
181
182struct rspi_data {
183 void __iomem *addr;
184 u32 speed_hz;
185 struct spi_controller *ctlr;
186 struct platform_device *pdev;
187 wait_queue_head_t wait;
188 spinlock_t lock;
189 struct clk *clk;
190 u16 spcmd;
191 u8 spsr;
192 u8 sppcr;
193 int rx_irq, tx_irq;
194 const struct spi_ops *ops;
195
196 unsigned dma_callbacked:1;
197 unsigned byte_access:1;
198};
199
200static void rspi_write8(const struct rspi_data *rspi, u8 data, u16 offset)
201{
202 iowrite8(data, rspi->addr + offset);
203}
204
205static void rspi_write16(const struct rspi_data *rspi, u16 data, u16 offset)
206{
207 iowrite16(data, rspi->addr + offset);
208}
209
210static void rspi_write32(const struct rspi_data *rspi, u32 data, u16 offset)
211{
212 iowrite32(data, rspi->addr + offset);
213}
214
215static u8 rspi_read8(const struct rspi_data *rspi, u16 offset)
216{
217 return ioread8(rspi->addr + offset);
218}
219
220static u16 rspi_read16(const struct rspi_data *rspi, u16 offset)
221{
222 return ioread16(rspi->addr + offset);
223}
224
225static void rspi_write_data(const struct rspi_data *rspi, u16 data)
226{
227 if (rspi->byte_access)
228 rspi_write8(rspi, data, RSPI_SPDR);
229 else
230 rspi_write16(rspi, data, RSPI_SPDR);
231}
232
233static u16 rspi_read_data(const struct rspi_data *rspi)
234{
235 if (rspi->byte_access)
236 return rspi_read8(rspi, RSPI_SPDR);
237 else
238 return rspi_read16(rspi, RSPI_SPDR);
239}
240
241
242struct spi_ops {
243 int (*set_config_register)(struct rspi_data *rspi, int access_size);
244 int (*transfer_one)(struct spi_controller *ctlr,
245 struct spi_device *spi, struct spi_transfer *xfer);
246 u16 extra_mode_bits;
247 u16 min_div;
248 u16 max_div;
249 u16 flags;
250 u16 fifo_size;
251 u8 num_hw_ss;
252};
253
254static void rspi_set_rate(struct rspi_data *rspi)
255{
256 unsigned long clksrc;
257 int brdv = 0, spbr;
258
259 clksrc = clk_get_rate(rspi->clk);
260 spbr = DIV_ROUND_UP(clksrc, 2 * rspi->speed_hz) - 1;
261 while (spbr > 255 && brdv < 3) {
262 brdv++;
263 spbr = DIV_ROUND_UP(spbr + 1, 2) - 1;
264 }
265
266 rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR);
267 rspi->spcmd |= SPCMD_BRDV(brdv);
268 rspi->speed_hz = DIV_ROUND_UP(clksrc, (2U << brdv) * (spbr + 1));
269}
270
271
272
273
274static int rspi_set_config_register(struct rspi_data *rspi, int access_size)
275{
276
277 rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);
278
279
280 rspi_set_rate(rspi);
281
282
283 rspi_write8(rspi, 0, RSPI_SPDCR);
284 rspi->byte_access = 0;
285
286
287 rspi_write8(rspi, 0x00, RSPI_SPCKD);
288 rspi_write8(rspi, 0x00, RSPI_SSLND);
289 rspi_write8(rspi, 0x00, RSPI_SPND);
290
291
292 rspi_write8(rspi, 0x00, RSPI_SPCR2);
293
294
295 rspi_write8(rspi, 0, RSPI_SPSCR);
296 rspi->spcmd |= SPCMD_SPB_8_TO_16(access_size);
297 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
298
299
300 rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR);
301
302 return 0;
303}
304
305
306
307
308static int rspi_rz_set_config_register(struct rspi_data *rspi, int access_size)
309{
310
311 rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);
312
313
314 rspi_set_rate(rspi);
315
316
317 rspi_write8(rspi, SPDCR_SPLBYTE, RSPI_SPDCR);
318 rspi->byte_access = 1;
319
320
321 rspi_write8(rspi, 0x00, RSPI_SPCKD);
322 rspi_write8(rspi, 0x00, RSPI_SSLND);
323 rspi_write8(rspi, 0x00, RSPI_SPND);
324
325
326 rspi_write8(rspi, 0, RSPI_SPSCR);
327 rspi->spcmd |= SPCMD_SPB_8_TO_16(access_size);
328 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
329
330
331 rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR);
332
333 return 0;
334}
335
336
337
338
339static int qspi_set_config_register(struct rspi_data *rspi, int access_size)
340{
341 unsigned long clksrc;
342 int brdv = 0, spbr;
343
344
345 rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);
346
347
348 clksrc = clk_get_rate(rspi->clk);
349 if (rspi->speed_hz >= clksrc) {
350 spbr = 0;
351 rspi->speed_hz = clksrc;
352 } else {
353 spbr = DIV_ROUND_UP(clksrc, 2 * rspi->speed_hz);
354 while (spbr > 255 && brdv < 3) {
355 brdv++;
356 spbr = DIV_ROUND_UP(spbr, 2);
357 }
358 spbr = clamp(spbr, 0, 255);
359 rspi->speed_hz = DIV_ROUND_UP(clksrc, (2U << brdv) * spbr);
360 }
361 rspi_write8(rspi, spbr, RSPI_SPBR);
362 rspi->spcmd |= SPCMD_BRDV(brdv);
363
364
365 rspi_write8(rspi, 0, RSPI_SPDCR);
366 rspi->byte_access = 1;
367
368
369 rspi_write8(rspi, 0x00, RSPI_SPCKD);
370 rspi_write8(rspi, 0x00, RSPI_SSLND);
371 rspi_write8(rspi, 0x00, RSPI_SPND);
372
373
374 if (access_size == 8)
375 rspi->spcmd |= SPCMD_SPB_8BIT;
376 else if (access_size == 16)
377 rspi->spcmd |= SPCMD_SPB_16BIT;
378 else
379 rspi->spcmd |= SPCMD_SPB_32BIT;
380
381 rspi->spcmd |= SPCMD_SCKDEN | SPCMD_SLNDEN | SPCMD_SPNDEN;
382
383
384 rspi_write32(rspi, 0, QSPI_SPBMUL0);
385
386
387 rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR);
388
389 rspi_write8(rspi, 0x00, QSPI_SPBFCR);
390
391
392 rspi_write8(rspi, 0, RSPI_SPSCR);
393 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
394
395
396 rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR);
397
398 return 0;
399}
400
401static void qspi_update(const struct rspi_data *rspi, u8 mask, u8 val, u8 reg)
402{
403 u8 data;
404
405 data = rspi_read8(rspi, reg);
406 data &= ~mask;
407 data |= (val & mask);
408 rspi_write8(rspi, data, reg);
409}
410
411static unsigned int qspi_set_send_trigger(struct rspi_data *rspi,
412 unsigned int len)
413{
414 unsigned int n;
415
416 n = min(len, QSPI_BUFFER_SIZE);
417
418 if (len >= QSPI_BUFFER_SIZE) {
419
420 qspi_update(rspi, SPBFCR_TXTRG_MASK,
421 SPBFCR_TXTRG_32B, QSPI_SPBFCR);
422 } else {
423
424 qspi_update(rspi, SPBFCR_TXTRG_MASK,
425 SPBFCR_TXTRG_1B, QSPI_SPBFCR);
426 }
427
428 return n;
429}
430
431static int qspi_set_receive_trigger(struct rspi_data *rspi, unsigned int len)
432{
433 unsigned int n;
434
435 n = min(len, QSPI_BUFFER_SIZE);
436
437 if (len >= QSPI_BUFFER_SIZE) {
438
439 qspi_update(rspi, SPBFCR_RXTRG_MASK,
440 SPBFCR_RXTRG_32B, QSPI_SPBFCR);
441 } else {
442
443 qspi_update(rspi, SPBFCR_RXTRG_MASK,
444 SPBFCR_RXTRG_1B, QSPI_SPBFCR);
445 }
446 return n;
447}
448
449static void rspi_enable_irq(const struct rspi_data *rspi, u8 enable)
450{
451 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | enable, RSPI_SPCR);
452}
453
454static void rspi_disable_irq(const struct rspi_data *rspi, u8 disable)
455{
456 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~disable, RSPI_SPCR);
457}
458
459static int rspi_wait_for_interrupt(struct rspi_data *rspi, u8 wait_mask,
460 u8 enable_bit)
461{
462 int ret;
463
464 rspi->spsr = rspi_read8(rspi, RSPI_SPSR);
465 if (rspi->spsr & wait_mask)
466 return 0;
467
468 rspi_enable_irq(rspi, enable_bit);
469 ret = wait_event_timeout(rspi->wait, rspi->spsr & wait_mask, HZ);
470 if (ret == 0 && !(rspi->spsr & wait_mask))
471 return -ETIMEDOUT;
472
473 return 0;
474}
475
476static inline int rspi_wait_for_tx_empty(struct rspi_data *rspi)
477{
478 return rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE);
479}
480
481static inline int rspi_wait_for_rx_full(struct rspi_data *rspi)
482{
483 return rspi_wait_for_interrupt(rspi, SPSR_SPRF, SPCR_SPRIE);
484}
485
486static int rspi_data_out(struct rspi_data *rspi, u8 data)
487{
488 int error = rspi_wait_for_tx_empty(rspi);
489 if (error < 0) {
490 dev_err(&rspi->ctlr->dev, "transmit timeout\n");
491 return error;
492 }
493 rspi_write_data(rspi, data);
494 return 0;
495}
496
497static int rspi_data_in(struct rspi_data *rspi)
498{
499 int error;
500 u8 data;
501
502 error = rspi_wait_for_rx_full(rspi);
503 if (error < 0) {
504 dev_err(&rspi->ctlr->dev, "receive timeout\n");
505 return error;
506 }
507 data = rspi_read_data(rspi);
508 return data;
509}
510
511static int rspi_pio_transfer(struct rspi_data *rspi, const u8 *tx, u8 *rx,
512 unsigned int n)
513{
514 while (n-- > 0) {
515 if (tx) {
516 int ret = rspi_data_out(rspi, *tx++);
517 if (ret < 0)
518 return ret;
519 }
520 if (rx) {
521 int ret = rspi_data_in(rspi);
522 if (ret < 0)
523 return ret;
524 *rx++ = ret;
525 }
526 }
527
528 return 0;
529}
530
531static void rspi_dma_complete(void *arg)
532{
533 struct rspi_data *rspi = arg;
534
535 rspi->dma_callbacked = 1;
536 wake_up_interruptible(&rspi->wait);
537}
538
539static int rspi_dma_transfer(struct rspi_data *rspi, struct sg_table *tx,
540 struct sg_table *rx)
541{
542 struct dma_async_tx_descriptor *desc_tx = NULL, *desc_rx = NULL;
543 u8 irq_mask = 0;
544 unsigned int other_irq = 0;
545 dma_cookie_t cookie;
546 int ret;
547
548
549 if (rx) {
550 desc_rx = dmaengine_prep_slave_sg(rspi->ctlr->dma_rx, rx->sgl,
551 rx->nents, DMA_DEV_TO_MEM,
552 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
553 if (!desc_rx) {
554 ret = -EAGAIN;
555 goto no_dma_rx;
556 }
557
558 desc_rx->callback = rspi_dma_complete;
559 desc_rx->callback_param = rspi;
560 cookie = dmaengine_submit(desc_rx);
561 if (dma_submit_error(cookie)) {
562 ret = cookie;
563 goto no_dma_rx;
564 }
565
566 irq_mask |= SPCR_SPRIE;
567 }
568
569 if (tx) {
570 desc_tx = dmaengine_prep_slave_sg(rspi->ctlr->dma_tx, tx->sgl,
571 tx->nents, DMA_MEM_TO_DEV,
572 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
573 if (!desc_tx) {
574 ret = -EAGAIN;
575 goto no_dma_tx;
576 }
577
578 if (rx) {
579
580 desc_tx->callback = NULL;
581 } else {
582 desc_tx->callback = rspi_dma_complete;
583 desc_tx->callback_param = rspi;
584 }
585 cookie = dmaengine_submit(desc_tx);
586 if (dma_submit_error(cookie)) {
587 ret = cookie;
588 goto no_dma_tx;
589 }
590
591 irq_mask |= SPCR_SPTIE;
592 }
593
594
595
596
597
598 if (tx)
599 disable_irq(other_irq = rspi->tx_irq);
600 if (rx && rspi->rx_irq != other_irq)
601 disable_irq(rspi->rx_irq);
602
603 rspi_enable_irq(rspi, irq_mask);
604 rspi->dma_callbacked = 0;
605
606
607 if (rx)
608 dma_async_issue_pending(rspi->ctlr->dma_rx);
609 if (tx)
610 dma_async_issue_pending(rspi->ctlr->dma_tx);
611
612 ret = wait_event_interruptible_timeout(rspi->wait,
613 rspi->dma_callbacked, HZ);
614 if (ret > 0 && rspi->dma_callbacked) {
615 ret = 0;
616 } else {
617 if (!ret) {
618 dev_err(&rspi->ctlr->dev, "DMA timeout\n");
619 ret = -ETIMEDOUT;
620 }
621 if (tx)
622 dmaengine_terminate_sync(rspi->ctlr->dma_tx);
623 if (rx)
624 dmaengine_terminate_sync(rspi->ctlr->dma_rx);
625 }
626
627 rspi_disable_irq(rspi, irq_mask);
628
629 if (tx)
630 enable_irq(rspi->tx_irq);
631 if (rx && rspi->rx_irq != other_irq)
632 enable_irq(rspi->rx_irq);
633
634 return ret;
635
636no_dma_tx:
637 if (rx)
638 dmaengine_terminate_sync(rspi->ctlr->dma_rx);
639no_dma_rx:
640 if (ret == -EAGAIN) {
641 dev_warn_once(&rspi->ctlr->dev,
642 "DMA not available, falling back to PIO\n");
643 }
644 return ret;
645}
646
647static void rspi_receive_init(const struct rspi_data *rspi)
648{
649 u8 spsr;
650
651 spsr = rspi_read8(rspi, RSPI_SPSR);
652 if (spsr & SPSR_SPRF)
653 rspi_read_data(rspi);
654 if (spsr & SPSR_OVRF)
655 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPSR) & ~SPSR_OVRF,
656 RSPI_SPSR);
657}
658
659static void rspi_rz_receive_init(const struct rspi_data *rspi)
660{
661 rspi_receive_init(rspi);
662 rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, RSPI_SPBFCR);
663 rspi_write8(rspi, 0, RSPI_SPBFCR);
664}
665
666static void qspi_receive_init(const struct rspi_data *rspi)
667{
668 u8 spsr;
669
670 spsr = rspi_read8(rspi, RSPI_SPSR);
671 if (spsr & SPSR_SPRF)
672 rspi_read_data(rspi);
673 rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR);
674 rspi_write8(rspi, 0, QSPI_SPBFCR);
675}
676
677static bool __rspi_can_dma(const struct rspi_data *rspi,
678 const struct spi_transfer *xfer)
679{
680 return xfer->len > rspi->ops->fifo_size;
681}
682
683static bool rspi_can_dma(struct spi_controller *ctlr, struct spi_device *spi,
684 struct spi_transfer *xfer)
685{
686 struct rspi_data *rspi = spi_controller_get_devdata(ctlr);
687
688 return __rspi_can_dma(rspi, xfer);
689}
690
691static int rspi_dma_check_then_transfer(struct rspi_data *rspi,
692 struct spi_transfer *xfer)
693{
694 if (!rspi->ctlr->can_dma || !__rspi_can_dma(rspi, xfer))
695 return -EAGAIN;
696
697
698 return rspi_dma_transfer(rspi, &xfer->tx_sg,
699 xfer->rx_buf ? &xfer->rx_sg : NULL);
700}
701
702static int rspi_common_transfer(struct rspi_data *rspi,
703 struct spi_transfer *xfer)
704{
705 int ret;
706
707 xfer->effective_speed_hz = rspi->speed_hz;
708
709 ret = rspi_dma_check_then_transfer(rspi, xfer);
710 if (ret != -EAGAIN)
711 return ret;
712
713 ret = rspi_pio_transfer(rspi, xfer->tx_buf, xfer->rx_buf, xfer->len);
714 if (ret < 0)
715 return ret;
716
717
718 rspi_wait_for_tx_empty(rspi);
719
720 return 0;
721}
722
723static int rspi_transfer_one(struct spi_controller *ctlr,
724 struct spi_device *spi, struct spi_transfer *xfer)
725{
726 struct rspi_data *rspi = spi_controller_get_devdata(ctlr);
727 u8 spcr;
728
729 spcr = rspi_read8(rspi, RSPI_SPCR);
730 if (xfer->rx_buf) {
731 rspi_receive_init(rspi);
732 spcr &= ~SPCR_TXMD;
733 } else {
734 spcr |= SPCR_TXMD;
735 }
736 rspi_write8(rspi, spcr, RSPI_SPCR);
737
738 return rspi_common_transfer(rspi, xfer);
739}
740
741static int rspi_rz_transfer_one(struct spi_controller *ctlr,
742 struct spi_device *spi,
743 struct spi_transfer *xfer)
744{
745 struct rspi_data *rspi = spi_controller_get_devdata(ctlr);
746
747 rspi_rz_receive_init(rspi);
748
749 return rspi_common_transfer(rspi, xfer);
750}
751
752static int qspi_trigger_transfer_out_in(struct rspi_data *rspi, const u8 *tx,
753 u8 *rx, unsigned int len)
754{
755 unsigned int i, n;
756 int ret;
757
758 while (len > 0) {
759 n = qspi_set_send_trigger(rspi, len);
760 qspi_set_receive_trigger(rspi, len);
761 ret = rspi_wait_for_tx_empty(rspi);
762 if (ret < 0) {
763 dev_err(&rspi->ctlr->dev, "transmit timeout\n");
764 return ret;
765 }
766 for (i = 0; i < n; i++)
767 rspi_write_data(rspi, *tx++);
768
769 ret = rspi_wait_for_rx_full(rspi);
770 if (ret < 0) {
771 dev_err(&rspi->ctlr->dev, "receive timeout\n");
772 return ret;
773 }
774 for (i = 0; i < n; i++)
775 *rx++ = rspi_read_data(rspi);
776
777 len -= n;
778 }
779
780 return 0;
781}
782
783static int qspi_transfer_out_in(struct rspi_data *rspi,
784 struct spi_transfer *xfer)
785{
786 int ret;
787
788 qspi_receive_init(rspi);
789
790 ret = rspi_dma_check_then_transfer(rspi, xfer);
791 if (ret != -EAGAIN)
792 return ret;
793
794 return qspi_trigger_transfer_out_in(rspi, xfer->tx_buf,
795 xfer->rx_buf, xfer->len);
796}
797
798static int qspi_transfer_out(struct rspi_data *rspi, struct spi_transfer *xfer)
799{
800 const u8 *tx = xfer->tx_buf;
801 unsigned int n = xfer->len;
802 unsigned int i, len;
803 int ret;
804
805 if (rspi->ctlr->can_dma && __rspi_can_dma(rspi, xfer)) {
806 ret = rspi_dma_transfer(rspi, &xfer->tx_sg, NULL);
807 if (ret != -EAGAIN)
808 return ret;
809 }
810
811 while (n > 0) {
812 len = qspi_set_send_trigger(rspi, n);
813 ret = rspi_wait_for_tx_empty(rspi);
814 if (ret < 0) {
815 dev_err(&rspi->ctlr->dev, "transmit timeout\n");
816 return ret;
817 }
818 for (i = 0; i < len; i++)
819 rspi_write_data(rspi, *tx++);
820
821 n -= len;
822 }
823
824
825 rspi_wait_for_tx_empty(rspi);
826
827 return 0;
828}
829
830static int qspi_transfer_in(struct rspi_data *rspi, struct spi_transfer *xfer)
831{
832 u8 *rx = xfer->rx_buf;
833 unsigned int n = xfer->len;
834 unsigned int i, len;
835 int ret;
836
837 if (rspi->ctlr->can_dma && __rspi_can_dma(rspi, xfer)) {
838 ret = rspi_dma_transfer(rspi, NULL, &xfer->rx_sg);
839 if (ret != -EAGAIN)
840 return ret;
841 }
842
843 while (n > 0) {
844 len = qspi_set_receive_trigger(rspi, n);
845 ret = rspi_wait_for_rx_full(rspi);
846 if (ret < 0) {
847 dev_err(&rspi->ctlr->dev, "receive timeout\n");
848 return ret;
849 }
850 for (i = 0; i < len; i++)
851 *rx++ = rspi_read_data(rspi);
852
853 n -= len;
854 }
855
856 return 0;
857}
858
859static int qspi_transfer_one(struct spi_controller *ctlr,
860 struct spi_device *spi, struct spi_transfer *xfer)
861{
862 struct rspi_data *rspi = spi_controller_get_devdata(ctlr);
863
864 xfer->effective_speed_hz = rspi->speed_hz;
865 if (spi->mode & SPI_LOOP) {
866 return qspi_transfer_out_in(rspi, xfer);
867 } else if (xfer->tx_nbits > SPI_NBITS_SINGLE) {
868
869 return qspi_transfer_out(rspi, xfer);
870 } else if (xfer->rx_nbits > SPI_NBITS_SINGLE) {
871
872 return qspi_transfer_in(rspi, xfer);
873 } else {
874
875 return qspi_transfer_out_in(rspi, xfer);
876 }
877}
878
879static u16 qspi_transfer_mode(const struct spi_transfer *xfer)
880{
881 if (xfer->tx_buf)
882 switch (xfer->tx_nbits) {
883 case SPI_NBITS_QUAD:
884 return SPCMD_SPIMOD_QUAD;
885 case SPI_NBITS_DUAL:
886 return SPCMD_SPIMOD_DUAL;
887 default:
888 return 0;
889 }
890 if (xfer->rx_buf)
891 switch (xfer->rx_nbits) {
892 case SPI_NBITS_QUAD:
893 return SPCMD_SPIMOD_QUAD | SPCMD_SPRW;
894 case SPI_NBITS_DUAL:
895 return SPCMD_SPIMOD_DUAL | SPCMD_SPRW;
896 default:
897 return 0;
898 }
899
900 return 0;
901}
902
903static int qspi_setup_sequencer(struct rspi_data *rspi,
904 const struct spi_message *msg)
905{
906 const struct spi_transfer *xfer;
907 unsigned int i = 0, len = 0;
908 u16 current_mode = 0xffff, mode;
909
910 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
911 mode = qspi_transfer_mode(xfer);
912 if (mode == current_mode) {
913 len += xfer->len;
914 continue;
915 }
916
917
918 if (i) {
919
920 rspi_write32(rspi, len, QSPI_SPBMUL(i - 1));
921 }
922
923 if (i >= QSPI_NUM_SPCMD) {
924 dev_err(&msg->spi->dev,
925 "Too many different transfer modes");
926 return -EINVAL;
927 }
928
929
930 rspi_write16(rspi, rspi->spcmd | mode, RSPI_SPCMD(i));
931 current_mode = mode;
932 len = xfer->len;
933 i++;
934 }
935 if (i) {
936
937 rspi_write32(rspi, len, QSPI_SPBMUL(i - 1));
938 rspi_write8(rspi, i - 1, RSPI_SPSCR);
939 }
940
941 return 0;
942}
943
944static int rspi_setup(struct spi_device *spi)
945{
946 struct rspi_data *rspi = spi_controller_get_devdata(spi->controller);
947 u8 sslp;
948
949 if (spi->cs_gpiod)
950 return 0;
951
952 pm_runtime_get_sync(&rspi->pdev->dev);
953 spin_lock_irq(&rspi->lock);
954
955 sslp = rspi_read8(rspi, RSPI_SSLP);
956 if (spi->mode & SPI_CS_HIGH)
957 sslp |= SSLP_SSLP(spi->chip_select);
958 else
959 sslp &= ~SSLP_SSLP(spi->chip_select);
960 rspi_write8(rspi, sslp, RSPI_SSLP);
961
962 spin_unlock_irq(&rspi->lock);
963 pm_runtime_put(&rspi->pdev->dev);
964 return 0;
965}
966
967static int rspi_prepare_message(struct spi_controller *ctlr,
968 struct spi_message *msg)
969{
970 struct rspi_data *rspi = spi_controller_get_devdata(ctlr);
971 struct spi_device *spi = msg->spi;
972 const struct spi_transfer *xfer;
973 int ret;
974
975
976
977
978
979
980
981
982
983
984
985 rspi->speed_hz = spi->max_speed_hz;
986 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
987 if (xfer->speed_hz < rspi->speed_hz)
988 rspi->speed_hz = xfer->speed_hz;
989 }
990
991 rspi->spcmd = SPCMD_SSLKP;
992 if (spi->mode & SPI_CPOL)
993 rspi->spcmd |= SPCMD_CPOL;
994 if (spi->mode & SPI_CPHA)
995 rspi->spcmd |= SPCMD_CPHA;
996 if (spi->mode & SPI_LSB_FIRST)
997 rspi->spcmd |= SPCMD_LSBF;
998
999
1000 rspi->spcmd |= SPCMD_SSLA(spi->cs_gpiod ? rspi->ctlr->unused_native_cs
1001 : spi->chip_select);
1002
1003
1004 rspi->sppcr = 0;
1005 if (spi->mode & SPI_LOOP)
1006 rspi->sppcr |= SPPCR_SPLP;
1007
1008 rspi->ops->set_config_register(rspi, 8);
1009
1010 if (msg->spi->mode &
1011 (SPI_TX_DUAL | SPI_TX_QUAD | SPI_RX_DUAL | SPI_RX_QUAD)) {
1012
1013 ret = qspi_setup_sequencer(rspi, msg);
1014 if (ret < 0)
1015 return ret;
1016 }
1017
1018
1019 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_SPE, RSPI_SPCR);
1020 return 0;
1021}
1022
1023static int rspi_unprepare_message(struct spi_controller *ctlr,
1024 struct spi_message *msg)
1025{
1026 struct rspi_data *rspi = spi_controller_get_devdata(ctlr);
1027
1028
1029 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_SPE, RSPI_SPCR);
1030
1031
1032 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
1033 rspi_write8(rspi, 0, RSPI_SPSCR);
1034 return 0;
1035}
1036
1037static irqreturn_t rspi_irq_mux(int irq, void *_sr)
1038{
1039 struct rspi_data *rspi = _sr;
1040 u8 spsr;
1041 irqreturn_t ret = IRQ_NONE;
1042 u8 disable_irq = 0;
1043
1044 rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR);
1045 if (spsr & SPSR_SPRF)
1046 disable_irq |= SPCR_SPRIE;
1047 if (spsr & SPSR_SPTEF)
1048 disable_irq |= SPCR_SPTIE;
1049
1050 if (disable_irq) {
1051 ret = IRQ_HANDLED;
1052 rspi_disable_irq(rspi, disable_irq);
1053 wake_up(&rspi->wait);
1054 }
1055
1056 return ret;
1057}
1058
1059static irqreturn_t rspi_irq_rx(int irq, void *_sr)
1060{
1061 struct rspi_data *rspi = _sr;
1062 u8 spsr;
1063
1064 rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR);
1065 if (spsr & SPSR_SPRF) {
1066 rspi_disable_irq(rspi, SPCR_SPRIE);
1067 wake_up(&rspi->wait);
1068 return IRQ_HANDLED;
1069 }
1070
1071 return 0;
1072}
1073
1074static irqreturn_t rspi_irq_tx(int irq, void *_sr)
1075{
1076 struct rspi_data *rspi = _sr;
1077 u8 spsr;
1078
1079 rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR);
1080 if (spsr & SPSR_SPTEF) {
1081 rspi_disable_irq(rspi, SPCR_SPTIE);
1082 wake_up(&rspi->wait);
1083 return IRQ_HANDLED;
1084 }
1085
1086 return 0;
1087}
1088
1089static struct dma_chan *rspi_request_dma_chan(struct device *dev,
1090 enum dma_transfer_direction dir,
1091 unsigned int id,
1092 dma_addr_t port_addr)
1093{
1094 dma_cap_mask_t mask;
1095 struct dma_chan *chan;
1096 struct dma_slave_config cfg;
1097 int ret;
1098
1099 dma_cap_zero(mask);
1100 dma_cap_set(DMA_SLAVE, mask);
1101
1102 chan = dma_request_slave_channel_compat(mask, shdma_chan_filter,
1103 (void *)(unsigned long)id, dev,
1104 dir == DMA_MEM_TO_DEV ? "tx" : "rx");
1105 if (!chan) {
1106 dev_warn(dev, "dma_request_slave_channel_compat failed\n");
1107 return NULL;
1108 }
1109
1110 memset(&cfg, 0, sizeof(cfg));
1111 cfg.direction = dir;
1112 if (dir == DMA_MEM_TO_DEV) {
1113 cfg.dst_addr = port_addr;
1114 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1115 } else {
1116 cfg.src_addr = port_addr;
1117 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1118 }
1119
1120 ret = dmaengine_slave_config(chan, &cfg);
1121 if (ret) {
1122 dev_warn(dev, "dmaengine_slave_config failed %d\n", ret);
1123 dma_release_channel(chan);
1124 return NULL;
1125 }
1126
1127 return chan;
1128}
1129
1130static int rspi_request_dma(struct device *dev, struct spi_controller *ctlr,
1131 const struct resource *res)
1132{
1133 const struct rspi_plat_data *rspi_pd = dev_get_platdata(dev);
1134 unsigned int dma_tx_id, dma_rx_id;
1135
1136 if (dev->of_node) {
1137
1138 dma_tx_id = 0;
1139 dma_rx_id = 0;
1140 } else if (rspi_pd && rspi_pd->dma_tx_id && rspi_pd->dma_rx_id) {
1141 dma_tx_id = rspi_pd->dma_tx_id;
1142 dma_rx_id = rspi_pd->dma_rx_id;
1143 } else {
1144
1145 return 0;
1146 }
1147
1148 ctlr->dma_tx = rspi_request_dma_chan(dev, DMA_MEM_TO_DEV, dma_tx_id,
1149 res->start + RSPI_SPDR);
1150 if (!ctlr->dma_tx)
1151 return -ENODEV;
1152
1153 ctlr->dma_rx = rspi_request_dma_chan(dev, DMA_DEV_TO_MEM, dma_rx_id,
1154 res->start + RSPI_SPDR);
1155 if (!ctlr->dma_rx) {
1156 dma_release_channel(ctlr->dma_tx);
1157 ctlr->dma_tx = NULL;
1158 return -ENODEV;
1159 }
1160
1161 ctlr->can_dma = rspi_can_dma;
1162 dev_info(dev, "DMA available");
1163 return 0;
1164}
1165
1166static void rspi_release_dma(struct spi_controller *ctlr)
1167{
1168 if (ctlr->dma_tx)
1169 dma_release_channel(ctlr->dma_tx);
1170 if (ctlr->dma_rx)
1171 dma_release_channel(ctlr->dma_rx);
1172}
1173
1174static int rspi_remove(struct platform_device *pdev)
1175{
1176 struct rspi_data *rspi = platform_get_drvdata(pdev);
1177
1178 rspi_release_dma(rspi->ctlr);
1179 pm_runtime_disable(&pdev->dev);
1180
1181 return 0;
1182}
1183
1184static const struct spi_ops rspi_ops = {
1185 .set_config_register = rspi_set_config_register,
1186 .transfer_one = rspi_transfer_one,
1187 .min_div = 2,
1188 .max_div = 4096,
1189 .flags = SPI_CONTROLLER_MUST_TX,
1190 .fifo_size = 8,
1191 .num_hw_ss = 2,
1192};
1193
1194static const struct spi_ops rspi_rz_ops = {
1195 .set_config_register = rspi_rz_set_config_register,
1196 .transfer_one = rspi_rz_transfer_one,
1197 .min_div = 2,
1198 .max_div = 4096,
1199 .flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX,
1200 .fifo_size = 8,
1201 .num_hw_ss = 1,
1202};
1203
1204static const struct spi_ops qspi_ops = {
1205 .set_config_register = qspi_set_config_register,
1206 .transfer_one = qspi_transfer_one,
1207 .extra_mode_bits = SPI_TX_DUAL | SPI_TX_QUAD |
1208 SPI_RX_DUAL | SPI_RX_QUAD,
1209 .min_div = 1,
1210 .max_div = 4080,
1211 .flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX,
1212 .fifo_size = 32,
1213 .num_hw_ss = 1,
1214};
1215
1216#ifdef CONFIG_OF
1217static const struct of_device_id rspi_of_match[] = {
1218
1219 { .compatible = "renesas,rspi", .data = &rspi_ops },
1220
1221 { .compatible = "renesas,rspi-rz", .data = &rspi_rz_ops },
1222
1223 { .compatible = "renesas,qspi", .data = &qspi_ops },
1224 { }
1225};
1226
1227MODULE_DEVICE_TABLE(of, rspi_of_match);
1228
1229static void rspi_reset_control_assert(void *data)
1230{
1231 reset_control_assert(data);
1232}
1233
1234static int rspi_parse_dt(struct device *dev, struct spi_controller *ctlr)
1235{
1236 struct reset_control *rstc;
1237 u32 num_cs;
1238 int error;
1239
1240
1241 error = of_property_read_u32(dev->of_node, "num-cs", &num_cs);
1242 if (error) {
1243 dev_err(dev, "of_property_read_u32 num-cs failed %d\n", error);
1244 return error;
1245 }
1246
1247 ctlr->num_chipselect = num_cs;
1248
1249 rstc = devm_reset_control_get_optional_exclusive(dev, NULL);
1250 if (IS_ERR(rstc))
1251 return dev_err_probe(dev, PTR_ERR(rstc),
1252 "failed to get reset ctrl\n");
1253
1254 error = reset_control_deassert(rstc);
1255 if (error) {
1256 dev_err(dev, "failed to deassert reset %d\n", error);
1257 return error;
1258 }
1259
1260 error = devm_add_action_or_reset(dev, rspi_reset_control_assert, rstc);
1261 if (error) {
1262 dev_err(dev, "failed to register assert devm action, %d\n", error);
1263 return error;
1264 }
1265
1266 return 0;
1267}
1268#else
1269#define rspi_of_match NULL
1270static inline int rspi_parse_dt(struct device *dev, struct spi_controller *ctlr)
1271{
1272 return -EINVAL;
1273}
1274#endif
1275
1276static int rspi_request_irq(struct device *dev, unsigned int irq,
1277 irq_handler_t handler, const char *suffix,
1278 void *dev_id)
1279{
1280 const char *name = devm_kasprintf(dev, GFP_KERNEL, "%s:%s",
1281 dev_name(dev), suffix);
1282 if (!name)
1283 return -ENOMEM;
1284
1285 return devm_request_irq(dev, irq, handler, 0, name, dev_id);
1286}
1287
1288static int rspi_probe(struct platform_device *pdev)
1289{
1290 struct resource *res;
1291 struct spi_controller *ctlr;
1292 struct rspi_data *rspi;
1293 int ret;
1294 const struct rspi_plat_data *rspi_pd;
1295 const struct spi_ops *ops;
1296 unsigned long clksrc;
1297
1298 ctlr = spi_alloc_master(&pdev->dev, sizeof(struct rspi_data));
1299 if (ctlr == NULL)
1300 return -ENOMEM;
1301
1302 ops = of_device_get_match_data(&pdev->dev);
1303 if (ops) {
1304 ret = rspi_parse_dt(&pdev->dev, ctlr);
1305 if (ret)
1306 goto error1;
1307 } else {
1308 ops = (struct spi_ops *)pdev->id_entry->driver_data;
1309 rspi_pd = dev_get_platdata(&pdev->dev);
1310 if (rspi_pd && rspi_pd->num_chipselect)
1311 ctlr->num_chipselect = rspi_pd->num_chipselect;
1312 else
1313 ctlr->num_chipselect = 2;
1314 }
1315
1316 rspi = spi_controller_get_devdata(ctlr);
1317 platform_set_drvdata(pdev, rspi);
1318 rspi->ops = ops;
1319 rspi->ctlr = ctlr;
1320
1321 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1322 rspi->addr = devm_ioremap_resource(&pdev->dev, res);
1323 if (IS_ERR(rspi->addr)) {
1324 ret = PTR_ERR(rspi->addr);
1325 goto error1;
1326 }
1327
1328 rspi->clk = devm_clk_get(&pdev->dev, NULL);
1329 if (IS_ERR(rspi->clk)) {
1330 dev_err(&pdev->dev, "cannot get clock\n");
1331 ret = PTR_ERR(rspi->clk);
1332 goto error1;
1333 }
1334
1335 rspi->pdev = pdev;
1336 pm_runtime_enable(&pdev->dev);
1337
1338 init_waitqueue_head(&rspi->wait);
1339 spin_lock_init(&rspi->lock);
1340
1341 ctlr->bus_num = pdev->id;
1342 ctlr->setup = rspi_setup;
1343 ctlr->auto_runtime_pm = true;
1344 ctlr->transfer_one = ops->transfer_one;
1345 ctlr->prepare_message = rspi_prepare_message;
1346 ctlr->unprepare_message = rspi_unprepare_message;
1347 ctlr->mode_bits = SPI_CPHA | SPI_CPOL | SPI_CS_HIGH | SPI_LSB_FIRST |
1348 SPI_LOOP | ops->extra_mode_bits;
1349 clksrc = clk_get_rate(rspi->clk);
1350 ctlr->min_speed_hz = DIV_ROUND_UP(clksrc, ops->max_div);
1351 ctlr->max_speed_hz = DIV_ROUND_UP(clksrc, ops->min_div);
1352 ctlr->flags = ops->flags;
1353 ctlr->dev.of_node = pdev->dev.of_node;
1354 ctlr->use_gpio_descriptors = true;
1355 ctlr->max_native_cs = rspi->ops->num_hw_ss;
1356
1357 ret = platform_get_irq_byname_optional(pdev, "rx");
1358 if (ret < 0) {
1359 ret = platform_get_irq_byname_optional(pdev, "mux");
1360 if (ret < 0)
1361 ret = platform_get_irq(pdev, 0);
1362 if (ret >= 0)
1363 rspi->rx_irq = rspi->tx_irq = ret;
1364 } else {
1365 rspi->rx_irq = ret;
1366 ret = platform_get_irq_byname(pdev, "tx");
1367 if (ret >= 0)
1368 rspi->tx_irq = ret;
1369 }
1370
1371 if (rspi->rx_irq == rspi->tx_irq) {
1372
1373 ret = rspi_request_irq(&pdev->dev, rspi->rx_irq, rspi_irq_mux,
1374 "mux", rspi);
1375 } else {
1376
1377 ret = rspi_request_irq(&pdev->dev, rspi->rx_irq, rspi_irq_rx,
1378 "rx", rspi);
1379 if (!ret)
1380 ret = rspi_request_irq(&pdev->dev, rspi->tx_irq,
1381 rspi_irq_tx, "tx", rspi);
1382 }
1383 if (ret < 0) {
1384 dev_err(&pdev->dev, "request_irq error\n");
1385 goto error2;
1386 }
1387
1388 ret = rspi_request_dma(&pdev->dev, ctlr, res);
1389 if (ret < 0)
1390 dev_warn(&pdev->dev, "DMA not available, using PIO\n");
1391
1392 ret = devm_spi_register_controller(&pdev->dev, ctlr);
1393 if (ret < 0) {
1394 dev_err(&pdev->dev, "devm_spi_register_controller error.\n");
1395 goto error3;
1396 }
1397
1398 dev_info(&pdev->dev, "probed\n");
1399
1400 return 0;
1401
1402error3:
1403 rspi_release_dma(ctlr);
1404error2:
1405 pm_runtime_disable(&pdev->dev);
1406error1:
1407 spi_controller_put(ctlr);
1408
1409 return ret;
1410}
1411
1412static const struct platform_device_id spi_driver_ids[] = {
1413 { "rspi", (kernel_ulong_t)&rspi_ops },
1414 {},
1415};
1416
1417MODULE_DEVICE_TABLE(platform, spi_driver_ids);
1418
1419#ifdef CONFIG_PM_SLEEP
1420static int rspi_suspend(struct device *dev)
1421{
1422 struct rspi_data *rspi = dev_get_drvdata(dev);
1423
1424 return spi_controller_suspend(rspi->ctlr);
1425}
1426
1427static int rspi_resume(struct device *dev)
1428{
1429 struct rspi_data *rspi = dev_get_drvdata(dev);
1430
1431 return spi_controller_resume(rspi->ctlr);
1432}
1433
1434static SIMPLE_DEV_PM_OPS(rspi_pm_ops, rspi_suspend, rspi_resume);
1435#define DEV_PM_OPS &rspi_pm_ops
1436#else
1437#define DEV_PM_OPS NULL
1438#endif
1439
1440static struct platform_driver rspi_driver = {
1441 .probe = rspi_probe,
1442 .remove = rspi_remove,
1443 .id_table = spi_driver_ids,
1444 .driver = {
1445 .name = "renesas_spi",
1446 .pm = DEV_PM_OPS,
1447 .of_match_table = of_match_ptr(rspi_of_match),
1448 },
1449};
1450module_platform_driver(rspi_driver);
1451
1452MODULE_DESCRIPTION("Renesas RSPI bus driver");
1453MODULE_LICENSE("GPL v2");
1454MODULE_AUTHOR("Yoshihiro Shimoda");
1455