LXR linux/drivers/staging/r8188eu/include/rtl8188e

   1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
   2/* Copyright(c) 2007 - 2011 Realtek Corporation. */
   3
   4#ifndef __RTL8188E_HAL_H__
   5#define __RTL8188E_HAL_H__
   6
   7/* include HAL Related header after HAL Related compiling flags */
   8#include "rtl8188e_spec.h"
   9#include "Hal8188EPhyReg.h"
  10#include "Hal8188EPhyCfg.h"
  11#include "rtl8188e_rf.h"
  12#include "rtl8188e_dm.h"
  13#include "rtl8188e_recv.h"
  14#include "rtl8188e_xmit.h"
  15#include "rtl8188e_cmd.h"
  16#include "rtw_efuse.h"
  17#include "odm_types.h"
  18#include "odm.h"
  19#include "odm_HWConfig.h"
  20#include "odm_RegDefine11N.h"
  21#include "HalPhyRf_8188e.h"
  22#include "Hal8188ERateAdaptive.h"
  23#include "HalHWImg8188E_MAC.h"
  24#include "HalHWImg8188E_RF.h"
  25#include "HalHWImg8188E_BB.h"
  26#include "odm_RegConfig8188E.h"
  27#include "odm_RTL8188E.h"
  28
  29/*              RTL8188E Power Configuration CMDs for USB/SDIO interfaces */
  30#define Rtl8188E_NIC_PWR_ON_FLOW                rtl8188E_power_on_flow
  31#define Rtl8188E_NIC_DISABLE_FLOW               rtl8188E_card_disable_flow
  32#define Rtl8188E_NIC_LPS_ENTER_FLOW             rtl8188E_enter_lps_flow
  33
  34#define DRVINFO_SZ      4 /*  unit is 8bytes */
  35#define PageNum_128(_Len)       (u32)(((_Len)>>7) + ((_Len) & 0x7F ? 1 : 0))
  36
  37/*  download firmware related data structure */
  38#define FW_8188E_SIZE                   0x4000 /* 16384,16k */
  39#define FW_8188E_START_ADDRESS          0x1000
  40
  41#define MAX_PAGE_SIZE                   4096    /*  @ page : 4k bytes */
  42
  43#define IS_FW_HEADER_EXIST(_pFwHdr)                             \
  44        ((le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x92C0 ||  \
  45        (le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x88C0 ||   \
  46        (le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x2300 ||   \
  47        (le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x88E0)
  48
  49/*  This structure must be careful with byte-ordering */
  50
  51struct rt_firmware_hdr {
  52        /*  8-byte alinment required */
  53        /*  LONG WORD 0 ---- */
  54        __le16          Signature;      /* 92C0: test chip; 92C,
  55                                         * 88C0: test chip; 88C1: MP A-cut;
  56                                         * 92C1: MP A-cut */
  57        u8              Category;       /*  AP/NIC and USB/PCI */
  58        u8              Function;       /*  Reserved for different FW function
  59                                         *  indcation, for further use when
  60                                         *  driver needs to download different
  61                                         *  FW for different conditions */
  62        __le16          Version;        /*  FW Version */
  63        u8              Subversion;     /*  FW Subversion, default 0x00 */
  64        u16             Rsvd1;
  65
  66        /*  LONG WORD 1 ---- */
  67        u8              Month;  /*  Release time Month field */
  68        u8              Date;   /*  Release time Date field */
  69        u8              Hour;   /*  Release time Hour field */
  70        u8              Minute; /*  Release time Minute field */
  71        __le16          RamCodeSize;    /*  The size of RAM code */
  72        u8              Foundry;
  73        u8              Rsvd2;
  74
  75        /*  LONG WORD 2 ---- */
  76        __le32          SvnIdx; /*  The SVN entry index */
  77        u32             Rsvd3;
  78
  79        /*  LONG WORD 3 ---- */
  80        u32             Rsvd4;
  81        u32             Rsvd5;
  82};
  83
  84#define DRIVER_EARLY_INT_TIME           0x05
  85#define BCN_DMA_ATIME_INT_TIME          0x02
  86
  87enum usb_rx_agg_mode {
  88        USB_RX_AGG_DISABLE,
  89        USB_RX_AGG_DMA,
  90        USB_RX_AGG_USB,
  91        USB_RX_AGG_MIX
  92};
  93
  94#define MAX_RX_DMA_BUFFER_SIZE_88E                              \
  95      0x2400 /* 9k for 88E nornal chip , MaxRxBuff=10k-max(TxReportSize(64*8),
  96              * WOLPattern(16*24)) */
  97
  98#define TX_SELE_HQ                      BIT(0)          /*  High Queue */
  99#define TX_SELE_LQ                      BIT(1)          /*  Low Queue */
 100#define TX_SELE_NQ                      BIT(2)          /*  Normal Queue */
 101
 102/*  Note: We will divide number of page equally for each queue other
 103 *  than public queue! */
 104/*  22k = 22528 bytes = 176 pages (@page =  128 bytes) */
 105/*  must reserved about 7 pages for LPS =>  176-7 = 169 (0xA9) */
 106/*  2*BCN / 1*ps-poll / 1*null-data /1*prob_rsp /1*QOS null-data /1*BT QOS
 107 *  null-data */
 108
 109#define TX_TOTAL_PAGE_NUMBER_88E                0xA9/*   169 (21632=> 21k) */
 110
 111#define TX_PAGE_BOUNDARY_88E (TX_TOTAL_PAGE_NUMBER_88E + 1)
 112
 113/* Note: For Normal Chip Setting ,modify later */
 114#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER                 \
 115        TX_TOTAL_PAGE_NUMBER_88E  /* 0xA9 , 0xb0=>176=>22k */
 116#define WMM_NORMAL_TX_PAGE_BOUNDARY_88E                 \
 117        (WMM_NORMAL_TX_TOTAL_PAGE_NUMBER + 1) /* 0xA9 */
 118
 119#include "HalVerDef.h"
 120#include "hal_com.h"
 121
 122/*      Channel Plan */
 123enum ChannelPlan {
 124        CHPL_FCC        = 0,
 125        CHPL_IC         = 1,
 126        CHPL_ETSI       = 2,
 127        CHPL_SPA        = 3,
 128        CHPL_FRANCE     = 4,
 129        CHPL_MKK        = 5,
 130        CHPL_MKK1       = 6,
 131        CHPL_ISRAEL     = 7,
 132        CHPL_TELEC      = 8,
 133        CHPL_GLOBAL     = 9,
 134        CHPL_WORLD      = 10,
 135};
 136
 137struct txpowerinfo24g {
 138        u8 IndexCCK_Base[RF_PATH_MAX][MAX_CHNL_GROUP_24G];
 139        u8 IndexBW40_Base[RF_PATH_MAX][MAX_CHNL_GROUP_24G];
 140        /* If only one tx, only BW20 and OFDM are used. */
 141        s8 CCK_Diff[RF_PATH_MAX][MAX_TX_COUNT];
 142        s8 OFDM_Diff[RF_PATH_MAX][MAX_TX_COUNT];
 143        s8 BW20_Diff[RF_PATH_MAX][MAX_TX_COUNT];
 144        s8 BW40_Diff[RF_PATH_MAX][MAX_TX_COUNT];
 145};
 146
 147#define EFUSE_REAL_CONTENT_LEN          512
 148#define AVAILABLE_EFUSE_ADDR(addr)      (addr < EFUSE_REAL_CONTENT_LEN)
 149
 150#define         EFUSE_REAL_CONTENT_LEN_88E      256
 151#define         EFUSE_MAP_LEN_88E               512
 152#define         EFUSE_MAX_SECTION_88E           64
 153/*  To prevent out of boundary programming case, leave 1byte and program
 154 *  full section */
 155/*  9bytes + 1byt + 5bytes and pre 1byte. */
 156/*  For worst case: */
 157/*  | 2byte|----8bytes----|1byte|--7bytes--| 92D */
 158/*  PG data exclude header, dummy 7 bytes frome CP test and reserved 1byte. */
 159#define         EFUSE_OOB_PROTECT_BYTES_88E     18
 160
 161#define EFUSE_PROTECT_BYTES_BANK        16
 162
 163struct hal_data_8188e {
 164        struct HAL_VERSION      VersionID;
 165        u16     FirmwareVersion;
 166        u16     FirmwareVersionRev;
 167        u16     FirmwareSubVersion;
 168        u16     FirmwareSignature;
 169        u8      PGMaxGroup;
 170        /* current WIFI_PHY values */
 171        u32     ReceiveConfig;
 172        enum ht_channel_width CurrentChannelBW;
 173        u8      CurrentChannel;
 174        u8      nCur40MhzPrimeSC;/*  Control channel sub-carrier */
 175
 176        u16     BasicRateSet;
 177
 178        u8      EEPROMRegulatory;
 179        u8      EEPROMThermalMeter;
 180
 181        u8      Index24G_CCK_Base[CHANNEL_MAX_NUMBER];
 182        u8      Index24G_BW40_Base[CHANNEL_MAX_NUMBER];
 183        /* If only one tx, only BW20 and OFDM are used. */
 184        s8      OFDM_24G_Diff[MAX_TX_COUNT];
 185        s8      BW20_24G_Diff[MAX_TX_COUNT];
 186
 187        /*  HT 20<->40 Pwr diff */
 188        u8      TxPwrHt20Diff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
 189        /*  For HT<->legacy pwr diff */
 190        u8      TxPwrLegacyHtDiff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
 191        /*  For power group */
 192        u8      PwrGroupHT20[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
 193        u8      PwrGroupHT40[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
 194
 195        /*  The current Tx Power Level */
 196        u8      CurrentCckTxPwrIdx;
 197        u8      CurrentOfdm24GTxPwrIdx;
 198        u8      CurrentBW2024GTxPwrIdx;
 199        u8      CurrentBW4024GTxPwrIdx;
 200
 201        /*  Read/write are allow for following hardware information variables */
 202        u8      pwrGroupCnt;
 203        u32     MCSTxPowerLevelOriginalOffset[MAX_PG_GROUP][16];
 204
 205        u8      CrystalCap;
 206        u8      ExternalPA;
 207
 208        u32     AcParam_BE; /* Original parameter for BE, use for EDCA turbo. */
 209
 210        struct bb_reg_def PHYRegDef[2]; /* Radio A/B */
 211
 212        u32     RfRegChnlVal[2];
 213
 214        /* for host message to fw */
 215        u8      LastHMEBoxNum;
 216
 217        u8      fw_ractrl;
 218        u8      RegFwHwTxQCtrl;
 219        u8      RegReg542;
 220        u8      RegCR_1;
 221
 222        struct dm_priv  dmpriv;
 223        struct odm_dm_struct odmpriv;
 224
 225        u8      CurAntenna;
 226        u8      AntDivCfg;
 227        u8      TRxAntDivType;
 228
 229        u8      bDumpRxPkt;/* for debug */
 230        u8      bDumpTxPkt;/* for debug */
 231
 232        u8      OutEpQueueSel;
 233        u8      OutEpNumber;
 234
 235        u16     EfuseUsedBytes;
 236
 237        struct P2P_PS_Offload_t p2p_ps_offload;
 238
 239        /*  Auto FSM to Turn On, include clock, isolation, power control
 240         *  for MAC only */
 241        u8      bMacPwrCtrlOn;
 242
 243        u32     UsbBulkOutSize;
 244
 245        u8      UsbTxAggMode;
 246        u8      UsbTxAggDescNum;
 247
 248        enum usb_rx_agg_mode UsbRxAggMode;
 249        u8      UsbRxAggBlockCount;     /*  USB Block count. Block size is
 250                                         * 512-byte in high speed and 64-byte
 251                                         * in full speed */
 252        u8      UsbRxAggBlockTimeout;
 253        u8      UsbRxAggPageCount;      /*  8192C DMA page count */
 254        u8      UsbRxAggPageTimeout;
 255};
 256
 257/*  rtl8188e_hal_init.c */
 258s32 rtl8188e_FirmwareDownload(struct adapter *padapter);
 259void _8051Reset88E(struct adapter *padapter);
 260void rtl8188e_InitializeFirmwareVars(struct adapter *padapter);
 261
 262s32 InitLLTTable(struct adapter *padapter, u8 txpktbuf_bndy);
 263
 264/*  EFuse */
 265u8 GetEEPROMSize8188E(struct adapter *padapter);
 266void Hal_EfuseParseIDCode88E(struct adapter *padapter, u8 *hwinfo);
 267void Hal_ReadTxPowerInfo88E(struct adapter *padapter, u8 *hwinfo,
 268                            bool AutoLoadFail);
 269
 270void rtl8188e_EfuseParseChnlPlan(struct adapter *padapter, u8 *hwinfo,
 271                                 bool AutoLoadFail);
 272void Hal_ReadAntennaDiversity88E(struct adapter *pAdapter,u8 *PROMContent,
 273                                 bool AutoLoadFail);
 274void Hal_ReadThermalMeter_88E(struct adapter *  dapter, u8 *PROMContent,
 275                              bool AutoloadFail);
 276void Hal_EfuseParseXtal_8188E(struct adapter *pAdapter, u8 *hwinfo,
 277                              bool AutoLoadFail);
 278void Hal_ReadPowerSavingMode88E(struct adapter *pAdapter, u8 *hwinfo,
 279                                bool AutoLoadFail);
 280
 281void rtl8188e_read_chip_version(struct adapter *padapter);
 282
 283s32 rtl8188e_iol_efuse_patch(struct adapter *padapter);
 284void rtw_cancel_all_timer(struct adapter *padapter);
 285
 286#endif /* __RTL8188E_HAL_H__ */
 287