1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * This header provides macros for ams AS3722 device bindings. 4 * 5 * Copyright (c) 2013, NVIDIA Corporation. 6 * 7 * Author: Laxman Dewangan <ldewangan@nvidia.com> 8 * 9 */ 10 11#ifndef __DT_BINDINGS_AS3722_H__ 12#define __DT_BINDINGS_AS3722_H__ 13 14/* External control pins */ 15#define AS3722_EXT_CONTROL_PIN_ENABLE1 1 16#define AS3722_EXT_CONTROL_PIN_ENABLE2 2 17#define AS3722_EXT_CONTROL_PIN_ENABLE3 3 18 19/* Interrupt numbers for AS3722 */ 20#define AS3722_IRQ_LID 0 21#define AS3722_IRQ_ACOK 1 22#define AS3722_IRQ_ENABLE1 2 23#define AS3722_IRQ_OCCUR_ALARM_SD0 3 24#define AS3722_IRQ_ONKEY_LONG_PRESS 4 25#define AS3722_IRQ_ONKEY 5 26#define AS3722_IRQ_OVTMP 6 27#define AS3722_IRQ_LOWBAT 7 28#define AS3722_IRQ_SD0_LV 8 29#define AS3722_IRQ_SD1_LV 9 30#define AS3722_IRQ_SD2_LV 10 31#define AS3722_IRQ_PWM1_OV_PROT 11 32#define AS3722_IRQ_PWM2_OV_PROT 12 33#define AS3722_IRQ_ENABLE2 13 34#define AS3722_IRQ_SD6_LV 14 35#define AS3722_IRQ_RTC_REP 15 36#define AS3722_IRQ_RTC_ALARM 16 37#define AS3722_IRQ_GPIO1 17 38#define AS3722_IRQ_GPIO2 18 39#define AS3722_IRQ_GPIO3 19 40#define AS3722_IRQ_GPIO4 20 41#define AS3722_IRQ_GPIO5 21 42#define AS3722_IRQ_WATCHDOG 22 43#define AS3722_IRQ_ENABLE3 23 44#define AS3722_IRQ_TEMP_SD0_SHUTDOWN 24 45#define AS3722_IRQ_TEMP_SD1_SHUTDOWN 25 46#define AS3722_IRQ_TEMP_SD2_SHUTDOWN 26 47#define AS3722_IRQ_TEMP_SD0_ALARM 27 48#define AS3722_IRQ_TEMP_SD1_ALARM 28 49#define AS3722_IRQ_TEMP_SD6_ALARM 29 50#define AS3722_IRQ_OCCUR_ALARM_SD6 30 51#define AS3722_IRQ_ADC 31 52 53#endif /* __DT_BINDINGS_AS3722_H__ */ 54