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32#ifndef __AMDGPU_DRM_H__
33#define __AMDGPU_DRM_H__
34
35#include "drm.h"
36
37#if defined(__cplusplus)
38extern "C" {
39#endif
40
41#define DRM_AMDGPU_GEM_CREATE 0x00
42#define DRM_AMDGPU_GEM_MMAP 0x01
43#define DRM_AMDGPU_CTX 0x02
44#define DRM_AMDGPU_BO_LIST 0x03
45#define DRM_AMDGPU_CS 0x04
46#define DRM_AMDGPU_INFO 0x05
47#define DRM_AMDGPU_GEM_METADATA 0x06
48#define DRM_AMDGPU_GEM_WAIT_IDLE 0x07
49#define DRM_AMDGPU_GEM_VA 0x08
50#define DRM_AMDGPU_WAIT_CS 0x09
51#define DRM_AMDGPU_GEM_OP 0x10
52#define DRM_AMDGPU_GEM_USERPTR 0x11
53#define DRM_AMDGPU_WAIT_FENCES 0x12
54#define DRM_AMDGPU_VM 0x13
55#define DRM_AMDGPU_FENCE_TO_HANDLE 0x14
56#define DRM_AMDGPU_SCHED 0x15
57
58#define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
59#define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
60#define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx)
61#define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list)
62#define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs)
63#define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info)
64#define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata)
65#define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle)
66#define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va)
67#define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs)
68#define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op)
69#define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr)
70#define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences)
71#define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm)
72#define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle)
73#define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched)
74
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97
98#define AMDGPU_GEM_DOMAIN_CPU 0x1
99#define AMDGPU_GEM_DOMAIN_GTT 0x2
100#define AMDGPU_GEM_DOMAIN_VRAM 0x4
101#define AMDGPU_GEM_DOMAIN_GDS 0x8
102#define AMDGPU_GEM_DOMAIN_GWS 0x10
103#define AMDGPU_GEM_DOMAIN_OA 0x20
104#define AMDGPU_GEM_DOMAIN_MASK (AMDGPU_GEM_DOMAIN_CPU | \
105 AMDGPU_GEM_DOMAIN_GTT | \
106 AMDGPU_GEM_DOMAIN_VRAM | \
107 AMDGPU_GEM_DOMAIN_GDS | \
108 AMDGPU_GEM_DOMAIN_GWS | \
109 AMDGPU_GEM_DOMAIN_OA)
110
111
112#define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0)
113
114#define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1)
115
116#define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2)
117
118#define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3)
119
120#define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5)
121
122#define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6)
123
124#define AMDGPU_GEM_CREATE_EXPLICIT_SYNC (1 << 7)
125
126
127
128
129#define AMDGPU_GEM_CREATE_CP_MQD_GFX9 (1 << 8)
130
131
132
133#define AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE (1 << 9)
134
135
136
137
138#define AMDGPU_GEM_CREATE_ENCRYPTED (1 << 10)
139
140
141
142#define AMDGPU_GEM_CREATE_PREEMPTIBLE (1 << 11)
143
144struct drm_amdgpu_gem_create_in {
145
146 __u64 bo_size;
147
148 __u64 alignment;
149
150 __u64 domains;
151
152 __u64 domain_flags;
153};
154
155struct drm_amdgpu_gem_create_out {
156
157 __u32 handle;
158 __u32 _pad;
159};
160
161union drm_amdgpu_gem_create {
162 struct drm_amdgpu_gem_create_in in;
163 struct drm_amdgpu_gem_create_out out;
164};
165
166
167#define AMDGPU_BO_LIST_OP_CREATE 0
168
169#define AMDGPU_BO_LIST_OP_DESTROY 1
170
171#define AMDGPU_BO_LIST_OP_UPDATE 2
172
173struct drm_amdgpu_bo_list_in {
174
175 __u32 operation;
176
177 __u32 list_handle;
178
179 __u32 bo_number;
180
181 __u32 bo_info_size;
182
183 __u64 bo_info_ptr;
184};
185
186struct drm_amdgpu_bo_list_entry {
187
188 __u32 bo_handle;
189
190 __u32 bo_priority;
191};
192
193struct drm_amdgpu_bo_list_out {
194
195 __u32 list_handle;
196 __u32 _pad;
197};
198
199union drm_amdgpu_bo_list {
200 struct drm_amdgpu_bo_list_in in;
201 struct drm_amdgpu_bo_list_out out;
202};
203
204
205#define AMDGPU_CTX_OP_ALLOC_CTX 1
206#define AMDGPU_CTX_OP_FREE_CTX 2
207#define AMDGPU_CTX_OP_QUERY_STATE 3
208#define AMDGPU_CTX_OP_QUERY_STATE2 4
209
210
211#define AMDGPU_CTX_NO_RESET 0
212
213#define AMDGPU_CTX_GUILTY_RESET 1
214
215#define AMDGPU_CTX_INNOCENT_RESET 2
216
217#define AMDGPU_CTX_UNKNOWN_RESET 3
218
219
220#define AMDGPU_CTX_QUERY2_FLAGS_RESET (1<<0)
221
222#define AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST (1<<1)
223
224#define AMDGPU_CTX_QUERY2_FLAGS_GUILTY (1<<2)
225
226#define AMDGPU_CTX_QUERY2_FLAGS_RAS_CE (1<<3)
227#define AMDGPU_CTX_QUERY2_FLAGS_RAS_UE (1<<4)
228
229
230#define AMDGPU_CTX_PRIORITY_UNSET -2048
231#define AMDGPU_CTX_PRIORITY_VERY_LOW -1023
232#define AMDGPU_CTX_PRIORITY_LOW -512
233#define AMDGPU_CTX_PRIORITY_NORMAL 0
234
235
236
237
238#define AMDGPU_CTX_PRIORITY_HIGH 512
239#define AMDGPU_CTX_PRIORITY_VERY_HIGH 1023
240
241struct drm_amdgpu_ctx_in {
242
243 __u32 op;
244
245 __u32 flags;
246 __u32 ctx_id;
247
248 __s32 priority;
249};
250
251union drm_amdgpu_ctx_out {
252 struct {
253 __u32 ctx_id;
254 __u32 _pad;
255 } alloc;
256
257 struct {
258
259 __u64 flags;
260
261 __u32 hangs;
262
263 __u32 reset_status;
264 } state;
265};
266
267union drm_amdgpu_ctx {
268 struct drm_amdgpu_ctx_in in;
269 union drm_amdgpu_ctx_out out;
270};
271
272
273#define AMDGPU_VM_OP_RESERVE_VMID 1
274#define AMDGPU_VM_OP_UNRESERVE_VMID 2
275
276struct drm_amdgpu_vm_in {
277
278 __u32 op;
279 __u32 flags;
280};
281
282struct drm_amdgpu_vm_out {
283
284 __u64 flags;
285};
286
287union drm_amdgpu_vm {
288 struct drm_amdgpu_vm_in in;
289 struct drm_amdgpu_vm_out out;
290};
291
292
293#define AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE 1
294#define AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE 2
295
296struct drm_amdgpu_sched_in {
297
298 __u32 op;
299 __u32 fd;
300
301 __s32 priority;
302 __u32 ctx_id;
303};
304
305union drm_amdgpu_sched {
306 struct drm_amdgpu_sched_in in;
307};
308
309
310
311
312
313
314#define AMDGPU_GEM_USERPTR_READONLY (1 << 0)
315#define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1)
316#define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2)
317#define AMDGPU_GEM_USERPTR_REGISTER (1 << 3)
318
319struct drm_amdgpu_gem_userptr {
320 __u64 addr;
321 __u64 size;
322
323 __u32 flags;
324
325 __u32 handle;
326};
327
328
329
330#define AMDGPU_TILING_ARRAY_MODE_SHIFT 0
331#define AMDGPU_TILING_ARRAY_MODE_MASK 0xf
332#define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4
333#define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f
334#define AMDGPU_TILING_TILE_SPLIT_SHIFT 9
335#define AMDGPU_TILING_TILE_SPLIT_MASK 0x7
336#define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12
337#define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7
338#define AMDGPU_TILING_BANK_WIDTH_SHIFT 15
339#define AMDGPU_TILING_BANK_WIDTH_MASK 0x3
340#define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17
341#define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3
342#define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19
343#define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3
344#define AMDGPU_TILING_NUM_BANKS_SHIFT 21
345#define AMDGPU_TILING_NUM_BANKS_MASK 0x3
346
347
348#define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0
349#define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f
350#define AMDGPU_TILING_DCC_OFFSET_256B_SHIFT 5
351#define AMDGPU_TILING_DCC_OFFSET_256B_MASK 0xFFFFFF
352#define AMDGPU_TILING_DCC_PITCH_MAX_SHIFT 29
353#define AMDGPU_TILING_DCC_PITCH_MAX_MASK 0x3FFF
354#define AMDGPU_TILING_DCC_INDEPENDENT_64B_SHIFT 43
355#define AMDGPU_TILING_DCC_INDEPENDENT_64B_MASK 0x1
356#define AMDGPU_TILING_DCC_INDEPENDENT_128B_SHIFT 44
357#define AMDGPU_TILING_DCC_INDEPENDENT_128B_MASK 0x1
358#define AMDGPU_TILING_SCANOUT_SHIFT 63
359#define AMDGPU_TILING_SCANOUT_MASK 0x1
360
361
362#define AMDGPU_TILING_SET(field, value) \
363 (((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT)
364#define AMDGPU_TILING_GET(value, field) \
365 (((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK)
366
367#define AMDGPU_GEM_METADATA_OP_SET_METADATA 1
368#define AMDGPU_GEM_METADATA_OP_GET_METADATA 2
369
370
371struct drm_amdgpu_gem_metadata {
372
373 __u32 handle;
374
375 __u32 op;
376 struct {
377
378 __u64 flags;
379
380 __u64 tiling_info;
381 __u32 data_size_bytes;
382 __u32 data[64];
383 } data;
384};
385
386struct drm_amdgpu_gem_mmap_in {
387
388 __u32 handle;
389 __u32 _pad;
390};
391
392struct drm_amdgpu_gem_mmap_out {
393
394 __u64 addr_ptr;
395};
396
397union drm_amdgpu_gem_mmap {
398 struct drm_amdgpu_gem_mmap_in in;
399 struct drm_amdgpu_gem_mmap_out out;
400};
401
402struct drm_amdgpu_gem_wait_idle_in {
403
404 __u32 handle;
405
406 __u32 flags;
407
408 __u64 timeout;
409};
410
411struct drm_amdgpu_gem_wait_idle_out {
412
413 __u32 status;
414
415 __u32 domain;
416};
417
418union drm_amdgpu_gem_wait_idle {
419 struct drm_amdgpu_gem_wait_idle_in in;
420 struct drm_amdgpu_gem_wait_idle_out out;
421};
422
423struct drm_amdgpu_wait_cs_in {
424
425
426
427
428 __u64 handle;
429
430 __u64 timeout;
431 __u32 ip_type;
432 __u32 ip_instance;
433 __u32 ring;
434 __u32 ctx_id;
435};
436
437struct drm_amdgpu_wait_cs_out {
438
439 __u64 status;
440};
441
442union drm_amdgpu_wait_cs {
443 struct drm_amdgpu_wait_cs_in in;
444 struct drm_amdgpu_wait_cs_out out;
445};
446
447struct drm_amdgpu_fence {
448 __u32 ctx_id;
449 __u32 ip_type;
450 __u32 ip_instance;
451 __u32 ring;
452 __u64 seq_no;
453};
454
455struct drm_amdgpu_wait_fences_in {
456
457 __u64 fences;
458 __u32 fence_count;
459 __u32 wait_all;
460 __u64 timeout_ns;
461};
462
463struct drm_amdgpu_wait_fences_out {
464 __u32 status;
465 __u32 first_signaled;
466};
467
468union drm_amdgpu_wait_fences {
469 struct drm_amdgpu_wait_fences_in in;
470 struct drm_amdgpu_wait_fences_out out;
471};
472
473#define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0
474#define AMDGPU_GEM_OP_SET_PLACEMENT 1
475
476
477struct drm_amdgpu_gem_op {
478
479 __u32 handle;
480
481 __u32 op;
482
483 __u64 value;
484};
485
486#define AMDGPU_VA_OP_MAP 1
487#define AMDGPU_VA_OP_UNMAP 2
488#define AMDGPU_VA_OP_CLEAR 3
489#define AMDGPU_VA_OP_REPLACE 4
490
491
492#define AMDGPU_VM_DELAY_UPDATE (1 << 0)
493
494
495
496#define AMDGPU_VM_PAGE_READABLE (1 << 1)
497
498#define AMDGPU_VM_PAGE_WRITEABLE (1 << 2)
499
500#define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3)
501
502#define AMDGPU_VM_PAGE_PRT (1 << 4)
503
504#define AMDGPU_VM_MTYPE_MASK (0xf << 5)
505
506#define AMDGPU_VM_MTYPE_DEFAULT (0 << 5)
507
508#define AMDGPU_VM_MTYPE_NC (1 << 5)
509
510#define AMDGPU_VM_MTYPE_WC (2 << 5)
511
512#define AMDGPU_VM_MTYPE_CC (3 << 5)
513
514#define AMDGPU_VM_MTYPE_UC (4 << 5)
515
516#define AMDGPU_VM_MTYPE_RW (5 << 5)
517
518struct drm_amdgpu_gem_va {
519
520 __u32 handle;
521 __u32 _pad;
522
523 __u32 operation;
524
525 __u32 flags;
526
527 __u64 va_address;
528
529 __u64 offset_in_bo;
530
531 __u64 map_size;
532};
533
534#define AMDGPU_HW_IP_GFX 0
535#define AMDGPU_HW_IP_COMPUTE 1
536#define AMDGPU_HW_IP_DMA 2
537#define AMDGPU_HW_IP_UVD 3
538#define AMDGPU_HW_IP_VCE 4
539#define AMDGPU_HW_IP_UVD_ENC 5
540#define AMDGPU_HW_IP_VCN_DEC 6
541#define AMDGPU_HW_IP_VCN_ENC 7
542#define AMDGPU_HW_IP_VCN_JPEG 8
543#define AMDGPU_HW_IP_NUM 9
544
545#define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1
546
547#define AMDGPU_CHUNK_ID_IB 0x01
548#define AMDGPU_CHUNK_ID_FENCE 0x02
549#define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03
550#define AMDGPU_CHUNK_ID_SYNCOBJ_IN 0x04
551#define AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05
552#define AMDGPU_CHUNK_ID_BO_HANDLES 0x06
553#define AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 0x07
554#define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT 0x08
555#define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL 0x09
556
557struct drm_amdgpu_cs_chunk {
558 __u32 chunk_id;
559 __u32 length_dw;
560 __u64 chunk_data;
561};
562
563struct drm_amdgpu_cs_in {
564
565 __u32 ctx_id;
566
567 __u32 bo_list_handle;
568 __u32 num_chunks;
569 __u32 flags;
570
571 __u64 chunks;
572};
573
574struct drm_amdgpu_cs_out {
575 __u64 handle;
576};
577
578union drm_amdgpu_cs {
579 struct drm_amdgpu_cs_in in;
580 struct drm_amdgpu_cs_out out;
581};
582
583
584
585
586#define AMDGPU_IB_FLAG_CE (1<<0)
587
588
589#define AMDGPU_IB_FLAG_PREAMBLE (1<<1)
590
591
592#define AMDGPU_IB_FLAG_PREEMPT (1<<2)
593
594
595
596#define AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE (1 << 3)
597
598
599
600
601#define AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID (1 << 4)
602
603
604
605#define AMDGPU_IB_FLAGS_SECURE (1 << 5)
606
607
608
609#define AMDGPU_IB_FLAG_EMIT_MEM_SYNC (1 << 6)
610
611struct drm_amdgpu_cs_chunk_ib {
612 __u32 _pad;
613
614 __u32 flags;
615
616 __u64 va_start;
617
618 __u32 ib_bytes;
619
620 __u32 ip_type;
621
622 __u32 ip_instance;
623
624 __u32 ring;
625};
626
627struct drm_amdgpu_cs_chunk_dep {
628 __u32 ip_type;
629 __u32 ip_instance;
630 __u32 ring;
631 __u32 ctx_id;
632 __u64 handle;
633};
634
635struct drm_amdgpu_cs_chunk_fence {
636 __u32 handle;
637 __u32 offset;
638};
639
640struct drm_amdgpu_cs_chunk_sem {
641 __u32 handle;
642};
643
644struct drm_amdgpu_cs_chunk_syncobj {
645 __u32 handle;
646 __u32 flags;
647 __u64 point;
648};
649
650#define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ 0
651#define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD 1
652#define AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD 2
653
654union drm_amdgpu_fence_to_handle {
655 struct {
656 struct drm_amdgpu_fence fence;
657 __u32 what;
658 __u32 pad;
659 } in;
660 struct {
661 __u32 handle;
662 } out;
663};
664
665struct drm_amdgpu_cs_chunk_data {
666 union {
667 struct drm_amdgpu_cs_chunk_ib ib_data;
668 struct drm_amdgpu_cs_chunk_fence fence_data;
669 };
670};
671
672
673
674
675
676#define AMDGPU_IDS_FLAGS_FUSION 0x1
677#define AMDGPU_IDS_FLAGS_PREEMPTION 0x2
678#define AMDGPU_IDS_FLAGS_TMZ 0x4
679
680
681#define AMDGPU_INFO_ACCEL_WORKING 0x00
682
683#define AMDGPU_INFO_CRTC_FROM_ID 0x01
684
685#define AMDGPU_INFO_HW_IP_INFO 0x02
686
687#define AMDGPU_INFO_HW_IP_COUNT 0x03
688
689#define AMDGPU_INFO_TIMESTAMP 0x05
690
691#define AMDGPU_INFO_FW_VERSION 0x0e
692
693 #define AMDGPU_INFO_FW_VCE 0x1
694
695 #define AMDGPU_INFO_FW_UVD 0x2
696
697 #define AMDGPU_INFO_FW_GMC 0x03
698
699 #define AMDGPU_INFO_FW_GFX_ME 0x04
700
701 #define AMDGPU_INFO_FW_GFX_PFP 0x05
702
703 #define AMDGPU_INFO_FW_GFX_CE 0x06
704
705 #define AMDGPU_INFO_FW_GFX_RLC 0x07
706
707 #define AMDGPU_INFO_FW_GFX_MEC 0x08
708
709 #define AMDGPU_INFO_FW_SMC 0x0a
710
711 #define AMDGPU_INFO_FW_SDMA 0x0b
712
713 #define AMDGPU_INFO_FW_SOS 0x0c
714
715 #define AMDGPU_INFO_FW_ASD 0x0d
716
717 #define AMDGPU_INFO_FW_VCN 0x0e
718
719 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL 0x0f
720
721 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM 0x10
722
723 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM 0x11
724
725 #define AMDGPU_INFO_FW_DMCU 0x12
726 #define AMDGPU_INFO_FW_TA 0x13
727
728 #define AMDGPU_INFO_FW_DMCUB 0x14
729
730 #define AMDGPU_INFO_FW_TOC 0x15
731
732
733#define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f
734
735#define AMDGPU_INFO_VRAM_USAGE 0x10
736
737#define AMDGPU_INFO_GTT_USAGE 0x11
738
739#define AMDGPU_INFO_GDS_CONFIG 0x13
740
741#define AMDGPU_INFO_VRAM_GTT 0x14
742
743#define AMDGPU_INFO_READ_MMR_REG 0x15
744
745#define AMDGPU_INFO_DEV_INFO 0x16
746
747#define AMDGPU_INFO_VIS_VRAM_USAGE 0x17
748
749#define AMDGPU_INFO_NUM_EVICTIONS 0x18
750
751#define AMDGPU_INFO_MEMORY 0x19
752
753#define AMDGPU_INFO_VCE_CLOCK_TABLE 0x1A
754
755#define AMDGPU_INFO_VBIOS 0x1B
756
757 #define AMDGPU_INFO_VBIOS_SIZE 0x1
758
759 #define AMDGPU_INFO_VBIOS_IMAGE 0x2
760
761 #define AMDGPU_INFO_VBIOS_INFO 0x3
762
763#define AMDGPU_INFO_NUM_HANDLES 0x1C
764
765#define AMDGPU_INFO_SENSOR 0x1D
766
767 #define AMDGPU_INFO_SENSOR_GFX_SCLK 0x1
768
769 #define AMDGPU_INFO_SENSOR_GFX_MCLK 0x2
770
771 #define AMDGPU_INFO_SENSOR_GPU_TEMP 0x3
772
773 #define AMDGPU_INFO_SENSOR_GPU_LOAD 0x4
774
775 #define AMDGPU_INFO_SENSOR_GPU_AVG_POWER 0x5
776
777 #define AMDGPU_INFO_SENSOR_VDDNB 0x6
778
779 #define AMDGPU_INFO_SENSOR_VDDGFX 0x7
780
781 #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK 0x8
782
783 #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK 0x9
784
785#define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E
786#define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F
787
788#define AMDGPU_INFO_RAS_ENABLED_FEATURES 0x20
789
790#define AMDGPU_INFO_RAS_ENABLED_UMC (1 << 0)
791
792#define AMDGPU_INFO_RAS_ENABLED_SDMA (1 << 1)
793
794#define AMDGPU_INFO_RAS_ENABLED_GFX (1 << 2)
795
796#define AMDGPU_INFO_RAS_ENABLED_MMHUB (1 << 3)
797
798#define AMDGPU_INFO_RAS_ENABLED_ATHUB (1 << 4)
799
800#define AMDGPU_INFO_RAS_ENABLED_PCIE (1 << 5)
801
802#define AMDGPU_INFO_RAS_ENABLED_HDP (1 << 6)
803
804#define AMDGPU_INFO_RAS_ENABLED_XGMI (1 << 7)
805
806#define AMDGPU_INFO_RAS_ENABLED_DF (1 << 8)
807
808#define AMDGPU_INFO_RAS_ENABLED_SMN (1 << 9)
809
810#define AMDGPU_INFO_RAS_ENABLED_SEM (1 << 10)
811
812#define AMDGPU_INFO_RAS_ENABLED_MP0 (1 << 11)
813
814#define AMDGPU_INFO_RAS_ENABLED_MP1 (1 << 12)
815
816#define AMDGPU_INFO_RAS_ENABLED_FUSE (1 << 13)
817
818#define AMDGPU_INFO_VIDEO_CAPS 0x21
819
820 #define AMDGPU_INFO_VIDEO_CAPS_DECODE 0
821
822 #define AMDGPU_INFO_VIDEO_CAPS_ENCODE 1
823
824#define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0
825#define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff
826#define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8
827#define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff
828
829struct drm_amdgpu_query_fw {
830
831 __u32 fw_type;
832
833
834
835
836 __u32 ip_instance;
837
838
839
840
841 __u32 index;
842 __u32 _pad;
843};
844
845
846struct drm_amdgpu_info {
847
848 __u64 return_pointer;
849
850
851 __u32 return_size;
852
853 __u32 query;
854
855 union {
856 struct {
857 __u32 id;
858 __u32 _pad;
859 } mode_crtc;
860
861 struct {
862
863 __u32 type;
864
865
866
867
868 __u32 ip_instance;
869 } query_hw_ip;
870
871 struct {
872 __u32 dword_offset;
873
874 __u32 count;
875 __u32 instance;
876
877 __u32 flags;
878 } read_mmr_reg;
879
880 struct drm_amdgpu_query_fw query_fw;
881
882 struct {
883 __u32 type;
884 __u32 offset;
885 } vbios_info;
886
887 struct {
888 __u32 type;
889 } sensor_info;
890
891 struct {
892 __u32 type;
893 } video_cap;
894 };
895};
896
897struct drm_amdgpu_info_gds {
898
899 __u32 gds_gfx_partition_size;
900
901 __u32 compute_partition_size;
902
903 __u32 gds_total_size;
904
905 __u32 gws_per_gfx_partition;
906
907 __u32 gws_per_compute_partition;
908
909 __u32 oa_per_gfx_partition;
910
911 __u32 oa_per_compute_partition;
912 __u32 _pad;
913};
914
915struct drm_amdgpu_info_vram_gtt {
916 __u64 vram_size;
917 __u64 vram_cpu_accessible_size;
918 __u64 gtt_size;
919};
920
921struct drm_amdgpu_heap_info {
922
923 __u64 total_heap_size;
924
925
926 __u64 usable_heap_size;
927
928
929
930
931
932
933
934 __u64 heap_usage;
935
936
937
938
939
940 __u64 max_allocation;
941};
942
943struct drm_amdgpu_memory_info {
944 struct drm_amdgpu_heap_info vram;
945 struct drm_amdgpu_heap_info cpu_accessible_vram;
946 struct drm_amdgpu_heap_info gtt;
947};
948
949struct drm_amdgpu_info_firmware {
950 __u32 ver;
951 __u32 feature;
952};
953
954struct drm_amdgpu_info_vbios {
955 __u8 name[64];
956 __u8 vbios_pn[64];
957 __u32 version;
958 __u32 pad;
959 __u8 vbios_ver_str[32];
960 __u8 date[32];
961};
962
963#define AMDGPU_VRAM_TYPE_UNKNOWN 0
964#define AMDGPU_VRAM_TYPE_GDDR1 1
965#define AMDGPU_VRAM_TYPE_DDR2 2
966#define AMDGPU_VRAM_TYPE_GDDR3 3
967#define AMDGPU_VRAM_TYPE_GDDR4 4
968#define AMDGPU_VRAM_TYPE_GDDR5 5
969#define AMDGPU_VRAM_TYPE_HBM 6
970#define AMDGPU_VRAM_TYPE_DDR3 7
971#define AMDGPU_VRAM_TYPE_DDR4 8
972#define AMDGPU_VRAM_TYPE_GDDR6 9
973#define AMDGPU_VRAM_TYPE_DDR5 10
974
975struct drm_amdgpu_info_device {
976
977 __u32 device_id;
978
979 __u32 chip_rev;
980 __u32 external_rev;
981
982 __u32 pci_rev;
983 __u32 family;
984 __u32 num_shader_engines;
985 __u32 num_shader_arrays_per_engine;
986
987 __u32 gpu_counter_freq;
988 __u64 max_engine_clock;
989 __u64 max_memory_clock;
990
991 __u32 cu_active_number;
992
993 __u32 cu_ao_mask;
994 __u32 cu_bitmap[4][4];
995
996 __u32 enabled_rb_pipes_mask;
997 __u32 num_rb_pipes;
998 __u32 num_hw_gfx_contexts;
999 __u32 _pad;
1000 __u64 ids_flags;
1001
1002 __u64 virtual_address_offset;
1003
1004 __u64 virtual_address_max;
1005
1006 __u32 virtual_address_alignment;
1007
1008 __u32 pte_fragment_size;
1009 __u32 gart_page_size;
1010
1011 __u32 ce_ram_size;
1012
1013 __u32 vram_type;
1014
1015 __u32 vram_bit_width;
1016
1017 __u32 vce_harvest_config;
1018
1019 __u32 gc_double_offchip_lds_buf;
1020
1021 __u64 prim_buf_gpu_addr;
1022
1023 __u64 pos_buf_gpu_addr;
1024
1025 __u64 cntl_sb_buf_gpu_addr;
1026
1027 __u64 param_buf_gpu_addr;
1028 __u32 prim_buf_size;
1029 __u32 pos_buf_size;
1030 __u32 cntl_sb_buf_size;
1031 __u32 param_buf_size;
1032
1033 __u32 wave_front_size;
1034
1035 __u32 num_shader_visible_vgprs;
1036
1037 __u32 num_cu_per_sh;
1038
1039 __u32 num_tcc_blocks;
1040
1041 __u32 gs_vgt_table_depth;
1042
1043 __u32 gs_prim_buffer_depth;
1044
1045 __u32 max_gs_waves_per_vgt;
1046 __u32 _pad1;
1047
1048 __u32 cu_ao_bitmap[4][4];
1049
1050 __u64 high_va_offset;
1051
1052 __u64 high_va_max;
1053
1054 __u32 pa_sc_tile_steering_override;
1055
1056 __u64 tcc_disabled_mask;
1057};
1058
1059struct drm_amdgpu_info_hw_ip {
1060
1061 __u32 hw_ip_version_major;
1062 __u32 hw_ip_version_minor;
1063
1064 __u64 capabilities_flags;
1065
1066 __u32 ib_start_alignment;
1067
1068 __u32 ib_size_alignment;
1069
1070 __u32 available_rings;
1071 __u32 _pad;
1072};
1073
1074struct drm_amdgpu_info_num_handles {
1075
1076 __u32 uvd_max_handles;
1077
1078 __u32 uvd_used_handles;
1079};
1080
1081#define AMDGPU_VCE_CLOCK_TABLE_ENTRIES 6
1082
1083struct drm_amdgpu_info_vce_clock_table_entry {
1084
1085 __u32 sclk;
1086
1087 __u32 mclk;
1088
1089 __u32 eclk;
1090 __u32 pad;
1091};
1092
1093struct drm_amdgpu_info_vce_clock_table {
1094 struct drm_amdgpu_info_vce_clock_table_entry entries[AMDGPU_VCE_CLOCK_TABLE_ENTRIES];
1095 __u32 num_valid_entries;
1096 __u32 pad;
1097};
1098
1099
1100#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2 0
1101#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4 1
1102#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1 2
1103#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC 3
1104#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC 4
1105#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG 5
1106#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9 6
1107#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1 7
1108#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT 8
1109
1110struct drm_amdgpu_info_video_codec_info {
1111 __u32 valid;
1112 __u32 max_width;
1113 __u32 max_height;
1114 __u32 max_pixels_per_frame;
1115 __u32 max_level;
1116 __u32 pad;
1117};
1118
1119struct drm_amdgpu_info_video_caps {
1120 struct drm_amdgpu_info_video_codec_info codec_info[AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT];
1121};
1122
1123
1124
1125
1126#define AMDGPU_FAMILY_UNKNOWN 0
1127#define AMDGPU_FAMILY_SI 110
1128#define AMDGPU_FAMILY_CI 120
1129#define AMDGPU_FAMILY_KV 125
1130#define AMDGPU_FAMILY_VI 130
1131#define AMDGPU_FAMILY_CZ 135
1132#define AMDGPU_FAMILY_AI 141
1133#define AMDGPU_FAMILY_RV 142
1134#define AMDGPU_FAMILY_NV 143
1135#define AMDGPU_FAMILY_VGH 144
1136#define AMDGPU_FAMILY_YC 146
1137
1138#if defined(__cplusplus)
1139}
1140#endif
1141
1142#endif
1143