1
2
3
4#include <linux/acpi.h>
5#include <linux/delay.h>
6#include <linux/module.h>
7#include <linux/mod_devicetable.h>
8#include <linux/pm_runtime.h>
9#include <linux/regmap.h>
10#include <linux/slab.h>
11#include <sound/pcm.h>
12#include <sound/pcm_params.h>
13#include <sound/soc.h>
14#include <sound/tlv.h>
15#include <linux/of.h>
16#include <linux/soundwire/sdw.h>
17#include <linux/soundwire/sdw_type.h>
18#include <linux/soundwire/sdw_registers.h>
19#include "max98373.h"
20#include "max98373-sdw.h"
21
22struct sdw_stream_data {
23 struct sdw_stream_runtime *sdw_stream;
24};
25
26static const u32 max98373_sdw_cache_reg[] = {
27 MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK,
28 MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK,
29 MAX98373_R20B6_BDE_CUR_STATE_READBACK,
30};
31
32static struct reg_default max98373_reg[] = {
33 {MAX98373_R0040_SCP_INIT_STAT_1, 0x00},
34 {MAX98373_R0041_SCP_INIT_MASK_1, 0x00},
35 {MAX98373_R0042_SCP_INIT_STAT_2, 0x00},
36 {MAX98373_R0044_SCP_CTRL, 0x00},
37 {MAX98373_R0045_SCP_SYSTEM_CTRL, 0x00},
38 {MAX98373_R0046_SCP_DEV_NUMBER, 0x00},
39 {MAX98373_R0050_SCP_DEV_ID_0, 0x21},
40 {MAX98373_R0051_SCP_DEV_ID_1, 0x01},
41 {MAX98373_R0052_SCP_DEV_ID_2, 0x9F},
42 {MAX98373_R0053_SCP_DEV_ID_3, 0x87},
43 {MAX98373_R0054_SCP_DEV_ID_4, 0x08},
44 {MAX98373_R0055_SCP_DEV_ID_5, 0x00},
45 {MAX98373_R0060_SCP_FRAME_CTLR, 0x00},
46 {MAX98373_R0070_SCP_FRAME_CTLR, 0x00},
47 {MAX98373_R0100_DP1_INIT_STAT, 0x00},
48 {MAX98373_R0101_DP1_INIT_MASK, 0x00},
49 {MAX98373_R0102_DP1_PORT_CTRL, 0x00},
50 {MAX98373_R0103_DP1_BLOCK_CTRL_1, 0x00},
51 {MAX98373_R0104_DP1_PREPARE_STATUS, 0x00},
52 {MAX98373_R0105_DP1_PREPARE_CTRL, 0x00},
53 {MAX98373_R0120_DP1_CHANNEL_EN, 0x00},
54 {MAX98373_R0122_DP1_SAMPLE_CTRL1, 0x00},
55 {MAX98373_R0123_DP1_SAMPLE_CTRL2, 0x00},
56 {MAX98373_R0124_DP1_OFFSET_CTRL1, 0x00},
57 {MAX98373_R0125_DP1_OFFSET_CTRL2, 0x00},
58 {MAX98373_R0126_DP1_HCTRL, 0x00},
59 {MAX98373_R0127_DP1_BLOCK_CTRL3, 0x00},
60 {MAX98373_R0130_DP1_CHANNEL_EN, 0x00},
61 {MAX98373_R0132_DP1_SAMPLE_CTRL1, 0x00},
62 {MAX98373_R0133_DP1_SAMPLE_CTRL2, 0x00},
63 {MAX98373_R0134_DP1_OFFSET_CTRL1, 0x00},
64 {MAX98373_R0135_DP1_OFFSET_CTRL2, 0x00},
65 {MAX98373_R0136_DP1_HCTRL, 0x0136},
66 {MAX98373_R0137_DP1_BLOCK_CTRL3, 0x00},
67 {MAX98373_R0300_DP3_INIT_STAT, 0x00},
68 {MAX98373_R0301_DP3_INIT_MASK, 0x00},
69 {MAX98373_R0302_DP3_PORT_CTRL, 0x00},
70 {MAX98373_R0303_DP3_BLOCK_CTRL_1, 0x00},
71 {MAX98373_R0304_DP3_PREPARE_STATUS, 0x00},
72 {MAX98373_R0305_DP3_PREPARE_CTRL, 0x00},
73 {MAX98373_R0320_DP3_CHANNEL_EN, 0x00},
74 {MAX98373_R0322_DP3_SAMPLE_CTRL1, 0x00},
75 {MAX98373_R0323_DP3_SAMPLE_CTRL2, 0x00},
76 {MAX98373_R0324_DP3_OFFSET_CTRL1, 0x00},
77 {MAX98373_R0325_DP3_OFFSET_CTRL2, 0x00},
78 {MAX98373_R0326_DP3_HCTRL, 0x00},
79 {MAX98373_R0327_DP3_BLOCK_CTRL3, 0x00},
80 {MAX98373_R0330_DP3_CHANNEL_EN, 0x00},
81 {MAX98373_R0332_DP3_SAMPLE_CTRL1, 0x00},
82 {MAX98373_R0333_DP3_SAMPLE_CTRL2, 0x00},
83 {MAX98373_R0334_DP3_OFFSET_CTRL1, 0x00},
84 {MAX98373_R0335_DP3_OFFSET_CTRL2, 0x00},
85 {MAX98373_R0336_DP3_HCTRL, 0x00},
86 {MAX98373_R0337_DP3_BLOCK_CTRL3, 0x00},
87 {MAX98373_R2000_SW_RESET, 0x00},
88 {MAX98373_R2001_INT_RAW1, 0x00},
89 {MAX98373_R2002_INT_RAW2, 0x00},
90 {MAX98373_R2003_INT_RAW3, 0x00},
91 {MAX98373_R2004_INT_STATE1, 0x00},
92 {MAX98373_R2005_INT_STATE2, 0x00},
93 {MAX98373_R2006_INT_STATE3, 0x00},
94 {MAX98373_R2007_INT_FLAG1, 0x00},
95 {MAX98373_R2008_INT_FLAG2, 0x00},
96 {MAX98373_R2009_INT_FLAG3, 0x00},
97 {MAX98373_R200A_INT_EN1, 0x00},
98 {MAX98373_R200B_INT_EN2, 0x00},
99 {MAX98373_R200C_INT_EN3, 0x00},
100 {MAX98373_R200D_INT_FLAG_CLR1, 0x00},
101 {MAX98373_R200E_INT_FLAG_CLR2, 0x00},
102 {MAX98373_R200F_INT_FLAG_CLR3, 0x00},
103 {MAX98373_R2010_IRQ_CTRL, 0x00},
104 {MAX98373_R2014_THERM_WARN_THRESH, 0x10},
105 {MAX98373_R2015_THERM_SHDN_THRESH, 0x27},
106 {MAX98373_R2016_THERM_HYSTERESIS, 0x01},
107 {MAX98373_R2017_THERM_FOLDBACK_SET, 0xC0},
108 {MAX98373_R2018_THERM_FOLDBACK_EN, 0x00},
109 {MAX98373_R201E_PIN_DRIVE_STRENGTH, 0x55},
110 {MAX98373_R2020_PCM_TX_HIZ_EN_1, 0xFE},
111 {MAX98373_R2021_PCM_TX_HIZ_EN_2, 0xFF},
112 {MAX98373_R2022_PCM_TX_SRC_1, 0x00},
113 {MAX98373_R2023_PCM_TX_SRC_2, 0x00},
114 {MAX98373_R2024_PCM_DATA_FMT_CFG, 0xC0},
115 {MAX98373_R2025_AUDIO_IF_MODE, 0x00},
116 {MAX98373_R2026_PCM_CLOCK_RATIO, 0x04},
117 {MAX98373_R2027_PCM_SR_SETUP_1, 0x08},
118 {MAX98373_R2028_PCM_SR_SETUP_2, 0x88},
119 {MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1, 0x00},
120 {MAX98373_R202A_PCM_TO_SPK_MONO_MIX_2, 0x00},
121 {MAX98373_R202B_PCM_RX_EN, 0x00},
122 {MAX98373_R202C_PCM_TX_EN, 0x00},
123 {MAX98373_R202E_ICC_RX_CH_EN_1, 0x00},
124 {MAX98373_R202F_ICC_RX_CH_EN_2, 0x00},
125 {MAX98373_R2030_ICC_TX_HIZ_EN_1, 0xFF},
126 {MAX98373_R2031_ICC_TX_HIZ_EN_2, 0xFF},
127 {MAX98373_R2032_ICC_LINK_EN_CFG, 0x30},
128 {MAX98373_R2034_ICC_TX_CNTL, 0x00},
129 {MAX98373_R2035_ICC_TX_EN, 0x00},
130 {MAX98373_R2036_SOUNDWIRE_CTRL, 0x05},
131 {MAX98373_R203D_AMP_DIG_VOL_CTRL, 0x00},
132 {MAX98373_R203E_AMP_PATH_GAIN, 0x08},
133 {MAX98373_R203F_AMP_DSP_CFG, 0x02},
134 {MAX98373_R2040_TONE_GEN_CFG, 0x00},
135 {MAX98373_R2041_AMP_CFG, 0x03},
136 {MAX98373_R2042_AMP_EDGE_RATE_CFG, 0x00},
137 {MAX98373_R2043_AMP_EN, 0x00},
138 {MAX98373_R2046_IV_SENSE_ADC_DSP_CFG, 0x04},
139 {MAX98373_R2047_IV_SENSE_ADC_EN, 0x00},
140 {MAX98373_R2051_MEAS_ADC_SAMPLING_RATE, 0x00},
141 {MAX98373_R2052_MEAS_ADC_PVDD_FLT_CFG, 0x00},
142 {MAX98373_R2053_MEAS_ADC_THERM_FLT_CFG, 0x00},
143 {MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK, 0x00},
144 {MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK, 0x00},
145 {MAX98373_R2056_MEAS_ADC_PVDD_CH_EN, 0x00},
146 {MAX98373_R2090_BDE_LVL_HOLD, 0x00},
147 {MAX98373_R2091_BDE_GAIN_ATK_REL_RATE, 0x00},
148 {MAX98373_R2092_BDE_CLIPPER_MODE, 0x00},
149 {MAX98373_R2097_BDE_L1_THRESH, 0x00},
150 {MAX98373_R2098_BDE_L2_THRESH, 0x00},
151 {MAX98373_R2099_BDE_L3_THRESH, 0x00},
152 {MAX98373_R209A_BDE_L4_THRESH, 0x00},
153 {MAX98373_R209B_BDE_THRESH_HYST, 0x00},
154 {MAX98373_R20A8_BDE_L1_CFG_1, 0x00},
155 {MAX98373_R20A9_BDE_L1_CFG_2, 0x00},
156 {MAX98373_R20AA_BDE_L1_CFG_3, 0x00},
157 {MAX98373_R20AB_BDE_L2_CFG_1, 0x00},
158 {MAX98373_R20AC_BDE_L2_CFG_2, 0x00},
159 {MAX98373_R20AD_BDE_L2_CFG_3, 0x00},
160 {MAX98373_R20AE_BDE_L3_CFG_1, 0x00},
161 {MAX98373_R20AF_BDE_L3_CFG_2, 0x00},
162 {MAX98373_R20B0_BDE_L3_CFG_3, 0x00},
163 {MAX98373_R20B1_BDE_L4_CFG_1, 0x00},
164 {MAX98373_R20B2_BDE_L4_CFG_2, 0x00},
165 {MAX98373_R20B3_BDE_L4_CFG_3, 0x00},
166 {MAX98373_R20B4_BDE_INFINITE_HOLD_RELEASE, 0x00},
167 {MAX98373_R20B5_BDE_EN, 0x00},
168 {MAX98373_R20B6_BDE_CUR_STATE_READBACK, 0x00},
169 {MAX98373_R20D1_DHT_CFG, 0x01},
170 {MAX98373_R20D2_DHT_ATTACK_CFG, 0x02},
171 {MAX98373_R20D3_DHT_RELEASE_CFG, 0x03},
172 {MAX98373_R20D4_DHT_EN, 0x00},
173 {MAX98373_R20E0_LIMITER_THRESH_CFG, 0x00},
174 {MAX98373_R20E1_LIMITER_ATK_REL_RATES, 0x00},
175 {MAX98373_R20E2_LIMITER_EN, 0x00},
176 {MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG, 0x00},
177 {MAX98373_R20FF_GLOBAL_SHDN, 0x00},
178 {MAX98373_R21FF_REV_ID, 0x42},
179};
180
181static bool max98373_readable_register(struct device *dev, unsigned int reg)
182{
183 switch (reg) {
184 case MAX98373_R21FF_REV_ID:
185 case MAX98373_R2010_IRQ_CTRL:
186
187 case MAX98373_R0040_SCP_INIT_STAT_1 ... MAX98373_R0070_SCP_FRAME_CTLR:
188
189 case MAX98373_R0100_DP1_INIT_STAT ... MAX98373_R0137_DP1_BLOCK_CTRL3:
190
191 case MAX98373_R0300_DP3_INIT_STAT ... MAX98373_R0337_DP3_BLOCK_CTRL3:
192 case MAX98373_R2000_SW_RESET ... MAX98373_R200C_INT_EN3:
193 case MAX98373_R2014_THERM_WARN_THRESH
194 ... MAX98373_R2018_THERM_FOLDBACK_EN:
195 case MAX98373_R201E_PIN_DRIVE_STRENGTH
196 ... MAX98373_R2036_SOUNDWIRE_CTRL:
197 case MAX98373_R203D_AMP_DIG_VOL_CTRL ... MAX98373_R2043_AMP_EN:
198 case MAX98373_R2046_IV_SENSE_ADC_DSP_CFG
199 ... MAX98373_R2047_IV_SENSE_ADC_EN:
200 case MAX98373_R2051_MEAS_ADC_SAMPLING_RATE
201 ... MAX98373_R2056_MEAS_ADC_PVDD_CH_EN:
202 case MAX98373_R2090_BDE_LVL_HOLD ... MAX98373_R2092_BDE_CLIPPER_MODE:
203 case MAX98373_R2097_BDE_L1_THRESH
204 ... MAX98373_R209B_BDE_THRESH_HYST:
205 case MAX98373_R20A8_BDE_L1_CFG_1 ... MAX98373_R20B3_BDE_L4_CFG_3:
206 case MAX98373_R20B5_BDE_EN ... MAX98373_R20B6_BDE_CUR_STATE_READBACK:
207 case MAX98373_R20D1_DHT_CFG ... MAX98373_R20D4_DHT_EN:
208 case MAX98373_R20E0_LIMITER_THRESH_CFG ... MAX98373_R20E2_LIMITER_EN:
209 case MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG
210 ... MAX98373_R20FF_GLOBAL_SHDN:
211 return true;
212 default:
213 return false;
214 }
215};
216
217static bool max98373_volatile_reg(struct device *dev, unsigned int reg)
218{
219 switch (reg) {
220 case MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK:
221 case MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK:
222 case MAX98373_R20B6_BDE_CUR_STATE_READBACK:
223 case MAX98373_R20FF_GLOBAL_SHDN:
224 case MAX98373_R21FF_REV_ID:
225
226 case MAX98373_R0040_SCP_INIT_STAT_1 ... MAX98373_R0070_SCP_FRAME_CTLR:
227
228 case MAX98373_R0100_DP1_INIT_STAT ... MAX98373_R0137_DP1_BLOCK_CTRL3:
229
230 case MAX98373_R0300_DP3_INIT_STAT ... MAX98373_R0337_DP3_BLOCK_CTRL3:
231 case MAX98373_R2000_SW_RESET ... MAX98373_R2009_INT_FLAG3:
232 return true;
233 default:
234 return false;
235 }
236}
237
238static const struct regmap_config max98373_sdw_regmap = {
239 .reg_bits = 32,
240 .val_bits = 8,
241 .max_register = MAX98373_R21FF_REV_ID,
242 .reg_defaults = max98373_reg,
243 .num_reg_defaults = ARRAY_SIZE(max98373_reg),
244 .readable_reg = max98373_readable_register,
245 .volatile_reg = max98373_volatile_reg,
246 .cache_type = REGCACHE_RBTREE,
247 .use_single_read = true,
248 .use_single_write = true,
249};
250
251
252static __maybe_unused int max98373_suspend(struct device *dev)
253{
254 struct max98373_priv *max98373 = dev_get_drvdata(dev);
255 int i;
256
257
258 for (i = 0; i < max98373->cache_num; i++)
259 regmap_read(max98373->regmap, max98373->cache[i].reg, &max98373->cache[i].val);
260
261 regcache_cache_only(max98373->regmap, true);
262
263 return 0;
264}
265
266#define MAX98373_PROBE_TIMEOUT 5000
267
268static __maybe_unused int max98373_resume(struct device *dev)
269{
270 struct sdw_slave *slave = dev_to_sdw_dev(dev);
271 struct max98373_priv *max98373 = dev_get_drvdata(dev);
272 unsigned long time;
273
274 if (!max98373->first_hw_init)
275 return 0;
276
277 if (!slave->unattach_request)
278 goto regmap_sync;
279
280 time = wait_for_completion_timeout(&slave->initialization_complete,
281 msecs_to_jiffies(MAX98373_PROBE_TIMEOUT));
282 if (!time) {
283 dev_err(dev, "Initialization not complete, timed out\n");
284 return -ETIMEDOUT;
285 }
286
287regmap_sync:
288 slave->unattach_request = 0;
289 regcache_cache_only(max98373->regmap, false);
290 regcache_sync(max98373->regmap);
291
292 return 0;
293}
294
295static const struct dev_pm_ops max98373_pm = {
296 SET_SYSTEM_SLEEP_PM_OPS(max98373_suspend, max98373_resume)
297 SET_RUNTIME_PM_OPS(max98373_suspend, max98373_resume, NULL)
298};
299
300static int max98373_read_prop(struct sdw_slave *slave)
301{
302 struct sdw_slave_prop *prop = &slave->prop;
303 int nval, i;
304 u32 bit;
305 unsigned long addr;
306 struct sdw_dpn_prop *dpn;
307
308 prop->scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY;
309
310
311 prop->source_ports = BIT(3);
312
313 prop->sink_ports = BIT(1);
314 prop->paging_support = true;
315 prop->clk_stop_timeout = 20;
316
317 nval = hweight32(prop->source_ports);
318 prop->src_dpn_prop = devm_kcalloc(&slave->dev, nval,
319 sizeof(*prop->src_dpn_prop),
320 GFP_KERNEL);
321 if (!prop->src_dpn_prop)
322 return -ENOMEM;
323
324 i = 0;
325 dpn = prop->src_dpn_prop;
326 addr = prop->source_ports;
327 for_each_set_bit(bit, &addr, 32) {
328 dpn[i].num = bit;
329 dpn[i].type = SDW_DPN_FULL;
330 dpn[i].simple_ch_prep_sm = true;
331 dpn[i].ch_prep_timeout = 10;
332 i++;
333 }
334
335
336 nval = hweight32(prop->sink_ports);
337 prop->sink_dpn_prop = devm_kcalloc(&slave->dev, nval,
338 sizeof(*prop->sink_dpn_prop),
339 GFP_KERNEL);
340 if (!prop->sink_dpn_prop)
341 return -ENOMEM;
342
343 i = 0;
344 dpn = prop->sink_dpn_prop;
345 addr = prop->sink_ports;
346 for_each_set_bit(bit, &addr, 32) {
347 dpn[i].num = bit;
348 dpn[i].type = SDW_DPN_FULL;
349 dpn[i].simple_ch_prep_sm = true;
350 dpn[i].ch_prep_timeout = 10;
351 i++;
352 }
353
354
355 prop->clk_stop_timeout = 20;
356
357 return 0;
358}
359
360static int max98373_io_init(struct sdw_slave *slave)
361{
362 struct device *dev = &slave->dev;
363 struct max98373_priv *max98373 = dev_get_drvdata(dev);
364
365 if (max98373->first_hw_init) {
366 regcache_cache_only(max98373->regmap, false);
367 regcache_cache_bypass(max98373->regmap, true);
368 }
369
370
371
372
373 if (!max98373->first_hw_init) {
374
375 pm_runtime_set_autosuspend_delay(dev, 3000);
376 pm_runtime_use_autosuspend(dev);
377
378
379 pm_runtime_set_active(dev);
380
381
382 pm_runtime_mark_last_busy(dev);
383
384 pm_runtime_enable(dev);
385 }
386
387 pm_runtime_get_noresume(dev);
388
389
390 max98373_reset(max98373, dev);
391
392
393 regmap_write(max98373->regmap, MAX98373_R2025_AUDIO_IF_MODE, 3);
394
395 regmap_write(max98373->regmap, MAX98373_R2047_IV_SENSE_ADC_EN, 3);
396
397 regmap_write(max98373->regmap, MAX98373_R2036_SOUNDWIRE_CTRL, 5);
398
399 regmap_write(max98373->regmap, MAX98373_R2028_PCM_SR_SETUP_2, 0x88);
400
401 regmap_write(max98373->regmap,
402 MAX98373_R2020_PCM_TX_HIZ_EN_1,
403 0xFF);
404 regmap_write(max98373->regmap,
405 MAX98373_R2021_PCM_TX_HIZ_EN_2,
406 0xFF);
407
408 regmap_write(max98373->regmap,
409 MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1,
410 0x80);
411 regmap_write(max98373->regmap,
412 MAX98373_R202A_PCM_TO_SPK_MONO_MIX_2,
413 0x1);
414
415 regmap_write(max98373->regmap,
416 MAX98373_R203F_AMP_DSP_CFG,
417 0x3);
418
419 regmap_write(max98373->regmap,
420 MAX98373_R2046_IV_SENSE_ADC_DSP_CFG,
421 0x7);
422
423 regmap_write(max98373->regmap,
424 MAX98373_R2022_PCM_TX_SRC_1,
425 (max98373->i_slot << MAX98373_PCM_TX_CH_SRC_A_I_SHIFT |
426 max98373->v_slot) & 0xFF);
427 if (max98373->v_slot < 8)
428 regmap_update_bits(max98373->regmap,
429 MAX98373_R2020_PCM_TX_HIZ_EN_1,
430 1 << max98373->v_slot, 0);
431 else
432 regmap_update_bits(max98373->regmap,
433 MAX98373_R2021_PCM_TX_HIZ_EN_2,
434 1 << (max98373->v_slot - 8), 0);
435
436 if (max98373->i_slot < 8)
437 regmap_update_bits(max98373->regmap,
438 MAX98373_R2020_PCM_TX_HIZ_EN_1,
439 1 << max98373->i_slot, 0);
440 else
441 regmap_update_bits(max98373->regmap,
442 MAX98373_R2021_PCM_TX_HIZ_EN_2,
443 1 << (max98373->i_slot - 8), 0);
444
445
446 regmap_write(max98373->regmap,
447 MAX98373_R2023_PCM_TX_SRC_2,
448 max98373->spkfb_slot & 0xFF);
449
450
451 if (max98373->interleave_mode)
452 regmap_update_bits(max98373->regmap,
453 MAX98373_R2024_PCM_DATA_FMT_CFG,
454 MAX98373_PCM_TX_CH_INTERLEAVE_MASK,
455 MAX98373_PCM_TX_CH_INTERLEAVE_MASK);
456
457
458 regmap_update_bits(max98373->regmap,
459 MAX98373_R2043_AMP_EN,
460 MAX98373_SPK_EN_MASK, 1);
461
462 regmap_write(max98373->regmap, MAX98373_R20B5_BDE_EN, 1);
463 regmap_write(max98373->regmap, MAX98373_R20E2_LIMITER_EN, 1);
464
465 if (max98373->first_hw_init) {
466 regcache_cache_bypass(max98373->regmap, false);
467 regcache_mark_dirty(max98373->regmap);
468 }
469
470 max98373->first_hw_init = true;
471 max98373->hw_init = true;
472
473 pm_runtime_mark_last_busy(dev);
474 pm_runtime_put_autosuspend(dev);
475
476 return 0;
477}
478
479static int max98373_clock_calculate(struct sdw_slave *slave,
480 unsigned int clk_freq)
481{
482 int x, y;
483 static const int max98373_clk_family[] = {
484 7680000, 8400000, 9600000, 11289600,
485 12000000, 12288000, 13000000
486 };
487
488 for (x = 0; x < 4; x++)
489 for (y = 0; y < ARRAY_SIZE(max98373_clk_family); y++)
490 if (clk_freq == (max98373_clk_family[y] >> x))
491 return (x << 3) + y;
492
493
494 dev_err(&slave->dev, "Requested clock not found. (clk_freq = %d)\n",
495 clk_freq);
496 return 0x5;
497}
498
499static int max98373_clock_config(struct sdw_slave *slave,
500 struct sdw_bus_params *params)
501{
502 struct device *dev = &slave->dev;
503 struct max98373_priv *max98373 = dev_get_drvdata(dev);
504 unsigned int clk_freq, value;
505
506 clk_freq = (params->curr_dr_freq >> 1);
507
508
509
510
511
512
513 value = max98373_clock_calculate(slave, clk_freq);
514
515
516 regmap_write(max98373->regmap, MAX98373_R2036_SOUNDWIRE_CTRL, value);
517
518
519 regmap_write(max98373->regmap, MAX98373_R2028_PCM_SR_SETUP_2, 0x88);
520
521 return 0;
522}
523
524#define MAX98373_RATES SNDRV_PCM_RATE_8000_96000
525#define MAX98373_FORMATS (SNDRV_PCM_FMTBIT_S32_LE)
526
527static int max98373_sdw_dai_hw_params(struct snd_pcm_substream *substream,
528 struct snd_pcm_hw_params *params,
529 struct snd_soc_dai *dai)
530{
531 struct snd_soc_component *component = dai->component;
532 struct max98373_priv *max98373 =
533 snd_soc_component_get_drvdata(component);
534
535 struct sdw_stream_config stream_config;
536 struct sdw_port_config port_config;
537 enum sdw_data_direction direction;
538 struct sdw_stream_data *stream;
539 int ret, chan_sz, sampling_rate;
540
541 stream = snd_soc_dai_get_dma_data(dai, substream);
542
543 if (!stream)
544 return -EINVAL;
545
546 if (!max98373->slave)
547 return -EINVAL;
548
549 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
550 direction = SDW_DATA_DIR_RX;
551 port_config.num = 1;
552 } else {
553 direction = SDW_DATA_DIR_TX;
554 port_config.num = 3;
555 }
556
557 stream_config.frame_rate = params_rate(params);
558 stream_config.bps = snd_pcm_format_width(params_format(params));
559 stream_config.direction = direction;
560
561 if (max98373->slot && direction == SDW_DATA_DIR_RX) {
562 stream_config.ch_count = max98373->slot;
563 port_config.ch_mask = max98373->rx_mask;
564 } else {
565
566 if (direction == SDW_DATA_DIR_TX)
567 stream_config.ch_count = 2;
568 else
569 stream_config.ch_count = params_channels(params);
570
571 port_config.ch_mask = GENMASK((int)stream_config.ch_count - 1, 0);
572 }
573
574 ret = sdw_stream_add_slave(max98373->slave, &stream_config,
575 &port_config, 1, stream->sdw_stream);
576 if (ret) {
577 dev_err(dai->dev, "Unable to configure port\n");
578 return ret;
579 }
580
581 if (params_channels(params) > 16) {
582 dev_err(component->dev, "Unsupported channels %d\n",
583 params_channels(params));
584 return -EINVAL;
585 }
586
587
588 switch (snd_pcm_format_width(params_format(params))) {
589 case 16:
590 chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_16;
591 break;
592 case 24:
593 chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_24;
594 break;
595 case 32:
596 chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_32;
597 break;
598 default:
599 dev_err(component->dev, "Channel size unsupported %d\n",
600 params_format(params));
601 return -EINVAL;
602 }
603
604 max98373->ch_size = snd_pcm_format_width(params_format(params));
605
606 regmap_update_bits(max98373->regmap,
607 MAX98373_R2024_PCM_DATA_FMT_CFG,
608 MAX98373_PCM_MODE_CFG_CHANSZ_MASK, chan_sz);
609
610 dev_dbg(component->dev, "Format supported %d", params_format(params));
611
612
613 switch (params_rate(params)) {
614 case 8000:
615 sampling_rate = MAX98373_PCM_SR_SET1_SR_8000;
616 break;
617 case 11025:
618 sampling_rate = MAX98373_PCM_SR_SET1_SR_11025;
619 break;
620 case 12000:
621 sampling_rate = MAX98373_PCM_SR_SET1_SR_12000;
622 break;
623 case 16000:
624 sampling_rate = MAX98373_PCM_SR_SET1_SR_16000;
625 break;
626 case 22050:
627 sampling_rate = MAX98373_PCM_SR_SET1_SR_22050;
628 break;
629 case 24000:
630 sampling_rate = MAX98373_PCM_SR_SET1_SR_24000;
631 break;
632 case 32000:
633 sampling_rate = MAX98373_PCM_SR_SET1_SR_32000;
634 break;
635 case 44100:
636 sampling_rate = MAX98373_PCM_SR_SET1_SR_44100;
637 break;
638 case 48000:
639 sampling_rate = MAX98373_PCM_SR_SET1_SR_48000;
640 break;
641 case 88200:
642 sampling_rate = MAX98373_PCM_SR_SET1_SR_88200;
643 break;
644 case 96000:
645 sampling_rate = MAX98373_PCM_SR_SET1_SR_96000;
646 break;
647 default:
648 dev_err(component->dev, "Rate %d is not supported\n",
649 params_rate(params));
650 return -EINVAL;
651 }
652
653
654 regmap_update_bits(max98373->regmap,
655 MAX98373_R2028_PCM_SR_SETUP_2,
656 MAX98373_PCM_SR_SET2_SR_MASK,
657 sampling_rate << MAX98373_PCM_SR_SET2_SR_SHIFT);
658
659
660 regmap_update_bits(max98373->regmap,
661 MAX98373_R2028_PCM_SR_SETUP_2,
662 MAX98373_PCM_SR_SET2_IVADC_SR_MASK,
663 sampling_rate);
664
665 return 0;
666}
667
668static int max98373_pcm_hw_free(struct snd_pcm_substream *substream,
669 struct snd_soc_dai *dai)
670{
671 struct snd_soc_component *component = dai->component;
672 struct max98373_priv *max98373 =
673 snd_soc_component_get_drvdata(component);
674 struct sdw_stream_data *stream =
675 snd_soc_dai_get_dma_data(dai, substream);
676
677 if (!max98373->slave)
678 return -EINVAL;
679
680 sdw_stream_remove_slave(max98373->slave, stream->sdw_stream);
681 return 0;
682}
683
684static int max98373_set_sdw_stream(struct snd_soc_dai *dai,
685 void *sdw_stream, int direction)
686{
687 struct sdw_stream_data *stream;
688
689 if (!sdw_stream)
690 return 0;
691
692 stream = kzalloc(sizeof(*stream), GFP_KERNEL);
693 if (!stream)
694 return -ENOMEM;
695
696 stream->sdw_stream = sdw_stream;
697
698
699 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
700 dai->playback_dma_data = stream;
701 else
702 dai->capture_dma_data = stream;
703
704 return 0;
705}
706
707static void max98373_shutdown(struct snd_pcm_substream *substream,
708 struct snd_soc_dai *dai)
709{
710 struct sdw_stream_data *stream;
711
712 stream = snd_soc_dai_get_dma_data(dai, substream);
713 snd_soc_dai_set_dma_data(dai, substream, NULL);
714 kfree(stream);
715}
716
717static int max98373_sdw_set_tdm_slot(struct snd_soc_dai *dai,
718 unsigned int tx_mask,
719 unsigned int rx_mask,
720 int slots, int slot_width)
721{
722 struct snd_soc_component *component = dai->component;
723 struct max98373_priv *max98373 =
724 snd_soc_component_get_drvdata(component);
725
726
727 if (tx_mask)
728 return -EINVAL;
729
730 if (!rx_mask && !slots && !slot_width)
731 max98373->tdm_mode = false;
732 else
733 max98373->tdm_mode = true;
734
735 max98373->rx_mask = rx_mask;
736 max98373->slot = slots;
737
738 return 0;
739}
740
741static const struct snd_soc_dai_ops max98373_dai_sdw_ops = {
742 .hw_params = max98373_sdw_dai_hw_params,
743 .hw_free = max98373_pcm_hw_free,
744 .set_stream = max98373_set_sdw_stream,
745 .shutdown = max98373_shutdown,
746 .set_tdm_slot = max98373_sdw_set_tdm_slot,
747};
748
749static struct snd_soc_dai_driver max98373_sdw_dai[] = {
750 {
751 .name = "max98373-aif1",
752 .playback = {
753 .stream_name = "HiFi Playback",
754 .channels_min = 1,
755 .channels_max = 2,
756 .rates = MAX98373_RATES,
757 .formats = MAX98373_FORMATS,
758 },
759 .capture = {
760 .stream_name = "HiFi Capture",
761 .channels_min = 1,
762 .channels_max = 2,
763 .rates = MAX98373_RATES,
764 .formats = MAX98373_FORMATS,
765 },
766 .ops = &max98373_dai_sdw_ops,
767 }
768};
769
770static int max98373_init(struct sdw_slave *slave, struct regmap *regmap)
771{
772 struct max98373_priv *max98373;
773 int ret;
774 int i;
775 struct device *dev = &slave->dev;
776
777
778 max98373 = devm_kzalloc(dev, sizeof(*max98373), GFP_KERNEL);
779 if (!max98373)
780 return -ENOMEM;
781
782 dev_set_drvdata(dev, max98373);
783 max98373->regmap = regmap;
784 max98373->slave = slave;
785
786 max98373->cache_num = ARRAY_SIZE(max98373_sdw_cache_reg);
787 max98373->cache = devm_kcalloc(dev, max98373->cache_num,
788 sizeof(*max98373->cache),
789 GFP_KERNEL);
790 if (!max98373->cache)
791 return -ENOMEM;
792
793 for (i = 0; i < max98373->cache_num; i++)
794 max98373->cache[i].reg = max98373_sdw_cache_reg[i];
795
796
797 max98373_slot_config(dev, max98373);
798
799 max98373->hw_init = false;
800 max98373->first_hw_init = false;
801
802
803 ret = devm_snd_soc_register_component(dev, &soc_codec_dev_max98373_sdw,
804 max98373_sdw_dai,
805 ARRAY_SIZE(max98373_sdw_dai));
806 if (ret < 0)
807 dev_err(dev, "Failed to register codec: %d\n", ret);
808
809 return ret;
810}
811
812static int max98373_update_status(struct sdw_slave *slave,
813 enum sdw_slave_status status)
814{
815 struct max98373_priv *max98373 = dev_get_drvdata(&slave->dev);
816
817 if (status == SDW_SLAVE_UNATTACHED)
818 max98373->hw_init = false;
819
820
821
822
823 if (max98373->hw_init || status != SDW_SLAVE_ATTACHED)
824 return 0;
825
826
827 return max98373_io_init(slave);
828}
829
830static int max98373_bus_config(struct sdw_slave *slave,
831 struct sdw_bus_params *params)
832{
833 int ret;
834
835 ret = max98373_clock_config(slave, params);
836 if (ret < 0)
837 dev_err(&slave->dev, "Invalid clk config");
838
839 return ret;
840}
841
842
843
844
845
846static struct sdw_slave_ops max98373_slave_ops = {
847 .read_prop = max98373_read_prop,
848 .update_status = max98373_update_status,
849 .bus_config = max98373_bus_config,
850};
851
852static int max98373_sdw_probe(struct sdw_slave *slave,
853 const struct sdw_device_id *id)
854{
855 struct regmap *regmap;
856
857
858 regmap = devm_regmap_init_sdw(slave, &max98373_sdw_regmap);
859 if (IS_ERR(regmap))
860 return PTR_ERR(regmap);
861
862 return max98373_init(slave, regmap);
863}
864
865#if defined(CONFIG_OF)
866static const struct of_device_id max98373_of_match[] = {
867 { .compatible = "maxim,max98373", },
868 {},
869};
870MODULE_DEVICE_TABLE(of, max98373_of_match);
871#endif
872
873#ifdef CONFIG_ACPI
874static const struct acpi_device_id max98373_acpi_match[] = {
875 { "MX98373", 0 },
876 {},
877};
878MODULE_DEVICE_TABLE(acpi, max98373_acpi_match);
879#endif
880
881static const struct sdw_device_id max98373_id[] = {
882 SDW_SLAVE_ENTRY(0x019F, 0x8373, 0),
883 {},
884};
885MODULE_DEVICE_TABLE(sdw, max98373_id);
886
887static struct sdw_driver max98373_sdw_driver = {
888 .driver = {
889 .name = "max98373",
890 .owner = THIS_MODULE,
891 .of_match_table = of_match_ptr(max98373_of_match),
892 .acpi_match_table = ACPI_PTR(max98373_acpi_match),
893 .pm = &max98373_pm,
894 },
895 .probe = max98373_sdw_probe,
896 .remove = NULL,
897 .ops = &max98373_slave_ops,
898 .id_table = max98373_id,
899};
900
901module_sdw_driver(max98373_sdw_driver);
902
903MODULE_DESCRIPTION("ASoC MAX98373 driver SDW");
904MODULE_AUTHOR("Oleg Sherbakov <oleg.sherbakov@maximintegrated.com>");
905MODULE_LICENSE("GPL v2");
906
