linux/sound/soc/codecs/mt6359.c
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   1// SPDX-License-Identifier: GPL-2.0
   2//
   3// mt6359.c  --  mt6359 ALSA SoC audio codec driver
   4//
   5// Copyright (c) 2020 MediaTek Inc.
   6// Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com>
   7
   8#include <linux/delay.h>
   9#include <linux/kthread.h>
  10#include <linux/mfd/mt6397/core.h>
  11#include <linux/module.h>
  12#include <linux/of_device.h>
  13#include <linux/platform_device.h>
  14#include <linux/regulator/consumer.h>
  15#include <linux/sched.h>
  16#include <sound/soc.h>
  17#include <sound/tlv.h>
  18
  19#include "mt6359.h"
  20
  21static void mt6359_set_playback_gpio(struct mt6359_priv *priv)
  22{
  23        /* set gpio mosi mode, clk / data mosi */
  24        regmap_write(priv->regmap, MT6359_GPIO_MODE2_CLR, 0x0ffe);
  25        regmap_write(priv->regmap, MT6359_GPIO_MODE2_SET, 0x0249);
  26
  27        /* sync mosi */
  28        regmap_write(priv->regmap, MT6359_GPIO_MODE3_CLR, 0x6);
  29        regmap_write(priv->regmap, MT6359_GPIO_MODE3_SET, 0x1);
  30}
  31
  32static void mt6359_reset_playback_gpio(struct mt6359_priv *priv)
  33{
  34        /* set pad_aud_*_mosi to GPIO mode and dir input
  35         * reason:
  36         * pad_aud_dat_mosi*, because the pin is used as boot strap
  37         * don't clean clk/sync, for mtkaif protocol 2
  38         */
  39        regmap_write(priv->regmap, MT6359_GPIO_MODE2_CLR, 0x0ff8);
  40        regmap_update_bits(priv->regmap, MT6359_GPIO_DIR0, 0x7 << 9, 0x0);
  41}
  42
  43static void mt6359_set_capture_gpio(struct mt6359_priv *priv)
  44{
  45        /* set gpio miso mode */
  46        regmap_write(priv->regmap, MT6359_GPIO_MODE3_CLR, 0x0e00);
  47        regmap_write(priv->regmap, MT6359_GPIO_MODE3_SET, 0x0200);
  48
  49        regmap_write(priv->regmap, MT6359_GPIO_MODE4_CLR, 0x003f);
  50        regmap_write(priv->regmap, MT6359_GPIO_MODE4_SET, 0x0009);
  51}
  52
  53static void mt6359_reset_capture_gpio(struct mt6359_priv *priv)
  54{
  55        /* set pad_aud_*_miso to GPIO mode and dir input
  56         * reason:
  57         * pad_aud_clk_miso, because when playback only the miso_clk
  58         * will also have 26m, so will have power leak
  59         * pad_aud_dat_miso*, because the pin is used as boot strap
  60         */
  61        regmap_write(priv->regmap, MT6359_GPIO_MODE3_CLR, 0x0e00);
  62
  63        regmap_write(priv->regmap, MT6359_GPIO_MODE4_CLR, 0x003f);
  64
  65        regmap_update_bits(priv->regmap, MT6359_GPIO_DIR0,
  66                           0x7 << 13, 0x0);
  67        regmap_update_bits(priv->regmap, MT6359_GPIO_DIR1,
  68                           0x3 << 0, 0x0);
  69}
  70
  71/* use only when doing mtkaif calibraiton at the boot time */
  72static void mt6359_set_dcxo(struct mt6359_priv *priv, bool enable)
  73{
  74        regmap_update_bits(priv->regmap, MT6359_DCXO_CW12,
  75                           0x1 << RG_XO_AUDIO_EN_M_SFT,
  76                           (enable ? 1 : 0) << RG_XO_AUDIO_EN_M_SFT);
  77}
  78
  79/* use only when doing mtkaif calibraiton at the boot time */
  80static void mt6359_set_clksq(struct mt6359_priv *priv, bool enable)
  81{
  82        /* Enable/disable CLKSQ 26MHz */
  83        regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON23,
  84                           RG_CLKSQ_EN_MASK_SFT,
  85                           (enable ? 1 : 0) << RG_CLKSQ_EN_SFT);
  86}
  87
  88/* use only when doing mtkaif calibraiton at the boot time */
  89static void mt6359_set_aud_global_bias(struct mt6359_priv *priv, bool enable)
  90{
  91        regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON13,
  92                           RG_AUDGLB_PWRDN_VA32_MASK_SFT,
  93                           (enable ? 0 : 1) << RG_AUDGLB_PWRDN_VA32_SFT);
  94}
  95
  96/* use only when doing mtkaif calibraiton at the boot time */
  97static void mt6359_set_topck(struct mt6359_priv *priv, bool enable)
  98{
  99        regmap_update_bits(priv->regmap, MT6359_AUD_TOP_CKPDN_CON0,
 100                           0x0066, enable ? 0x0 : 0x66);
 101}
 102
 103static void mt6359_set_decoder_clk(struct mt6359_priv *priv, bool enable)
 104{
 105        regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON13,
 106                           RG_RSTB_DECODER_VA32_MASK_SFT,
 107                           (enable ? 1 : 0) << RG_RSTB_DECODER_VA32_SFT);
 108}
 109
 110static void mt6359_mtkaif_tx_enable(struct mt6359_priv *priv)
 111{
 112        switch (priv->mtkaif_protocol) {
 113        case MT6359_MTKAIF_PROTOCOL_2_CLK_P2:
 114                /* MTKAIF TX format setting */
 115                regmap_update_bits(priv->regmap,
 116                                   MT6359_AFE_ADDA_MTKAIF_CFG0,
 117                                   0xffff, 0x0210);
 118                /* enable aud_pad TX fifos */
 119                regmap_update_bits(priv->regmap,
 120                                   MT6359_AFE_AUD_PAD_TOP,
 121                                   0xff00, 0x3800);
 122                regmap_update_bits(priv->regmap,
 123                                   MT6359_AFE_AUD_PAD_TOP,
 124                                   0xff00, 0x3900);
 125                break;
 126        case MT6359_MTKAIF_PROTOCOL_2:
 127                /* MTKAIF TX format setting */
 128                regmap_update_bits(priv->regmap,
 129                                   MT6359_AFE_ADDA_MTKAIF_CFG0,
 130                                   0xffff, 0x0210);
 131                /* enable aud_pad TX fifos */
 132                regmap_update_bits(priv->regmap,
 133                                   MT6359_AFE_AUD_PAD_TOP,
 134                                   0xff00, 0x3100);
 135                break;
 136        case MT6359_MTKAIF_PROTOCOL_1:
 137        default:
 138                /* MTKAIF TX format setting */
 139                regmap_update_bits(priv->regmap,
 140                                   MT6359_AFE_ADDA_MTKAIF_CFG0,
 141                                   0xffff, 0x0000);
 142                /* enable aud_pad TX fifos */
 143                regmap_update_bits(priv->regmap,
 144                                   MT6359_AFE_AUD_PAD_TOP,
 145                                   0xff00, 0x3100);
 146                break;
 147        }
 148}
 149
 150static void mt6359_mtkaif_tx_disable(struct mt6359_priv *priv)
 151{
 152        /* disable aud_pad TX fifos */
 153        regmap_update_bits(priv->regmap, MT6359_AFE_AUD_PAD_TOP,
 154                           0xff00, 0x3000);
 155}
 156
 157void mt6359_set_mtkaif_protocol(struct snd_soc_component *cmpnt,
 158                                int mtkaif_protocol)
 159{
 160        struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
 161
 162        priv->mtkaif_protocol = mtkaif_protocol;
 163}
 164EXPORT_SYMBOL_GPL(mt6359_set_mtkaif_protocol);
 165
 166void mt6359_mtkaif_calibration_enable(struct snd_soc_component *cmpnt)
 167{
 168        struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
 169
 170        mt6359_set_playback_gpio(priv);
 171        mt6359_set_capture_gpio(priv);
 172        mt6359_mtkaif_tx_enable(priv);
 173
 174        mt6359_set_dcxo(priv, true);
 175        mt6359_set_aud_global_bias(priv, true);
 176        mt6359_set_clksq(priv, true);
 177        mt6359_set_topck(priv, true);
 178
 179        /* set dat_miso_loopback on */
 180        regmap_update_bits(priv->regmap, MT6359_AUDIO_DIG_CFG,
 181                           RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_MASK_SFT,
 182                           1 << RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_SFT);
 183        regmap_update_bits(priv->regmap, MT6359_AUDIO_DIG_CFG,
 184                           RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_MASK_SFT,
 185                           1 << RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_SFT);
 186        regmap_update_bits(priv->regmap, MT6359_AUDIO_DIG_CFG1,
 187                           RG_AUD_PAD_TOP_DAT_MISO3_LOOPBACK_MASK_SFT,
 188                           1 << RG_AUD_PAD_TOP_DAT_MISO3_LOOPBACK_SFT);
 189}
 190EXPORT_SYMBOL_GPL(mt6359_mtkaif_calibration_enable);
 191
 192void mt6359_mtkaif_calibration_disable(struct snd_soc_component *cmpnt)
 193{
 194        struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
 195
 196        /* set dat_miso_loopback off */
 197        regmap_update_bits(priv->regmap, MT6359_AUDIO_DIG_CFG,
 198                           RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_MASK_SFT,
 199                           0 << RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_SFT);
 200        regmap_update_bits(priv->regmap, MT6359_AUDIO_DIG_CFG,
 201                           RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_MASK_SFT,
 202                           0 << RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_SFT);
 203        regmap_update_bits(priv->regmap, MT6359_AUDIO_DIG_CFG1,
 204                           RG_AUD_PAD_TOP_DAT_MISO3_LOOPBACK_MASK_SFT,
 205                           0 << RG_AUD_PAD_TOP_DAT_MISO3_LOOPBACK_SFT);
 206
 207        mt6359_set_topck(priv, false);
 208        mt6359_set_clksq(priv, false);
 209        mt6359_set_aud_global_bias(priv, false);
 210        mt6359_set_dcxo(priv, false);
 211
 212        mt6359_mtkaif_tx_disable(priv);
 213        mt6359_reset_playback_gpio(priv);
 214        mt6359_reset_capture_gpio(priv);
 215}
 216EXPORT_SYMBOL_GPL(mt6359_mtkaif_calibration_disable);
 217
 218void mt6359_set_mtkaif_calibration_phase(struct snd_soc_component *cmpnt,
 219                                         int phase_1, int phase_2, int phase_3)
 220{
 221        struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
 222
 223        regmap_update_bits(priv->regmap, MT6359_AUDIO_DIG_CFG,
 224                           RG_AUD_PAD_TOP_PHASE_MODE_MASK_SFT,
 225                           phase_1 << RG_AUD_PAD_TOP_PHASE_MODE_SFT);
 226        regmap_update_bits(priv->regmap, MT6359_AUDIO_DIG_CFG,
 227                           RG_AUD_PAD_TOP_PHASE_MODE2_MASK_SFT,
 228                           phase_2 << RG_AUD_PAD_TOP_PHASE_MODE2_SFT);
 229        regmap_update_bits(priv->regmap, MT6359_AUDIO_DIG_CFG1,
 230                           RG_AUD_PAD_TOP_PHASE_MODE3_MASK_SFT,
 231                           phase_3 << RG_AUD_PAD_TOP_PHASE_MODE3_SFT);
 232}
 233EXPORT_SYMBOL_GPL(mt6359_set_mtkaif_calibration_phase);
 234
 235static void zcd_disable(struct mt6359_priv *priv)
 236{
 237        regmap_write(priv->regmap, MT6359_ZCD_CON0, 0x0000);
 238}
 239
 240static void hp_main_output_ramp(struct mt6359_priv *priv, bool up)
 241{
 242        int i, stage;
 243        int target = 7;
 244
 245        /* Enable/Reduce HPL/R main output stage step by step */
 246        for (i = 0; i <= target; i++) {
 247                stage = up ? i : target - i;
 248                regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON1,
 249                                   RG_HPLOUTSTGCTRL_VAUDP32_MASK_SFT,
 250                                   stage << RG_HPLOUTSTGCTRL_VAUDP32_SFT);
 251                regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON1,
 252                                   RG_HPROUTSTGCTRL_VAUDP32_MASK_SFT,
 253                                   stage << RG_HPROUTSTGCTRL_VAUDP32_SFT);
 254                usleep_range(600, 650);
 255        }
 256}
 257
 258static void hp_aux_feedback_loop_gain_ramp(struct mt6359_priv *priv, bool up)
 259{
 260        int i, stage;
 261        int target = 0xf;
 262
 263        /* Enable/Reduce HP aux feedback loop gain step by step */
 264        for (i = 0; i <= target; i++) {
 265                stage = up ? i : target - i;
 266                regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON9,
 267                                   0xf << 12, stage << 12);
 268                usleep_range(600, 650);
 269        }
 270}
 271
 272static void hp_in_pair_current(struct mt6359_priv *priv, bool increase)
 273{
 274        int i, stage;
 275        int target = 0x3;
 276
 277        /* Set input diff pair bias select (Hi-Fi mode) */
 278        if (priv->hp_hifi_mode) {
 279                /* Reduce HP aux feedback loop gain step by step */
 280                for (i = 0; i <= target; i++) {
 281                        stage = increase ? i : target - i;
 282                        regmap_update_bits(priv->regmap,
 283                                           MT6359_AUDDEC_ANA_CON10,
 284                                           0x3 << 3, stage << 3);
 285                        usleep_range(100, 150);
 286                }
 287        }
 288}
 289
 290static void hp_pull_down(struct mt6359_priv *priv, bool enable)
 291{
 292        int i;
 293
 294        if (enable) {
 295                for (i = 0x0; i <= 0x7; i++) {
 296                        regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON2,
 297                                           RG_HPPSHORT2VCM_VAUDP32_MASK_SFT,
 298                                           i << RG_HPPSHORT2VCM_VAUDP32_SFT);
 299                        usleep_range(100, 150);
 300                }
 301        } else {
 302                for (i = 0x7; i >= 0x0; i--) {
 303                        regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON2,
 304                                           RG_HPPSHORT2VCM_VAUDP32_MASK_SFT,
 305                                           i << RG_HPPSHORT2VCM_VAUDP32_SFT);
 306                        usleep_range(100, 150);
 307                }
 308        }
 309}
 310
 311static bool is_valid_hp_pga_idx(int reg_idx)
 312{
 313        return (reg_idx >= DL_GAIN_8DB && reg_idx <= DL_GAIN_N_22DB) ||
 314               reg_idx == DL_GAIN_N_40DB;
 315}
 316
 317static void headset_volume_ramp(struct mt6359_priv *priv,
 318                                int from, int to)
 319{
 320        int offset = 0, count = 1, reg_idx;
 321
 322        if (!is_valid_hp_pga_idx(from) || !is_valid_hp_pga_idx(to)) {
 323                dev_warn(priv->dev, "%s(), volume index is not valid, from %d, to %d\n",
 324                         __func__, from, to);
 325                return;
 326        }
 327
 328        dev_dbg(priv->dev, "%s(), from %d, to %d\n", __func__, from, to);
 329
 330        if (to > from)
 331                offset = to - from;
 332        else
 333                offset = from - to;
 334
 335        while (offset > 0) {
 336                if (to > from)
 337                        reg_idx = from + count;
 338                else
 339                        reg_idx = from - count;
 340
 341                if (is_valid_hp_pga_idx(reg_idx)) {
 342                        regmap_update_bits(priv->regmap,
 343                                           MT6359_ZCD_CON2,
 344                                           DL_GAIN_REG_MASK,
 345                                           (reg_idx << 7) | reg_idx);
 346                        usleep_range(600, 650);
 347                }
 348                offset--;
 349                count++;
 350        }
 351}
 352
 353static int mt6359_put_volsw(struct snd_kcontrol *kcontrol,
 354                            struct snd_ctl_elem_value *ucontrol)
 355{
 356        struct snd_soc_component *component =
 357                        snd_soc_kcontrol_component(kcontrol);
 358        struct mt6359_priv *priv = snd_soc_component_get_drvdata(component);
 359        struct soc_mixer_control *mc =
 360                        (struct soc_mixer_control *)kcontrol->private_value;
 361        unsigned int reg;
 362        int index = ucontrol->value.integer.value[0];
 363        int ret;
 364
 365        ret = snd_soc_put_volsw(kcontrol, ucontrol);
 366        if (ret < 0)
 367                return ret;
 368
 369        switch (mc->reg) {
 370        case MT6359_ZCD_CON2:
 371                regmap_read(priv->regmap, MT6359_ZCD_CON2, &reg);
 372                priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL] =
 373                        (reg >> RG_AUDHPLGAIN_SFT) & RG_AUDHPLGAIN_MASK;
 374                priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTR] =
 375                        (reg >> RG_AUDHPRGAIN_SFT) & RG_AUDHPRGAIN_MASK;
 376                break;
 377        case MT6359_ZCD_CON1:
 378                regmap_read(priv->regmap, MT6359_ZCD_CON1, &reg);
 379                priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTL] =
 380                        (reg >> RG_AUDLOLGAIN_SFT) & RG_AUDLOLGAIN_MASK;
 381                priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTR] =
 382                        (reg >> RG_AUDLORGAIN_SFT) & RG_AUDLORGAIN_MASK;
 383                break;
 384        case MT6359_ZCD_CON3:
 385                regmap_read(priv->regmap, MT6359_ZCD_CON3, &reg);
 386                priv->ana_gain[AUDIO_ANALOG_VOLUME_HSOUTL] =
 387                        (reg >> RG_AUDHSGAIN_SFT) & RG_AUDHSGAIN_MASK;
 388                break;
 389        case MT6359_AUDENC_ANA_CON0:
 390                regmap_read(priv->regmap, MT6359_AUDENC_ANA_CON0, &reg);
 391                priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP1] =
 392                        (reg >> RG_AUDPREAMPLGAIN_SFT) & RG_AUDPREAMPLGAIN_MASK;
 393                break;
 394        case MT6359_AUDENC_ANA_CON1:
 395                regmap_read(priv->regmap, MT6359_AUDENC_ANA_CON1, &reg);
 396                priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP2] =
 397                        (reg >> RG_AUDPREAMPRGAIN_SFT) & RG_AUDPREAMPRGAIN_MASK;
 398                break;
 399        case MT6359_AUDENC_ANA_CON2:
 400                regmap_read(priv->regmap, MT6359_AUDENC_ANA_CON2, &reg);
 401                priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP3] =
 402                        (reg >> RG_AUDPREAMP3GAIN_SFT) & RG_AUDPREAMP3GAIN_MASK;
 403                break;
 404        }
 405
 406        dev_dbg(priv->dev, "%s(), name %s, reg(0x%x) = 0x%x, set index = %x\n",
 407                __func__, kcontrol->id.name, mc->reg, reg, index);
 408
 409        return ret;
 410}
 411
 412/* MUX */
 413
 414/* LOL MUX */
 415static const char * const lo_in_mux_map[] = {
 416        "Open", "Playback_L_DAC", "Playback", "Test Mode"
 417};
 418
 419static SOC_ENUM_SINGLE_DECL(lo_in_mux_map_enum, SND_SOC_NOPM, 0, lo_in_mux_map);
 420
 421static const struct snd_kcontrol_new lo_in_mux_control =
 422        SOC_DAPM_ENUM("LO Select", lo_in_mux_map_enum);
 423
 424/*HP MUX */
 425static const char * const hp_in_mux_map[] = {
 426        "Open",
 427        "LoudSPK Playback",
 428        "Audio Playback",
 429        "Test Mode",
 430        "HP Impedance",
 431};
 432
 433static SOC_ENUM_SINGLE_DECL(hp_in_mux_map_enum,
 434                                  SND_SOC_NOPM,
 435                                  0,
 436                                  hp_in_mux_map);
 437
 438static const struct snd_kcontrol_new hp_in_mux_control =
 439        SOC_DAPM_ENUM("HP Select", hp_in_mux_map_enum);
 440
 441/* RCV MUX */
 442static const char * const rcv_in_mux_map[] = {
 443        "Open", "Mute", "Voice Playback", "Test Mode"
 444};
 445
 446static SOC_ENUM_SINGLE_DECL(rcv_in_mux_map_enum,
 447                                  SND_SOC_NOPM,
 448                                  0,
 449                                  rcv_in_mux_map);
 450
 451static const struct snd_kcontrol_new rcv_in_mux_control =
 452        SOC_DAPM_ENUM("RCV Select", rcv_in_mux_map_enum);
 453
 454/* DAC In MUX */
 455static const char * const dac_in_mux_map[] = {
 456        "Normal Path", "Sgen"
 457};
 458
 459static int dac_in_mux_map_value[] = {
 460        0x0, 0x1,
 461};
 462
 463static SOC_VALUE_ENUM_SINGLE_DECL(dac_in_mux_map_enum,
 464                                  MT6359_AFE_TOP_CON0,
 465                                  DL_SINE_ON_SFT,
 466                                  DL_SINE_ON_MASK,
 467                                  dac_in_mux_map,
 468                                  dac_in_mux_map_value);
 469
 470static const struct snd_kcontrol_new dac_in_mux_control =
 471        SOC_DAPM_ENUM("DAC Select", dac_in_mux_map_enum);
 472
 473/* AIF Out MUX */
 474static SOC_VALUE_ENUM_SINGLE_DECL(aif_out_mux_map_enum,
 475                                  MT6359_AFE_TOP_CON0,
 476                                  UL_SINE_ON_SFT,
 477                                  UL_SINE_ON_MASK,
 478                                  dac_in_mux_map,
 479                                  dac_in_mux_map_value);
 480
 481static const struct snd_kcontrol_new aif_out_mux_control =
 482        SOC_DAPM_ENUM("AIF Out Select", aif_out_mux_map_enum);
 483
 484static SOC_VALUE_ENUM_SINGLE_DECL(aif2_out_mux_map_enum,
 485                                  MT6359_AFE_TOP_CON0,
 486                                  ADDA6_UL_SINE_ON_SFT,
 487                                  ADDA6_UL_SINE_ON_MASK,
 488                                  dac_in_mux_map,
 489                                  dac_in_mux_map_value);
 490
 491static const struct snd_kcontrol_new aif2_out_mux_control =
 492        SOC_DAPM_ENUM("AIF Out Select", aif2_out_mux_map_enum);
 493
 494static const char * const ul_src_mux_map[] = {
 495        "AMIC",
 496        "DMIC",
 497};
 498
 499static int ul_src_mux_map_value[] = {
 500        UL_SRC_MUX_AMIC,
 501        UL_SRC_MUX_DMIC,
 502};
 503
 504static SOC_VALUE_ENUM_SINGLE_DECL(ul_src_mux_map_enum,
 505                                  MT6359_AFE_UL_SRC_CON0_L,
 506                                  UL_SDM_3_LEVEL_CTL_SFT,
 507                                  UL_SDM_3_LEVEL_CTL_MASK,
 508                                  ul_src_mux_map,
 509                                  ul_src_mux_map_value);
 510
 511static const struct snd_kcontrol_new ul_src_mux_control =
 512        SOC_DAPM_ENUM("UL_SRC_MUX Select", ul_src_mux_map_enum);
 513
 514static SOC_VALUE_ENUM_SINGLE_DECL(ul2_src_mux_map_enum,
 515                                  MT6359_AFE_ADDA6_UL_SRC_CON0_L,
 516                                  ADDA6_UL_SDM_3_LEVEL_CTL_SFT,
 517                                  ADDA6_UL_SDM_3_LEVEL_CTL_MASK,
 518                                  ul_src_mux_map,
 519                                  ul_src_mux_map_value);
 520
 521static const struct snd_kcontrol_new ul2_src_mux_control =
 522        SOC_DAPM_ENUM("UL_SRC_MUX Select", ul2_src_mux_map_enum);
 523
 524static const char * const miso_mux_map[] = {
 525        "UL1_CH1",
 526        "UL1_CH2",
 527        "UL2_CH1",
 528        "UL2_CH2",
 529};
 530
 531static int miso_mux_map_value[] = {
 532        MISO_MUX_UL1_CH1,
 533        MISO_MUX_UL1_CH2,
 534        MISO_MUX_UL2_CH1,
 535        MISO_MUX_UL2_CH2,
 536};
 537
 538static SOC_VALUE_ENUM_SINGLE_DECL(miso0_mux_map_enum,
 539                                  MT6359_AFE_MTKAIF_MUX_CFG,
 540                                  RG_ADDA_CH1_SEL_SFT,
 541                                  RG_ADDA_CH1_SEL_MASK,
 542                                  miso_mux_map,
 543                                  miso_mux_map_value);
 544
 545static const struct snd_kcontrol_new miso0_mux_control =
 546        SOC_DAPM_ENUM("MISO_MUX Select", miso0_mux_map_enum);
 547
 548static SOC_VALUE_ENUM_SINGLE_DECL(miso1_mux_map_enum,
 549                                  MT6359_AFE_MTKAIF_MUX_CFG,
 550                                  RG_ADDA_CH2_SEL_SFT,
 551                                  RG_ADDA_CH2_SEL_MASK,
 552                                  miso_mux_map,
 553                                  miso_mux_map_value);
 554
 555static const struct snd_kcontrol_new miso1_mux_control =
 556        SOC_DAPM_ENUM("MISO_MUX Select", miso1_mux_map_enum);
 557
 558static SOC_VALUE_ENUM_SINGLE_DECL(miso2_mux_map_enum,
 559                                  MT6359_AFE_MTKAIF_MUX_CFG,
 560                                  RG_ADDA6_CH1_SEL_SFT,
 561                                  RG_ADDA6_CH1_SEL_MASK,
 562                                  miso_mux_map,
 563                                  miso_mux_map_value);
 564
 565static const struct snd_kcontrol_new miso2_mux_control =
 566        SOC_DAPM_ENUM("MISO_MUX Select", miso2_mux_map_enum);
 567
 568static const char * const dmic_mux_map[] = {
 569        "DMIC_DATA0",
 570        "DMIC_DATA1_L",
 571        "DMIC_DATA1_L_1",
 572        "DMIC_DATA1_R",
 573};
 574
 575static int dmic_mux_map_value[] = {
 576        DMIC_MUX_DMIC_DATA0,
 577        DMIC_MUX_DMIC_DATA1_L,
 578        DMIC_MUX_DMIC_DATA1_L_1,
 579        DMIC_MUX_DMIC_DATA1_R,
 580};
 581
 582static SOC_VALUE_ENUM_SINGLE_DECL(dmic0_mux_map_enum,
 583                                  MT6359_AFE_MIC_ARRAY_CFG,
 584                                  RG_DMIC_ADC1_SOURCE_SEL_SFT,
 585                                  RG_DMIC_ADC1_SOURCE_SEL_MASK,
 586                                  dmic_mux_map,
 587                                  dmic_mux_map_value);
 588
 589static const struct snd_kcontrol_new dmic0_mux_control =
 590        SOC_DAPM_ENUM("DMIC_MUX Select", dmic0_mux_map_enum);
 591
 592/* ul1 ch2 use RG_DMIC_ADC3_SOURCE_SEL */
 593static SOC_VALUE_ENUM_SINGLE_DECL(dmic1_mux_map_enum,
 594                                  MT6359_AFE_MIC_ARRAY_CFG,
 595                                  RG_DMIC_ADC3_SOURCE_SEL_SFT,
 596                                  RG_DMIC_ADC3_SOURCE_SEL_MASK,
 597                                  dmic_mux_map,
 598                                  dmic_mux_map_value);
 599
 600static const struct snd_kcontrol_new dmic1_mux_control =
 601        SOC_DAPM_ENUM("DMIC_MUX Select", dmic1_mux_map_enum);
 602
 603/* ul2 ch1 use RG_DMIC_ADC2_SOURCE_SEL */
 604static SOC_VALUE_ENUM_SINGLE_DECL(dmic2_mux_map_enum,
 605                                  MT6359_AFE_MIC_ARRAY_CFG,
 606                                  RG_DMIC_ADC2_SOURCE_SEL_SFT,
 607                                  RG_DMIC_ADC2_SOURCE_SEL_MASK,
 608                                  dmic_mux_map,
 609                                  dmic_mux_map_value);
 610
 611static const struct snd_kcontrol_new dmic2_mux_control =
 612        SOC_DAPM_ENUM("DMIC_MUX Select", dmic2_mux_map_enum);
 613
 614/* ADC L MUX */
 615static const char * const adc_left_mux_map[] = {
 616        "Idle", "AIN0", "Left Preamplifier", "Idle_1"
 617};
 618
 619static int adc_mux_map_value[] = {
 620        ADC_MUX_IDLE,
 621        ADC_MUX_AIN0,
 622        ADC_MUX_PREAMPLIFIER,
 623        ADC_MUX_IDLE1,
 624};
 625
 626static SOC_VALUE_ENUM_SINGLE_DECL(adc_left_mux_map_enum,
 627                                  MT6359_AUDENC_ANA_CON0,
 628                                  RG_AUDADCLINPUTSEL_SFT,
 629                                  RG_AUDADCLINPUTSEL_MASK,
 630                                  adc_left_mux_map,
 631                                  adc_mux_map_value);
 632
 633static const struct snd_kcontrol_new adc_left_mux_control =
 634        SOC_DAPM_ENUM("ADC L Select", adc_left_mux_map_enum);
 635
 636/* ADC R MUX */
 637static const char * const adc_right_mux_map[] = {
 638        "Idle", "AIN0", "Right Preamplifier", "Idle_1"
 639};
 640
 641static SOC_VALUE_ENUM_SINGLE_DECL(adc_right_mux_map_enum,
 642                                  MT6359_AUDENC_ANA_CON1,
 643                                  RG_AUDADCRINPUTSEL_SFT,
 644                                  RG_AUDADCRINPUTSEL_MASK,
 645                                  adc_right_mux_map,
 646                                  adc_mux_map_value);
 647
 648static const struct snd_kcontrol_new adc_right_mux_control =
 649        SOC_DAPM_ENUM("ADC R Select", adc_right_mux_map_enum);
 650
 651/* ADC 3 MUX */
 652static const char * const adc_3_mux_map[] = {
 653        "Idle", "AIN0", "Preamplifier", "Idle_1"
 654};
 655
 656static SOC_VALUE_ENUM_SINGLE_DECL(adc_3_mux_map_enum,
 657                                  MT6359_AUDENC_ANA_CON2,
 658                                  RG_AUDADC3INPUTSEL_SFT,
 659                                  RG_AUDADC3INPUTSEL_MASK,
 660                                  adc_3_mux_map,
 661                                  adc_mux_map_value);
 662
 663static const struct snd_kcontrol_new adc_3_mux_control =
 664        SOC_DAPM_ENUM("ADC 3 Select", adc_3_mux_map_enum);
 665
 666static const char * const pga_l_mux_map[] = {
 667        "None", "AIN0", "AIN1"
 668};
 669
 670static int pga_l_mux_map_value[] = {
 671        PGA_L_MUX_NONE,
 672        PGA_L_MUX_AIN0,
 673        PGA_L_MUX_AIN1
 674};
 675
 676static SOC_VALUE_ENUM_SINGLE_DECL(pga_left_mux_map_enum,
 677                                  MT6359_AUDENC_ANA_CON0,
 678                                  RG_AUDPREAMPLINPUTSEL_SFT,
 679                                  RG_AUDPREAMPLINPUTSEL_MASK,
 680                                  pga_l_mux_map,
 681                                  pga_l_mux_map_value);
 682
 683static const struct snd_kcontrol_new pga_left_mux_control =
 684        SOC_DAPM_ENUM("PGA L Select", pga_left_mux_map_enum);
 685
 686static const char * const pga_r_mux_map[] = {
 687        "None", "AIN2", "AIN3", "AIN0"
 688};
 689
 690static int pga_r_mux_map_value[] = {
 691        PGA_R_MUX_NONE,
 692        PGA_R_MUX_AIN2,
 693        PGA_R_MUX_AIN3,
 694        PGA_R_MUX_AIN0
 695};
 696
 697static SOC_VALUE_ENUM_SINGLE_DECL(pga_right_mux_map_enum,
 698                                  MT6359_AUDENC_ANA_CON1,
 699                                  RG_AUDPREAMPRINPUTSEL_SFT,
 700                                  RG_AUDPREAMPRINPUTSEL_MASK,
 701                                  pga_r_mux_map,
 702                                  pga_r_mux_map_value);
 703
 704static const struct snd_kcontrol_new pga_right_mux_control =
 705        SOC_DAPM_ENUM("PGA R Select", pga_right_mux_map_enum);
 706
 707static const char * const pga_3_mux_map[] = {
 708        "None", "AIN3", "AIN2"
 709};
 710
 711static int pga_3_mux_map_value[] = {
 712        PGA_3_MUX_NONE,
 713        PGA_3_MUX_AIN3,
 714        PGA_3_MUX_AIN2
 715};
 716
 717static SOC_VALUE_ENUM_SINGLE_DECL(pga_3_mux_map_enum,
 718                                  MT6359_AUDENC_ANA_CON2,
 719                                  RG_AUDPREAMP3INPUTSEL_SFT,
 720                                  RG_AUDPREAMP3INPUTSEL_MASK,
 721                                  pga_3_mux_map,
 722                                  pga_3_mux_map_value);
 723
 724static const struct snd_kcontrol_new pga_3_mux_control =
 725        SOC_DAPM_ENUM("PGA 3 Select", pga_3_mux_map_enum);
 726
 727static int mt_sgen_event(struct snd_soc_dapm_widget *w,
 728                         struct snd_kcontrol *kcontrol,
 729                         int event)
 730{
 731        struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
 732        struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
 733
 734        dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event);
 735
 736        switch (event) {
 737        case SND_SOC_DAPM_PRE_PMU:
 738                /* sdm audio fifo clock power on */
 739                regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON2, 0x0006);
 740                /* scrambler clock on enable */
 741                regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON0, 0xcba1);
 742                /* sdm power on */
 743                regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON2, 0x0003);
 744                /* sdm fifo enable */
 745                regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON2, 0x000b);
 746
 747                regmap_update_bits(priv->regmap, MT6359_AFE_SGEN_CFG0,
 748                                   0xff3f,
 749                                   0x0000);
 750                regmap_update_bits(priv->regmap, MT6359_AFE_SGEN_CFG1,
 751                                   0xffff,
 752                                   0x0001);
 753                break;
 754        case SND_SOC_DAPM_POST_PMD:
 755                /* DL scrambler disabling sequence */
 756                regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON2, 0x0000);
 757                regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON0, 0xcba0);
 758                break;
 759        default:
 760                break;
 761        }
 762
 763        return 0;
 764}
 765
 766static void mtk_hp_enable(struct mt6359_priv *priv)
 767{
 768        if (priv->hp_hifi_mode) {
 769                /* Set HP DR bias current optimization, 010: 6uA */
 770                regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON11,
 771                                   DRBIAS_HP_MASK_SFT,
 772                                   DRBIAS_6UA << DRBIAS_HP_SFT);
 773                /* Set HP & ZCD bias current optimization */
 774                /* 01: ZCD: 4uA, HP/HS/LO: 5uA */
 775                regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON12,
 776                                   IBIAS_ZCD_MASK_SFT,
 777                                   IBIAS_ZCD_4UA << IBIAS_ZCD_SFT);
 778                regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON12,
 779                                   IBIAS_HP_MASK_SFT,
 780                                   IBIAS_5UA << IBIAS_HP_SFT);
 781        } else {
 782                /* Set HP DR bias current optimization, 001: 5uA */
 783                regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON11,
 784                                   DRBIAS_HP_MASK_SFT,
 785                                   DRBIAS_5UA << DRBIAS_HP_SFT);
 786                /* Set HP & ZCD bias current optimization */
 787                /* 00: ZCD: 3uA, HP/HS/LO: 4uA */
 788                regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON12,
 789                                   IBIAS_ZCD_MASK_SFT,
 790                                   IBIAS_ZCD_3UA << IBIAS_ZCD_SFT);
 791                regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON12,
 792                                   IBIAS_HP_MASK_SFT,
 793                                   IBIAS_4UA << IBIAS_HP_SFT);
 794        }
 795
 796        /* HP damp circuit enable */
 797        /* Enable HPRN/HPLN output 4K to VCM */
 798        regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON10, 0x0087);
 799
 800        /* HP Feedback Cap select 2'b00: 15pF */
 801        /* for >= 96KHz sampling rate: 2'b01: 10.5pF */
 802        if (priv->dl_rate[MT6359_AIF_1] >= 96000)
 803                regmap_update_bits(priv->regmap,
 804                                   MT6359_AUDDEC_ANA_CON4,
 805                                   RG_AUDHPHFCOMPBUFGAINSEL_VAUDP32_MASK_SFT,
 806                                   0x1 << RG_AUDHPHFCOMPBUFGAINSEL_VAUDP32_SFT);
 807        else
 808                regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON4, 0x0000);
 809
 810        /* Set HPP/N STB enhance circuits */
 811        regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON2, 0xf133);
 812
 813        /* Enable HP aux output stage */
 814        regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x000c);
 815        /* Enable HP aux feedback loop */
 816        regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x003c);
 817        /* Enable HP aux CMFB loop */
 818        regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0x0c00);
 819        /* Enable HP driver bias circuits */
 820        regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON0, 0x30c0);
 821        /* Enable HP driver core circuits */
 822        regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON0, 0x30f0);
 823        /* Short HP main output to HP aux output stage */
 824        regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x00fc);
 825
 826        /* Increase HP input pair current to HPM step by step */
 827        hp_in_pair_current(priv, true);
 828
 829        /* Enable HP main CMFB loop */
 830        regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0x0e00);
 831        /* Disable HP aux CMFB loop */
 832        regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0x0200);
 833
 834        /* Enable HP main output stage */
 835        regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x00ff);
 836        /* Enable HPR/L main output stage step by step */
 837        hp_main_output_ramp(priv, true);
 838
 839        /* Reduce HP aux feedback loop gain */
 840        hp_aux_feedback_loop_gain_ramp(priv, true);
 841        /* Disable HP aux feedback loop */
 842        regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x77cf);
 843
 844        /* apply volume setting */
 845        headset_volume_ramp(priv,
 846                            DL_GAIN_N_22DB,
 847                            priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL]);
 848
 849        /* Disable HP aux output stage */
 850        regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x77c3);
 851        /* Unshort HP main output to HP aux output stage */
 852        regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x7703);
 853        usleep_range(100, 120);
 854
 855        /* Enable AUD_CLK */
 856        mt6359_set_decoder_clk(priv, true);
 857
 858        /* Enable Audio DAC  */
 859        regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON0, 0x30ff);
 860        if (priv->hp_hifi_mode) {
 861                /* Enable low-noise mode of DAC */
 862                regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0xf201);
 863        } else {
 864                /* Disable low-noise mode of DAC */
 865                regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0xf200);
 866        }
 867        usleep_range(100, 120);
 868
 869        /* Switch HPL MUX to audio DAC */
 870        regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON0, 0x32ff);
 871        /* Switch HPR MUX to audio DAC */
 872        regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON0, 0x3aff);
 873
 874        /* Disable Pull-down HPL/R to AVSS28_AUD */
 875        hp_pull_down(priv, false);
 876}
 877
 878static void mtk_hp_disable(struct mt6359_priv *priv)
 879{
 880        /* Pull-down HPL/R to AVSS28_AUD */
 881        hp_pull_down(priv, true);
 882
 883        /* HPR/HPL mux to open */
 884        regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON0,
 885                           0x0f00, 0x0000);
 886
 887        /* Disable low-noise mode of DAC */
 888        regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON9,
 889                           0x0001, 0x0000);
 890
 891        /* Disable Audio DAC */
 892        regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON0,
 893                           0x000f, 0x0000);
 894
 895        /* Disable AUD_CLK */
 896        mt6359_set_decoder_clk(priv, false);
 897
 898        /* Short HP main output to HP aux output stage */
 899        regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x77c3);
 900        /* Enable HP aux output stage */
 901        regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x77cf);
 902
 903        /* decrease HPL/R gain to normal gain step by step */
 904        headset_volume_ramp(priv,
 905                            priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL],
 906                            DL_GAIN_N_22DB);
 907
 908        /* Enable HP aux feedback loop */
 909        regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x77ff);
 910
 911        /* Reduce HP aux feedback loop gain */
 912        hp_aux_feedback_loop_gain_ramp(priv, false);
 913
 914        /* decrease HPR/L main output stage step by step */
 915        hp_main_output_ramp(priv, false);
 916
 917        /* Disable HP main output stage */
 918        regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x3, 0x0);
 919
 920        /* Enable HP aux CMFB loop */
 921        regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0x0e01);
 922
 923        /* Disable HP main CMFB loop */
 924        regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0x0c01);
 925
 926        /* Decrease HP input pair current to 2'b00 step by step */
 927        hp_in_pair_current(priv, false);
 928
 929        /* Unshort HP main output to HP aux output stage */
 930        regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON1,
 931                           0x3 << 6, 0x0);
 932
 933        /* Disable HP driver core circuits */
 934        regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON0,
 935                           0x3 << 4, 0x0);
 936
 937        /* Disable HP driver bias circuits */
 938        regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON0,
 939                           0x3 << 6, 0x0);
 940
 941        /* Disable HP aux CMFB loop */
 942        regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0x201);
 943
 944        /* Disable HP aux feedback loop */
 945        regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON1,
 946                           0x3 << 4, 0x0);
 947
 948        /* Disable HP aux output stage */
 949        regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON1,
 950                           0x3 << 2, 0x0);
 951}
 952
 953static int mt_hp_event(struct snd_soc_dapm_widget *w,
 954                       struct snd_kcontrol *kcontrol,
 955                       int event)
 956{
 957        struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
 958        struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
 959        unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
 960        int device = DEVICE_HP;
 961
 962        dev_dbg(priv->dev, "%s(), event 0x%x, dev_counter[DEV_HP] %d, mux %u\n",
 963                __func__, event, priv->dev_counter[device], mux);
 964
 965        switch (event) {
 966        case SND_SOC_DAPM_PRE_PMU:
 967                priv->dev_counter[device]++;
 968                if (mux == HP_MUX_HP)
 969                        mtk_hp_enable(priv);
 970                break;
 971        case SND_SOC_DAPM_PRE_PMD:
 972                priv->dev_counter[device]--;
 973                if (mux == HP_MUX_HP)
 974                        mtk_hp_disable(priv);
 975                break;
 976        default:
 977                break;
 978        }
 979
 980        return 0;
 981}
 982
 983static int mt_rcv_event(struct snd_soc_dapm_widget *w,
 984                        struct snd_kcontrol *kcontrol,
 985                        int event)
 986{
 987        struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
 988        struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
 989
 990        dev_dbg(priv->dev, "%s(), event 0x%x, mux %u\n",
 991                __func__, event, dapm_kcontrol_get_value(w->kcontrols[0]));
 992
 993        switch (event) {
 994        case SND_SOC_DAPM_PRE_PMU:
 995                /* Disable handset short-circuit protection */
 996                regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON6, 0x0010);
 997
 998                /* Set RCV DR bias current optimization, 010: 6uA */
 999                regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON11,
1000                                   DRBIAS_HS_MASK_SFT,
1001                                   DRBIAS_6UA << DRBIAS_HS_SFT);
1002                /* Set RCV & ZCD bias current optimization */
1003                /* 01: ZCD: 4uA, HP/HS/LO: 5uA */
1004                regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON12,
1005                                   IBIAS_ZCD_MASK_SFT,
1006                                   IBIAS_ZCD_4UA << IBIAS_ZCD_SFT);
1007                regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON12,
1008                                   IBIAS_HS_MASK_SFT,
1009                                   IBIAS_5UA << IBIAS_HS_SFT);
1010
1011                /* Set HS STB enhance circuits */
1012                regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON6, 0x0090);
1013
1014                /* Set HS output stage (3'b111 = 8x) */
1015                regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON10, 0x7000);
1016
1017                /* Enable HS driver bias circuits */
1018                regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON6, 0x0092);
1019                /* Enable HS driver core circuits */
1020                regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON6, 0x0093);
1021
1022                /* Set HS gain to normal gain step by step */
1023                regmap_write(priv->regmap, MT6359_ZCD_CON3,
1024                             priv->ana_gain[AUDIO_ANALOG_VOLUME_HSOUTL]);
1025
1026                /* Enable AUD_CLK */
1027                mt6359_set_decoder_clk(priv, true);
1028
1029                /* Enable Audio DAC  */
1030                regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON0, 0x0009);
1031                /* Enable low-noise mode of DAC */
1032                regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0x0001);
1033                /* Switch HS MUX to audio DAC */
1034                regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON6, 0x009b);
1035                break;
1036        case SND_SOC_DAPM_PRE_PMD:
1037                /* HS mux to open */
1038                regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON6,
1039                                   RG_AUDHSMUXINPUTSEL_VAUDP32_MASK_SFT,
1040                                   RCV_MUX_OPEN);
1041
1042                /* Disable Audio DAC */
1043                regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON0,
1044                                   0x000f, 0x0000);
1045
1046                /* Disable AUD_CLK */
1047                mt6359_set_decoder_clk(priv, false);
1048
1049                /* decrease HS gain to minimum gain step by step */
1050                regmap_write(priv->regmap, MT6359_ZCD_CON3, DL_GAIN_N_40DB);
1051
1052                /* Disable HS driver core circuits */
1053                regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON6,
1054                                   RG_AUDHSPWRUP_VAUDP32_MASK_SFT, 0x0);
1055
1056                /* Disable HS driver bias circuits */
1057                regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON6,
1058                                   RG_AUDHSPWRUP_IBIAS_VAUDP32_MASK_SFT, 0x0);
1059                break;
1060        default:
1061                break;
1062        }
1063
1064        return 0;
1065}
1066
1067static int mt_lo_event(struct snd_soc_dapm_widget *w,
1068                       struct snd_kcontrol *kcontrol,
1069                       int event)
1070{
1071        struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1072        struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1073
1074        dev_dbg(priv->dev, "%s(), event 0x%x, mux %u\n",
1075                __func__, event, dapm_kcontrol_get_value(w->kcontrols[0]));
1076
1077        switch (event) {
1078        case SND_SOC_DAPM_PRE_PMU:
1079                /* Disable handset short-circuit protection */
1080                regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON7, 0x0010);
1081
1082                /* Set LO DR bias current optimization, 010: 6uA */
1083                regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON11,
1084                                   DRBIAS_LO_MASK_SFT,
1085                                   DRBIAS_6UA << DRBIAS_LO_SFT);
1086                /* Set LO & ZCD bias current optimization */
1087                /* 01: ZCD: 4uA, HP/HS/LO: 5uA */
1088                if (priv->dev_counter[DEVICE_HP] == 0)
1089                        regmap_update_bits(priv->regmap,
1090                                           MT6359_AUDDEC_ANA_CON12,
1091                                           IBIAS_ZCD_MASK_SFT,
1092                                           IBIAS_ZCD_4UA << IBIAS_ZCD_SFT);
1093
1094                regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON12,
1095                                   IBIAS_LO_MASK_SFT,
1096                                   IBIAS_5UA << IBIAS_LO_SFT);
1097
1098                /* Set LO STB enhance circuits */
1099                regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON7, 0x0110);
1100
1101                /* Enable LO driver bias circuits */
1102                regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON7, 0x0112);
1103                /* Enable LO driver core circuits */
1104                regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON7, 0x0113);
1105
1106                /* Set LO gain to normal gain step by step */
1107                regmap_write(priv->regmap, MT6359_ZCD_CON1,
1108                             priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTL]);
1109
1110                /* Enable AUD_CLK */
1111                mt6359_set_decoder_clk(priv, true);
1112
1113                /* Enable Audio DAC (3rd DAC) */
1114                regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON7, 0x3113);
1115                /* Enable low-noise mode of DAC */
1116                if (priv->dev_counter[DEVICE_HP] == 0)
1117                        regmap_write(priv->regmap,
1118                                     MT6359_AUDDEC_ANA_CON9, 0x0001);
1119                /* Switch LOL MUX to audio 3rd DAC */
1120                regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON7, 0x311b);
1121                break;
1122        case SND_SOC_DAPM_PRE_PMD:
1123                /* Switch LOL MUX to open */
1124                regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON7,
1125                                   RG_AUDLOLMUXINPUTSEL_VAUDP32_MASK_SFT,
1126                                   LO_MUX_OPEN);
1127
1128                /* Disable Audio DAC */
1129                regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON0,
1130                                   0x000f, 0x0000);
1131
1132                /* Disable AUD_CLK */
1133                mt6359_set_decoder_clk(priv, false);
1134
1135                /* decrease LO gain to minimum gain step by step */
1136                regmap_write(priv->regmap, MT6359_ZCD_CON1, DL_GAIN_N_40DB);
1137
1138                /* Disable LO driver core circuits */
1139                regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON7,
1140                                   RG_AUDLOLPWRUP_VAUDP32_MASK_SFT, 0x0);
1141
1142                /* Disable LO driver bias circuits */
1143                regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON7,
1144                                   RG_AUDLOLPWRUP_IBIAS_VAUDP32_MASK_SFT, 0x0);
1145                break;
1146        default:
1147                break;
1148        }
1149
1150        return 0;
1151}
1152
1153static int mt_adc_clk_gen_event(struct snd_soc_dapm_widget *w,
1154                                struct snd_kcontrol *kcontrol,
1155                                int event)
1156{
1157        struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1158        struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1159
1160        dev_dbg(priv->dev, "%s(), event 0x%x\n", __func__, event);
1161
1162        switch (event) {
1163        case SND_SOC_DAPM_POST_PMU:
1164                /* ADC CLK from CLKGEN (6.5MHz) */
1165                regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON5,
1166                                   RG_AUDADCCLKRSTB_MASK_SFT,
1167                                   0x1 << RG_AUDADCCLKRSTB_SFT);
1168                regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON5,
1169                                   RG_AUDADCCLKSOURCE_MASK_SFT, 0x0);
1170                regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON5,
1171                                   RG_AUDADCCLKSEL_MASK_SFT, 0x0);
1172                regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON5,
1173                                   RG_AUDADCCLKGENMODE_MASK_SFT,
1174                                   0x1 << RG_AUDADCCLKGENMODE_SFT);
1175                break;
1176        case SND_SOC_DAPM_PRE_PMD:
1177                regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON5,
1178                                   RG_AUDADCCLKSOURCE_MASK_SFT, 0x0);
1179                regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON5,
1180                                   RG_AUDADCCLKSEL_MASK_SFT, 0x0);
1181                regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON5,
1182                                   RG_AUDADCCLKGENMODE_MASK_SFT, 0x0);
1183                regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON5,
1184                                   RG_AUDADCCLKRSTB_MASK_SFT, 0x0);
1185                break;
1186        default:
1187                break;
1188        }
1189
1190        return 0;
1191}
1192
1193static int mt_dcc_clk_event(struct snd_soc_dapm_widget *w,
1194                            struct snd_kcontrol *kcontrol,
1195                            int event)
1196{
1197        struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1198        struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1199
1200        dev_dbg(priv->dev, "%s(), event 0x%x\n", __func__, event);
1201
1202        switch (event) {
1203        case SND_SOC_DAPM_PRE_PMU:
1204                /* DCC 50k CLK (from 26M) */
1205                /* MT6359_AFE_DCCLK_CFG0, bit 3 for dm ck swap */
1206                regmap_update_bits(priv->regmap, MT6359_AFE_DCCLK_CFG0,
1207                                   0xfff7, 0x2062);
1208                regmap_update_bits(priv->regmap, MT6359_AFE_DCCLK_CFG0,
1209                                   0xfff7, 0x2060);
1210                regmap_update_bits(priv->regmap, MT6359_AFE_DCCLK_CFG0,
1211                                   0xfff7, 0x2061);
1212
1213                regmap_write(priv->regmap, MT6359_AFE_DCCLK_CFG1, 0x0100);
1214                break;
1215        case SND_SOC_DAPM_POST_PMD:
1216                regmap_update_bits(priv->regmap, MT6359_AFE_DCCLK_CFG0,
1217                                   0xfff7, 0x2060);
1218                regmap_update_bits(priv->regmap, MT6359_AFE_DCCLK_CFG0,
1219                                   0xfff7, 0x2062);
1220                break;
1221        default:
1222                break;
1223        }
1224
1225        return 0;
1226}
1227
1228static int mt_mic_bias_0_event(struct snd_soc_dapm_widget *w,
1229                               struct snd_kcontrol *kcontrol,
1230                               int event)
1231{
1232        struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1233        struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1234        unsigned int mic_type = priv->mux_select[MUX_MIC_TYPE_0];
1235
1236        dev_dbg(priv->dev, "%s(), event 0x%x, mic_type %d\n",
1237                __func__, event, mic_type);
1238
1239        switch (event) {
1240        case SND_SOC_DAPM_PRE_PMU:
1241                switch (mic_type) {
1242                case MIC_TYPE_MUX_DCC_ECM_DIFF:
1243                        regmap_update_bits(priv->regmap,
1244                                           MT6359_AUDENC_ANA_CON15,
1245                                           0xff00, 0x7700);
1246                        break;
1247                case MIC_TYPE_MUX_DCC_ECM_SINGLE:
1248                        regmap_update_bits(priv->regmap,
1249                                           MT6359_AUDENC_ANA_CON15,
1250                                           0xff00, 0x1100);
1251                        break;
1252                default:
1253                        regmap_update_bits(priv->regmap,
1254                                           MT6359_AUDENC_ANA_CON15,
1255                                           0xff00, 0x0000);
1256                        break;
1257                }
1258
1259                /* DMIC enable */
1260                regmap_write(priv->regmap,
1261                             MT6359_AUDENC_ANA_CON14, 0x0004);
1262                /* MISBIAS0 = 1P9V */
1263                regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON15,
1264                                   RG_AUDMICBIAS0VREF_MASK_SFT,
1265                                   MIC_BIAS_1P9 << RG_AUDMICBIAS0VREF_SFT);
1266                /* normal power select */
1267                regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON15,
1268                                   RG_AUDMICBIAS0LOWPEN_MASK_SFT,
1269                                   0 << RG_AUDMICBIAS0LOWPEN_SFT);
1270                break;
1271        case SND_SOC_DAPM_POST_PMD:
1272                /* Disable MICBIAS0, MISBIAS0 = 1P7V */
1273                regmap_write(priv->regmap, MT6359_AUDENC_ANA_CON15, 0x0000);
1274                break;
1275        default:
1276                break;
1277        }
1278
1279        return 0;
1280}
1281
1282static int mt_mic_bias_1_event(struct snd_soc_dapm_widget *w,
1283                               struct snd_kcontrol *kcontrol,
1284                               int event)
1285{
1286        struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1287        struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1288        unsigned int mic_type = priv->mux_select[MUX_MIC_TYPE_1];
1289
1290        dev_dbg(priv->dev, "%s(), event 0x%x, mic_type %d\n",
1291                __func__, event, mic_type);
1292
1293        switch (event) {
1294        case SND_SOC_DAPM_PRE_PMU:
1295                /* MISBIAS1 = 2P6V */
1296                if (mic_type == MIC_TYPE_MUX_DCC_ECM_SINGLE)
1297                        regmap_write(priv->regmap,
1298                                     MT6359_AUDENC_ANA_CON16, 0x0160);
1299                else
1300                        regmap_write(priv->regmap,
1301                                     MT6359_AUDENC_ANA_CON16, 0x0060);
1302
1303                /* normal power select */
1304                regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON16,
1305                                   RG_AUDMICBIAS1LOWPEN_MASK_SFT,
1306                                   0 << RG_AUDMICBIAS1LOWPEN_SFT);
1307                break;
1308        default:
1309                break;
1310        }
1311
1312        return 0;
1313}
1314
1315static int mt_mic_bias_2_event(struct snd_soc_dapm_widget *w,
1316                               struct snd_kcontrol *kcontrol,
1317                               int event)
1318{
1319        struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1320        struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1321        unsigned int mic_type = priv->mux_select[MUX_MIC_TYPE_2];
1322
1323        dev_dbg(priv->dev, "%s(), event 0x%x, mic_type %d\n",
1324                __func__, event, mic_type);
1325
1326        switch (event) {
1327        case SND_SOC_DAPM_PRE_PMU:
1328                switch (mic_type) {
1329                case MIC_TYPE_MUX_DCC_ECM_DIFF:
1330                        regmap_update_bits(priv->regmap,
1331                                           MT6359_AUDENC_ANA_CON17,
1332                                           0xff00, 0x7700);
1333                        break;
1334                case MIC_TYPE_MUX_DCC_ECM_SINGLE:
1335                        regmap_update_bits(priv->regmap,
1336                                           MT6359_AUDENC_ANA_CON17,
1337                                           0xff00, 0x1100);
1338                        break;
1339                default:
1340                        regmap_update_bits(priv->regmap,
1341                                           MT6359_AUDENC_ANA_CON17,
1342                                           0xff00, 0x0000);
1343                        break;
1344                }
1345
1346                /* MISBIAS2 = 1P9V */
1347                regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON17,
1348                                   RG_AUDMICBIAS2VREF_MASK_SFT,
1349                                   MIC_BIAS_1P9 << RG_AUDMICBIAS2VREF_SFT);
1350                /* normal power select */
1351                regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON17,
1352                                   RG_AUDMICBIAS2LOWPEN_MASK_SFT,
1353                                   0 << RG_AUDMICBIAS2LOWPEN_SFT);
1354                break;
1355        case SND_SOC_DAPM_POST_PMD:
1356                /* Disable MICBIAS2, MISBIAS0 = 1P7V */
1357                regmap_write(priv->regmap, MT6359_AUDENC_ANA_CON17, 0x0000);
1358                break;
1359        default:
1360                break;
1361        }
1362
1363        return 0;
1364}
1365
1366static int mt_mtkaif_tx_event(struct snd_soc_dapm_widget *w,
1367                              struct snd_kcontrol *kcontrol,
1368                              int event)
1369{
1370        struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1371        struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1372
1373        dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event);
1374
1375        switch (event) {
1376        case SND_SOC_DAPM_PRE_PMU:
1377                mt6359_mtkaif_tx_enable(priv);
1378                break;
1379        case SND_SOC_DAPM_POST_PMD:
1380                mt6359_mtkaif_tx_disable(priv);
1381                break;
1382        default:
1383                break;
1384        }
1385
1386        return 0;
1387}
1388
1389static int mt_ul_src_dmic_event(struct snd_soc_dapm_widget *w,
1390                                struct snd_kcontrol *kcontrol,
1391                                int event)
1392{
1393        struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1394        struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1395
1396        dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event);
1397
1398        switch (event) {
1399        case SND_SOC_DAPM_PRE_PMU:
1400                /* UL dmic setting */
1401                if (priv->dmic_one_wire_mode)
1402                        regmap_write(priv->regmap, MT6359_AFE_UL_SRC_CON0_H,
1403                                     0x0400);
1404                else
1405                        regmap_write(priv->regmap, MT6359_AFE_UL_SRC_CON0_H,
1406                                     0x0080);
1407                /* default one wire, 3.25M */
1408                regmap_update_bits(priv->regmap, MT6359_AFE_UL_SRC_CON0_L,
1409                                   0xfffc, 0x0000);
1410                break;
1411        case SND_SOC_DAPM_POST_PMD:
1412                regmap_write(priv->regmap,
1413                             MT6359_AFE_UL_SRC_CON0_H, 0x0000);
1414                break;
1415        default:
1416                break;
1417        }
1418
1419        return 0;
1420}
1421
1422static int mt_ul_src_34_dmic_event(struct snd_soc_dapm_widget *w,
1423                                   struct snd_kcontrol *kcontrol,
1424                                   int event)
1425{
1426        struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1427        struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1428
1429        dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event);
1430
1431        switch (event) {
1432        case SND_SOC_DAPM_PRE_PMU:
1433                /* default two wire, 3.25M */
1434                regmap_write(priv->regmap,
1435                             MT6359_AFE_ADDA6_L_SRC_CON0_H, 0x0080);
1436                regmap_update_bits(priv->regmap, MT6359_AFE_ADDA6_UL_SRC_CON0_L,
1437                                   0xfffc, 0x0000);
1438                break;
1439        case SND_SOC_DAPM_POST_PMD:
1440                regmap_write(priv->regmap,
1441                             MT6359_AFE_ADDA6_L_SRC_CON0_H, 0x0000);
1442                break;
1443        default:
1444                break;
1445        }
1446
1447        return 0;
1448}
1449
1450static int mt_adc_l_event(struct snd_soc_dapm_widget *w,
1451                          struct snd_kcontrol *kcontrol,
1452                          int event)
1453{
1454        struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1455        struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1456
1457        dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event);
1458
1459        switch (event) {
1460        case SND_SOC_DAPM_POST_PMU:
1461                usleep_range(100, 120);
1462                /* Audio L preamplifier DCC precharge off */
1463                regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON0,
1464                                   RG_AUDPREAMPLDCPRECHARGE_MASK_SFT,
1465                                   0x0);
1466                break;
1467        default:
1468                break;
1469        }
1470
1471        return 0;
1472}
1473
1474static int mt_adc_r_event(struct snd_soc_dapm_widget *w,
1475                          struct snd_kcontrol *kcontrol,
1476                          int event)
1477{
1478        struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1479        struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1480
1481        dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event);
1482
1483        switch (event) {
1484        case SND_SOC_DAPM_POST_PMU:
1485                usleep_range(100, 120);
1486                /* Audio R preamplifier DCC precharge off */
1487                regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON1,
1488                                   RG_AUDPREAMPRDCPRECHARGE_MASK_SFT,
1489                                   0x0);
1490                break;
1491        default:
1492                break;
1493        }
1494
1495        return 0;
1496}
1497
1498static int mt_adc_3_event(struct snd_soc_dapm_widget *w,
1499                          struct snd_kcontrol *kcontrol,
1500                          int event)
1501{
1502        struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1503        struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1504
1505        dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event);
1506
1507        switch (event) {
1508        case SND_SOC_DAPM_POST_PMU:
1509                usleep_range(100, 120);
1510                /* Audio R preamplifier DCC precharge off */
1511                regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON2,
1512                                   RG_AUDPREAMP3DCPRECHARGE_MASK_SFT,
1513                                   0x0);
1514                break;
1515        default:
1516                break;
1517        }
1518
1519        return 0;
1520}
1521
1522static int mt_pga_l_mux_event(struct snd_soc_dapm_widget *w,
1523                              struct snd_kcontrol *kcontrol,
1524                              int event)
1525{
1526        struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1527        struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1528        unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
1529
1530        dev_dbg(priv->dev, "%s(), mux %d\n", __func__, mux);
1531        priv->mux_select[MUX_PGA_L] = mux >> RG_AUDPREAMPLINPUTSEL_SFT;
1532        return 0;
1533}
1534
1535static int mt_pga_r_mux_event(struct snd_soc_dapm_widget *w,
1536                              struct snd_kcontrol *kcontrol,
1537                              int event)
1538{
1539        struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1540        struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1541        unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
1542
1543        dev_dbg(priv->dev, "%s(), mux %d\n", __func__, mux);
1544        priv->mux_select[MUX_PGA_R] = mux >> RG_AUDPREAMPRINPUTSEL_SFT;
1545        return 0;
1546}
1547
1548static int mt_pga_3_mux_event(struct snd_soc_dapm_widget *w,
1549                              struct snd_kcontrol *kcontrol,
1550                              int event)
1551{
1552        struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1553        struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1554        unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
1555
1556        dev_dbg(priv->dev, "%s(), mux %d\n", __func__, mux);
1557        priv->mux_select[MUX_PGA_3] = mux >> RG_AUDPREAMP3INPUTSEL_SFT;
1558        return 0;
1559}
1560
1561static int mt_pga_l_event(struct snd_soc_dapm_widget *w,
1562                          struct snd_kcontrol *kcontrol,
1563                          int event)
1564{
1565        struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1566        struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1567        int mic_gain_l = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP1];
1568        unsigned int mux_pga = priv->mux_select[MUX_PGA_L];
1569        unsigned int mic_type;
1570
1571        switch (mux_pga) {
1572        case PGA_L_MUX_AIN0:
1573                mic_type = priv->mux_select[MUX_MIC_TYPE_0];
1574                break;
1575        case PGA_L_MUX_AIN1:
1576                mic_type = priv->mux_select[MUX_MIC_TYPE_1];
1577                break;
1578        default:
1579                dev_err(priv->dev, "%s(), invalid pga mux %d\n",
1580                        __func__, mux_pga);
1581                return -EINVAL;
1582        }
1583
1584        switch (event) {
1585        case SND_SOC_DAPM_PRE_PMU:
1586                if (IS_DCC_BASE(mic_type)) {
1587                        /* Audio L preamplifier DCC precharge */
1588                        regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON0,
1589                                           RG_AUDPREAMPLDCPRECHARGE_MASK_SFT,
1590                                           0x1 << RG_AUDPREAMPLDCPRECHARGE_SFT);
1591                }
1592                break;
1593        case SND_SOC_DAPM_POST_PMU:
1594                /* set mic pga gain */
1595                regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON0,
1596                                   RG_AUDPREAMPLGAIN_MASK_SFT,
1597                                   mic_gain_l << RG_AUDPREAMPLGAIN_SFT);
1598
1599                if (IS_DCC_BASE(mic_type)) {
1600                        /* L preamplifier DCCEN */
1601                        regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON0,
1602                                           RG_AUDPREAMPLDCCEN_MASK_SFT,
1603                                           0x1 << RG_AUDPREAMPLDCCEN_SFT);
1604                }
1605                break;
1606        case SND_SOC_DAPM_POST_PMD:
1607                /* L preamplifier DCCEN */
1608                regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON0,
1609                                   RG_AUDPREAMPLDCCEN_MASK_SFT,
1610                                   0x0 << RG_AUDPREAMPLDCCEN_SFT);
1611                break;
1612        default:
1613                break;
1614        }
1615
1616        return 0;
1617}
1618
1619static int mt_pga_r_event(struct snd_soc_dapm_widget *w,
1620                          struct snd_kcontrol *kcontrol,
1621                          int event)
1622{
1623        struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1624        struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1625        int mic_gain_r = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP2];
1626        unsigned int mux_pga = priv->mux_select[MUX_PGA_R];
1627        unsigned int mic_type;
1628
1629        switch (mux_pga) {
1630        case PGA_R_MUX_AIN0:
1631                mic_type = priv->mux_select[MUX_MIC_TYPE_0];
1632                break;
1633        case PGA_R_MUX_AIN2:
1634        case PGA_R_MUX_AIN3:
1635                mic_type = priv->mux_select[MUX_MIC_TYPE_2];
1636                break;
1637        default:
1638                dev_err(priv->dev, "%s(), invalid pga mux %d\n",
1639                        __func__, mux_pga);
1640                return -EINVAL;
1641        }
1642
1643        switch (event) {
1644        case SND_SOC_DAPM_PRE_PMU:
1645                if (IS_DCC_BASE(mic_type)) {
1646                        /* Audio R preamplifier DCC precharge */
1647                        regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON1,
1648                                           RG_AUDPREAMPRDCPRECHARGE_MASK_SFT,
1649                                           0x1 << RG_AUDPREAMPRDCPRECHARGE_SFT);
1650                }
1651                break;
1652        case SND_SOC_DAPM_POST_PMU:
1653                /* set mic pga gain */
1654                regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON1,
1655                                   RG_AUDPREAMPRGAIN_MASK_SFT,
1656                                   mic_gain_r << RG_AUDPREAMPRGAIN_SFT);
1657
1658                if (IS_DCC_BASE(mic_type)) {
1659                        /* R preamplifier DCCEN */
1660                        regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON1,
1661                                           RG_AUDPREAMPRDCCEN_MASK_SFT,
1662                                           0x1 << RG_AUDPREAMPRDCCEN_SFT);
1663                }
1664                break;
1665        case SND_SOC_DAPM_POST_PMD:
1666                /* R preamplifier DCCEN */
1667                regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON1,
1668                                   RG_AUDPREAMPRDCCEN_MASK_SFT,
1669                                   0x0 << RG_AUDPREAMPRDCCEN_SFT);
1670                break;
1671        default:
1672                break;
1673        }
1674
1675        return 0;
1676}
1677
1678static int mt_pga_3_event(struct snd_soc_dapm_widget *w,
1679                          struct snd_kcontrol *kcontrol,
1680                          int event)
1681{
1682        struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1683        struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1684        int mic_gain_3 = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP3];
1685        unsigned int mux_pga = priv->mux_select[MUX_PGA_3];
1686        unsigned int mic_type;
1687
1688        switch (mux_pga) {
1689        case PGA_3_MUX_AIN2:
1690        case PGA_3_MUX_AIN3:
1691                mic_type = priv->mux_select[MUX_MIC_TYPE_2];
1692                break;
1693        default:
1694                dev_err(priv->dev, "%s(), invalid pga mux %d\n",
1695                        __func__, mux_pga);
1696                return -EINVAL;
1697        }
1698
1699        switch (event) {
1700        case SND_SOC_DAPM_PRE_PMU:
1701                if (IS_DCC_BASE(mic_type)) {
1702                        /* Audio 3 preamplifier DCC precharge */
1703                        regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON2,
1704                                           RG_AUDPREAMP3DCPRECHARGE_MASK_SFT,
1705                                           0x1 << RG_AUDPREAMP3DCPRECHARGE_SFT);
1706                }
1707                break;
1708        case SND_SOC_DAPM_POST_PMU:
1709                /* set mic pga gain */
1710                regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON2,
1711                                   RG_AUDPREAMP3GAIN_MASK_SFT,
1712                                   mic_gain_3 << RG_AUDPREAMP3GAIN_SFT);
1713
1714                if (IS_DCC_BASE(mic_type)) {
1715                        /* 3 preamplifier DCCEN */
1716                        regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON2,
1717                                           RG_AUDPREAMP3DCCEN_MASK_SFT,
1718                                           0x1 << RG_AUDPREAMP3DCCEN_SFT);
1719                }
1720                break;
1721        case SND_SOC_DAPM_POST_PMD:
1722                /* 3 preamplifier DCCEN */
1723                regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON2,
1724                                   RG_AUDPREAMP3DCCEN_MASK_SFT,
1725                                   0x0 << RG_AUDPREAMP3DCCEN_SFT);
1726                break;
1727        default:
1728                break;
1729        }
1730
1731        return 0;
1732}
1733
1734/* It is based on hw's control sequenece to add some delay when PMU/PMD */
1735static int mt_delay_250_event(struct snd_soc_dapm_widget *w,
1736                              struct snd_kcontrol *kcontrol,
1737                              int event)
1738{
1739        switch (event) {
1740        case SND_SOC_DAPM_POST_PMU:
1741        case SND_SOC_DAPM_PRE_PMD:
1742                usleep_range(250, 270);
1743                break;
1744        default:
1745                break;
1746        }
1747
1748        return 0;
1749}
1750
1751static int mt_delay_100_event(struct snd_soc_dapm_widget *w,
1752                              struct snd_kcontrol *kcontrol,
1753                              int event)
1754{
1755        switch (event) {
1756        case SND_SOC_DAPM_POST_PMU:
1757        case SND_SOC_DAPM_PRE_PMD:
1758                usleep_range(100, 120);
1759                break;
1760        default:
1761                break;
1762        }
1763
1764        return 0;
1765}
1766
1767static int mt_hp_pull_down_event(struct snd_soc_dapm_widget *w,
1768                                 struct snd_kcontrol *kcontrol,
1769                                 int event)
1770{
1771        struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1772        struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1773
1774        switch (event) {
1775        case SND_SOC_DAPM_PRE_PMU:
1776                hp_pull_down(priv, true);
1777                break;
1778        case SND_SOC_DAPM_POST_PMD:
1779                hp_pull_down(priv, false);
1780                break;
1781        default:
1782                break;
1783        }
1784
1785        return 0;
1786}
1787
1788static int mt_hp_mute_event(struct snd_soc_dapm_widget *w,
1789                            struct snd_kcontrol *kcontrol,
1790                            int event)
1791{
1792        struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1793        struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1794
1795        switch (event) {
1796        case SND_SOC_DAPM_PRE_PMU:
1797                /* Set HPR/HPL gain to -22dB */
1798                regmap_write(priv->regmap, MT6359_ZCD_CON2, DL_GAIN_N_22DB_REG);
1799                break;
1800        case SND_SOC_DAPM_POST_PMD:
1801                /* Set HPL/HPR gain to mute */
1802                regmap_write(priv->regmap, MT6359_ZCD_CON2, DL_GAIN_N_40DB_REG);
1803                break;
1804        default:
1805                break;
1806        }
1807
1808        return 0;
1809}
1810
1811static int mt_hp_damp_event(struct snd_soc_dapm_widget *w,
1812                            struct snd_kcontrol *kcontrol,
1813                            int event)
1814{
1815        struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1816        struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1817
1818        switch (event) {
1819        case SND_SOC_DAPM_POST_PMD:
1820                /* Disable HP damping circuit & HPN 4K load */
1821                /* reset CMFB PW level */
1822                regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON10, 0x0000);
1823                break;
1824        default:
1825                break;
1826        }
1827
1828        return 0;
1829}
1830
1831static int mt_esd_resist_event(struct snd_soc_dapm_widget *w,
1832                               struct snd_kcontrol *kcontrol,
1833                               int event)
1834{
1835        struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1836        struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1837
1838        switch (event) {
1839        case SND_SOC_DAPM_PRE_PMU:
1840                /* Reduce ESD resistance of AU_REFN */
1841                regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON2,
1842                                   RG_AUDREFN_DERES_EN_VAUDP32_MASK_SFT,
1843                                   0x1 << RG_AUDREFN_DERES_EN_VAUDP32_SFT);
1844                usleep_range(250, 270);
1845                break;
1846        case SND_SOC_DAPM_POST_PMD:
1847                /* Increase ESD resistance of AU_REFN */
1848                regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON2,
1849                                   RG_AUDREFN_DERES_EN_VAUDP32_MASK_SFT, 0x0);
1850                break;
1851        default:
1852                break;
1853        }
1854
1855        return 0;
1856}
1857
1858static int mt_sdm_event(struct snd_soc_dapm_widget *w,
1859                        struct snd_kcontrol *kcontrol,
1860                        int event)
1861{
1862        struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1863        struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1864
1865        switch (event) {
1866        case SND_SOC_DAPM_PRE_PMU:
1867                /* sdm audio fifo clock power on */
1868                regmap_update_bits(priv->regmap, MT6359_AFUNC_AUD_CON2,
1869                                   0xfffd, 0x0006);
1870                /* scrambler clock on enable */
1871                regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON0, 0xcba1);
1872                /* sdm power on */
1873                regmap_update_bits(priv->regmap, MT6359_AFUNC_AUD_CON2,
1874                                   0xfffd, 0x0003);
1875                /* sdm fifo enable */
1876                regmap_update_bits(priv->regmap, MT6359_AFUNC_AUD_CON2,
1877                                   0xfffd, 0x000B);
1878                break;
1879        case SND_SOC_DAPM_POST_PMD:
1880                /* DL scrambler disabling sequence */
1881                regmap_update_bits(priv->regmap, MT6359_AFUNC_AUD_CON2,
1882                                   0xfffd, 0x0000);
1883                regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON0, 0xcba0);
1884                break;
1885        default:
1886                break;
1887        }
1888
1889        return 0;
1890}
1891
1892static int mt_sdm_3rd_event(struct snd_soc_dapm_widget *w,
1893                            struct snd_kcontrol *kcontrol,
1894                            int event)
1895{
1896        struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1897        struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1898
1899        switch (event) {
1900        case SND_SOC_DAPM_PRE_PMU:
1901                /* sdm audio fifo clock power on */
1902                regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON11, 0x0006);
1903                /* scrambler clock on enable */
1904                regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON9, 0xcba1);
1905                /* sdm power on */
1906                regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON11, 0x0003);
1907                /* sdm fifo enable */
1908                regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON11, 0x000b);
1909                break;
1910        case SND_SOC_DAPM_POST_PMD:
1911                /* DL scrambler disabling sequence */
1912                regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON11, 0x0000);
1913                regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON9, 0xcba0);
1914                break;
1915        default:
1916                break;
1917        }
1918
1919        return 0;
1920}
1921
1922static int mt_ncp_event(struct snd_soc_dapm_widget *w,
1923                        struct snd_kcontrol *kcontrol,
1924                        int event)
1925{
1926        struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1927        struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1928
1929        switch (event) {
1930        case SND_SOC_DAPM_PRE_PMU:
1931                regmap_write(priv->regmap, MT6359_AFE_NCP_CFG0, 0xc800);
1932                break;
1933        default:
1934                break;
1935        }
1936
1937        return 0;
1938}
1939
1940/* DAPM Widgets */
1941static const struct snd_soc_dapm_widget mt6359_dapm_widgets[] = {
1942        /* Global Supply*/
1943        SND_SOC_DAPM_SUPPLY_S("CLK_BUF", SUPPLY_SEQ_CLK_BUF,
1944                              MT6359_DCXO_CW12,
1945                              RG_XO_AUDIO_EN_M_SFT, 0, NULL, 0),
1946        SND_SOC_DAPM_SUPPLY_S("AUDGLB", SUPPLY_SEQ_AUD_GLB,
1947                              MT6359_AUDDEC_ANA_CON13,
1948                              RG_AUDGLB_PWRDN_VA32_SFT, 1, NULL, 0),
1949        SND_SOC_DAPM_SUPPLY_S("CLKSQ Audio", SUPPLY_SEQ_CLKSQ,
1950                              MT6359_AUDENC_ANA_CON23,
1951                              RG_CLKSQ_EN_SFT, 0, NULL, SND_SOC_DAPM_PRE_PMU),
1952        SND_SOC_DAPM_SUPPLY_S("AUDNCP_CK", SUPPLY_SEQ_TOP_CK,
1953                              MT6359_AUD_TOP_CKPDN_CON0,
1954                              RG_AUDNCP_CK_PDN_SFT, 1, NULL, 0),
1955        SND_SOC_DAPM_SUPPLY_S("ZCD13M_CK", SUPPLY_SEQ_TOP_CK,
1956                              MT6359_AUD_TOP_CKPDN_CON0,
1957                              RG_ZCD13M_CK_PDN_SFT, 1, NULL, 0),
1958        SND_SOC_DAPM_SUPPLY_S("AUD_CK", SUPPLY_SEQ_TOP_CK_LAST,
1959                              MT6359_AUD_TOP_CKPDN_CON0,
1960                              RG_AUD_CK_PDN_SFT, 1, mt_delay_250_event,
1961                              SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1962        SND_SOC_DAPM_SUPPLY_S("AUDIF_CK", SUPPLY_SEQ_TOP_CK,
1963                              MT6359_AUD_TOP_CKPDN_CON0,
1964                              RG_AUDIF_CK_PDN_SFT, 1, NULL, 0),
1965        SND_SOC_DAPM_REGULATOR_SUPPLY("vaud18", 0, 0),
1966
1967        /* Digital Clock */
1968        SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_AFE_CTL", SUPPLY_SEQ_AUD_TOP_LAST,
1969                              MT6359_AUDIO_TOP_CON0,
1970                              PDN_AFE_CTL_SFT, 1,
1971                              mt_delay_250_event,
1972                              SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1973        SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_DAC_CTL", SUPPLY_SEQ_AUD_TOP,
1974                              MT6359_AUDIO_TOP_CON0,
1975                              PDN_DAC_CTL_SFT, 1, NULL, 0),
1976        SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_ADC_CTL", SUPPLY_SEQ_AUD_TOP,
1977                              MT6359_AUDIO_TOP_CON0,
1978                              PDN_ADC_CTL_SFT, 1, NULL, 0),
1979        SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_ADDA6_ADC_CTL", SUPPLY_SEQ_AUD_TOP,
1980                              MT6359_AUDIO_TOP_CON0,
1981                              PDN_ADDA6_ADC_CTL_SFT, 1, NULL, 0),
1982        SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_I2S_DL", SUPPLY_SEQ_AUD_TOP,
1983                              MT6359_AUDIO_TOP_CON0,
1984                              PDN_I2S_DL_CTL_SFT, 1, NULL, 0),
1985        SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_PWR_CLK", SUPPLY_SEQ_AUD_TOP,
1986                              MT6359_AUDIO_TOP_CON0,
1987                              PWR_CLK_DIS_CTL_SFT, 1, NULL, 0),
1988        SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_PDN_AFE_TESTMODEL", SUPPLY_SEQ_AUD_TOP,
1989                              MT6359_AUDIO_TOP_CON0,
1990                              PDN_AFE_TESTMODEL_CTL_SFT, 1, NULL, 0),
1991        SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_PDN_RESERVED", SUPPLY_SEQ_AUD_TOP,
1992                              MT6359_AUDIO_TOP_CON0,
1993                              PDN_RESERVED_SFT, 1, NULL, 0),
1994
1995        SND_SOC_DAPM_SUPPLY_S("SDM", SUPPLY_SEQ_DL_SDM,
1996                              SND_SOC_NOPM, 0, 0,
1997                              mt_sdm_event,
1998                              SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1999        SND_SOC_DAPM_SUPPLY_S("SDM_3RD", SUPPLY_SEQ_DL_SDM,
2000                              SND_SOC_NOPM, 0, 0,
2001                              mt_sdm_3rd_event,
2002                              SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2003
2004        /* ch123 share SDM FIFO CLK */
2005        SND_SOC_DAPM_SUPPLY_S("SDM_FIFO_CLK", SUPPLY_SEQ_DL_SDM_FIFO_CLK,
2006                              MT6359_AFUNC_AUD_CON2,
2007                              CCI_AFIFO_CLK_PWDB_SFT, 0,
2008                              NULL, 0),
2009
2010        SND_SOC_DAPM_SUPPLY_S("NCP", SUPPLY_SEQ_DL_NCP,
2011                              MT6359_AFE_NCP_CFG0,
2012                              RG_NCP_ON_SFT, 0,
2013                              mt_ncp_event,
2014                              SND_SOC_DAPM_PRE_PMU),
2015
2016        SND_SOC_DAPM_SUPPLY("DL Digital Clock", SND_SOC_NOPM,
2017                            0, 0, NULL, 0),
2018        SND_SOC_DAPM_SUPPLY("DL Digital Clock CH_1_2", SND_SOC_NOPM,
2019                            0, 0, NULL, 0),
2020        SND_SOC_DAPM_SUPPLY("DL Digital Clock CH_3", SND_SOC_NOPM,
2021                            0, 0, NULL, 0),
2022
2023        /* AFE ON */
2024        SND_SOC_DAPM_SUPPLY_S("AFE_ON", SUPPLY_SEQ_AFE,
2025                              MT6359_AFE_UL_DL_CON0, AFE_ON_SFT, 0,
2026                              NULL, 0),
2027
2028        /* AIF Rx*/
2029        SND_SOC_DAPM_AIF_IN("AIF_RX", "AIF1 Playback", 0,
2030                            SND_SOC_NOPM, 0, 0),
2031
2032        SND_SOC_DAPM_AIF_IN("AIF2_RX", "AIF2 Playback", 0,
2033                            SND_SOC_NOPM, 0, 0),
2034
2035        SND_SOC_DAPM_SUPPLY_S("AFE_DL_SRC", SUPPLY_SEQ_DL_SRC,
2036                              MT6359_AFE_DL_SRC2_CON0_L,
2037                              DL_2_SRC_ON_TMP_CTL_PRE_SFT, 0,
2038                              NULL, 0),
2039
2040        /* DL Supply */
2041        SND_SOC_DAPM_SUPPLY("DL Power Supply", SND_SOC_NOPM,
2042                            0, 0, NULL, 0),
2043
2044        SND_SOC_DAPM_SUPPLY_S("ESD_RESIST", SUPPLY_SEQ_DL_ESD_RESIST,
2045                              SND_SOC_NOPM,
2046                              0, 0,
2047                              mt_esd_resist_event,
2048                              SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2049        SND_SOC_DAPM_SUPPLY_S("LDO", SUPPLY_SEQ_DL_LDO,
2050                              MT6359_AUDDEC_ANA_CON14,
2051                              RG_LCLDO_DEC_EN_VA32_SFT, 0,
2052                              NULL, 0),
2053        SND_SOC_DAPM_SUPPLY_S("LDO_REMOTE", SUPPLY_SEQ_DL_LDO_REMOTE_SENSE,
2054                              MT6359_AUDDEC_ANA_CON14,
2055                              RG_LCLDO_DEC_REMOTE_SENSE_VA18_SFT, 0,
2056                              NULL, 0),
2057        SND_SOC_DAPM_SUPPLY_S("NV_REGULATOR", SUPPLY_SEQ_DL_NV,
2058                              MT6359_AUDDEC_ANA_CON14,
2059                              RG_NVREG_EN_VAUDP32_SFT, 0,
2060                              mt_delay_100_event, SND_SOC_DAPM_POST_PMU),
2061        SND_SOC_DAPM_SUPPLY_S("IBIST", SUPPLY_SEQ_DL_IBIST,
2062                              MT6359_AUDDEC_ANA_CON12,
2063                              RG_AUDIBIASPWRDN_VAUDP32_SFT, 1,
2064                              NULL, 0),
2065
2066        /* DAC */
2067        SND_SOC_DAPM_MUX("DAC In Mux", SND_SOC_NOPM, 0, 0, &dac_in_mux_control),
2068
2069        SND_SOC_DAPM_DAC("DACL", NULL, SND_SOC_NOPM, 0, 0),
2070
2071        SND_SOC_DAPM_DAC("DACR", NULL, SND_SOC_NOPM, 0, 0),
2072
2073        SND_SOC_DAPM_DAC("DAC_3RD", NULL, SND_SOC_NOPM, 0, 0),
2074
2075        /* Headphone */
2076        SND_SOC_DAPM_MUX_E("HP Mux", SND_SOC_NOPM, 0, 0,
2077                           &hp_in_mux_control,
2078                           mt_hp_event,
2079                           SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
2080
2081        SND_SOC_DAPM_SUPPLY("HP_Supply", SND_SOC_NOPM,
2082                            0, 0, NULL, 0),
2083        SND_SOC_DAPM_SUPPLY_S("HP_PULL_DOWN", SUPPLY_SEQ_HP_PULL_DOWN,
2084                              SND_SOC_NOPM,
2085                              0, 0,
2086                              mt_hp_pull_down_event,
2087                              SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2088        SND_SOC_DAPM_SUPPLY_S("HP_MUTE", SUPPLY_SEQ_HP_MUTE,
2089                              SND_SOC_NOPM,
2090                              0, 0,
2091                              mt_hp_mute_event,
2092                              SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2093        SND_SOC_DAPM_SUPPLY_S("HP_DAMP", SUPPLY_SEQ_HP_DAMPING_OFF_RESET_CMFB,
2094                              SND_SOC_NOPM,
2095                              0, 0,
2096                              mt_hp_damp_event,
2097                              SND_SOC_DAPM_POST_PMD),
2098
2099        /* Receiver */
2100        SND_SOC_DAPM_MUX_E("RCV Mux", SND_SOC_NOPM, 0, 0,
2101                           &rcv_in_mux_control,
2102                           mt_rcv_event,
2103                           SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
2104
2105        /* LOL */
2106        SND_SOC_DAPM_MUX_E("LOL Mux", SND_SOC_NOPM, 0, 0,
2107                           &lo_in_mux_control,
2108                           mt_lo_event,
2109                           SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
2110
2111        /* Outputs */
2112        SND_SOC_DAPM_OUTPUT("Receiver"),
2113        SND_SOC_DAPM_OUTPUT("Headphone L"),
2114        SND_SOC_DAPM_OUTPUT("Headphone R"),
2115        SND_SOC_DAPM_OUTPUT("Headphone L Ext Spk Amp"),
2116        SND_SOC_DAPM_OUTPUT("Headphone R Ext Spk Amp"),
2117        SND_SOC_DAPM_OUTPUT("LINEOUT L"),
2118
2119        /* SGEN */
2120        SND_SOC_DAPM_SUPPLY("SGEN DL Enable", MT6359_AFE_SGEN_CFG0,
2121                            SGEN_DAC_EN_CTL_SFT, 0, NULL, 0),
2122        SND_SOC_DAPM_SUPPLY("SGEN MUTE", MT6359_AFE_SGEN_CFG0,
2123                            SGEN_MUTE_SW_CTL_SFT, 1,
2124                            mt_sgen_event,
2125                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2126        SND_SOC_DAPM_SUPPLY("SGEN DL SRC", MT6359_AFE_DL_SRC2_CON0_L,
2127                            DL_2_SRC_ON_TMP_CTL_PRE_SFT, 0, NULL, 0),
2128
2129        SND_SOC_DAPM_INPUT("SGEN DL"),
2130
2131        /* Uplinks */
2132        SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0,
2133                             SND_SOC_NOPM, 0, 0),
2134        SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0,
2135                             SND_SOC_NOPM, 0, 0),
2136
2137        SND_SOC_DAPM_SUPPLY_S("ADC_CLKGEN", SUPPLY_SEQ_ADC_CLKGEN,
2138                              SND_SOC_NOPM, 0, 0,
2139                              mt_adc_clk_gen_event,
2140                              SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
2141
2142        SND_SOC_DAPM_SUPPLY_S("DCC_CLK", SUPPLY_SEQ_DCC_CLK,
2143                              SND_SOC_NOPM, 0, 0,
2144                              mt_dcc_clk_event,
2145                              SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2146
2147        /* Uplinks MUX */
2148        SND_SOC_DAPM_MUX("AIF Out Mux", SND_SOC_NOPM, 0, 0,
2149                         &aif_out_mux_control),
2150
2151        SND_SOC_DAPM_MUX("AIF2 Out Mux", SND_SOC_NOPM, 0, 0,
2152                         &aif2_out_mux_control),
2153
2154        SND_SOC_DAPM_SUPPLY("AIFTX_Supply", SND_SOC_NOPM, 0, 0, NULL, 0),
2155
2156        SND_SOC_DAPM_SUPPLY_S("MTKAIF_TX", SUPPLY_SEQ_UL_MTKAIF,
2157                              SND_SOC_NOPM, 0, 0,
2158                              mt_mtkaif_tx_event,
2159                              SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2160
2161        SND_SOC_DAPM_SUPPLY_S("UL_SRC", SUPPLY_SEQ_UL_SRC,
2162                              MT6359_AFE_UL_SRC_CON0_L,
2163                              UL_SRC_ON_TMP_CTL_SFT, 0,
2164                              NULL, 0),
2165
2166        SND_SOC_DAPM_SUPPLY_S("UL_SRC_DMIC", SUPPLY_SEQ_UL_SRC_DMIC,
2167                              SND_SOC_NOPM, 0, 0,
2168                              mt_ul_src_dmic_event,
2169                              SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2170
2171        SND_SOC_DAPM_SUPPLY_S("UL_SRC_34", SUPPLY_SEQ_UL_SRC,
2172                              MT6359_AFE_ADDA6_UL_SRC_CON0_L,
2173                              ADDA6_UL_SRC_ON_TMP_CTL_SFT, 0,
2174                              NULL, 0),
2175
2176        SND_SOC_DAPM_SUPPLY_S("UL_SRC_34_DMIC", SUPPLY_SEQ_UL_SRC_DMIC,
2177                              SND_SOC_NOPM, 0, 0,
2178                              mt_ul_src_34_dmic_event,
2179                              SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2180
2181        SND_SOC_DAPM_MUX("MISO0_MUX", SND_SOC_NOPM, 0, 0, &miso0_mux_control),
2182        SND_SOC_DAPM_MUX("MISO1_MUX", SND_SOC_NOPM, 0, 0, &miso1_mux_control),
2183        SND_SOC_DAPM_MUX("MISO2_MUX", SND_SOC_NOPM, 0, 0, &miso2_mux_control),
2184
2185        SND_SOC_DAPM_MUX("UL_SRC_MUX", SND_SOC_NOPM, 0, 0,
2186                         &ul_src_mux_control),
2187        SND_SOC_DAPM_MUX("UL2_SRC_MUX", SND_SOC_NOPM, 0, 0,
2188                         &ul2_src_mux_control),
2189
2190        SND_SOC_DAPM_MUX("DMIC0_MUX", SND_SOC_NOPM, 0, 0, &dmic0_mux_control),
2191        SND_SOC_DAPM_MUX("DMIC1_MUX", SND_SOC_NOPM, 0, 0, &dmic1_mux_control),
2192        SND_SOC_DAPM_MUX("DMIC2_MUX", SND_SOC_NOPM, 0, 0, &dmic2_mux_control),
2193
2194        SND_SOC_DAPM_MUX_E("ADC_L_Mux", SND_SOC_NOPM, 0, 0,
2195                           &adc_left_mux_control, NULL, 0),
2196        SND_SOC_DAPM_MUX_E("ADC_R_Mux", SND_SOC_NOPM, 0, 0,
2197                           &adc_right_mux_control, NULL, 0),
2198        SND_SOC_DAPM_MUX_E("ADC_3_Mux", SND_SOC_NOPM, 0, 0,
2199                           &adc_3_mux_control, NULL, 0),
2200
2201        SND_SOC_DAPM_ADC("ADC_L", NULL, SND_SOC_NOPM, 0, 0),
2202        SND_SOC_DAPM_ADC("ADC_R", NULL, SND_SOC_NOPM, 0, 0),
2203        SND_SOC_DAPM_ADC("ADC_3", NULL, SND_SOC_NOPM, 0, 0),
2204
2205        SND_SOC_DAPM_SUPPLY_S("ADC_L_EN", SUPPLY_SEQ_UL_ADC,
2206                              MT6359_AUDENC_ANA_CON0,
2207                              RG_AUDADCLPWRUP_SFT, 0,
2208                              mt_adc_l_event,
2209                              SND_SOC_DAPM_POST_PMU),
2210        SND_SOC_DAPM_SUPPLY_S("ADC_R_EN", SUPPLY_SEQ_UL_ADC,
2211                              MT6359_AUDENC_ANA_CON1,
2212                              RG_AUDADCRPWRUP_SFT, 0,
2213                              mt_adc_r_event,
2214                              SND_SOC_DAPM_POST_PMU),
2215        SND_SOC_DAPM_SUPPLY_S("ADC_3_EN", SUPPLY_SEQ_UL_ADC,
2216                              MT6359_AUDENC_ANA_CON2,
2217                              RG_AUDADC3PWRUP_SFT, 0,
2218                              mt_adc_3_event,
2219                              SND_SOC_DAPM_POST_PMU),
2220
2221        SND_SOC_DAPM_MUX_E("PGA_L_Mux", SND_SOC_NOPM, 0, 0,
2222                           &pga_left_mux_control,
2223                           mt_pga_l_mux_event,
2224                           SND_SOC_DAPM_WILL_PMU),
2225        SND_SOC_DAPM_MUX_E("PGA_R_Mux", SND_SOC_NOPM, 0, 0,
2226                           &pga_right_mux_control,
2227                           mt_pga_r_mux_event,
2228                           SND_SOC_DAPM_WILL_PMU),
2229        SND_SOC_DAPM_MUX_E("PGA_3_Mux", SND_SOC_NOPM, 0, 0,
2230                           &pga_3_mux_control,
2231                           mt_pga_3_mux_event,
2232                           SND_SOC_DAPM_WILL_PMU),
2233
2234        SND_SOC_DAPM_PGA("PGA_L", SND_SOC_NOPM, 0, 0, NULL, 0),
2235        SND_SOC_DAPM_PGA("PGA_R", SND_SOC_NOPM, 0, 0, NULL, 0),
2236        SND_SOC_DAPM_PGA("PGA_3", SND_SOC_NOPM, 0, 0, NULL, 0),
2237
2238        SND_SOC_DAPM_SUPPLY_S("PGA_L_EN", SUPPLY_SEQ_UL_PGA,
2239                              MT6359_AUDENC_ANA_CON0,
2240                              RG_AUDPREAMPLON_SFT, 0,
2241                              mt_pga_l_event,
2242                              SND_SOC_DAPM_PRE_PMU |
2243                              SND_SOC_DAPM_POST_PMU |
2244                              SND_SOC_DAPM_POST_PMD),
2245        SND_SOC_DAPM_SUPPLY_S("PGA_R_EN", SUPPLY_SEQ_UL_PGA,
2246                              MT6359_AUDENC_ANA_CON1,
2247                              RG_AUDPREAMPRON_SFT, 0,
2248                              mt_pga_r_event,
2249                              SND_SOC_DAPM_PRE_PMU |
2250                              SND_SOC_DAPM_POST_PMU |
2251                              SND_SOC_DAPM_POST_PMD),
2252        SND_SOC_DAPM_SUPPLY_S("PGA_3_EN", SUPPLY_SEQ_UL_PGA,
2253                              MT6359_AUDENC_ANA_CON2,
2254                              RG_AUDPREAMP3ON_SFT, 0,
2255                              mt_pga_3_event,
2256                              SND_SOC_DAPM_PRE_PMU |
2257                              SND_SOC_DAPM_POST_PMU |
2258                              SND_SOC_DAPM_POST_PMD),
2259
2260        /* UL input */
2261        SND_SOC_DAPM_INPUT("AIN0"),
2262        SND_SOC_DAPM_INPUT("AIN1"),
2263        SND_SOC_DAPM_INPUT("AIN2"),
2264        SND_SOC_DAPM_INPUT("AIN3"),
2265
2266        SND_SOC_DAPM_INPUT("AIN0_DMIC"),
2267        SND_SOC_DAPM_INPUT("AIN2_DMIC"),
2268        SND_SOC_DAPM_INPUT("AIN3_DMIC"),
2269
2270        /* mic bias */
2271        SND_SOC_DAPM_SUPPLY_S("MIC_BIAS_0", SUPPLY_SEQ_MIC_BIAS,
2272                              MT6359_AUDENC_ANA_CON15,
2273                              RG_AUDPWDBMICBIAS0_SFT, 0,
2274                              mt_mic_bias_0_event,
2275                              SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2276        SND_SOC_DAPM_SUPPLY_S("MIC_BIAS_1", SUPPLY_SEQ_MIC_BIAS,
2277                              MT6359_AUDENC_ANA_CON16,
2278                              RG_AUDPWDBMICBIAS1_SFT, 0,
2279                              mt_mic_bias_1_event,
2280                              SND_SOC_DAPM_PRE_PMU),
2281        SND_SOC_DAPM_SUPPLY_S("MIC_BIAS_2", SUPPLY_SEQ_MIC_BIAS,
2282                              MT6359_AUDENC_ANA_CON17,
2283                              RG_AUDPWDBMICBIAS2_SFT, 0,
2284                              mt_mic_bias_2_event,
2285                              SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2286
2287        /* dmic */
2288        SND_SOC_DAPM_SUPPLY_S("DMIC_0", SUPPLY_SEQ_DMIC,
2289                              MT6359_AUDENC_ANA_CON13,
2290                              RG_AUDDIGMICEN_SFT, 0,
2291                              NULL, 0),
2292        SND_SOC_DAPM_SUPPLY_S("DMIC_1", SUPPLY_SEQ_DMIC,
2293                              MT6359_AUDENC_ANA_CON14,
2294                              RG_AUDDIGMIC1EN_SFT, 0,
2295                              NULL, 0),
2296};
2297
2298static int mt_dcc_clk_connect(struct snd_soc_dapm_widget *source,
2299                              struct snd_soc_dapm_widget *sink)
2300{
2301        struct snd_soc_dapm_widget *w = sink;
2302        struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
2303        struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
2304
2305        if (IS_DCC_BASE(priv->mux_select[MUX_MIC_TYPE_0]) ||
2306            IS_DCC_BASE(priv->mux_select[MUX_MIC_TYPE_1]) ||
2307            IS_DCC_BASE(priv->mux_select[MUX_MIC_TYPE_2]))
2308                return 1;
2309        else
2310                return 0;
2311}
2312
2313static const struct snd_soc_dapm_route mt6359_dapm_routes[] = {
2314        /* Capture */
2315        {"AIFTX_Supply", NULL, "CLK_BUF"},
2316        {"AIFTX_Supply", NULL, "vaud18"},
2317        {"AIFTX_Supply", NULL, "AUDGLB"},
2318        {"AIFTX_Supply", NULL, "CLKSQ Audio"},
2319        {"AIFTX_Supply", NULL, "AUD_CK"},
2320        {"AIFTX_Supply", NULL, "AUDIF_CK"},
2321        {"AIFTX_Supply", NULL, "AUDIO_TOP_AFE_CTL"},
2322        {"AIFTX_Supply", NULL, "AUDIO_TOP_PWR_CLK"},
2323        {"AIFTX_Supply", NULL, "AUDIO_TOP_PDN_RESERVED"},
2324        {"AIFTX_Supply", NULL, "AUDIO_TOP_I2S_DL"},
2325        /*
2326         * *_ADC_CTL should enable only if UL_SRC in use,
2327         * but dm ck may be needed even UL_SRC_x not in use
2328         */
2329        {"AIFTX_Supply", NULL, "AUDIO_TOP_ADC_CTL"},
2330        {"AIFTX_Supply", NULL, "AUDIO_TOP_ADDA6_ADC_CTL"},
2331        {"AIFTX_Supply", NULL, "AFE_ON"},
2332
2333        /* ul ch 12 */
2334        {"AIF1TX", NULL, "AIF Out Mux"},
2335        {"AIF1TX", NULL, "AIFTX_Supply"},
2336        {"AIF1TX", NULL, "MTKAIF_TX"},
2337
2338        {"AIF2TX", NULL, "AIF2 Out Mux"},
2339        {"AIF2TX", NULL, "AIFTX_Supply"},
2340        {"AIF2TX", NULL, "MTKAIF_TX"},
2341
2342        {"AIF Out Mux", "Normal Path", "MISO0_MUX"},
2343        {"AIF Out Mux", "Normal Path", "MISO1_MUX"},
2344        {"AIF2 Out Mux", "Normal Path", "MISO2_MUX"},
2345
2346        {"MISO0_MUX", "UL1_CH1", "UL_SRC_MUX"},
2347        {"MISO0_MUX", "UL1_CH2", "UL_SRC_MUX"},
2348        {"MISO0_MUX", "UL2_CH1", "UL2_SRC_MUX"},
2349        {"MISO0_MUX", "UL2_CH2", "UL2_SRC_MUX"},
2350
2351        {"MISO1_MUX", "UL1_CH1", "UL_SRC_MUX"},
2352        {"MISO1_MUX", "UL1_CH2", "UL_SRC_MUX"},
2353        {"MISO1_MUX", "UL2_CH1", "UL2_SRC_MUX"},
2354        {"MISO1_MUX", "UL2_CH2", "UL2_SRC_MUX"},
2355
2356        {"MISO2_MUX", "UL1_CH1", "UL_SRC_MUX"},
2357        {"MISO2_MUX", "UL1_CH2", "UL_SRC_MUX"},
2358        {"MISO2_MUX", "UL2_CH1", "UL2_SRC_MUX"},
2359        {"MISO2_MUX", "UL2_CH2", "UL2_SRC_MUX"},
2360
2361        {"UL_SRC_MUX", "AMIC", "ADC_L"},
2362        {"UL_SRC_MUX", "AMIC", "ADC_R"},
2363        {"UL_SRC_MUX", "DMIC", "DMIC0_MUX"},
2364        {"UL_SRC_MUX", "DMIC", "DMIC1_MUX"},
2365        {"UL_SRC_MUX", NULL, "UL_SRC"},
2366
2367        {"UL2_SRC_MUX", "AMIC", "ADC_3"},
2368        {"UL2_SRC_MUX", "DMIC", "DMIC2_MUX"},
2369        {"UL2_SRC_MUX", NULL, "UL_SRC_34"},
2370
2371        {"DMIC0_MUX", "DMIC_DATA0", "AIN0_DMIC"},
2372        {"DMIC0_MUX", "DMIC_DATA1_L", "AIN2_DMIC"},
2373        {"DMIC0_MUX", "DMIC_DATA1_L_1", "AIN2_DMIC"},
2374        {"DMIC0_MUX", "DMIC_DATA1_R", "AIN3_DMIC"},
2375        {"DMIC1_MUX", "DMIC_DATA0", "AIN0_DMIC"},
2376        {"DMIC1_MUX", "DMIC_DATA1_L", "AIN2_DMIC"},
2377        {"DMIC1_MUX", "DMIC_DATA1_L_1", "AIN2_DMIC"},
2378        {"DMIC1_MUX", "DMIC_DATA1_R", "AIN3_DMIC"},
2379        {"DMIC2_MUX", "DMIC_DATA0", "AIN0_DMIC"},
2380        {"DMIC2_MUX", "DMIC_DATA1_L", "AIN2_DMIC"},
2381        {"DMIC2_MUX", "DMIC_DATA1_L_1", "AIN2_DMIC"},
2382        {"DMIC2_MUX", "DMIC_DATA1_R", "AIN3_DMIC"},
2383
2384        {"DMIC0_MUX", NULL, "UL_SRC_DMIC"},
2385        {"DMIC1_MUX", NULL, "UL_SRC_DMIC"},
2386        {"DMIC2_MUX", NULL, "UL_SRC_34_DMIC"},
2387
2388        {"AIN0_DMIC", NULL, "DMIC_0"},
2389        {"AIN2_DMIC", NULL, "DMIC_1"},
2390        {"AIN3_DMIC", NULL, "DMIC_1"},
2391        {"AIN0_DMIC", NULL, "MIC_BIAS_0"},
2392        {"AIN2_DMIC", NULL, "MIC_BIAS_2"},
2393        {"AIN3_DMIC", NULL, "MIC_BIAS_2"},
2394
2395        /* adc */
2396        {"ADC_L", NULL, "ADC_L_Mux"},
2397        {"ADC_L", NULL, "ADC_CLKGEN"},
2398        {"ADC_L", NULL, "ADC_L_EN"},
2399        {"ADC_R", NULL, "ADC_R_Mux"},
2400        {"ADC_R", NULL, "ADC_CLKGEN"},
2401        {"ADC_R", NULL, "ADC_R_EN"},
2402        /*
2403         * amic fifo ch1/2 clk from ADC_L,
2404         * enable ADC_L even use ADC_R only
2405         */
2406        {"ADC_R", NULL, "ADC_L_EN"},
2407        {"ADC_3", NULL, "ADC_3_Mux"},
2408        {"ADC_3", NULL, "ADC_CLKGEN"},
2409        {"ADC_3", NULL, "ADC_3_EN"},
2410
2411        {"ADC_L_Mux", "Left Preamplifier", "PGA_L"},
2412        {"ADC_R_Mux", "Right Preamplifier", "PGA_R"},
2413        {"ADC_3_Mux", "Preamplifier", "PGA_3"},
2414
2415        {"PGA_L", NULL, "PGA_L_Mux"},
2416        {"PGA_L", NULL, "PGA_L_EN"},
2417        {"PGA_R", NULL, "PGA_R_Mux"},
2418        {"PGA_R", NULL, "PGA_R_EN"},
2419        {"PGA_3", NULL, "PGA_3_Mux"},
2420        {"PGA_3", NULL, "PGA_3_EN"},
2421
2422        {"PGA_L", NULL, "DCC_CLK", mt_dcc_clk_connect},
2423        {"PGA_R", NULL, "DCC_CLK", mt_dcc_clk_connect},
2424        {"PGA_3", NULL, "DCC_CLK", mt_dcc_clk_connect},
2425
2426        {"PGA_L_Mux", "AIN0", "AIN0"},
2427        {"PGA_L_Mux", "AIN1", "AIN1"},
2428
2429        {"PGA_R_Mux", "AIN0", "AIN0"},
2430        {"PGA_R_Mux", "AIN2", "AIN2"},
2431        {"PGA_R_Mux", "AIN3", "AIN3"},
2432
2433        {"PGA_3_Mux", "AIN2", "AIN2"},
2434        {"PGA_3_Mux", "AIN3", "AIN3"},
2435
2436        {"AIN0", NULL, "MIC_BIAS_0"},
2437        {"AIN1", NULL, "MIC_BIAS_1"},
2438        {"AIN2", NULL, "MIC_BIAS_0"},
2439        {"AIN2", NULL, "MIC_BIAS_2"},
2440        {"AIN3", NULL, "MIC_BIAS_2"},
2441
2442        /* DL Supply */
2443        {"DL Power Supply", NULL, "CLK_BUF"},
2444        {"DL Power Supply", NULL, "vaud18"},
2445        {"DL Power Supply", NULL, "AUDGLB"},
2446        {"DL Power Supply", NULL, "CLKSQ Audio"},
2447        {"DL Power Supply", NULL, "AUDNCP_CK"},
2448        {"DL Power Supply", NULL, "ZCD13M_CK"},
2449        {"DL Power Supply", NULL, "AUD_CK"},
2450        {"DL Power Supply", NULL, "AUDIF_CK"},
2451        {"DL Power Supply", NULL, "ESD_RESIST"},
2452        {"DL Power Supply", NULL, "LDO"},
2453        {"DL Power Supply", NULL, "LDO_REMOTE"},
2454        {"DL Power Supply", NULL, "NV_REGULATOR"},
2455        {"DL Power Supply", NULL, "IBIST"},
2456
2457        /* DL Digital Supply */
2458        {"DL Digital Clock", NULL, "AUDIO_TOP_AFE_CTL"},
2459        {"DL Digital Clock", NULL, "AUDIO_TOP_DAC_CTL"},
2460        {"DL Digital Clock", NULL, "AUDIO_TOP_PWR_CLK"},
2461        {"DL Digital Clock", NULL, "AUDIO_TOP_PDN_RESERVED"},
2462        {"DL Digital Clock", NULL, "SDM_FIFO_CLK"},
2463        {"DL Digital Clock", NULL, "NCP"},
2464        {"DL Digital Clock", NULL, "AFE_ON"},
2465        {"DL Digital Clock", NULL, "AFE_DL_SRC"},
2466
2467        {"DL Digital Clock CH_1_2", NULL, "DL Digital Clock"},
2468        {"DL Digital Clock CH_1_2", NULL, "SDM"},
2469
2470        {"DL Digital Clock CH_3", NULL, "DL Digital Clock"},
2471        {"DL Digital Clock CH_3", NULL, "SDM_3RD"},
2472
2473        {"AIF_RX", NULL, "DL Digital Clock CH_1_2"},
2474
2475        {"AIF2_RX", NULL, "DL Digital Clock CH_3"},
2476
2477        /* DL Path */
2478        {"DAC In Mux", "Normal Path", "AIF_RX"},
2479        {"DAC In Mux", "Sgen", "SGEN DL"},
2480        {"SGEN DL", NULL, "SGEN DL SRC"},
2481        {"SGEN DL", NULL, "SGEN MUTE"},
2482        {"SGEN DL", NULL, "SGEN DL Enable"},
2483        {"SGEN DL", NULL, "DL Digital Clock CH_1_2"},
2484        {"SGEN DL", NULL, "DL Digital Clock CH_3"},
2485        {"SGEN DL", NULL, "AUDIO_TOP_PDN_AFE_TESTMODEL"},
2486
2487        {"DACL", NULL, "DAC In Mux"},
2488        {"DACL", NULL, "DL Power Supply"},
2489
2490        {"DACR", NULL, "DAC In Mux"},
2491        {"DACR", NULL, "DL Power Supply"},
2492
2493        /* DAC 3RD */
2494        {"DAC In Mux", "Normal Path", "AIF2_RX"},
2495        {"DAC_3RD", NULL, "DAC In Mux"},
2496        {"DAC_3RD", NULL, "DL Power Supply"},
2497
2498        /* Lineout Path */
2499        {"LOL Mux", "Playback", "DAC_3RD"},
2500        {"LINEOUT L", NULL, "LOL Mux"},
2501
2502        /* Headphone Path */
2503        {"HP_Supply", NULL, "HP_PULL_DOWN"},
2504        {"HP_Supply", NULL, "HP_MUTE"},
2505        {"HP_Supply", NULL, "HP_DAMP"},
2506        {"HP Mux", NULL, "HP_Supply"},
2507
2508        {"HP Mux", "Audio Playback", "DACL"},
2509        {"HP Mux", "Audio Playback", "DACR"},
2510        {"HP Mux", "HP Impedance", "DACL"},
2511        {"HP Mux", "HP Impedance", "DACR"},
2512        {"HP Mux", "LoudSPK Playback", "DACL"},
2513        {"HP Mux", "LoudSPK Playback", "DACR"},
2514
2515        {"Headphone L", NULL, "HP Mux"},
2516        {"Headphone R", NULL, "HP Mux"},
2517        {"Headphone L Ext Spk Amp", NULL, "HP Mux"},
2518        {"Headphone R Ext Spk Amp", NULL, "HP Mux"},
2519
2520        /* Receiver Path */
2521        {"RCV Mux", "Voice Playback", "DACL"},
2522        {"Receiver", NULL, "RCV Mux"},
2523};
2524
2525static int mt6359_codec_dai_hw_params(struct snd_pcm_substream *substream,
2526                                      struct snd_pcm_hw_params *params,
2527                                      struct snd_soc_dai *dai)
2528{
2529        struct snd_soc_component *cmpnt = dai->component;
2530        struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
2531        unsigned int rate = params_rate(params);
2532        int id = dai->id;
2533
2534        dev_dbg(priv->dev, "%s(), id %d, substream->stream %d, rate %d, number %d\n",
2535                __func__, id, substream->stream, rate, substream->number);
2536
2537        if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
2538                priv->dl_rate[id] = rate;
2539        else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
2540                priv->ul_rate[id] = rate;
2541
2542        return 0;
2543}
2544
2545static int mt6359_codec_dai_startup(struct snd_pcm_substream *substream,
2546                                    struct snd_soc_dai *dai)
2547{
2548        struct snd_soc_component *cmpnt = dai->component;
2549        struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
2550
2551        dev_dbg(priv->dev, "%s stream %d\n", __func__, substream->stream);
2552        if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
2553                mt6359_set_playback_gpio(priv);
2554        else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
2555                mt6359_set_capture_gpio(priv);
2556
2557        return 0;
2558}
2559
2560static void mt6359_codec_dai_shutdown(struct snd_pcm_substream *substream,
2561                                      struct snd_soc_dai *dai)
2562{
2563        struct snd_soc_component *cmpnt = dai->component;
2564        struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
2565
2566        dev_dbg(priv->dev, "%s stream %d\n", __func__, substream->stream);
2567        if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
2568                mt6359_reset_playback_gpio(priv);
2569        else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
2570                mt6359_reset_capture_gpio(priv);
2571}
2572
2573static const struct snd_soc_dai_ops mt6359_codec_dai_ops = {
2574        .hw_params = mt6359_codec_dai_hw_params,
2575        .startup = mt6359_codec_dai_startup,
2576        .shutdown = mt6359_codec_dai_shutdown,
2577};
2578
2579#define MT6359_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE |\
2580                        SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_U16_BE |\
2581                        SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S24_BE |\
2582                        SNDRV_PCM_FMTBIT_U24_LE | SNDRV_PCM_FMTBIT_U24_BE |\
2583                        SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_S32_BE |\
2584                        SNDRV_PCM_FMTBIT_U32_LE | SNDRV_PCM_FMTBIT_U32_BE)
2585
2586static struct snd_soc_dai_driver mt6359_dai_driver[] = {
2587        {
2588                .id = MT6359_AIF_1,
2589                .name = "mt6359-snd-codec-aif1",
2590                .playback = {
2591                        .stream_name = "AIF1 Playback",
2592                        .channels_min = 1,
2593                        .channels_max = 2,
2594                        .rates = SNDRV_PCM_RATE_8000_48000 |
2595                                 SNDRV_PCM_RATE_96000 |
2596                                 SNDRV_PCM_RATE_192000,
2597                        .formats = MT6359_FORMATS,
2598                },
2599                .capture = {
2600                        .stream_name = "AIF1 Capture",
2601                        .channels_min = 1,
2602                        .channels_max = 2,
2603                        .rates = SNDRV_PCM_RATE_8000 |
2604                                 SNDRV_PCM_RATE_16000 |
2605                                 SNDRV_PCM_RATE_32000 |
2606                                 SNDRV_PCM_RATE_48000 |
2607                                 SNDRV_PCM_RATE_96000 |
2608                                 SNDRV_PCM_RATE_192000,
2609                        .formats = MT6359_FORMATS,
2610                },
2611                .ops = &mt6359_codec_dai_ops,
2612        },
2613        {
2614                .id = MT6359_AIF_2,
2615                .name = "mt6359-snd-codec-aif2",
2616                .playback = {
2617                        .stream_name = "AIF2 Playback",
2618                        .channels_min = 1,
2619                        .channels_max = 2,
2620                        .rates = SNDRV_PCM_RATE_8000_48000 |
2621                                 SNDRV_PCM_RATE_96000 |
2622                                 SNDRV_PCM_RATE_192000,
2623                        .formats = MT6359_FORMATS,
2624                },
2625                .capture = {
2626                        .stream_name = "AIF2 Capture",
2627                        .channels_min = 1,
2628                        .channels_max = 2,
2629                        .rates = SNDRV_PCM_RATE_8000 |
2630                                 SNDRV_PCM_RATE_16000 |
2631                                 SNDRV_PCM_RATE_32000 |
2632                                 SNDRV_PCM_RATE_48000,
2633                        .formats = MT6359_FORMATS,
2634                },
2635                .ops = &mt6359_codec_dai_ops,
2636        },
2637};
2638
2639static int mt6359_codec_init_reg(struct snd_soc_component *cmpnt)
2640{
2641        struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
2642
2643        /* enable clk buf */
2644        regmap_update_bits(priv->regmap, MT6359_DCXO_CW12,
2645                           0x1 << RG_XO_AUDIO_EN_M_SFT,
2646                           0x1 << RG_XO_AUDIO_EN_M_SFT);
2647
2648        /* set those not controlled by dapm widget */
2649
2650        /* audio clk source from internal dcxo */
2651        regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON23,
2652                           RG_CLKSQ_IN_SEL_TEST_MASK_SFT,
2653                           0x0);
2654
2655        /* Disable HeadphoneL/HeadphoneR short circuit protection */
2656        regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON0,
2657                           RG_AUDHPLSCDISABLE_VAUDP32_MASK_SFT,
2658                           0x1 << RG_AUDHPLSCDISABLE_VAUDP32_SFT);
2659        regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON0,
2660                           RG_AUDHPRSCDISABLE_VAUDP32_MASK_SFT,
2661                           0x1 << RG_AUDHPRSCDISABLE_VAUDP32_SFT);
2662        /* Disable voice short circuit protection */
2663        regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON6,
2664                           RG_AUDHSSCDISABLE_VAUDP32_MASK_SFT,
2665                           0x1 << RG_AUDHSSCDISABLE_VAUDP32_SFT);
2666        /* disable LO buffer left short circuit protection */
2667        regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON7,
2668                           RG_AUDLOLSCDISABLE_VAUDP32_MASK_SFT,
2669                           0x1 << RG_AUDLOLSCDISABLE_VAUDP32_SFT);
2670
2671        /* set gpio */
2672        mt6359_reset_playback_gpio(priv);
2673        mt6359_reset_capture_gpio(priv);
2674
2675        /* hp hifi mode, default normal mode */
2676        priv->hp_hifi_mode = 0;
2677
2678        /* Disable AUD_ZCD */
2679        zcd_disable(priv);
2680
2681        /* disable clk buf */
2682        regmap_update_bits(priv->regmap, MT6359_DCXO_CW12,
2683                           0x1 << RG_XO_AUDIO_EN_M_SFT,
2684                           0x0 << RG_XO_AUDIO_EN_M_SFT);
2685
2686        return 0;
2687}
2688
2689static int mt6359_codec_probe(struct snd_soc_component *cmpnt)
2690{
2691        struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
2692
2693        snd_soc_component_init_regmap(cmpnt, priv->regmap);
2694
2695        return mt6359_codec_init_reg(cmpnt);
2696}
2697
2698static void mt6359_codec_remove(struct snd_soc_component *cmpnt)
2699{
2700        cmpnt->regmap = NULL;
2701}
2702
2703static const DECLARE_TLV_DB_SCALE(hp_playback_tlv, -2200, 100, 0);
2704static const DECLARE_TLV_DB_SCALE(playback_tlv, -1000, 100, 0);
2705static const DECLARE_TLV_DB_SCALE(capture_tlv, 0, 600, 0);
2706
2707static const struct snd_kcontrol_new mt6359_snd_controls[] = {
2708        /* dl pga gain */
2709        SOC_DOUBLE_EXT_TLV("Headset Volume",
2710                           MT6359_ZCD_CON2, 0, 7, 0x1E, 0,
2711                           snd_soc_get_volsw, mt6359_put_volsw,
2712                           hp_playback_tlv),
2713        SOC_DOUBLE_EXT_TLV("Lineout Volume",
2714                           MT6359_ZCD_CON1, 0, 7, 0x12, 0,
2715                           snd_soc_get_volsw, mt6359_put_volsw, playback_tlv),
2716        SOC_SINGLE_EXT_TLV("Handset Volume",
2717                           MT6359_ZCD_CON3, 0, 0x12, 0,
2718                           snd_soc_get_volsw, mt6359_put_volsw, playback_tlv),
2719
2720        /* ul pga gain */
2721        SOC_SINGLE_EXT_TLV("PGA1 Volume",
2722                           MT6359_AUDENC_ANA_CON0, RG_AUDPREAMPLGAIN_SFT, 4, 0,
2723                           snd_soc_get_volsw, mt6359_put_volsw, capture_tlv),
2724        SOC_SINGLE_EXT_TLV("PGA2 Volume",
2725                           MT6359_AUDENC_ANA_CON1, RG_AUDPREAMPRGAIN_SFT, 4, 0,
2726                           snd_soc_get_volsw, mt6359_put_volsw, capture_tlv),
2727        SOC_SINGLE_EXT_TLV("PGA3 Volume",
2728                           MT6359_AUDENC_ANA_CON2, RG_AUDPREAMP3GAIN_SFT, 4, 0,
2729                           snd_soc_get_volsw, mt6359_put_volsw, capture_tlv),
2730};
2731
2732static const struct snd_soc_component_driver mt6359_soc_component_driver = {
2733        .name = CODEC_MT6359_NAME,
2734        .probe = mt6359_codec_probe,
2735        .remove = mt6359_codec_remove,
2736        .controls = mt6359_snd_controls,
2737        .num_controls = ARRAY_SIZE(mt6359_snd_controls),
2738        .dapm_widgets = mt6359_dapm_widgets,
2739        .num_dapm_widgets = ARRAY_SIZE(mt6359_dapm_widgets),
2740        .dapm_routes = mt6359_dapm_routes,
2741        .num_dapm_routes = ARRAY_SIZE(mt6359_dapm_routes),
2742};
2743
2744static int mt6359_parse_dt(struct mt6359_priv *priv)
2745{
2746        int ret;
2747        struct device *dev = priv->dev;
2748        struct device_node *np;
2749
2750        np = of_get_child_by_name(dev->parent->of_node, "mt6359codec");
2751        if (!np)
2752                return -EINVAL;
2753
2754        ret = of_property_read_u32(np, "mediatek,dmic-mode",
2755                                   &priv->dmic_one_wire_mode);
2756        if (ret) {
2757                dev_info(priv->dev,
2758                         "%s() failed to read dmic-mode, use default (0)\n",
2759                         __func__);
2760                priv->dmic_one_wire_mode = 0;
2761        }
2762
2763        ret = of_property_read_u32(np, "mediatek,mic-type-0",
2764                                   &priv->mux_select[MUX_MIC_TYPE_0]);
2765        if (ret) {
2766                dev_info(priv->dev,
2767                         "%s() failed to read mic-type-0, use default (%d)\n",
2768                         __func__, MIC_TYPE_MUX_IDLE);
2769                priv->mux_select[MUX_MIC_TYPE_0] = MIC_TYPE_MUX_IDLE;
2770        }
2771
2772        ret = of_property_read_u32(np, "mediatek,mic-type-1",
2773                                   &priv->mux_select[MUX_MIC_TYPE_1]);
2774        if (ret) {
2775                dev_info(priv->dev,
2776                         "%s() failed to read mic-type-1, use default (%d)\n",
2777                         __func__, MIC_TYPE_MUX_IDLE);
2778                priv->mux_select[MUX_MIC_TYPE_1] = MIC_TYPE_MUX_IDLE;
2779        }
2780
2781        ret = of_property_read_u32(np, "mediatek,mic-type-2",
2782                                   &priv->mux_select[MUX_MIC_TYPE_2]);
2783        if (ret) {
2784                dev_info(priv->dev,
2785                         "%s() failed to read mic-type-2, use default (%d)\n",
2786                         __func__, MIC_TYPE_MUX_IDLE);
2787                priv->mux_select[MUX_MIC_TYPE_2] = MIC_TYPE_MUX_IDLE;
2788        }
2789
2790        return 0;
2791}
2792
2793static int mt6359_platform_driver_probe(struct platform_device *pdev)
2794{
2795        struct mt6359_priv *priv;
2796        int ret;
2797        struct mt6397_chip *mt6397 = dev_get_drvdata(pdev->dev.parent);
2798
2799        dev_dbg(&pdev->dev, "%s(), dev name %s\n",
2800                __func__, dev_name(&pdev->dev));
2801
2802        priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
2803        if (!priv)
2804                return -ENOMEM;
2805
2806        priv->regmap = mt6397->regmap;
2807        if (IS_ERR(priv->regmap))
2808                return PTR_ERR(priv->regmap);
2809
2810        dev_set_drvdata(&pdev->dev, priv);
2811        priv->dev = &pdev->dev;
2812
2813        ret = mt6359_parse_dt(priv);
2814        if (ret) {
2815                dev_warn(&pdev->dev, "%s() failed to parse dts\n", __func__);
2816                return ret;
2817        }
2818
2819        return devm_snd_soc_register_component(&pdev->dev,
2820                                               &mt6359_soc_component_driver,
2821                                               mt6359_dai_driver,
2822                                               ARRAY_SIZE(mt6359_dai_driver));
2823}
2824
2825static struct platform_driver mt6359_platform_driver = {
2826        .driver = {
2827                .name = "mt6359-sound",
2828        },
2829        .probe = mt6359_platform_driver_probe,
2830};
2831
2832module_platform_driver(mt6359_platform_driver)
2833
2834/* Module information */
2835MODULE_DESCRIPTION("MT6359 ALSA SoC codec driver");
2836MODULE_AUTHOR("KaiChieh Chuang <kaichieh.chuang@mediatek.com>");
2837MODULE_AUTHOR("Eason Yen <eason.yen@mediatek.com>");
2838MODULE_LICENSE("GPL v2");
2839